PCS2P99446G-32-LT

September 2006 rev 0.5 2.5V and 3.3V LVCMOS Clock Distribution Buffer Features • • • • • • • • • • • Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3V/2.5V Voltage supply Wide range output clock frequency up to 250MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Max. output skew of 200pS (150pS within one bank) Selectable output configurations per output bank Tristatable outputs 32 lead LQFP & TQFP Packages Pin and Function compatible with MPC9446 Ambient operating temperature range of -40 to 85°C PCS2I99446 is specified for the extended temperature range of -40°C to 85°C. The PCS2I99446 is a full static fanout buffer design supporting clock frequencies up to 250MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The PCS2I99446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50Ω transmission lines. Please consult the PCS2I99456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the PCS2I99446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a lead LQFP and TQFP Packages. 7x7mm2 32- Functional Description The PCS2I99446 is a 2.5V and 3.3V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3V, 2.5V and dual supply voltages are supported for mixed-voltage applications. The PCS2I99446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The PCS2I99446 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 rev 0.5 Block Diagram CCLK0 CCLK1 CCLK_SEL VCC 25K 0 VCC 25K 1 CLK CLK-2 0 1 QA0 QA1 QA2 QB0 QB1 QB2 PCS2I99446 25K 0 1 QC0 FSELA FSELB FSELC MR/OE 0 25K 25K 25K 25K 1 QC1 QC2 QC3 Pin Configuration 32 – LEAD PACKAGE PINOUT -- Top View GND GND QB1 QB2 24 23 22 21 20 19 18 17 VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 QC3 GND QC2 VCCC QC1 GND QC0 VCCC PCS2I99446 VCCB VCCC 13 12 11 10 9 GND QB0 VCCB CCLK_SEL CCLK1 CCLK0 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. FSELA FSELB FSELC VCC 2 of 14 September 2006 rev 0.5 Table 1: Pin Configuration Pin Number 3,4 5,6,7 32 8,11,15,20,24,27,31 25,29 18,22 9,13,17 2 30,28, 26 23,21,19 10,12,14,16 PCS2I99446 Pin CCLK0, CCLK1 FSELA, FSELB, FSELC MR/OE GND VCCA, VCCB, VCCC VCC QA0 - QA2 QB0 - QB2 QC0 - QC3 I/O Input Input Input Type LVCMOS LVCMOS LVCMOS Supply Supply Supply Function LVCMOS clock inputs Output bank divide select input Internal reset and output (high impedance) control Negative voltage supply (GND) Positive voltage supply for output banks Positive voltage supply for core (VCC) Bank A outputs Bank B outputs Bank C outputs Output Output Output LVCMOS LVCMOS LVCMOS Note: VCCB is internally connected to VCC. Table 2: Supported Single and Dual Supply Configurations Supply voltage configuration 3.3V Mixed voltage supply 2.5V VCC1 3.3V 3.3V 2.5V VCCA2 3.3V 3.3V or 2.5V 2.5V VCCB3 3.3V 3.3V 2.5V VCCC4 3.3V 3.3V or 2.5V 2.5V VCC. GND 0V 0V 0V Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels 2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels 3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to 4 VCCC is the positive power supply of the bank B outputs. VCCC voltage defines bank C output levels. Table 3: Function Table (Controls) Control CCLK_SEL FSELA FSELB FSELC MR/OE Default 0 0 0 0 0 CCLK0 fQA0:2 = fREF FQBO:2 = fREF FQCO:3 = fREF Outputs enabled 0 CCLK1 f QA0:2 = fREF ÷2 f QBO:2 = fREF ÷2 f QCO:3 = fREF ÷2 1 Internal reset Outputs disabled (tristate) 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 3 of 14 September 2006 rev 0.5 Table 4: Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 PCS2I99446 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 ±20 ±50 125 Unit V V V mA mA °C Condition Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 5: General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch–Up Immunity Power Dissipation Capacitance Input Capacitance Min 200 2000 200 Typ VCC ÷2 Max Unit V V V mA Condition 10 4.0 pF pF Per output Table 6: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = -40°C to +85°C) Symbol VIH VIL IIN VOH VOL ZOUT ICCQ3 Characteristics Input High Voltage Input Low Voltage Input Current 1 Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current 14 - 17 2.0 2.4 0.55 0.30 Min 2.0 -0.3 Typ Max VCC + 0.3 0.8 200 Unit V V µA V V V Ω mA Condition LVCMOS LVCMOS VIN=GND or VIN=VCC IOH=-24 mA2 3 IOL= 24mA IOL= 12mA All VCC Pins transmission line to Note: 1 Input pull-up / pull-down resistors influence input current. 2 The PCS2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. 3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 4 of 14 September 2006 rev 0.5 Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C)1 Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) tsk(PP) tSK(P) DCQ tr, tf Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Output-to-output Skew Device-to-device Skew Output pulse skew4 Output Duty Cycle Output Rise/Fall Time ÷1 output ÷2 output 47 45 0.1 50 50 Within one bank Any output Bank, Same output divider Any output, Any output divider CCLK0,1 to any Q CCLK0,1 to any Q 2.2 2.2 2.8 2.8 ÷1 output ÷2 output PCS2I99446 Characteristics Min 0 0 0 1.4 Typ Max 2502 2502 125 1.03 4.45 4.2 10 10 150 200 350 2.25 200 53 55 1.0 Unit MHz MHz MHz nS nS nS nS nS nS pS pS pS nS pS % % nS Condition FSELx=0 FSELx=1 0.8 to 2.0V DCREF = 50% DCREF = 25%-75% 0.55 to 2.4V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT 2 The PCS2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. 3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4 Output pulse skew is the absolute difference of the propagation delay times | tpLH - tpHL |. Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ 3 Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum Quiescent Supply Current Min 1.7 -0.3 1.8 Typ Max VCC + 0.3 0.7 0.6 Unit V V V V Ω µA mA Condition LVCMOS LVCMOS IOH=-15 mA1 IOL= 15 mA VIN=GND or VIN=VCC All VCC Pins 17 - 20 2 ±200 2.0 Note: 1 The PCS2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output. 2 Input pull-up / pull-down resistors influence input current. 3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 5 of 14 September 2006 rev 0.5 Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)1,2 Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Within one bank tsk(O) Output-to-output Skew Any output Bank, Same output divider Any output, Any output divider CCLK0,1 to any Q CCLK0,1 to any Q 2.6 2.6 ÷1 output ÷2 output PCS2I99446 Characteristics Min 0 0 0 1.4 Typ Max 250 2502 125 1.0 4 3 Unit MHz MHz MHz nS nS nS nS nS nS pS pS pS nS pS % nS Condition FSELx=0 FSELx=1 0.7 to 1.7V 5.6 5.5 10 10 150 200 350 3.0 200 tsk(PP) tSK(P) DCQ tr, tf Device-to-device Skew Output pulse skew Output Duty Cycle Output Rise/Fall Time 5 ÷1 or ÷2 output 45 0.1 50 55 1.0 DCREF = 50% 0.6 to 1.8V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 AC specifications are design targets, final specification is pending device characterization. 3 The PCS2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. 4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = –40°C to +85°C)1,2 Symbol tsk(O) Output-to-output Skew Characteristics Within one bank Any output Bank, Same output divider Any output, Any output divider Min Typ Max 150 250 350 2.5 Unit pS pS pS nS pS % Condition tsk(PP) tPLH,HL tSK(P) DCQ Device-to-device Skew Propagation delay Output pulse skew Output Duty Cycle 3 CCLK0,1 to any Q ÷1 or ÷2 output 45 See 3.3V table 250 50 55 DCREF = 50% Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. 3 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 6 of 14 September 2006 rev 0.5 APPLICATIONS INFORMATION Driving Transmission Lines The PCS2I99446 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS2I99446 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the PCS2I99446 clock driver is effectively doubled due to its capability to drive multiple lines. PCS2I99446 OUTPUT BUFFER 14Ω Z0=50Ω 0.5 0 PCS2I99446 impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0 = 50Ω || 50Ω RS = 36Ω || 36Ω R0 = 14Ω VL = 3.0 ( 25 ÷ (18+14+25)) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). 3.0 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 RS=36Ω OutA tD = 3.8956 OutB tD = 3.9386 PCS2I99446 OUTPUT BUFFER 14Ω RS=36Ω Z0=50Ω Figure 2. SingleTIME (nS) Dual Waveforms versus RS=36Ω Z0=15Ω 2 4 6 8 10 12 14 Figure 1. Single versus Dual Transmission Lines The waveform plots in Figure 2. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCS2I99446 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCS2I99446. The output waveform in Figure 2 “Single versus Dual Line Termination Waveforms” shows a step in the waveform. This step is caused by the Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS2I99446 OUTPUT BUFFER 14Ω RS=22Ω RS=22Ω Z0=50Ω Z0=50Ω 14Ω + 22Ω║22Ω = 50Ω║50Ω 25Ω = 25Ω Figure 3. Optimized Dual Line Termination 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 7 of 14 September 2006 rev 0.5 Pulse Generator Z=50Ω Z0=50Ω PCS2I99446 Z0=50Ω PCS2I99446 RT=50Ω RT=50Ω VTT Figure 4. CCLK0, 1 PCS2I99446 AC test reference for VCC = 3.3V and VCC = 2.5V VCC CCLK VCC = 3.3V VCC = 2.5V 2.4 0.55 tF tR 1.8V 0.6V QX t(LH) t(HL) VCC ÷2 GND VCC VCC ÷2 GND Figure 5. Output Transition Time Test Reference VCC VCC ÷2 GND VOH VCC ÷2 tSK(LH) tSK(HL) GND Figure 6. Propagation Delay (tPD) Test Reference VCC CCLK VCC ÷2 GND VCC QX t(LH) t(HL) tSK(P) │tPLH- tPHL │ VCC ÷2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 7. Output–to–Output Skew tSK(LH,HL) VCC VCC ÷2 GND tP Figure 8. Propagation Delay (tSK(P)) Test Reference TJIT(CC) = |TN -TN + 1| TN TN + 1 T0 DC (tP ÷T0 Χ 100%) The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 10. Cycle–to–Cycle Jitter Figure 9. Output Duty Cycle (DC) Reference 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 8 of 14 September 2006 rev 0.5 Power Consumption of the PCS2I99446 and Thermal Management The PCS2I99446 AC specification is guaranteed for the entire operating frequency range up to 250MHz. The PCS2I99446 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS2I99446 die junction temperature and the associated device reliability. PCS2I99446 Where ICCQ is the static current consumption of the PCS2I99446, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the PCS2I99446). The PCS2I99446 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 11, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS2I99446 in a series terminated transmission line system, equation 4. Table 11. Die junction temperature and MTBF Junction temperature (°C) 100 110 MTBF (Years) 20.4 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS2I99446 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the PCS2I99446 is represented in equation 1. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 9 of 14 September 2006 rev 0.5 TJ,MAX should be selected according to the MTBF system requirements and Table 11. Rthja can be derived from Table 12. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. PCS2I99446 If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the PCS2I99446. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Table 12. Thermal package impedance of the 32LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), °C/W 86 76 71 68 66 60 Rthja (2P2S board), °C/W 61 56 54 53 52 49 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 10 of 14 September 2006 rev 0.5 Package Information 32-lead TQFP PCS2I99446 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 11 of 14 September 2006 rev 0.5 32-lead LQFP PCS2I99446 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 12 of 14 September 2006 rev 0.5 Ordering Information Part Number PCS2P99446G-32-LT PCS2P99446G-32-LR PCS2P99446G-32-ET PCS2P99446G-32-ER PCS2I99446G-32-LT PCS2I99446G-32-LR PCS2I99446G-32-ET PCS2I99446G-32-ER PCS2I99446 Marking PCS2P99446GL PCS2P99446GL PCS2P99446GE PCS2P99446GE PCS2I99446GL PCS2I99446GL PCS2I99446GE PCS2I99446GE Package Type 32-pin LQFP, Tray, Green 32-pin LQFP, Tape and Reel, Green 32-pin TQFP, Tray, Green 32-pin TQFP, Tape and Reel, Green 32-pin LQFP, Tray, Green 32-pin LQFP, Tape and Reel, Green 32-pin TQFP, Tray, Green 32-pin TQFP, Tape and Reel, Green Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Device Ordering Information PCS2I99446G-32-LT R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 13 of 14 September 2006 rev 0.5 PCS2I99446 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I99446 Document Version: 0.5 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 14 of 14