PCS2P99447G-32-LR

September 2006 rev 0.4 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Features • • • • • 9 LVCMOS Compatible Clock Outputs 2 Selectable, LVCMOS Compatible Inputs Maximum Clock Frequency of 350 MHz Maximum Clock Skew of 150 pS Synchronous Output Stop in Logic Low State Eliminates Output Runt Pulses • • • • • • High–Impedance Output Control 3.3V or 2.5V Power Supply Drives up to 18 Series Terminated Clock Lines Ambient Temperature Range -40°C to +85°C 32 Lead LQFP and TQFP Packaging Supports Clock Distribution in Networking, PCS2I99447 PCS2I99447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50Ω terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The PCS2I99447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high impedance mode. All inputs have an internal pull–up or pull–down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The Telecommunications and Computer Applications • Pin and Function Compatible to MPC947 and MPC9447 Functional Description The PCS2I99447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 pS, the device meets the needs of most demanding clock applications. PCS2I99447 is pin and function compatible but performance enhanced to the MPC947 and MPC9447. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 rev 0.4 Block Diagram PCS2I99447 Q0 CCLK0 CCLK1 0 1 CLK STOP Q1 VCC CLK_SEL Q2 Q3 SYNC Q4 Q5 VCC CLK_STOP Q5 Q6 VCC OE (All input resistors have a value of 25KΩ) Q7 GND GND Pin Configuration 24 GND Q2 VCC Q1 GND Q0 VCC GND 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 GND Q6 VCC Q7 GND Q8 VCC GND 13 12 11 10 9 8 GND VCC PCS2I99447 2 3 4 5 6 CLK_SEL 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. CLK_STOP CCLK0 CCLK1 GND VCC OE VCC 7 Q3 Q4 Q5 2 of 14 September 2006 rev 0.4 Table 1. Function Table Control CLK_SEL OE CLK_STOP PCS2I99447 Default 1 1 1 0 CLK0 input selected Outputs disabled (high–impedance state)1 Outputs synchronously stopped in logic low state 1 CLK1 input selected Outputs enabled Outputs active Note: 1. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configuration Pin # 3 4 2 5 6 11,13,15,19,21,23,26,28,30 1,8,9,12,16,17,20,24,25,29,32 7,10,14,18,22,27,31 Pin Name CCLK0 CCLK1 CLK_SEL CLK_STOP OE Q0 – Q8 GND VCC I/O Input Input Input Input Input Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Function Clock signal input Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high–impedance tristate) Clock outputs Negative power supply (GND) for Output and Core Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance Min 200 2000 200 Typ VCC ÷2 Max Unit V V V mA Condition 10 4.0 pF pF Per output Inputs Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 ±20 ±50 125 Unit V V V mA mA °C Condition -65 Note: 1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 3 of 14 September 2006 rev 0.4 Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ PCS2I99447 Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum Quiescent Supply Current3 Min 2.0 -0.3 2.4 Typ Max VCC + 0.3 0.8 0.55 0.30 Unit V V V V V W mA mA Condition LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA VIN = VCC or GND All VCC Pins 17 ±300 2.0 Note: 1. The PCS2I99447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V). 2. Inputs have pull-down or pull-up resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1 Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) 5Characteristics Input Frequency Output Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time CCLK0 or CCLK1 to CLK_STOP 3 3 Min 0 0 1.4 Typ Max 350 350 1.0 2 Unit MHz MHz nS nS nS nS nS nS nS Condition 0.8 to 2.0V CCLK0 or CCLK1 to any Q 1.3 3.3 11 11 0.0 1.0 150 2.0 300 55 1.0 TBD Hold Time CCLK0 or CCLK1 to CLK_STOP Output-to-Output Skew Device-to-Device Skew 4 Output Pulse Skew Output Duty Cycle MHz Output Rise/Fall Time Cycle-to-cycle jitter pS nS pS % nS pS DCREF = 50% 0.55 to 2.4V fQ