PCS5I9352G-32-ET

September 2006 PCS5I9352 rev 0.3 2.5V or 3.3V, 200MHz, 11 Output Zero Delay Buffer Features • • • • • • • • • • • • • • Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ± 2% max Output duty cycle variation 11 Clock outputs: Drive up to 22 clock lines LVCMOS reference clock input 125-pS max output-output skew PLL bypass mode Spread AwareTM Output enable/disable Pin compatible with MPC9352 and MPC952 Industrial temperature range: -40°C to +85°C 32-Pin 1.0mm TQFP & LQFP Packages The PLL is ensured stable given that the VCO is configured to run between 200MHz to 500MHz. This allows a wide range of output frequencies from 16.67MHz to 200MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. The PCS5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:22. Functional Description The PCS5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 PCS5I9352 rev 0.3 Block Diagram PLL_EN# REFCLK FB_IN VCO_SEL SELA Phase Detector VCO 200-500MHz ÷2 ÷4/ ÷6 QA0 QA1 QA2 QA3 QA4 LPF ÷4/ ÷2 QB0 QB1 QB2 QB3 SELB ÷2/ ÷4 SELC MR/OE# QC0 QC1 Pin Configuration VDDQC VSS QB3 VDDQB 24 23 22 QC1 QC0 VSS QB2 32 31 30 29 28 27 26 25 VCO_SEL SELC SELB SELA MR/OE# REFCLK AVSS FB_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS QB1 QB0 VDDQB VDDQA QA4 QA3 VSS PCS5I9352 21 20 19 18 17 PLL_EN# 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. VDDQA AVDD VDD VSS QA0 QA1 QA2 2 of 12 September 2006 PCS5I9352 rev 0.3 Pin Configuration1 Pin 6 12, 14, 15, 18, 19 22, 23, 26, 27 30, 31 8 1 5 9 2, 3, 4 16, 20 21, 25 32 10 11 7 13, 17, 24, 28, 29 Name REFCLK QA(0:4) QB(0:3) QC(0,1) FB_IN VCO_SEL MR/OE# PLL_EN# SEL(A:C) VDDQA VDDQB VDDQC AVDD VDD AVSS VSS I/O I, PD O O O I, PD I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Reference clock input. Clock output bank A. Clock output bank B. Clock output bank C. Description Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. VCO divider select input. See Table 2. Master reset/output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Frequency select input, Bank (A:C). See Table 2. 2.5V or 3.3V power supply for bank A output clocks2,3. 2.5V or 3.3V power supply for bank B output clocks.2,3 2.5V or 3.3V power supply for bank C output clocks. 2,3 2.5V or 3.3V power supply for PLL. 2,3 2.5V or 3.3V power supply for core and inputs. 2,3 Analog ground. Common ground. Note: 1. PD = Internal pull-down. 2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100MHz 0.6V to 1.8V TCLK to FB_IN, same VDD, does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency MHz DC tr, tf t (φ ) tsk(O) tsk(B) tPLZ, HZ tPZL, ZH Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time % nS pS pS pS 225 8 10 nS nS ÷2 Feedback ÷4 Feedback BW PLL Closed Loop Bandwidth (-3dB) ÷6 Feedback ÷8 Feedback ÷12 Feedback tJIT(CC) tJIT(PER) tJIT(φ) tLOCK Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300MHz VCO > 300MHz 2 1 - 1.5 0.6 0.75 0.5 100 300 100 150 150 100 1 pS pS pS mS MHz Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. . 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 12 September 2006 PCS5I9352 rev 0.3 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO Description VCO Frequency Condition ÷2 Feedback ÷4 Feedback ÷6 Feedback Min 200 100 50 33.33 25 16.67 0 25 Typ Max 500 200 125 83.33 62.5 41.67 200 75 1.0 200 125 83.33 62.5 41.67 52 56 1.0 200 125 175 235 425 8 10 Unit MHz fin Input Frequency ÷8 Feedback ÷12 Feedback Bypass mode (PLL_EN# = 1) MHz frefDC tr, tf Input Duty Cycle TCLK Input Rise/FallTime 0.8V to 2.0V ÷2 Output ÷4 Output % nS 100 50 33.33 25 16.67 48 44 0.1 -100 fMAX Maximum Output Frequency ÷6 Output ÷8 Output ÷12 Output fMAX< 100MHz fMAX > 100MHz 0.55V to 2.4V TCLK to FB_IN, same VDD, does not include jitter Skew within each Bank Banks at same voltage, same frequency MHz DC tr, tf t (φ ) tsk(O) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew % nS pS pS tsk(B) Bank-to-Bank Skew Banks at same voltage, different frequency Banks at different voltage pS tPLZ, HZ tPZL, ZH Output Disable Time Output Enable Time ÷2 Feedback ÷4 Feedback 2 1 - 1.5 0.6 0.75 0.5 nS nS BW PLL Closed Loop Bandwidth (-3dB) ÷6 Feedback ÷8 Feedback ÷12 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300MHz VCO > 300MHz MHz tJIT(CC) tJIT(PER) tJIT(φ) tLOCK Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time 100 275 100 150 150 100 1 pS pS pS mS Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. . 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 12 September 2006 PCS5I9352 rev 0.3 Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset VDD LVCMOS_CLK VDD/2 tP T0 GND DC = tP / T0 x 100% Figure 3. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 4. Output-to-Output Skew , tsk(O) 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 12 September 2006 PCS5I9352 rev 0.3 Package Diagram 32-lead TQFP Package SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 12 September 2006 PCS5I9352 rev 0.3 32-lead LQFP Package SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 12 September 2006 PCS5I9352 rev 0.3 Ordering Information Part Number PCS5I9352G-32-ET PCS5I9352G-32-LT Marking PCS5I9352G PCS5I9352G Package Type 32-pin TQFP, Green 32-pin LQFP –Tape and Reel, Green Temperature Industrial Industrial Device Ordering Information PCS 5I9352 G-32-LT R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 12 September 2006 PCS5I9352 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9352 Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 12