PCS5I961P

November 2006 rev 0.3 Low Voltage Zero Delay Buffer Features • • • • • • • • Fully Integrated PLL Up to 200MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance LVPECL Reference Clock Options LQFP Packaging ±50pS Cycle–Cycle Jitter 150pS Output Skews PCS5I961P reference clock while the PCS5I961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The PCS5I961P is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50Ω transmission lines. For series terminated lines the PCS5I961P can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance. Functional Description The PCS5I961P is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150pS the device meets the needs of the most demanding clock tree applications. The PCS5I961P is offered with two different input configurations. The PCS5I961P offers an LVCMOS Block Diagram VCC PCLK PCLK 50K Ref PLL 0 1 Q0 Q1 Q2 Q3 50K 50K FB 50K 100-200 MHz 50-100 MHz FB_IN F_RANGE 50K Q14 Q15 Q16 OE 50K QFB Figure 1. PCS5I961P Logic Diagram PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 0.3 Pin Configuration GND VCC Q10 Q11 Q6 Q7 Q8 Q9 PCS5I961P 24 23 22 21 20 19 18 17 Q5 Q4 Q3 GND Q2 Q1 Q0 VCC 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 QFB PPCS5I961C CS5I961P 13 12 11 10 9 FB_IN GND F_RANGE PCLK PCLK Figure 2. PCS5I961P 32-Lead Package Pinout (Top View) Table 1: Pin Configuration Pin # 2,3 7 4 6 31,30,29,27,26,25,23,22,21 ,19,18,17,15,14,13,11,10 9 1,12,20,28 Pin Name PCLK, ¯¯¯¯¯ PCLK FB_IN F_RANGE ¯¯ OE Q0 - Q16 QFB GND I/O Input Input Input Input Output Output Supply VCCA Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power VCC OE Function PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Output enable/disable Clock outputs PLL feedback signal output, connect to a FB_IN Negative power supply PLL positive power supply (analog power supply). The PCS5I961P requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core 5 VCCA Supply Power 8,16,24,32 VCC Supply Power Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 14 November 2006 rev 0.3 Table 2: Function Table Control F_RANGE ¯¯ OE PCS5I961P Default 0 0 0 PLL high frequency range. PCS5I961P input reference and output clock frequency range is 100 – 200 MHz Outputs enabled 1 PLL low frequency range. PCS5I961P input reference and output clock frequency range is 50 – 100 MHz Outputs disabled (high–impedance state) Table 3: Absolute Maximum Ratings Symbol Parameter VCC VIN VOUT IIN IOUT TS TDV Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Range Static Discharge Voltage (As per JEDEC STD 22- A114-B) Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 ±20 ±50 125 2 Unit V V V mA mA °C KV -40 Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 4: DC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristic Input HIGH Voltage Input LOW Voltage Peak–to–peak input voltage1 PECL_CLK, ¯¯¯¯¯¯¯¯¯¯ PECL_CLK Common Mode Range1 PECL_CLK, ¯¯¯¯¯¯¯¯¯¯ PECL_CLK Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage Min 2.0 -0.3 500 1.2 2.4 Typ Max VCC + 0.3 0.8 1000 VCC - 0.8 0.55 Unit V V mV V V V Ω mA pF pF mA mA V Condition LVCMOS LVCMOS LVPECL LVPECL IOH = –20mA2 IOL = 20mA2 14 4.0 8.0 2.0 VCC÷2 20 ±120 10 5.0 Per Output VCCA Pin All VCC Pins Notes: 1. Exceeding the specified VCMR/VPP window results in a tPD changes of approx. 250pS. 2. The PCS5I961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 14 November 2006 rev 0.3 Table 5: AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1 Symbol fref fmax frefDC t(φ) tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT(φ) tlock PCS5I961P Characteristic Input Frequency Maximum Output Frequency 2 Min 100 50 100 50 25 -50 Typ Max 200 100 200 100 75 225 Unit MHz MHz % pS pS % nS nS nS pS pS nS mS Condition F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Reference Input Duty Cycle PECL_CLK to Propagation Delay FB_IN (static phase offset) 3 Output to Output Skew F_RANGE = 0 Output Duty Cycle F_RANGE = 1 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle to Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time RMS (1σ) 4 PLL locked 90 42 45 0.1 50 50 150 55 55 1.0 10 10 15 0.55 to 2.4V RMS (1σ) RMS (1σ) F_RANGE = 0 F_RANGE = 1 7.0 10 0.0015 ⋅ T 0.0010 ⋅ T 10 T = Clock Signal Period Notes: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. tPD applies for VCMR = VCC–1.3V and VPP = 800mV 3. See applications section for part to part skew calculation 4. See applications section for calculation for other confidence factors than 1σ Table 6: DC Characteristics (VCC = 2.5V ± 5%, TA = -40° to 85°C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristic Input HIGH Voltage Input LOW Voltage Peak–to–peak input voltage1 PECL_CLK, ¯¯¯¯¯¯¯¯¯¯ PECL_CLK Common Mode Range1 PECL_CLK, ¯¯¯¯¯¯¯¯¯¯ PECL_CLK Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage Min 1.7 -0.3 500 1.2 1.8 Typ Max VCC + 0.3 0.7 1000 VCC - 0.7 0.6 Unit V V mV V V V Ω mA pF pF mA mA V Condition LVCMOS LVCMOS LVPECL LVPECL IOH = –15mA2 IOL = 15mA2 18 4.0 8.0 2.0 VCC÷2 26 ±120 10 5.0 Per Output VCCA Pin All VCC Pins Notes: 1. Exceeding the specified VCMR/VPP window results in a tPD changes of < 250 pS. 2. The PCS5I961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 14 November 2006 rev 0.3 Table 7: AC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C)1 Symbol fref fmax frefDC t(φ) tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT(φ) tlock PCS5I961P Characteristic Input Frequency Maximum Output Frequency 2 Min 100 50 100 50 25 -50 Typ Max 200 100 200 100 75 175 Unit MHz MHz % pS pS % nS nS nS pS pS nS mS Condition F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Reference Input Duty Cycle PECL_CLK to Propagation Delay FB_IN (static phase offset) 3 Output–to–Output Skew F_RANGE = 0 Output Duty Cycle F_RANGE = 1 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle–to–Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time RMS (1σ)4 RMS (1σ) RMS (1σ) F_RANGE = 0 F_RANGE = 1 PLL locked 90 40 45 0.1 50 50 150 60 55 1.0 10 10 15 0.6 to 1.8V 7.0 10 0.0015 ⋅ T 0.0010 ⋅ T 10 T = Clock Signal Period Notes: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. tPD applies for VCMR = VCC–1.3V and VPP = 800mV 3. See applications section for part–to–part skew calculation 4. See applications section for calculation for other confidence factors than 1σ Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 14 November 2006 rev 0.3 APPLICATIONS INFORMATION Power Supply Filtering The PCS5I961P is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The PCS5I961P provides separate power supplies for the output buffers (VCC) and the phase–locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is power supply filter on the VCCA pin for the PCS5I961P. Figure 3. illustrates a typical power supply filter scheme. The PCS5I961P is most susceptible to noise with spectral content in the 10KHz to 5MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the PCS5I961P. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2mA (5mA maximum), assuming that a minimum of 2.375V (VCC =3.3V or VCC = 2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3. must have a resistance of 270 (VCC = 3.3V) or 5 to 15 (VCC = 2.5V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. RF = 270Ω for VCC = 3.3V RF = 5-15Ω for VCC = 2.5V RF 22 µF 10 nF PCS5I961P Although the PCS5I961P has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The PCS5I961P clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point to point distribution of signals is the method of choice. In a point to point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS5I961P clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4. illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the PCS5I961P clock driver is effectively doubled due to its capability to drive multiple lines. PCS5I961P OUTPUT BUFFER IN 14Ω RS=36Ω Z0=50Ω OUTA PCS5I961P OUTPUT BUFFER IN 14Ω RS=36Ω Z0=50Ω OUTB0 VCC VCCA RS=36Ω Z0=50Ω OUTB1 PCS5I961P VCC 33…100 nF Figure 3. Power Supply Filter Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5. show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the PCS5I961P output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 14 November 2006 rev 0.3 the PCS5I961P. The output waveform in Figure 5. shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50Ω || 50Ω Rs = 36Ω || 36Ω Ro = 14Ω VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). 3.0 OutA tD = 3.8956 OutB tD = 3.9386 PCS5I961P Using the PCS5I961P in zero-delay applications Nested clock trees are typical applications for the PCS5I961P. Designs using the PCS5I961P, as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the PCS5I961P clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew The PCS5I961P zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more PCS5I961P are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t(φ) + tSK(O) + tPD, LINE(FB) + tJIT(φ) ⋅ CF 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 10 12 14 This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: PCLKCommon -t(Ø) QFBDevice 1 tJIT(Ø) Any QDevice 1 +tSK(O) +t(Ø QFBDevice 2 tJIT(Ø) RS=22Ω Z0=50Ω TIME (nS) tPD,LINE (FB) Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS5I961P OUTPUT BUFFER IN 14Ω RS=22Ω Z0=50Ω Any QDevice 2 +tSK(O) tSK(PP) 14Ω + 22Ω || 22Ω = 50Ω || 50Ω 25Ω = 25Ω Figure 6. Optimized Dual Line Termination Max. skew Figure 7. PCS5I961P max. device-to-device skew Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 14 November 2006 rev 0.3 Due to the statistical nature of I/O jitter a rms value (1σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8: Confidence Factor CF CF ± 1σ ± 2σ ± 3σ ± 4σ ± 5σ ± 6σ Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 PCS5I961P The PCS5I961P AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The PCS5I961P power consumption and the associated longterm reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS5I961P die junction temperature and the associated device reliability. Table 9: Die junction temperature and MTBF Junction temperature (°C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3 σ) is assumed, resulting in a worst case timing uncertainty from input to any output of -236pS to 361pS relative to PCLK (f=125 MHz, VCC=2.5V): tSK(PP) = [–50ps...175ps] + [–150ps...150ps] + [(12ps* –3)...(12ps *3)] + tPD, LINE(FB) tSK(PP) = [–236ps...361ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 8. “Max. I/O Jitter versus frequency” can be used for a more precise timing performance analysis. 18 tjit(Ø)[ps] RMS 16 14 12 10 8 6 4 2 0 50 70 90 110 130 170 190 150 Clock frequency [MHz] VCC=3.3V VCC=2.5V VCC=3.3V VCC=2.5V F_RANGE=1 F_RANGE=0 TA = 85°C Figure 8. Max. I/O Jitter versus frequency Power Consumption of the PCS5I961P and Thermal Management Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS5I961P needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the PCS5I961P is represented in equation 1. Where ICCQ is the static current consumption of the PCS5I961P, CPD is the power dissipation capacitance per output, (M)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the PCS5I961P). The PCS5I961P supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 14 November 2006 rev 0.3 PCS5I961P    PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅ VCC Equation 1 M       PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL Equation 2 M   P  TJ = T A + PTOT ⋅ Rthja Equation 3 [ ] f CLOCKMAX = C PD 1 2 ⋅ N ⋅ VCC  T − TA ⋅  JMAX − (I CCQ ⋅ VCC )   Rthja   Equation 4 Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS5I961P in a series terminated transmission line system. Table 10: Thermal package impedance of the 32LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), K/W 80 70 61 57 56 55 boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200 MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the PCS5I961P. The charts were calculated for a maximum tolerable die junction temperature of 110°C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120°C. TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 14 November 2006 rev 0.3 200 Operating frequency (MHz) 190 160 140 120 100 80 60 40 20 0 500 400 200 300 Convection Ifpm 100 0 TA = 85°C fMAX (AC) Operating frequency (MHz) 200 190 160 140 120 100 80 60 40 20 0 500 400 200 300 Convection Ifpm TA = 85°C fMAX (AC) PCS5I961P TA = 75°C Safe operation Safe operation 100 0 Figure 9. Maximum PCS5I961P frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines Figure 10. Maximum PCS5I961P frequency, VCC = 3.3V, MTBF 9.1 years, 4pF load per line Differential Pulse Generator Z=50Ω Z0=50Ω Z0=50Ω RT=50Ω RT=50Ω VTT VTT Figure 11. TCLK PCS5I961P AC test reference for VCC = 3.3V and VCC = 2.5V Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 14 November 2006 rev 0.3 PCLK PCLK VCC VCC ÷2 Ext_FB t(Ø) GND tF VPP VCMR PCS5I961P VCC = 3.3V 2.4 0.55 tR VCC = 2.5V 1.8V 0.6V Figure 12. Propagation Delay (t(Ø)). Static phase offset test reference VCC VCC ÷2 GND Figure 13. Output Transition Time Test Reference VCC VCC ÷2 GND VCC tP tSK(O) T0 DC= (tP ÷T0 Χ 100%) VCC ÷2 GND The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 15. Output–to–Output Skew tSK(O) Figure 14. Output Duty Cycle (DC) T0 TN TN-1 TJIT(CC) =│TN-TN-1 mean│ TJIT(PER) =│TN-1/f0│ The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-cycle Jitter PCLK PCLK Figure 17. Period Jitter Ext_FB TJIT(Ø) =│T0-T1 mean│ The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 18.I/O Jitter Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 14 November 2006 rev 0.3 Package Information 32-lead LQFP PCS5I961P SECTION A-A Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Dimensions Inches Millimeters Min Max Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 14 November 2006 rev 0.3 Ordering Information Part Number PCS5I961PG-32LR PCS5I961PG-32LR PCS5I961P Marking PCS5I961PG PCS5I961PG Package Type 32 pin LQFP, Green 32 pin LQFP – Tape and Reel, Green Temperature Industrial Industrial Device Ordering Information PCS 5I961P G-32-LR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 14 November 2006 rev 0.3 PCS5I961P PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I961P Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 14