PCS5I9773G-52-ET

September 2006 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features • • • • • • • • Output frequency range: 8.33MHz to 200MHz Input frequency range: 6.25MHz to 125MHz 2.5V or 3.3V operation Split 2.5V / 3.3V outputs ±2%( max ) Output duty cycle variation 12 Clock outputs: drive up to 24 clock lines One feedback output Three reference clock inputs: LVPECL or LVCMOS • • • • • 300pS ( max ) output-output skew Phase-locked loop (PLL) bypass mode ‘SpreadTrak’ Output enable/disable Pin-compatible with CY29773, MPC9773 and MPC973 • • • Industrial temperature range: -40°C to +85°C 52pin 1.0mm TQFP package RoHS Compliance PCS5I9773 The ASM5I9773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24. The PLL is ensured stable, given that the VCO is configured to run between 200MHz to 500MHz. This allows a wide range of output frequencies, from 8MHz to 200MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Table 1. Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification Functional Description The ASM5I9773 is a low-voltage high-performance does not apply. 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 rev 0. 4 Block Diagram PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL 0 TCLK0 TCLK1 TCLK_SEL FB_IN 0 1 LPF D Q Sync Frz Phase Detector VCO 1 D Q Sync Frz PCS5I9773 QA0 QA1 QA2 QA3 FB_SEL2 QB0 QB1 QB2 QB3 MR#/OE Power-On Reset /4,/6,/8,/12 /4,/6,/8,/10 SELA(0,1) SELB(0,1) SELC(0,1) 2 2 2 /2,/4,/6,/8 0 /4,/6,/8,/10 /2 Sync Pulse FB_SEL(0,1) SCLK SDATA Output Disable Circuitry 2 Data Generator D 12 Q Sync Frz SYNC 1 D Q D Q Sync Frz QC2 QC3 FB_OUT D Q Sync Frz QC0 QC1 Sync Frz INV_CLK VCO_SEL Pin Configuration VDDQA VDDQA SELA0 SELA1 QA0 VSS VSS QA1 AVSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 QA2 QA3 SELB0 SELB1 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDQB QB1 VSS QB2 VDDQB QB3 FB_IN VSS FB_OUT VDD FB_SEL0 PCS5I9773 14 15 16 17 18 19 20 21 22 23 24 25 26 VDDQC SYNC 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. INV_CLK FB_SEL1 VDDQC SELC1 QC2 SELC0 QC1 QC3 QC0 VSS VSS 2 of 16 September 2006 rev 0. 4 Pin 11 12 9 10 44,46,48,50 32,34,36,38 16,18,21,23 29 31 25 6 2 8 7 52 14 5,26,27 42,43 40,41 19,20 3 4 45,49 33,37 22,17 13 28 1 15,24,30,35, 39,47,51 PCS5I9773 Pin Configuration1 Name PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT FB_IN SYNC PLL_EN MR#/OE TCLK_SEL REF_SEL VCO_SEL INV_CLK FB_SEL(2:0) SELA(1,0) SELB(1,0) SELC(1,0) SCLK SDATA VDDQA VDDQB VDDQC AVDD VDD AVSS VSS I/O I, PU I I, PU I, PU O O O O I, PU O I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU Supply Supply Supply Supply Supply Supply Supply Type LVPECL LVPECL LVCMOS Description LVPECL reference clock input. LVPECL reference clock input. LVCMOS/LVTTL reference clock input. LVCMOS LVCMOS/LVTTL reference clock input. LVCMOS Clock output bank A. LVCMOS Clock output bank B. LVCMOS Clock output bank C. LVCMOS Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This LVCMOS input should be at the same voltage rail as input reference clock. See Table 1. Frequency Table. Synchronous pulse output. This output is used for system LVCMOS synchronization. PLL enable/bypass input. When Low, PLL is disabled/bypassed and LVCMOS the input clock connects to the output dividers. Master reset and Output enable/disable input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS Clock reference select input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS/LVPECL Reference select input. LVCMOS See Table 2. Function Table (Configuration Controls). VCO Operating frequency select input. LVCMOS See Table 2. Function Table (Configuration Controls). QC(2,3) Phase selection input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS Feedback divider select input. See Table 6. Frequency select input, Bank A. LVCMOS See Table 3. Function Table (Bank A). Frequency select input, Bank B. LVCMOS See Table 4. Function Table (Bank B). Frequency select input, Bank C. LVCMOS See Table 5. Function Table (Bank C). LVCMOS Serial clock input. LVCMOS Serial data input. VDD VDD VDD VDD VDD Ground Ground 2.5V or 3.3V Power supply for bank A output clocks2,3. 2.5V or 3.3V Power supply for bank B output clocks2,3. 2.5V or 3.3V Power supply for bank C output clocks2,3. 2.5V or 3.3V Power supply for PLL2,3. 2.5V or 3.3V Power supply for core and inputs2,3. Analog Ground. Common Ground. Notes: 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN MHz % nS pS 52.5 55 1.0 125 125 Notes: 7. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 16 September 2006 rev 0. 4 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = – 40°C to + 85°C)9 Parameter Description Condition tsk(O) tsk(B) tPLZ, HZ tPZL, ZH Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback Same frequency (125MHz) RMS (1σ) Same frequency Multiple frequencies Same frequency (125MHz) RMS (1σ) Same frequency Multiple frequencies 1.3 - 2.0 0.7 - 1.3 0.9 - 1.3 0.6 - 1.1 0.6 - 0.9 0.4 - 0.6 0.6 - 0.9 7 Skew within Bank A Skew within Bank B Skew within Bank C PCS5I9773 Min Typ Max 75 100 150 400 10 10 Unit pS pS nS nS BW PLL Closed Loop Bandwidth (-3dB) MHz 30 150 435 pS tJIT(CC) Cycle-to-Cycle Jitter 6 45 30 75 235 150 1 pS pS mS tJIT(PER) tJIT(φ) tLOCK Period Jitter I/O Phase Jitter Maximum PLL Lock Time AC Electrical Specifications (VDD = 3.3V ± 5%, TA = – 40°C to + 85°C)9 Parameter Description Condition fVCO VCO Frequency ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback ÷24 Feedback ÷32 Feedback ÷40 Feedback Bypass mode (PLL_EN = 0) LVPECL LVPECL 0.8V to 2.0V Min 200 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 500 1.2 Typ Max 500 125 83.3 62.5 50 41.6 31.25 25 20.8 15.625 12.5 200 75 1000 VDD–0.9 1.0 Unit MHz fin Input Frequency MHz frefDC VPP VCMR tr, tf Input Duty Cycle Peak-Peak Input Voltage Common Mode Range8 TCLK Input Rise/FallTime % mV V nS Notes: 9. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 16 September 2006 rev 0. 4 AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)10 Parameter Description Condition ÷2 Output ÷4 Output ÷6 Output ÷8 Output fMAX Maximum Output Frequency ÷10 Output ÷12 Output ÷16 Output ÷20 Output ÷24 Output fSCLK DC tr, tf t(φ) Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) fMAX < 100MHz fMAX > 100MHz 0.55V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Skew within Bank A Skew within Bank B Skew within Bank C tsk(B) tPLZ, HZ tPZL, ZH Bank-to-Bank Skew Output Disable Time Output Enable Time ÷4 Feedback ÷6 Feedback ÷8 Feedback BW PLL Closed Loop Bandwidth (–3 dB) ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback Same frequency (125MHz) RMS (1σ) Same frequency Multiple frequencies Same frequency (125MHz) RMS (1σ) Same frequency Multiple frequencies tJIT(φ) tLOCK I/O Phase Jitter Maximum PLL Lock Time I/O same VDD 6 45 1.3–2.0 0.7–1.3 0.9–1.3 0.6–1.1 0.6–0.9 0.4–0.6 0.6–0.9 7 PCS5I9773 Min 100 50 33.3 25 20 16.6 12.5 10 8.3 48 45 0.1 -125 -125 Typ Max 200 125 83.3 62.5 50 41.6 31.25 25 20.8 20 52 55 1.0 125 Unit MHz MHz MHz % nS pS 125 75 100 150 325 8 8 pS nS nS pS tsk(O) Output-to-Output Skew MHz 30 100 375 30 75 225 150 1 pS mS pS pS tJIT(CC) Cycle-to-Cycle Jitter tJIT(PER) Period Jitter Notes: 10. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 16 September 2006 rev 0. 4 SYNC Output In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The PCS5I9773 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement PCS5I9773 of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 16 September 2006 rev 0. 4 PCS5I9773 Power Management clocks. The QC0 and FB_OUT outputs can not be frozen The individual output enable/freeze control of the PCS5I9773 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output with the serial port, this avoids any potential lock up situation, should an error occur in the loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 16 September 2006 rev 0. 4 freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 PCS5I9773 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 16 September 2006 rev 0. 4 PCS5I9773 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 16 September 2006 rev 0. 4 Package Information 52-lead TQFP Package PCS5I9773 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.4646 0.3898 0.4646 0.3898 0.0177 0.0035 0.0038 0.0102 0.0106 0.0031 0° 0.0472 0.0059 0.0413 0.4803 0.3976 0.4803 0.3976 0.0295 0.0079 0.0062 0.0150 0.0130 0.0079 7° Millimeters Min Max … 0.05 0.95 11.8 9.9 11.8 9.9 0.45 0.09 0.097 0.26 0.27 0.08 0° 1.2 0.15 1.05 12.2 10.1 12.2 10.1 0.75 0.2 0.157 0.38 0.33 0.2 7° 0.03937 REF 1.00 REF 0.0256 BASE 0.65 BASE 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 16 September 2006 rev 0. 4 Ordering Information Part Number PCS5P9773G-52-ET PCS5P9773G-52-ER PCS5I9773G-52-ET PCS5I9773G-52-ER PCS5I9773 Marking PCS5P9773G PCS5P9773G PCS5I9773G PCS5I9773G Package Type 52-pin TQFP, Tray, Green 52-pin TQFP – Tape and Reel, Green 52-pin TQFP, Tray, Green 52-pin TQFP – Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Device Ordering Information PCS5I9773G-52-ET R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PULSECORE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 16 September 2006 rev 0. 4 PCS5I9773 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9773 Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use 2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 16 of 16