PCS5P23Z09CG-16-SR

May 2007 rev 0.3 PCS5P23Z05C PCS5P23Z09C Multiple Output Timing-Safe™ Peak EMI reduction IC General Features • • • • • • • • • • the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The PCS5P23Z09C has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple PCS5P23Z05C/09C devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. All outputs have less than 200pS of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than ±350pS, and the output to output skew is guaranteed to be less than 250pS. Refer “Spread Spectrum Control and Input-Output Skew Table” for deviations and Input-Output Skew for PCS5P23Z05C and PCS5P23Z09C devices. The PCS5P23Z05C/09C is available in two different package configurations, as shown in the ordering information table. Input frequency range:50MHz to 100MHz Clock distribution with Timing-Safe™ Peak EMI Reduction Zero input - output propagation delay Multiple low-skew outputs Output-output skew less than 250pS Device-device skew less than 700pS One input drives 9 outputs, grouped as 4 + 4 + 1(PCS5P23Z09C) One input drives 5 outputs (PCS5P23Z05C) Less than 200 pS cycle-to-cycle jitter Available in 16pin 150-mil SOIC, 4.4 mm TSSOP (PCS5P23Z09C), and in 8pin 150-mil SOIC, 4.4mm TSSOP package (PCS5P23Z05C) • • • • 3.3V operation Commercial temperature range Advanced 0.35µ CMOS technology The First True Drop-in Solution Functional Description PCS5P23Z05C/09C is a versatile, 3.3V zero-delay buffer designed to distribute high-speed Timing-Safe™ clocks with Peak EMI reduction. PCS5P23Z09C accepts one reference input and drives out nine low-skew clocks. It is available in a 16-pin package. The PCS5P23Z05C is the eight-pin version of the PCS5P23Z09C. It accepts one reference input and drives out five low-skew clocks. All parts have on-chip PLLs that lock to an input clock on Block Diagram PLL REF PLL CLKOUT CLK1 CLKA3 CLK2 CLK3 CLKA4 S2 CLK4 S1 Select Input Decoding CLKB1 CLKB2 CLKB3 REF MUX CLKOUT CLKA1 CLKA2 PCS5P23Z05C PCS5P23Z09C CLKB4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. May 2007 rev 0.3 Select Input Decoding for PCS5P23Z09C S2 0 0 1 1 PCS5P23Z05C PCS5P23Z09C S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven Driven Clock B1 - B4 Three-state Three-state Driven Driven CLKOUT1 Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shut-Down N N Y N Notes: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay. Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 2 of 14 May 2007 rev 0.1 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. Analysis shows that a square wave is composed of fundamental frequency and harmonics. The fundamental frequency and harmonics generate the energy peaks that become the source of EMI. Regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. In fact, the peak level allowed decreases as the frequency increases. The standard methods of PCS5P23Z05C PCS5P23Z09C reducing EMI are to use shielding, filtering, multi-layer PCBs etc. These methods are expensive. Spread spectrum clocking reduces the peak energy by reducing the Q factor of the clock. This is done by slowly modulating the clock frequency. The PCS5P23Z05C/09C uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. With center modulation, the average frequency is same as the unmodulated frequency and there is no performance degradation Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Pin Configuration REF 1 8 7 CLKOUT CLK4 VDD CLK3 CLK1 2 PCS5P23Z05C CLK2 GND 3 4 6 5 REF 1 CLKA1 CLKA2 VDD GND 2 3 4 5 16 CLKOUT 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 PCS5P23Z09C CLKB1 6 CLKB2 7 S2 8 S1 Zero Cycle Slip Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 14 May 2007 rev 0.3 Pin Description for PCS5P23Z05C Pin # 1 2 3 4 5 6 7 8 PCS5P23Z05C PCS5P23Z09C Pin Name REF CLK1 CLK2 CLK3 VDD CLK4 1 1,2 1 1 Description Input reference frequency, 5V-tolerant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin GND 1 CLKOUT Notes: 1. Weak pull-down on these outputs 2. This output is driven and has an internal feedback for the PLL 3. Buffered clock outputs are Timing-Safe™ Pin Description for PCS5P23Z09C Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF CLKA11 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 2 2 1 1 1 1 1 Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply CLKB3 CLKB4 GND VDD CLKA3 CLKA4 1 1 1,3 Buffered clock output, bank A Buffered clock output, bank A Buffered output, internal feedback on this pin CLKOUT Notes: 1. Weak pull-down on these outputs 2. Weak pull-up on these inputs 3. This output is driven and has an internal feedback for the PLL. 4. Buffered clock outputs are Timing-Safe™ Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 4 of 14 May 2007 rev 0.3 Spread Spectrum Control and Input-Output Skew Table (Note: The values given in the table are for an input frequency of 75MHz) PCS5P23Z05C PCS5P23Z09C Device PCS5P23Z05C PCS5P23Z09C Deviation ±0.5 % ±0.5 % Input-Output Skew(±TSKEW) 0.125 0.125 Note: TSKEW is measured in units of the Clock Period Absolute Maximum Ratings Symbol VDD TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Parameter Voltage on any pin with respect to Ground Rating -0.5 to +4.6 -65 to +125 260 150 2 Unit V °C °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions for PCS5P23Z05C and PCS5P23Z09C Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Description Min 3.0 0 Max 3.6 70 30 7 Unit V °C pF pF Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 5 of 14 May 2007 rev 0.3 Electrical Characteristics for PCS5P23Z05C and PCS5P23Z09C Parameter VIL VIH IIL IIH VOL VOH IDD Zo PCS5P23Z05C PCS5P23Z09C Description Input LOW Voltage1 Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Supply Current Output Impedance 2 2 1 Test Conditions Min 2.0 Typ Max 0.8 Unit V V µA µA V V mA Ω VIN = 0V VIN = VDD IOL = 8mA IOH = -8mA Unloaded outputs at 66.67MHz 23 2.4 50 100 0.4 34 Output HIGH Voltage Notes: 1. REF input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics for PCS5P23Z05C and PCS5P23Z09C Parameter 1/t1 t3 t4 t5 t6 t7 tJ tLOCK Description Output Frequency 2 Test Conditions 30pF load Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V 2 Min 50 40 Typ 50 Max 100 60 2.50 2.50 250 Unit MHz % nS nS pS pS pS pS mS Duty Cycle = (t2 / t1) * 100 Measured at 1.4V, FOUT = 66.67MHz Output Rise Time Output Fall Time 1,2 1,2 Output-to-output skew CLKOUT Rising Edge All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the CLKOUT pins of the device Measured at 66.67MHz, loaded outputs Stable power supply, valid clock presented on REF pin 0 0 Delay, REF Rising Edge to 2 ±350 700 200 1.0 Device-to-Device Skew 2 Cycle-to-cycle jitter 2 PLL Lock Time 2 Notes: 1. All parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 6 of 14 May 2007 rev 0.3 Switching Waveforms Duty Cycle Timing t1 t 2 PCS5P23Z05C PCS5P23Z09C 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay VDD /2 INPUT OUTPUT VDD /2 t6 Device - Device Skew CLKOUT, Device 1 V DD /2 CLKOUT, Device 2 t 7 V DD /2 Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 7 of 14 May 2007 rev 0.3 Input-Output Skew Timing-Safe™ Output +3.3V PCS5P23Z05C PCS5P23Z09C Test Circuit Input OUTPUTS TSKEW TSKEW+ 0.1uF One clock cycle N=1 when spread spectrum is ON For example, TSKEW = ± 0.125 for an Input clock 75MHz, translates in to (1/75MHz) * 0.125=1.66nS CLKOUT CLOAD VDD GND TSKEW represents input-output skew A Typical example of Timing-Safe™ waveform Input Input CLKOUT with SSOFF Timing-Safe™ CLKOUT Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 8 of 14 May 2007 rev 0.3 Package Information PCS5P23Z05C PCS5P23Z09C 8-lead (150-mil) SOIC Package E H D A2 A θ e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L θ Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0° 1.27 8° 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0° 0.050 8° Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 9 of 14 May 2007 rev 0.3 PCS5P23Z05C PCS5P23Z09C 8-lead TSSOP Package (4.40-MM Body) H E D A2 A θ e B A1 L C Dimensions Symbol Min A A1 A2 B c D E e H L θ 0.020 0° 0.002 0.033 0.008 0.004 0.114 0.169 0.026 BSC 0.252 BSC 0.028 8° 0.50 0° Inches Max 0.043 0.006 0.037 0.012 0.008 0.122 0.177 0.05 0.85 0.19 0.09 2.90 4.30 Millimeters Min Max 1.10 0.15 0.95 0.30 0.20 3.10 4.50 0.65 BSC 6.40 BSC 0.70 8° Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 10 of 14 May 2007 rev 0.3 16-lead (150 Mil) Molded SOIC Package PCS5P23Z05C PCS5P23Z09C 8 1 PIN 1 ID E H 9 D 16 Seating Plane A e B h A2 D 0.004 θ L C A1 Dimensions Symbol Min A A1 A2 B C D E e H h L θ 0.228 0.010 0.016 0° 0.053 0.004 0.049 0.013 0.008 0.386 0.150 0.050 BSC 0.244 0.016 0.035 8° 5.80 0.25 0.40 0° Inches Max 0.069 0.010 0.059 0.022 0.012 0.394 0.157 Millimeters Min 1.35 0.10 1.25 0.33 0.19 9.80 3.80 1.27 BSC 6.20 0.41 0.89 8° Max 1.75 0.25 1.50 0.53 0.27 10.01 4.00 Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 11 of 14 May 2007 rev 0.3 16-lead TSSOP Package (4.40-MM Body) PCS5P23Z05C PCS5P23Z09C 8 1 PIN 1 ID E H 9 16 A Seating Plane θ L C e D A2 B A1 D Dimensions Symbol Min A A1 A2 B C D E e H L θ 0.020 0° 0.002 0.031 0.007 0.004 0.193 0.169 0.026 BSC 0.252 BSC 0.030 8° 0.50 0° Inches Max 0.043 0.006 0.041 0.012 0.008 0.201 0.177 0.05 0.80 0.19 0.09 4.90 4.30 Millimeters Min Max 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.65 BSC 6.40 BSC 0.75 8° Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 12 of 14 May 2007 rev 0.3 Ordering Codes Ordering Code PCS5P23Z05CG-08-ST PCS5P23Z05CG-08-SR PCS5P23Z05CG-08-TT PCS5P23Z05CG-08-TR PCS5P23Z09CG-16-ST PCS5P23Z09CG-16-SR PCS5P23Z09CG-16-TT PCS5P23Z09CG-16-TR PCS5P23Z05C PCS5P23Z09C Marking 5P23Z05CG 5P23Z05CG 5P23Z05CG 5P23Z05CG 5P23Z09CG 5P23Z09CG 5P23Z09CG 5P23Z09CG Package Type 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 4.4-mm TSSOP - TUBE 8-pin 4.4-mm TSSOP - TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 4.4-mm TSSOP - TUBE 16-pin 4.4-mm TSSOP - TAPE & REEL Tempeature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Device Ordering Information PCS5P23Z05CG-08-TR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 13 of 14 May 2007 rev 0.3 PCS5P23Z05C PCS5P23Z09C PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS5P23Z05C PCS5P23Z09C Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Timing-Safe™ US Patent Pending. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Multiple Output Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 14 of 14