PCS5P9774G-52-ER

September 2006 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features • • • • • • • • • • • • • • • Output frequency range: 8.3MHz to 125MHz Input frequency range: 4.2MHz to 62.5MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150pS max output-output skew PLL bypass mode ‘SpreadTrak’ Output enable/disable Pin compatible with MPC9774 and CY29774 Industrial temperature range: -40°C to +85°C 52Pin 1.0mm TQFP package RoHS Compliance PCS5I9774 The PCS5I9774 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. The PLL is ensured stable given that the VCO is configured to run between 200MHz to 500MHz. This allows a wide range of output frequencies from 8.3MHz to 125MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table. Functional Description The PCS5I9774 is a low-voltage high-performance 125MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram VCO_SEL PLL_EN TCLK_SEL TCLK0 TCLK1 FB_IN SELA ÷2/÷4 CLK STOP ÷2 PLL 200500MHZ ÷2/÷4 ÷4 CLK STOP QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QB4 SELB ÷4/÷6 SELC CLK_STP# CLK STOP QC0 QC1 QC2 QC3 FB_OUT ÷4/÷6/÷8/÷12 FB_SEL(1.0) MR#/OE PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 rev 0.4 Pin Configuration PCS5I9774 VCO_SEL VDDQC VDDQC VDDQB QC1 QC2 QC3 VSS VSS VSS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 NC VDD AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 QC0 VSS QB0 39 38 37 36 35 34 33 32 31 30 29 28 27 NC VSS QB1 VDDQB QB2 VSS QB3 VDDQB QB4 FB_IN VSS FB_OUT VDDFB NC PCS5I9774 14 15 16 17 18 19 20 21 22 23 24 25 26 QA3 QA2 QA1 QA4 FB_SEL0 FB_SEL1 VSS AVSS VDDQA VDDQA VSS QA0 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. VDDQA 2 of 12 September 2006 rev 0.4 Pin Description1 Pin 9 10 16, 18, 21, 23, 25 32, 34, 36, 38, 40 44, 46, 48, 50 29 31 2 3 6 8 52 7, 4, 5 20, 14 17, 22, 26 33, 37, 41 45, 49 28 13 12 15 1, 19, 24, 30, 35, 39, 43, 47, 51 11, 27, 42 PCS5I9774 Name TCLK0 TCLK1 QA(4:0) QB(4:0) QC(3:0) FB_OUT FB_IN MR#/OE CLK_STP# PLL_EN TCLK_SEL VCO_SEL SEL(A:C) FB_SEL(1,0) VDDQA VDDQB VDDQC VDDFB AVDD VDD AVSS VSS NC I/O I, PD I, PU O O O O I, PU I, PU I, PU I, PU I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD VDD Ground Ground Description LVCMOS/LVTTL reference clock input LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. Clock stop enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. VCO divider select input. See Table 2. Frequency select input, Bank (A:C). See Table 3. Feedback dividers select input. See Table 4. 2.5V or 3.3V Power supply for bank A output clocks2,3 2.5V or 3.3V Power supply for bank B output clocks2,3 2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for feedback output clock2,3 2.5V or 3.3V Power supply for PLL2,3 2.5V or 3.3V Power supply for core and inputs2,3 Analog Ground Common Ground No Connection Note: 1.PU = Internal pull up, PD = Internal pull down. 2.A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (