P4C1023-55CWM

P4C1023/P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM FEATURES VCC Current — Operating: 35mA — CMOS Standby: 100µA Access Times —55/70 ns Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE CE OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 400 or 600 mil Ceramic DIP —32-Pin Ceramic SOJ DESCRIPTION The P4C1023L is a 1 Megabit low power CMOS static RAM organized as 128K x 8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1023L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE low) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE is HIGH or WE is LOW. The P4C1023L is packaged in a 32-pin 400 or 600 mil ceramic DIP and in a 32-pin ceramic SOJ. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (C10, C11), CERAMIC SOJ (CJ1) TOP VIEW Document # SRAM126 REV OR Revised October 2005 1 P4C1023/P4C1023L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Supply Voltage 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V °C °C mA mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Symbol VOH VOL VIH VIL ILI Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage Input Leakage Current GND ≤ VIN ≤ VCC Comm. Industrial Military Comm. Industrial Military ISB VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V 100 µA Test Conditions IOH = –1mA, VCC = 4.5V IOL = 2.1mA 2.2 -0.3 -2 -5 -10 -2 -5 -10 Min 2.4 0.4 VCC + 0.3 0.8 +2 +5 +10 +2 +5 +10 3 mA Max Unit V V V V µA GND ≤ VOUT ≤ VCC ILO Output Leakage Current CE1 ≥ VIH or CE2 ≤ VIL µA ISB1 Document # SRAM126 REV OR Page 2 of 11 P4C1023/P4C1023L CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current Industrial Military Note 1 -55 -70 20 25 35 20 25 35 mA Unit Note 1 - Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 55 5 20 0 70 -55 Min 55 55 55 5 10 20 30 5 25 5 10 25 35 Max Min 70 70 70 -70 Max Unit ns ns ns ns ns ns ns ns ns ns ns Document # SRAM126 REV OR Page 3 of 11 P4C1023/P4C1023L READ CYCLE NO. 1 (OE CONTROLLED)(1) READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1. WE is HIGH for READ cycle. 2. CE and OE are LOW for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE transition LOW. 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM126 REV OR Page 4 of 11 P4C1023/P4C1023L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 5 -55 Min 55 50 50 0 40 0 25 0 25 5 Max Min 70 60 60 0 50 0 30 0 30 -70 Max Unit ns ns ns ns ns ns ns ns ns ns WRITE CYCLE NO. 1 (WE CONTROLLED)(6) Notes: 6. CE and WE are LOW for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM126 REV OR Page 5 of 11 P4C1023/P4C1023L TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby DOUT Disabled Read Write CE OE WE H L L L X H L X X H H L I/O High Z High Z DOUT DIN Power Standby Active Active Active * including scope and test fixture. Note: Because of the high speed of the P4C1023L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). Document # SRAM126 REV OR Page 6 of 11 P4C1023/P4C1023L DATA RETENTION Symbol VDR Parameter VCC for Data Retention Test Conditions CE ≥ VCC -0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V VDR = 2.0V VDR = 3.0V See Retention Waveform 0 tRC Min 2.0 Max 5.5 50 100 Unit V µA µA ns ns ICCDR tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time 1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V LOW VCC DATA RETENTION WAVEFORM Document # SRAM126 REV OR Page 7 of 11 P4C1023/P4C1023L ORDERING INFORMATION SELECTION GUIDE The P4C1023L is available in the following temperature, speed and package options. Temperature Range Commercial Package Side Brazed DIP (400 mil) Side Brazed DIP (600 mil) Ceramic SOJ Industrial Side Brazed DIP (400 mil) Side Brazed DIP (600 mil) Ceramic SOJ Military Temperature Military Processed* Side Brazed DIP (400 mil) Side Brazed DIP (600 mil) Ceramic SOJ Side Brazed DIP (400 mil) Side Brazed DIP (600 mil) Ceramic SOJ Speed (ns) 55 -55CC -55CWC -55CJC -55CI -55CWI -55CJI -55CM -55CWM -55CJM -55CMB -55CWMB -55CJMB 70 -70CC -70CWC -70CJC -70CI -70CWI -70CJI -70CM -70CWM -70CJM -70CMB -70CWMB -70CJMB Document # SRAM126 REV OR Page 8 of 11 P4C1023/P4C1023L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C11 32 (400 mil) Min Max 0.232 0.014 0.023 0.038 0.065 0.008 0.018 1.700 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C10 32 (600 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.680 0.510 0.620 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE Document # SRAM126 REV OR Page 9 of 11 P4C1023/P4C1023L Pkg # # Pins Symbol A A1 A2 B B1 B2 B3 D D1 E E1 E2 e e1 e2 j S S1 CJ1 32 Min Max 0.120 0.165 0.088 0.120 0.070 REF 0.010 REF 0.030R TYP 0.020 REF 0.025 0.045 0.816 0.838 0.750 REF 0.419 0.431 0.430 0.445 0.360 0.380 0.050 BSC 0.038 TYP 0.005 0.005 TYP 0.030 0.040 0.020 TYP CERAMIC SOJ SMALL OUTLINE IC PACKAGE Document # SRAM126 REV OR Page 10 of 11 P4C1023/P4C1023L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Oct-05 SRAM126 P4C1023 / P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM ORIG. OF CHANGE JDB DESCRIPTION OF CHANGE New Data Sheet Document # SRAM126 REV OR Page 11 of 11