P4C1026-20CI

P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Low Power Single 5V±10% Power Supply Data Retention with 2.0V Supply Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil SOJ – 28-Pin 400 mil SOJ – 28-Pin 400 mil Ceramic DIP – 32-Pin Ceramic LCC DESCRIPTION The P4C1026 is a 1 Meg ultra high speed static RAM organized as 256K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. The P4C1026 is available in a 28-pin 300 mil and 400 mil SOJ packages, as well as Ceramic DIP and LCC packages, providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SOJ (J5, J7), DIP (C7) LCC(L13) Document # SRAM127 REV E 1 Revised April 2007 P4C1026 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Industrial Commercial Military Ambient Temperature –40°C to +85°C 0°C to +70°C -55°C to +125°C GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 7 10 pF pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO ISB ISB1 Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = –18 mA Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH VOUT = GND to VCC 2.4 –5 –5 ___ ___ +5 +5 35 10 Test Conditions P4C1026 Min Max 2.2 –0.5(3) –0.5 (3) Unit V V V V V V V µA µA mA VCC +0.5 0.8 0.2 –1.2 0.4 VCC –0.2 VCC +0.5 CE ≥ VIH Standby Power Supply Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC mA Document # SRAM127 REV E Page 2 of 10 P4C1026 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial Industrial –15 80 90 –20 75 80 –25 75 80 –35 75 80 Unit mA mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL DATA RETENTION CHARACTERISTICS Symbol VDR ICCDR tCDR tR† Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Test Conditions Min 2.0 10 0 tRC§ 15 250 500 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V µA ns ns *TA = +125°C § † tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM127 REV E Page 3 of10 P4C1026 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. t RC tAA tAC t OH tLZ t HZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Chip Enable to Power Up Time Chip Disable to Power Down Time -15 Min 15 15 15 2 2 8 0 15 0 2 3 Max 20 -20 Min Max 20 20 2 3 9 0 20 Min 25 -25 Max 25 25 2 3 10 0 25 Min 35 -35 Max 35 35 Unit ns ns ns ns ns ns ns ns 11 35 TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM127 REV E Page 4 of 10 P4C1026 TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP t AH tDW t DH tWZ tDW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 2 -15 13 12 12 0 12 0 7 0 6 2 20 15 15 0 15 0 8 0 8 2 -20 25 18 18 0 18 0 10 0 10 3 -25 35 25 25 0 25 0 15 0 15 -35 Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM127 REV E Page 5 of10 P4C1026 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby DOUT Disabled Read Write CE H L L L OE X H L X WE X H H L I/O High Z High Z DOUT High Z Power Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1258, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Figure 2. Thevenin Equivalent frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM127 REV E Page 6 of 10 P4C1026 ORDERING INFORMATION SELECTION GUIDE The P4C1026 is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Military Temperature Military Processeed* Package Plastic SOJ, 300 mil Plastic SOJ, 400 mil Plastic SOJ, 300 mil Plastic SOJ, 400 mil Ceramic DIP, 400 mil 28-Pin Ceramic LCC 32-Pin Ceramic LCC Ceramic DIP, 400 mil 28-Pin Ceramic LCC 32-Pin Ceramic LCC Speed 15 -15J3C -15J4C -15J3I -15J4I N/A N/A N/A N/A N/A N/A 20 -20J3C -20J4C -20J3I -20J4I -20CM -20L28M -20L32M -20CMB -20L28MB -20L32MB 25 -25J3C -25J4C -25J3I -25J4I -25CM -25L28M -25L32M -25CMB -25L28MB -25L32MB 35 -35J3C -35J4C -35J3I -35J4I -35CM -35L28M -35L32M -35CMB -35L28MB -35L32MB 1513 10 * Military temperature range with MIL-STD-883, Class B compliance N/A = Not Available Document # SRAM127 REV E Page 7 of10 P4C1026 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J5 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J7 28 (400 mil) Min Max 0.128 0.148 0.082 0.013 0.019 0.007 0.013 0.720 0.730 0.050 BSC 0.435 0.445 0.395 0.405 0.360 0.380 0.025 - SOJ SMALL OUTLINE IC PACKAGE Document # SRAM127 REV E Page 8 of 10 P4C1026 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C7 28 (400 mil) Min Max 0.115 0.255 0.016 0.020 0.045 0.065 0.008 0.018 1.384 1.416 0.387 0.403 0.400 BSC 0.100 TYP 0.125 0.200 0.015 0.070 0.005 — 0.005 — SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 e h j L L1 L2 ND NE L13 32 Min Max 0.070 0.093 0.054 0.066 0.025 0.031 0.442 0.458 0.300 BSC 0.150 BSC — 0.458 0.742 0.758 0.400 BSC 0.200 BSC 0.050 TYP RECTANGULAR LEADLESS CHIP CARRIER 0.045 0.055 0.045 0.055 0.090 REF 7 9 Document # SRAM127 REV E Page 9 of10 P4C1026 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C D E ISSUE DATE Oct-05 Aug-06 Oct-06 Dec-06 Mar-07 Apr-07 SRAM127 P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM ORIG. OF CHANGE JDB JDB JDB JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Updated SOJ package information Added Ceramic DIP, LCC packages and military processing Added L13 package, removed L12 package Minor typographic corrections Corrected LCC pin configuration Document # SRAM127 REV E Page 10 of 10