P4C1049L-35JMB

P4C1049/P4C1049L HIGH SPEED 512K x 8 STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) — 15/20/25 ns (Commercial) — 20/25/35 ns (Industrial) — 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE CE OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —36-Pin SOJ (400 mil) —36-Pin FLATPACK —36-Pin LCC (452 mil x 920 mil) DESCRIPTION The P4C1049 is a 4 Megabit high-speed CMOS static RAM organized as 512Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1049 is a member of a family of PACE RAM™ products offering fast access times. The P4C1049 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A18. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOLDER-SEAL FLATPACK (FS-4) SOJ (J9) LCC (L11) 1519B Document # SRAM128 REV OR 1 Revised October 2005 P4C1049 MAXIMUM RATINGS(1) Symbol V CC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA V TERM TA V °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 8 8 pF pF –55°C to +125°C –40°C to +85°C Industrial Commercial 0°C to +70°C Output Capacitance VOUT = 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC VOL VOH Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE ≥ VIH ISB Mil. ___ ___ 45 40 ___ ___ 40 n/a mA Standby Power Supply VCC= Max, Ind./Com’l. Current (TTL Input Levels) f = Max., Outputs Open Mil. Ind./Com’l. Mil. Ind./Com’l. 2.4 –10 –5 –10 –5 +10 +5 +10 +5 Test Conditions P4C1049 Min Max VCC +0.3 2.2 P4C1049L Unit Min Max VCC +0.3 V 2.2 V V V V V +5 n/a +5 n/a µA µA 0.8 0.8 –0.3(3) –0.3(3) VCC –0.2 VCC +0.3 VCC –0.2 VCC +0.3 –0.3 (3) 0.2 0.4 –0.3 (3) 0.2 0.4 2.4 –5 n/a –5 n/a ILI CE ≥ VHC ISB1 Standby Power Supply Current (CMOS Input Levels) VCC= Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC Mil. Ind./Com’l. ___ ___ 15 10 ___ ___ 10 n/a mA N/A = Not Applicable Document # SRAM128 REV OR Page 2 of 12 P4C1049 DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only) Symbol V DR ICCDR t CDR tR † *TA = +25°C §tRC = Read Cycle Time † Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditons Min 3.0 Typ.* VCC = 3.0V Max VCC = 3.0V Unit V CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V 0 tRC§ 2 3 mA ns ns This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current* Industrial Military –15 220 N/A N/A –20 185 190 200 –25 180 185 195 –35 N/A 175 185 –45 N/A N/A 175 –55 N/A N/A 170 –70 N/A N/A 165 Unit mA mA mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. Document # SRAM128 REV OR Page 3 of 12 P4C1049 AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. t RC tAA t AC t OH tLZ t HZ tOE tOLZ t OHZ t PU t PD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time -15 15 15 15 3 3 8 7 0 7 0 15 0 0 3 3 20 -20 25 20 20 3 3 9 9 0 9 0 20 -25 35 25 25 3 3 11 10 0 10 0 25 -35 45 35 35 3 3 15 15 0 15 0 35 -45 55 45 45 3 3 20 20 0 20 0 45 -55 70 55 55 3 3 25 25 0 25 0 55 -70 Min Max Min Max Min Max Min Max Min Max Min Max Min Max 70 70 Unit ns ns ns ns ns 30 30 ns ns ns 30 ns ns 70 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) Document # SRAM128 REV OR Page 4 of 12 P4C1049 TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –2.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM128 REV OR Page 5 of 12 P4C1049 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH tDW t DH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Date Hold Time Write Enable to Output in High Z Output Active from End of Write -15 15 12 12 0 12 0 9 0 8 3 3 20 -20 25 -25 35 -35 45 -45 55 -55 70 -70 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns 14 14 0 14 0 11 0 10 18 16 0 16 0 13 0 11 3 22 20 0 22 0 15 0 15 5 30 25 0 25 0 20 0 18 5 35 35 0 30 0 25 0 25 5 40 40 0 35 0 30 0 30 5 ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11) Document # SRAM128 REV OR Page 6 of 12 P4C1049 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM128 REV OR Page 7 of 12 P4C1049 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE O E W E H X L L L X X H L X X X H H L I/O High Z High Z High Z DOUT High Z Power Standby Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1049, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid Figure 2. Thevenin Equivalent signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM128 REV OR Page 8 of 12 P4C1049 ORDERING INFORMATION Document # SRAM128 REV OR Page 9 of 12 P4C1049 Pkg # # Pins Symbol A b c D E E1 E2 E3 e L Q S M N FS-4 36 Min Max 0.089 0.125 0.015 0.019 0.003 0.007 0.910 0.930 0.505 0.515 0.530 0.385 0.395 0.055 0.065 0.050 BSC 0.300 0.350 0.015 0.038 0.045 0.0015 36 SOLDER SEAL FLATPACK Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J9 36 Min Max 0.130 0.145 0.082 0.015 0.020 0.007 0.013 0.920 0.930 0.050 BSC 0.435 0.445 0.395 0.405 0.370 BSC 0.045 0.055 SOJ SMALL OUTLINE IC PACKAGE Document # SRAM128 REV OR Page 10 of 12 P4C1049 Pkg # # Pins Symbol A A1 B D D1 E e L L2 P R L11 36 Min Max 0.080 0.100 0.054 0.066 0.022 0.028 0.910 0.930 0.840 0.860 0.445 0.460 .050 BSC .100 TYP 0.115 0.135 0.006 .009 TYP RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM128 REV OR Page 11 of 12 P4C1049 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Oct-05 SRAM128 P4C1049 / P4C1049L HIGH SPEED 512K x 8 STATIC CMOS RAM ORIG. OF CHANGE JDB DESCRIPTION OF CHANGE New Data Sheet Document # SRAM128 REV OR Page 12 of 12