P4C116-15FSMB

P4C116/P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35 ns (Commercial) – 15/20/25/35 ns (Military) Low Power Operation Output Enable Control Function Single 5V±10% Power Supply Common Data I/O Fully TTL Compatible Inputs and Outputs Produced with PACE II TechnologyTM Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP, SOIC, SOJ – 24-Pin Solder Seal Flat Pack – 24-Pin Rectangular LCC (300 x 400 mils) – 28-Pin Square LCC (450 x 450 mils) – 32-Pin Rectangular LCC (450 x 550 mils) – 40-Pin Square LCC (480 x 480 mils) DESCRIPTION The P4C116/P4C116L are 16,384-bit ultra high-speed static RAMs organized as 2K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption. The P4C116 is available in 24-pin 300 mil DIP, SOJ and SOIC packages, a solder seal flatpack and 4 different LCC packages (24, 28, 32, and 40 pin). FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P4, C4), SOJ (J4), SOIC (S4) SOLDER SEAL FLAT PACK (FS-1) SIMILAR LCC configurations at end of datasheet Document # SRAM110 REV A 1 Revised October 2005 P4C116/P4C116L MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0°C to 70°C -55°C to +125°C Gnd 0V 0V Vcc 5.0V ±10% 5.0V ±10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT= 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = –18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current Standby Power Supply Current (TTL Input Levels) IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC CE ≥ VIH, VCC= Max, CE ≥ VHC, VCC= Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC f = Max., Outputs Open Mil. Ind./Com’l. ___ ___ 15 10 ___ ___ 1 n/a mA Mil. Com’l. Mil. Com’l. Mil. Ind./Com’l. 2.4 –10 –5 –10 –5 ___ ___ +10 +5 +10 +5 30 20 Test Conditions P4C116 Min Max 2.2 –0.5(3) –0.5 (3) P4C116L Min Max 2.2 –0.5(3) –0.5 (3) Unit V V V V V V V VCC +0.5 0.8 0.2 –1.2 0.4 VCC +0.5 0.8 0.2 –1.2 0.4 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 2.4 –5 n/a –5 n/a ___ ___ +5 n/a +5 n/a 20 n/a µA µA mA ISB1 Standby Power Supply Current (CMOS Input Levels) n/a = Not Applicable Document # SRAM110 REV A Page 2 of 14 P4C116/P4C116L DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only) Symbol VDR ICCDR tCDR tR† *TA = +25°C §tRC = Read Cycle Time † Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditons Min 2.0 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V 0 tRC§ 10 15 600 900 µA ns ns This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial Military –10 180 N/A –12 170 N/A –15 160 170 –20 155 160 –25 150 155 –35 140 150 Unit mA mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC tOH tLZ tHZ tOE Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid –10 10 10 10 2 2 5 6 0 6 0 10 0 0 2 2 –12 12 12 12 2 2 6 8 0 7 0 12 –15 15 15 15 2 2 7 10 0 8 0 15 –20 20 20 20 2 3 8 10 0 9 0 20 –25 25 25 25 2 3 10 15 0 12 0 20 –35 35 35 35 Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns 15 20 15 25 ns ns ns ns ns ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU tPD Chip Enable to Power Up Time Chip Disable to Power Down Document # SRAM110 REV A Page 3 of 14 P4C116/P4C116L TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM110 REV A Page 4 of 14 P4C116/P4C116L AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write –10 10 8 8 0 8 0 7 0 6 0 0 –12 12 10 10 0 10 0 8 0 7 0 –15 15 12 12 0 12 0 10 0 8 0 –20 –25 25 18 18 0 18 0 15 0 –35 35 25 25 0 20 0 20 0 Min Max Min Max Min Max Min Max Min Max Min Max 20 15 15 0 15 0 12 0 10 0 Unit ns ns ns ns ns ns ns ns 15 0 15 ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM110 REV A Page 5 of 14 P4C116/P4C116L AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby DOUT Disabled Read Write CE H L L L OE X H L X WE X H H L I/O High Z High Z DOUT High Z Power Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency Figure 2. Thevenin Equivalent capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM110 REV A Page 6 of 14 P4C116/P4C116L LCC PIN CONFIGURATIONS 24-Pin LCC (L8) 28-Pin LCC (L5-1) 32-Pin LCC (L6) 40-Pin LCC (L10) Document # SRAM110 REV A Page 7 of 14 P4C116/P4C116L ORDERING INFORMATION SELECTION GUIDE The P4C116 is available in the following temperature, speed and package options. Temperature Range Commercial Package Plastic DIP Plastic SOJ Plastic SOIC Military Temperature 24-Pin Rect. LCC 28-Pin Sq. LCC 32-Pin Rect. LCC 40-Pin Sq. LCC Side Brazed DIP CERPACK Military Processed* 24-Pin Rect. LCC 28-Pin Sq. LCC 32-Pin Rect. LCC 40-Pin Sq. LCC Side Brazed DIP CERPACK Speed (ns) 10 -10PC -10JC -10SC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC -12JC -12SC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15JC -15SC -15LM -15L28M -15L32M -15L40M -15CM -15FSM -15LMB -15L28MB -15L32MB -15L40MB -15CMB -15FSMB 20 -20PC -20JC -20SC -20LM -20L28M -20L32M -20L40M -20CM -20FSM -20LMB -20L28MB -20L32MB -20L40MB -20CMB -20FSMB 25 -25PC -25JC -25SC -25LM -25L28M -25L32M -25L40M -25CM -25FSM -25LMB -25L28MB -25L32MB -25L40MB -25CMB -25FSMB 35 -35PC -35JC -35SC -35LM -35L28M -35L32M -35L40M -35CM -35FSM -35LMB -35L28MB -35L32MB -35L40MB -35CMB -35FSMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM110 REV A Page 8 of 14 P4C116/P4C116L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C4 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b1 c c1 D E E1 E2 E3 e k L Q S1 M N FS-1 24 Min Max 0.045 0.115 0.015 0.022 0.015 0.019 0.004 0.009 0.004 0.006 0.640 0.350 0.420 0.450 0.180 0.030 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.000 0.0015 24 SOLDER SEAL FLATPACK Document # SRAM110 REV A Page 9 of 14 P4C116/P4C116L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J4 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 B1 D/E D1/E1 D2/E2 D3/E3 e h j L L1 L2 ND NE L5-1 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.460 0.300 BSC 0.150 BSC 0.460 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 7 SQUARE LEADLESS CHIP CARRIER Document # SRAM110 REV A Page 10 of 14 P4C116/P4C116L Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L6 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L8 24 Min Max 0.064 0.076 0.054 0.066 0.022 0.028 0.292 0.308 0.200 BSC 0.100 BSC 0.308 0.392 0.408 0.300 BSC 0.150 BSC 0.408 0.050 BSC 0.025 REF 0.015 REF 0.040 0.050 0.040 0.050 0.077 0.093 5 7 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM110 REV A Page 11 of 14 P4C116/P4C116L Pkg # # Pins Symbol A A1 B1 D/E D1/E1 D2/E2 D3/E3 e h j L L1 L2 ND/NE L10 40 Min Max 0.060 0.080 0.050 0.075 0.015 0.025 0.475 0.492 0.360 BSC 0.180 BSC 0.492 0.040 BSC R = .0075 0.026 REF 0.030 0.050 0.030 0.050 0.080 0.090 10 SQUARE LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P4 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE Document # SRAM110 REV A Page 12 of 14 P4C116/P4C116L Pkg # # Pins Symbol A A1 b2 C D e E H h L α S4 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0° 8° SOIC/SOP SMALL OUTLINE IC PACKAGE Document # SRAM110 REV A Page 13 of 14 P4C116/P4C116L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM110 P4C116 / P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM110 REV A Page 14 of 14