P4C1298-20PMB

P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 15/20/25/35/45 ns (Military) Low Power Single 5V±10% Power Supply Output Enable & Chip Enable control functions Data Retention with 2.0V Supply Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC DESCRIPTION The P4C1298/L are a 262,144-bit ultra high speed static RAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. The P4C1298 is available in a 28-pin 300 mil DIP or SOJ, as well as a 28-pin 350x500 mil LCC package, providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P5, C5) SOJ (J5) LCC (L5) Document # SRAM135 REV OR Revised April 2007 1 P4C1298/L MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG V °C PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA VTERM TA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Industrial Commercial Ambient Temperature -55°C to +125°C –40°C to +85°C 0°C to +70°C GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 5 7 pF pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC V CD VOL VOH ILI ILO ISB ISB1 Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current VCC = Min., IIN = 18 mA IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH VOUT = GND to VCC CE ≥ VIH VCC = Max ., f = Max., Outputs Open CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC Mil Ind/Comm Mil Ind/Comm 2.4 Test Conditions P4C1298 Min Max 2.2 –0.5(3) VCC –0.2 –0.5 (3) P4C1298L Min Max 2.2 –0.5(3) VCC +0.5 0.8 VCC +0.5 0.2 –1.2 0.4 2.4 Unit V V V V V V V VCC +0.5 0.8 VCC +0.5 VCC –0.2 0.2 –1.2 0.4 –0.5 (3) –5 +5 –10 +10 µA Output Leakage Current Standby Power Supply Current (TTL Input Levels) Standby Power Supply Current (CMOS Input Levels) –5 ___ ___ +5 40 20 10 10 –10 ___ ___ ___ ___ +10 20 N/A 10 N/A µA mA mA mA mA ___ ___ Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM135 REV OR Page 2 of 11 P4C1298/L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial Industrial Military –15 160 160 160 –20 125 135 150 –25 115 120 120 –35 110 115 120 Unit mA mA mA ICC Dynamic Operating Current* *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL DATA RETENTION CHARACTERISTICS (P4C1298L ONLY) Symbol VDR ICCDR tCDR tR† Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Test Conditions Min 2.0 10 0 tRC§ 15 1000 2000 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V µA ns ns *TA = +25°C § † tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM135 REV OR Page 3 of 11 P4C1298/L AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC tOH tLZ tHZ tOE tOLZ t OHZ tPU t PD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 0 3 3 15 -15 Min -20 -25 Min 25 20 20 25 25 3 3 10 10 15 15 0 9 15 0 20 25 0 0 3 3 -35 Max Min 35 35 35 3 3 15 25 0 20 0 35 Max -45 Min 45 45 45 Max Unit ns ns ns ns ns 20 30 20 45 ns ns ns ns ns ns Max Min Max 20 15 15 3 3 8 8 0 9 0 15 TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) Document # SRAM135 REV OR Page 4 of 11 P4C1298/L TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM135 REV OR Page 5 of 11 P4C1298/L AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -15 Sym tWC tCW t AW t AS t WP t AH tDW t DH t WZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 Min 15 10 10 0 10 0 9 0 7 0 Max Min 20 15 15 0 15 0 10 0 10 0 -20 Max Min 25 20 20 0 20 0 15 0 15 0 -25 Max Min 35 25 25 0 25 0 20 0 20 0 -35 Max Min 45 30 30 0 30 0 20 0 20 -45 Max TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9) Notes: 9. CE and WE must be LOW for WRITE cycle. 10. OE is LOW for this WRITE cycle. 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transition address. 13. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM135 REV OR Page 6 of 11 P4C1298/L TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9,10) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Read Write CE H L L WE X H L Output High Z DOUT DIN Power Standby Active Active Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1298, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Figure 2. Thevenin Equivalent frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM135 REV OR Page 7 of 11 P4C1298/L ORDERING INFORMATION SELECTION GUIDE The P4C1298 is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Military Temperature Military Processeed* Speed Package Plastic SOJ, 300 mil Plastic SOJ, 300 mil Ceramic DIP, 300 mil 28-Pin Ceramic LCC Ceramic DIP, 300 mil 28-Pin Ceramic LCC 15 -15J3C -15J3I -15CM -15L28M -15CMB -15L28MB 20 -20J3C -20J3I -20CM -20L28M -20CMB -20L28MB 25 -25J3C -25J3I -25CM -25L28M -25CMB -25L28MB 35 -35J3C -35J3I -35CM -25L28M -35CMB -25L28MB 1513 10 Document # SRAM135 REV OR Page 8 of 11 P4C1298/L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J5 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P5 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE α Document # SRAM135 REV OR Page 9 of 11 P4C1298/L Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L5 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C5 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE Document # SRAM135 REV OR Page 10 of 11 P4C1298/L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Apr-07 SRAM135 P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM ORIG. OF CHANGE JDB DESCRIPTION OF CHANGE New Data Sheet Document # SRAM135 REV OR Page 11 of 11