P4C147-10CC

P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Low Power Operation – 715 mW Active –10 (Commercial) – 550 mW Active –25 (Commercial) – 110 mW Standby (TTL Input) – 55 mW Standby (CMOS Input) Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 18 Pin 300 mil DIP – 18 Pin CERPACK – 18 Pin LCC (290 x 430 mils) – 18 Pin LCC (295 x 335 mils) DESCRIPTION The P4C147 is a 4,096-bit ultra high speed static RAM organized as 4K x 1. The CMOS memory requires no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption in both active and standby modes. In addition to very high performance, this device features latch-up protection and single-event-upset protection. The P4C147 is available in 18 pin 300 mil DIP packages, an 18-pin CERPACK package, and 2 different LCC packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P1, D1, C9), CERPACK (F1) SIMILAR LCC (L7, L7-1) Document # SRAM103 REV A 1 Revised October 2005 P4C147 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value – 0.5 to +7 – 0.5 to VCC +0.5 – 55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value – 55 to +125 – 65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0°C to 70°C -55°C to +125°C Gnd 0V 0V VCC 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT= 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Symbol VOH VOL VIH VIL ILI ILO ISB ISB1 Parameter Output High Voltage (TTL Load) Output Low Voltage (TTL Load) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current (TTL Input Levels) Standby Power Supply Current (CMOS Input Levels) VCC = Max., VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC CE ≥ VIH, VCC = Max., f=Max., Output Open CE ≥ VHC, VCC = Max., f= 0, Output Open VIN ≤ 0.2V or VIN ≥ VCC -0.2V Mil. Comm’l Mil. Comm’l Mil. Comm’l Mil. Comm’l Test Conditions IOH = –4 mA, VCC = Min. IOL = +8 mA, VCC = Min 2.2 –0.5(3) –10 –5 –10 –5 __ __ __ __ P4C147 Min. 2.4 0.4 VCC =+0.5 0.8 +10 +5 +10 +5 30 23 15 10 Max. Unit V V V V µA µA mA mA POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Military -10 130 N/A -12 130 N/A -15 120 145 -20 115 135 -25 100 125 -35 N/A 120 Unit mA mA Document # SRAM103 REV A Page 2 of 10 P4C147 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC tOH tLZ tHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Chip Enable to Power Up Time Chip Disable to Power Down Time -10 10 10 10 2 2 4 0 10 0 2 2 12 -12 15 12 12 2 2 5 0 12 -15 20 15 15 2 2 6 0 15 -20 -25 25 20 20 2 2 8 0 20 25 10 0 25 25 2 2 35 -35 Min Max Min Max Min Max Min Max Min Max Min Max 35 35 Unit ns ns ns ns ns 14 ns ns 35 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (6) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM103 REV A Page 3 of 10 P4C147 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max 10 8 8 0 8 0 5 0 5 0 0 12 10 10 0 10 0 6 0 6 0 15 12 12 0 12 0 7 0 7 0 20 15 15 0 14 0 9 0 9 0 25 20 20 0 15 0 12 0 12 0 35 25 25 0 18 0 15 0 15 ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9) Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM103 REV A Page 4 of 10 P4C147 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Read Write CE H L L WE X H L Output High Z DOUT High Z Power Standby Active Active Figure 1. Output Load * including scope and test fixture. Figure 2. Thevenin Equivalent Note: Due to the ultra-high speed of the P4C147, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM103 REV A Page 5 of 10 P4C147 ORDERING INFORMATION SELECTION GUIDE The P4C147 is available in the following temperature, speed and package options. Temperature Range Commercial Temperature Package Plastic DIP CERDIP Military Temperature Side Brazed DIP LCC (290 x 430 mil) LCC (295 x 335 mil) CERPACK CERDIP Military Processed* Side Brazed DIP LCC (290 x 430 mil) LCC (295 x 335 mil) CERPACK Speed (ns) 10 -10PC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15DM -15CM -15LM -15LSM -15FM -15DMB -15CMB -15LMB -15LSMB -15FMB 20 -20PC -20DM -20CM -20LM -20LSM -20FM -20DMB -20CMB -20LMB -20LSMB -20FMB 25 -25PC -25DM -25CM -25LM -25LSM -25FM -25DMB -25CMB -25LMB -25LSMB -25FMB 35 N/A -35DM -35CM -35LM -35LSM -35FM -35DMB -35CMB -35LMB -35LSMB -35FMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM103 REV A Page 6 of 10 P4C147 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C9 18 (300 Mil) Min Max 0.200 0.014 0.026 0.030 0.065 0.008 0.018 0.960 0.220 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α D1 18 (300 Mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 0.960 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0° 15° CERDIP DUAL IN-LINE PACKAGE Document # SRAM103 REV A Page 7 of 10 P4C147 Pkg # # Pins Symbol A b c D E e k L Q S S1 F1 18 Min Max 0.045 0.092 0.015 0.022 0.004 0.009 0.540 0.245 0.370 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGES Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L7 18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.417 0.440 0.200 BSC 0.100 BSC 0.440 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.075 0.090 0.075 0.148 4 5 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM103 REV A Page 8 of 10 P4C147 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L7-1 18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.345 0.365 0.200 BSC 0.100 BSC 0.365 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.125 4 5 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P1 18 Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 0.880 0.920 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE Document # SRAM103 REV A Page 9 of 10 P4C147 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM103 P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM103 REV A Page 10 of 10