P4C150-35DM

P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK DESCRIPTION The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTLcompatible. The RAM operates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds. Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level. The P4C150 is available in 24-pin 300 mil DIP and SOIC packages providing excellent board level densities. The device is also available in a 28-pin LCC package as well as a 24-pin FLATPACK for military applications. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P4, C4, D4), SOIC (S4) CERPACK (F3) SIMILAR LCC (L5) Document # SRAM105 REV A 1 Revised October 2005 P4C150 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value – 0.5 to +7 – 0.5 to VCC +0.5 – 55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value – 55 to +125 – 65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0°C to 70°C -55°C to +125°C Gnd 0V 0V VCC 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT= 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Symbol VOH VOL VIH VIL ILI ILO Parameter Output High Voltage (TTL Load) Output Low Voltage (TTL Load) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC Test Conditions IOH = –4 mA, VCC = Min. IOL = +8 mA, VCC = Min 2.2 –0.5(3) –5 –5 P4C150 Min. 2.4 0.4 VCC =+0.5 0.8 +5 +5 Max. Unit V V V V µA µA POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Military -10 130 N/A -12 130 N/A -15 120 145 -20 115 135 -25 100 125 -35 N/A 120 Unit mA mA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than – 3.0V and – 100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM105 REV A Page 2 of 11 P4C150 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Data Valid Output Enable to Output in Low Z Output Disable to Output in High Z -10 10 10 8 2 2 4 7 2 5 2 2 2 12 -12 15 12 10 2 2 6 9 2 7 -15 20 15 12 2 2 8 10 2 9 -20 -25 25 20 14 2 2 10 14 2 11 13 13 15 2 25 15 2 2 35 -35 Min Max Min Max Min Max Min Max Min Max Min Max 35 35 Unit ns ns ns ns ns 15 20 ns ns ns 16 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5,6) TIMING WAVEFORM OF READ CYCLE NO. 2 (CS CONTROLLED)(5, 7) Notes: 5.WE is HIGH for READ cycle. 6.CS and OE are LOW for READ cycle. 7.ADDRESS must be valid prior to, or concident with, CS transition LOW, tAA must still be met. 8. Transition is measured ±200 mV from steady state voltage prior to change, with loading as specified in Figure 1. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM105 REV A Page 3 of 11 P4C150 TIMING WAVEFORM OF READ CYCLE NO. 3 (OE Controlled)(5) AC CHARACTERISTICS—RESET CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol tRRC tWER tCR tRP tHCR tHWR tRLZ tRHZ Parameter Reset Cycle Time Write Enable High to Beginning of Reset Chip Select Low to Beginning of Reset Reset Pulse Width Chip Select Hold after End of Reset Write Enable Hold after End of Reset Reset High to Output in Low Z Reset Low to Output in High Z -10 Min Max 20 0 0 10 0 10 0 0 8 -12 Min Max 24 0 0 12 0 12 0 0 10 -15 Min Max 30 0 0 15 0 15 0 0 12 -20 Min Max 40 0 0 20 0 20 0 0 16 -25 Min Max 50 0 0 25 0 25 0 0 20 -35 Min Max 70 0 0 30 0 35 0 0 Unit ns ns ns ns ns ns ns ns TIMING WAVEFORM OF RESET CYCLE Document # SRAM105 REV A Page 4 of 11 P4C150 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max 10 8 8 0 8 0 5 0 5 2 2 12 10 10 1 10 1 8 1 8 2 15 11 13 1 11 1 11 1 12 3 20 13 16 1 13 1 13 1 15 3 25 15 20 2 15 2 15 2 20 3 35 20 25 2 20 2 20 2 25 ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED)(10) Notes: 10. CS and WE must be LOW for WRITE cycle. 11. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM105 REV A Page 5 of 11 P4C150 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Not Selected RESET Output Disabled READ WRITE RS X L H H H CS H L L L L OE X X H L X WE X H H H L Output High Z High Z High Z DOUT High Z Figure 1. Output Load * including scope and test fixture. Figure 2. Thevenin Equivalent Note: Due to the ultra-high speed of the P4C150, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM105 REV A Page 6 of 11 P4C150 ORDERING INFORMATION SELECTION GUIDE The P4C150 is available in the following temperature, speed and package options. Speed (ns) Temperature Package Range 10 12 15 20 Commercial Temperature Military Temperature Plastic DIP Plastic SOIC Side Brazed DIP CERDIP CERPACK LCC Side Brazed DIP Military Processed* CERDIP CERPACK LCC -10PC -10SC N/A N/A N/A N/A N/A N/A N/A N/A -12PC -12SC N/A N/A N/A N/A N/A N/A N/A N/A -15PC -15SC -15CM -15DM -15FM -15LM -15CMB -15DMB -15FMB -15LMB -20PC -20SC -20CM -20DM -20FM -20LM -20CMB -20DMB -20FMB -20LMB 25 -25PC -25SC -25CM -25DM -25FM -25LM -25CMB -25DMB -25FMB -25LMB 35 N/A N/A -35CM -35DM -35FM -35LM -35CMB -35DMB -35FMB -35LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM105 REV A Page 7 of 11 P4C150 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C4 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D4 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° CERDIP DUAL IN-LINE PACKAGE α Document # SRAM105 REV A Page 8 of 11 P4C150 Pkg # # Pins Symbol A b c D E e k L Q S S1 F3 24 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.630 0.330 0.380 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L5 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM105 REV A Page 9 of 11 P4C150 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P4 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 b2 C D e E H h L S4 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0° 8° SOIC/SOP SMALL OUTLINE IC PACKAGE α Document # SRAM105 REV A Page 10 of 11 P4C150 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM105 P4C150 ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM105 REV A Page 11 of 11