P4C187

P4C187/P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 12/15/20/25/35 /45 ns (Industrial) – 15/20/25/35/45/55/70/85 ns (Military) Low Power Operation – 743 mW Active -10 – 660/770 mW Active for -12/15 – 550/660 mW Active for -20/25/35 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C187 – 5.5 mW Standby (CMOS Input) P4C187L (Military) Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C187L Military) Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC DESCRIPTION The P4C187/P4C187L are 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10µA. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the P4C187L. The P4C187/P4C187L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P3, D3, C3) SOJ (J4) LCC Pin configurations at end of datasheet. Document # SRAM111 REV B 1 Revised April 2007 P4C187/187L MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 5 7 pF pF –55°C to +125°C –40°C to +85°C Industrial 0°C to +70°C Commercial DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = 18 mA Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC Mil. Com’l. Mil. Com’l. 2.4 –10 –5 –10 –5 ___ ___ ___ ___ +10 +5 +10 +5 40 35 20 15 Test Conditions P4C187 Min Max 2.2 VCC +0.5 –0.5(3) –0.5(3) 0.8 0.2 –1.2 0.4 2.4 –5 n/a –5 n/a ___ ___ ___ ___ +5 n/a +5 n/a 40 n/a 1.0 n/a P4C187L Unit Min Max 2.2 VCC +0.5 V –0.5(3) –0.5(3) 0.8 0.2 –1.2 0.4 V V V V V V µA µA mA VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 Standby Power Supply CE ≥ VIH Mil. Current (TTL Input Levels) VCC = Max ., Ind./Com’l. f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ISB1 mA n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM111 REV B Page 2 of 12 P4C187/187L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Dynamic Operating Current* Temperature Range Commercial Industrial Military –10 180 N/A N/A –12 170 180 N/A –15 160 170 170 –20 155 160 160 –25 150 155 155 –35 N/A 150 150 –45 N/A N/A 145 –55 N/A N/A 145 –70 N/A N/A 145 –85 Unit N/A N/A 145 mA mA mA ICC *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL. DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only) Symbol VDR ICCDR tCDR tR† *TA = +25°C §tRC = Read Cycle Time † Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditons Min 2.0 Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V Unit V CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V 0 tRC§ 10 15 600 900 µA ns ns This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM111 REV B Page 3 of 12 P4C187/187L AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter t RC t AA t AC t OH t LZ t HZ t PU t PD Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 10 2 2 5 0 12 -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 10 10 2 2 6 0 15 12 12 12 2 2 8 0 20 15 15 15 2 2 10 0 25 20 20 20 2 2 12 0 35 25 25 25 2 2 17 0 45 35 35 35 2 2 20 0 55 45 45 45 2 2 25 0 70 55 55 65 2 2 30 0 85 70 70 70 2 2 35 85 85 85 TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM111 REV B Page 4 of 12 P4C187/187L AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter t WC t CW t AW tAS t WP t AH t DW t DH t WZ t OW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 8 8 0 8 0 6 0 6 0 0 12 10 10 0 10 0 7 0 7 0 15 12 12 0 12 0 10 0 8 0 20 15 15 0 15 0 13 0 12 0 25 20 20 0 20 0 15 0 15 0 35 25 25 0 25 0 20 0 17 0 45 30 30 0 30 0 25 0 20 0 55 35 35 0 35 0 30 0 25 0 70 40 40 0 40 0 35 0 30 0 85 45 45 0 45 0 40 0 35 TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9) Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM111 REV B Page 5 of 12 P4C187/187L TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Read Write CE H L L WE X H L Output High Z DOUT High Z Power Standby Active Active Figure 1. Output Load * including scope and test fixture. Note: Due to the ultra-high speed of the P4C187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, Figure 2. Thevenin Equivalent proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM111 REV B Page 6 of 12 P4C187/187L LCC PIN CONFIGURATIONS 22-PIN LCC (L3) 28-PIN LCC (L5) Document # SRAM111 REV B Page 7 of 12 P4C187/187L ORDERING INFORMATION SELECTION GUIDE The P4C187 is available in the following temperature, speed and package options. The P4C187L is only available over the military temperature range. Temperature Range Commercial Industrial Military Temperature Package Plastic DIP Plastic SOJ Plastic DIP Plastic SOJ Side Brazed DIP CERDIP LCC (28 Pin) LCC (22 Pin) Military Processed* Side Brazed DIP CERDIP LCC (28 Pin) LCC (22 Pin) Speed (ns) 10 -10PC -10JC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC -12JC -12PI -12JI N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15JC -15PI -15JI -15CM -15DM -15L28M -15LM -15CMB -15DMB -15L28MB -15LMB 20 -20PC -20JC -20PI -20JI -20CM -20DM -20L28M -20LM -20CMB -20DMB -20L28MB -20LMB 25 -25PC -25JC -25PI -25JI -25CM -25DM -25L28M -25LM -25CMB -25DMB -25L28MB -25LMB 35 -35PC -35JC -35PI -35JI -35CM -35DM -35L28M -35LM -35CMB -35DMB -35L28MB -35LMB 45 -45PC -45JC -45PI -45JI -45CM -45DM -45L28M -45LM -45CMB -45DMB -45L28MB -45LMB 55 N/A N/A N/A N/A -55CM -55DM -55L28M -55LM -55CMB -55DMB -55L28MB -55LMB 70 N/A N/A N/A N/A -70CM -70DM -70L28M -70LM -70CMB -70DMB -70L28MB -70LMB 85 N/A N/A N/A N/A -85CM -85DM -85L28M -85LM -85CMB -85DMB -85L28MB -85LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM111 REV B Page 8 of 12 P4C187/187L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C3 22 (300 mil) Min Max 0.100 0.200 0.014 0.023 0.030 0.060 0.008 0.015 1.050 1.260 0.260 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGES Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D3 22 (300 mil) Min Max 0.225 0.015 0.020 0.045 0.065 0.009 0.012 1.060 1.110 0.290 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° CERDIP DUAL IN-LINE PACKAGE α Document # SRAM111 REV B Page 9 of 12 P4C187/187L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J4 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L1 ND NE L3 22 Min Max 0.060 0.080 0.050 0.068 0.022 0.028 0.284 0.296 0.150 BSC 0.075 BSC 0.296 0.484 0.496 0.300 BSC 0.150 BSC 0.496 0.050 BSC R = .012 R = .012 0.039 0.051 0.039 0.051 0.058 0.072 4 7 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM111 REV B Page 10 of 12 P4C187/187L Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L5 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P3 22 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.145 1.165 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE α Document # SRAM111 REV B Page 11 of 12 P4C187/187L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B ISSUE DATE 1997 Oct-05 Apr-07 SRAM111 P4C187 / P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS ORIG. OF CHANGE DAB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added 55, 70, and 85 ns speeds Document # SRAM111 REV B Page 12 of 12