AR8031-AL1B-R

Data Sheet August 2011 Version 1.1 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver General Description The AR8031 is part of the Arctic family of devices — which includes the AR8031, AR8033, and AR8035. The AR8031 is Atheros’ 4th generation, single port, 10/100/1000 Mbps, Trispeed Ethernet PHY. It supports both RGMII and SGMII interfaces to the MAC. The AR8031 provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including enterprise, carrier and home networks such as CPE, home gateway, enterprise switch, carrier switch/router, mobile base station and base station controller, optical module and media converter, industry automation and measurement. The AR8031 integrates Atheros Green ETHOS® power saving technologies and significantly saves power not only during the work time, but also overtime. Atheros Green ETHOS® power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length. The AR8031 also supports IEEE 802.3az EEE standard (Energy Efficient Ethernet) and Atheros proprietary SmartEEE. SmartEEE allows legacy MAC/SoC devices without 802.3az support to function as a complete 802.3az system. Further, the AR8031 supports Wake-on-LAN (WoL) feature to be able to help manage and regulate total system power requirements. The AR8031 embeds CDT (Cable Diagnostics Test) technology on-chip which allows customers to measure cable length, detect the cable status, and identify remote and local PHY malfunctions, bad or marginal patch cord segments or connectors. Some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a bad transformer. The AR8031 requires only a single, 3.3V power supply. On-chip regulators provide all the other required voltages. It integrates the termination R/C circuitry on both the MAC interfaces (RGMII/SGMII) and the serial resistors for the line side. The AR8031 device also incorporates a 1.25 GHz SerDes. This interface can be connected directly to a fiber-optic transceiver for 1000 BASE-X /100 BASE-FX mode or to MAC device for SGMII interface. The AR8031 supports both 1588v2 and synchronous Ethernet to offer a complete time synchronization solution to meet the next generation network requirements. The key new features supported by the device are: n Clock synchronization between slave and grandmaster by the exchange of PTP packets. Supports IEEE 1588v2 by offering a 1588 paket parser, accurate time-stamping and insertion to support both one-step and two-step clock modes n Supports both IEEE 1588v2 and Synchronous Ethernet by offering recovered clock output from data on the network-line side. The AR8031 supports IEEE 802.3az Energy Efficient Ethernet (EEE) standard. The key features supported by the device are: n 10 BASE-Te PHY uses reduced transmit amplitude. n 100 BASE-TX and 1000 BASE-T use Low Power Idle (LPI) mode to turn off unused analog and digital blocks to save power while data traffic is idle. Features n 10/100/1000 BASE-T IEEE 802.3 compliant n Supports 1000 BASE-T PCS and auto- negotiation with next page support n Supports RGMII and/or SGMII interfaces to MAC devices n Supports Fiber and Copper combo mode when MAC interface works in RGMII mode n Supports additional IEEE 1000 BASE-X and 100 BASE-FX with Integrated SerDes n RGMII timing modes support internal delay and external delay on Rx path © 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, UNav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice. COMPANY CONFIDENTIAL • 1 n Supports Atheros Green ETHOS® power n n n n n n n saving modes with internal automatic DSP power saving scheme Supports IEEE 802.3az (Energy Efficient Ethernet) Supports SmartEEE which allows MAC/ SoC devices withoug 802.3az support to function as the complete 802.3az system Supports Wake-on-LAN (WoL) to detect magic packet and notify the sleeping system to wake up Fully integrated digital adaptive equalizers, echo cancellers, and Near End Crosstalk (NEXT) cancellers Supports Synchronous Ethernet with selectable recovered clock output Robust Cable Discharge Event (CDE) protection of ±6 kV Error-free operation over up to 140 meters of CAT5 cable n n n n n n n n n n n Automatic channel swap (ACS) Automatic MDI/MDIX crossover Automatic polarity correction IEEE 802.3u compliant Auto-Negotiation Jumbo Frame support up to 10KB (full duplex) Multiple loopback modes for diagnostics Robust Surge Protection with ±750 V/ differential mode and ±4 kV/common mode Cable Diagnostic Test (CDT) Single power supply: 3.3V, optional for external regulator for core voltage 6mm x 6mm, 48-pin QFN package Industry temperature (I-temp) option available. AR8031 Functional Block Diagram Symbol Encoder Waveshape Filter DAC Echo Canceller PMA TRD[0:3] Hybrid Circut PGA ADC Decision Feedback Equalizer Next Canceller Feed Forward Equalizer Trellis Decoder Serial Interface Timing and Phase Recovery 2 2 • • Symbol Decoder RGMII Deskewer AGC AutoNegotiation RGMII MII Management Registers Sync-E 1588v2 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 SGMII/ SerDes PCS DLL Atheros Communications, Inc. COMPANY CONFIDENTIAL Revision History Date Revsion Details Revision 2010/11/15 First draft 0.1 2011/4/14 General Description n Overall update for revision from MPW to mass production n Block diagram: add SYNC-E and 1588v2 block Pin Descriptions n RXD [3:0], RX_DV pin damping resistor 22ohm requirement is deleted. n RST pin type change from "IH" to "I,” mass production chip does not have internal weak PU n INT, WOL_INT from "I/O active high" change to "D active low" need an external PU n Power on strapping LED_ACT from "1.1V/1.2V selection" to "PHY ADDRESS [2]". n LED_ACT/LED_LINK1000/LED_LINK10_100 from internal weak "PD" change to internal weak "PU". Functional Descriptions n 2.2.4 Mode definition adds work mode"1011" combo mode. Electrical Characteristics n 3.1 Absolute Maximum Rating: update CDM max n 3.2 Recommeded Operating Condition: update Tj max n 3.7 Clock Characteristics: update values in Table 3-13 Recommended Crystal Parameters n Update Table 3-11 MDIO AC Characteristic to add tmdelay row Register n 4.2.29LED Control (0x18): update register bit definitions n 4.2.30 Manual LED Override (0x19): new register Topside Marking n Add topside marking illustration 1.0 2011/8/29 Electrical Characteristics n 3.2 Recommended Operation Conditions: delete DVDDL/AVDDL, JA; add VDDH_REG, JT, AVDDL/DVDDL (industrial and commercial); add thermal conditions n 3.6 change title from MDIO DC Charateristics to MDIO/MDC DC...; change VIH min value and VIL max value 1.1 n 3.7 table 3-14: change Jitterpk-pk max value to 100 n 3.11 Digital pin design guide (new) Registers n 4.2.3 Status Register – Copper page, change bit[8] reset value to always 1 n 4.3.4 Hib control and auto-neg test register: change bit[12], [6:5] to reserved n 4.3.5 External loopback selection, change bit[0] to R/W n 4.3.7 Power saving control (new) n 4.4.75 SGMII Control register 2 (new) n 4.4.76 SGMII Control register 3(new) n 4.4.78 1588 RTC clock select register (new) Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • August 2011 • 3 3 4 4 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table of Contents General Description ........................................ 1 Features ............................................................ 1 AR8031 Functional Block Diagram .............. 2 Revision History ............................................. 3 Table of Contents ............................................ 5 1 Pin Descriptions ............................ 9 1.1 Power-on Strapping Pins ...................... 13 1.1.1 Mode Definition .......................... 14 2 Functional Description ............... 15 2.2 Modes of Operation ............................... 16 2.2.1 Operation Mode, Copper .......... 16 2.2.2 Operation Mode, Fiber ............... 16 2.2.3 Operation Mode, Media Converter 17 2.2.4 Operation Mode, Auto-Media Detect (Combo) ........................... 17 2.3 Transmit Functions ................................ 18 2.4 Receive Functions .................................. 18 2.4.1 Decoder Modes ........................... 18 2.4.2 Analog to Digital Converter ...... 18 2.4.3 Echo Canceller ............................. 18 2.4.4 NEXT Canceller .......................... 18 2.4.5 Baseline Wander Canceller ....... 18 2.4.6 Digital Adaptive Equalizer ....... 18 2.4.7 Auto-Negotiation ........................ 19 2.4.8 Smartspeed Function ................. 19 2.4.9 Automatic MDI/MDIX Crossover 19 2.4.10 Polarity Correction ..................... 19 2.5 Loopback Modes .................................... 19 2.5.1 Digital Loopback ......................... 19 2.5.2 External Cable Loopback ........... 19 2.5.3 Remote PHY Loopback .............. 20 2.6 Cable Diagnostic Test ............................ 20 2.7 Fiber Mode Support .............................. 20 2.7.1 IEEE 802.3 Remote Fault Indication Support ......................................... 20 2.7.2 Fault Propagation ....................... 21 2.8 LED Interface .......................................... 21 2.9 Power Supplies ....................................... 22 2.10 Management Interface .......................... 24 Atheros Communications, Inc. COMPANY CONFIDENTIAL 2.11 Timing Sychronization ......................... 26 2.11.1 Synchronous Ethernet — Physical Layer Timing Synchronization . 29 2.12 Atheros Green EthosTM ...................... 30 2.12.1 Low Power Modes ..................... 30 2.12.2 Shorter Cable Power Mode ....... 30 2.12.3 Hibernation Mode ...................... 30 2.13 IEEE 802.3az and Energy Efficient Ethernet 30 2.14 IEEE 802.3az Energy Efficient Ethernet 30 2.14.1 IEEE 802.3az LPI Mode .............. 30 2.14.2 Atheros SmartEEE ...................... 31 2.15 Wake On LAN (WoL) .......................... 32 3 Electrical Characteristics ............33 3.1 Absolute Maximum Ratings ................ 33 3.2 Recommended Operating Conditions 33 3.3 RGMII Characteristics ........................... 34 3.4 SerDes and SGMII Characteristics ...... 37 3.5 MDIO Timing ......................................... 39 3.6 MDIO/MDC DC Characteristic .......... 39 3.7 Clock Characteristics ............................. 40 3.8 Power Pin Current Consumption ....... 41 3.9 Typical Power Consumption Parameters 41 3.10 Power-on Sequence, Reset and Clock 44 3.10.1 Power-on Sequence .................... 44 3.10.2 Reset and Clock Timing ............. 44 3.11 Digital Pin Design Guide ..................... 44 4 Register Descriptions ..................47 4.1 Register Summary ................................. 47 4.2 MII Registers .......................................... 47 4.2.1 Control Register — Copper Page 49 4.2.2 Control — Fiber Page ................. 50 4.2.3 Status Register — Copper Page 51 4.2.4 Status Register — Fiber Page .... 53 4.2.5 PHY Identifier ............................. 54 4.2.6 PHY Identifier2 ........................... 55 4.2.7 Auto-Negotiation Advertisement Register — Copper Page ........... 55 4.2.8 Auto-Negotiation Advertisement Register — Fiber Page ................ 57 4.2.9 Link Partner Ability Register — AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • August 2011 • 5 5 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 4.2.19 4.2.20 4.2.21 4.2.22 4.2.23 4.2.24 4.2.25 4.2.26 4.2.27 4.2.28 4.2.29 4.2.30 4.2.31 4.2.32 4.2.33 4.2.34 4.2.35 Copper Page ................................ 58 Link Partner Ability Register — Fiber Page .................................... 59 Auto-Negotiation Expansion Register — Copper Page ............ 60 Auto-Negotiation Expansion Register — Fiber Page ................ 61 Next Page Transmit Register — Copper Page ................................ 62 Next Page Transmit Register — Fiber Page for 1000 BASE-X, SGMII 62 Link Partner Next Page Register — Copper Page ................................ 63 Link Partner Next Page Register — Fiber Page for 1000 BASE-X, SGMII 64 1000 BASE-T Control Register .. 64 1000 BASE-T Status Register ..... 66 MMD Access Control Register . 67 MMD Access Address Data Register ......................................... 67 Extended Status Register ........... 68 Function Control Register ......... 68 PHY-Specific Status Register — Copper Page ................................ 69 PHY-Specific Status Register — Fiber Page .................................... 71 Interrupt Enable Register .......... 72 Interrupt Status Register ............ 73 Smart Speed Register ................. 75 Cable Diagnostic Tester (CDT) Control Register .......................... 76 LED Control ................................. 76 Manual LED Override Register 77 Copper/Fiber Status Register ... 78 Cable Diagnostic Tester Status Register ......................................... 79 Debug Port (Address offset set) 80 Debug Port2 (R/W port) ............ 80 Chip Configure Register ............ 80 4.3 Debug Register Descriptions ................ 83 4.3.1 Analog Test Control ................... 83 4.3.2 SerDes Test and System Mode Control .......................................... 83 4.3.3 100BASE-TX Test Mode Select .. 84 4.3.4 Hib Control and Auto-Negotiation 6 6 • • Test Register ................................ 85 4.3.5 External Loopback Selection ..... 85 4.3.6 Test Configuration for 10BASE-T 85 4.3.7 Power Saving Control ................ 86 4.4 MDIO Interface Register ....................... 87 4.4.1 PCS Control ................................. 90 4.4.2 PCS Status .................................... 90 4.4.3 EEE Capability ............................ 91 4.4.4 EEE Wake Error Counter .......... 91 4.4.5 P1588 Control Register .............. 92 4.4.6 P1588 RX_seqid ........................... 93 4.4.7 P1588 rx_sourcePort_identity ... 93 4.4.8 P1588 rx_sourcePort_identity ... 93 4.4.9 P1588 rx_sourcePort_identity ... 93 4.4.10 P1588 rx_sourcePort_identity ... 94 4.4.11 P1588 rx_sourcePort_identity ... 94 4.4.12 P1588 rx_time_stamp ................. 94 4.4.13 P1588 rx_time_stamp ................. 94 4.4.14 P1588 rx_time_stamp ................. 95 4.4.15 P1588 rx_time_stamp ................. 95 4.4.16 P1588 rx_time_stamp ................. 95 4.4.17 P1588 Rx_frac_nano ................... 95 4.4.18 P1588 Rx_frac_nano ................... 96 4.4.19 P1588 Tx_seqid ........................... 96 4.4.20 P1588 tx_sourcePort_Identity ... 96 4.4.21 P1588 tx_sourcePort_Identity ... 96 4.4.22 P1588 tx_sourcePort_Identity ... 97 4.4.23 P1588 tx_sourcePort_Identity ... 97 4.4.24 P1588 tx_sourcePort_Identity ... 97 4.4.25 P1588 tx_sourcePort_Identity ... 97 4.4.26 P1588 tx_timestamp ................... 98 4.4.27 P1588 tx_timestamp ................... 98 4.4.28 P1588 tx_time_stamp ................. 98 4.4.29 P1588 tx_time_stamp ................. 98 4.4.30 P1588 tx_time_stamp ................. 98 4.4.31 P1588 Tx_frac_nano ................... 99 4.4.32 P1588 tx_frac_nano ..................... 99 4.4.33 P1588 Orgin_Correction_o ........ 99 4.4.34 P1588 Orgin_Correction_o ...... 100 4.4.35 P1588 Orgin_Correction_o ...... 100 4.4.36 P1588 Orgin_Correction_o ...... 100 4.4.37 P1588 Ingress_trig_time_o ...... 100 4.4.38 P1588 Ingress_trig_time_o ...... 100 4.4.39 P1588 Ingress_trig_time_o ...... 101 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.4.40 4.4.41 4.4.42 4.4.43 4.4.44 4.4.45 4.4.46 4.4.47 4.4.48 4.4.49 4.4.50 4.4.51 4.4.52 4.4.53 4.4.54 4.4.55 4.4.56 4.4.57 4.4.58 4.4.59 4.4.60 4.4.61 4.4.62 4.4.63 4.4.64 4.4.65 4.4.66 4.4.67 4.4.68 4.4.69 4.4.70 4.4.71 4.4.72 4.4.73 4.4.74 4.4.75 P1588 Ingress_trig_time_o ...... 101 P1588 Tx_latency_o .................. 101 P1588 Inc_value_o .................... 102 P1588 Inc_value_o .................... 102 P1588 Nano_offset_o ................ 102 P1588 Nano_offset_o ................ 102 P1588 Sec_offset_o .................... 103 P1588 Sec_offset_o .................... 103 P1588 Sec_offset_o .................... 103 P1588 Real_time_i ..................... 103 P1588 Real_time_i ..................... 103 P1588 Real_time_i ..................... 104 P1588 Real_time_i ..................... 104 P1588 Real_time_i ..................... 104 P1588 Rtc_frac_nano_i ............. 104 P1588 Rtc_frac_nano_i ............. 105 Wake-on-LAN Internal Address 1 105 Wake-on-LAN Internal Address 2 105 Wake-on-LAN Internal Address 3 105 Rem_phy_lpbk .......................... 106 SmartEEE Control 1 .................. 106 SmartEEE Control 2 .................. 106 SmartEEE control 3 ................... 107 Auto-Negotiation Control 1 .... 107 Auto-Negotiation Status .......... 108 Auto-Negotiation XNP Transmit . 108 Auto-Negotiation XNP transmit1 108 Auto-Negotiation XNP Transmit2 109 Auto-Negotiation LP XNP Ability 109 Auto-Negotiation LP XNP Ability1 109 Auto-Negotiation LP XNP ability2 109 EEE Advertisement .................. 110 EEE LP advertisement .............. 110 EEE Ability Auto-negotiation Result .......................................... 111 SGMII Control Register 1 ........ 111 SGMII Control Register 2 ........ 112 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.4.76 SGMII Control Register 3 ........ 112 4.4.77 CLK_25M Clock Select ............ 112 4.4.78 1588 Clock Select ...................... 113 5 Package Dimensions .................115 6 Ordering Information ...............117 7 Topside Marking .......................117 AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • August 2011 • 7 7 8 8 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 1. Pin Descriptions This section contains a package pinout for the AR8031 QFN 48 pin and a listing of the signal descriptions (see Figure 1-1). The following nomenclature is used for signal types described in Table 1-1: The following nomenclature is used for signal names: D Open drain IA Analog input signal NC No connection to the internal die is made from this pin I Digital input signal n At the end of the signal name, indicates active low signals IH Input signals with weak internal pull-up, to prevent signals from floating when left open P At the end of the signal name, indicates the positive side of a differential signal IL Input signals with weak internal pull-down, to prevent signals from floating when left open N At the end of the signal name indicates the negative side of a differential signal I/O A digital bidirectional signal OA An analog output signal O A digital output signal P A power or ground signal PD Internal pull-down for input PU Internal pull-up for input Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • August 2011 • 9 9 TXD1 TXD2 TXD3 WOL_INT SD SON SOP AVDDL SIN SIP DVDDL MDIO Figure 1-1 shows the pinout diagram for AR8031. 48 47 46 45 44 43 42 41 40 39 38 37 MDC 1 36 TXD0 RSTn 2 35 GTX_CLK LX 3 34 TX_EN VDD33 4 33 RX_CLK INT 5 XTLO 6 XTLI 7 AVDDL 8 RBIAS 9 AR8031 32 RX_DV 31 RXD0 TOP VIEW 30 RXD1 29 VDDIO_REG 28 RXD2 EXPOSED GROUND PAD ON BOTTOM VDDH_REG 10 27 RXD3 TRXP0 11 26 LED_LINK10_100 TRXN0 12 25 CLK_25M LED_LINK1000 LED_ACT PPS TRXN3 TRXP3 AVDDL TRXN2 TRXP2 AVDD33 TRXN1 TRXP1 AVDDL 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1-1. AR8031 48-pin QFN Pinout Diagram (Top View) NOTE: There is an exposed ground pad on the back side of the package. 10 10 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table 1-1. Signal to Pin Relationships and Descriptions Symbol Pin Type Description TRXP0, TRXN0 11, 12 IA, OA Media-dependent interface 0, differential 100 transmission line TRXP1, TRXN1 14, 15 IA, OA Media-dependent interface 1, differential 100 transmission line TRXP2, TRXN2 17, 18 IA, OA Media-dependent interface 2, differential 100 transmission line TRXP3, TRXN3 20, 21 IA, OA Media-dependent interface 3, differential 100 transmission line GTX_CLK 35 I, PD RX_CLK 33 I/O, PD RGMII receive clock, 125 MHz at 1000 Mbps, 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps digital clock output RX_DV 32 I/O, PD RGMII receive data valid RXD0 31 I/O, PD RGMII receive data 0 RXD1 30 I/O, PD RGMII receive data 1 RXD2 28 I/O, PD RGMII receive data 2 RXD3 27 I/O, PD RGMII receive data 3 TX_EN 34 I, PD RGMII transmit enable TXD0 36 I, PD RGMII transmit data 0 TXD1 37 I, PD RGMII transmit data 1 TXD2 38 I, PD RGMII transmit data 2 TXD3 39 I, PD RGMII transmit data 3 SIP/SIN 46, 45 IA 1.25 Gbps transmit differential inputs When this interface is used as a MAC interface, the MAC transmitter's positive output connects to SIP and the MAC transmitter's negative output connects to the SIN. When this interface is used as a fiber interface, the fiber-optic transceiver's positive output connects to the SIP and the fiber-optic transceiver's negative output connects to the SIN. SOP/SON 43, 42 OA 1.25 Gbps receive differential outputs When this interface is used as a MAC interface, the MAC receiver's positive input connects to SOP and the MAC receiver's negative input connects to the SON. When this interface is used as a fiber interface, the fiber-optic transceiver's positive input connects to the SOP and the fiber-optic transceiver's negative input connects to the SON. 41 IA Signal Detect. 1.2 V voltage level. Input signals must not exceed 1.4V. MDI RGMII RGMII transmit clock, 125 MHz at 1000 Mbps, 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps digital clock input SGMII/1000FX SD Management Interface and Interrupt Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 11 11 Table 1-1. Signal to Pin Relationships and Descriptions (continued) Symbol Pin Type Description MDC 1 I, PU Management data clock reference MDIO 48 I/O, D, PU Management data, 1.5 kpull-up resistor to 3.3 V/ 2.5 V LED LED_ACT 23 I/O, PU Parallel LED output for 10/100/1000 BASE-T activity; active blinking LED active based upon power-on strapping. If pulled up, active low; If pulled-down, active high LED_LINK1000 24 I/O, PU Parallel LED output for 1000 BASE-T link; LED active based upon power-on strapping. If pulled up, active low; If pulled-down, active high LED_LINK10_100 26 I/O, PU Parallel LED output for 10/100 BASE-T link. LED active based upon power-on strapping of LED_LINK1000. If LED_LINK1000 is pulled up, this pin is active low; if LED_LINK1000 is pulled-down, this pin is active high. High, external PU 10 Mbps Low, external PU 100 Mbps System Signal Group/Reference CLK_25M 25 I/O Synchronous Ethernet recovered clock (25MHz, 50MHz, 62.5MHzor 125MHz) output, register configurable, or IEEE 1588v2 reference 50 MHz- 125 MHz clock input. RSTn 2 I XTLI 7 IA Crystal oscillator input; 27 pF capacitor to GND. Support external 25 MHz 1.2 V swing clock input through this pin. XTLO 6 OA Crystal oscillator output; 27 pF capacitor to GND RBIAS 9 OA External 2.37 k 1% resistor to GND to set bias current INT 5 D, PD System Interrupt Output. This pin is OD-gate by default and requires external 10 k pull-up resistor, active low. WOL_INT 40 D, PD Wake-on-LAN interrupt output. This pin is OD-gate by default and requires external 10 kresistor pull-up, active with a low pulse of 32 link speed clock cycles. See “Wake On LAN (WoL)” on page 32 for details. LX 3 OA Power inductor pin. Add an external 4.7 µH/500 mA power inductor to this pin directly. VDDH_REG 10 OA 2.5V regulator output. VDDIO_REG 29 OA Regulator output for the RGMII I/O voltage. It can be either 1.5V (default) or 1.8V. If 2.5V is intended for the RGMII I/O, simply connect this pin with the 2.5V regulator output at pin 10. 8, 13, 19, 44 P System reset, active low. This pin requires an external pull-up resistor. Power AVDDL 12 12 • • 1.1V analog input. Connect to Pin 47 through a bead AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table 1-1. Signal to Pin Relationships and Descriptions (continued) Symbol Pin Type Description DVDDL 47 P 1.1V digital core power input. Connect to power inductor directly and 10uF+0.1uF ceramic capacitors to GND VDD33 4 P 3.3V input for switching regulator AVDD33 16 P 3.3V input for PHY, from VDD33 through a bead 22 O IEEEv2 Pulse Per Second output. 1 Hz clock which is synchronous with internal RTC. 1588v2 Pins PPS 1.1 Power-on Strapping Pins Table 1-2 shows the pin-to-PHY core Power-on strapping relationship Table 1-2. Power-on Strapping Pins PHY Pin PHY Core Config Signal RXD0 PHYADDRESS0 RXD1 PHYADDRESS1 LED_ACT PHYADDRESS2 Description Default Internal Weak Pull-up/down LED_ACT and RXD1-0 set the lower three bits of the physical address. The upper two bits of the physical address are set to the default, “00”. 0 0 1 RX_DV MODE[0] Mode select bit 0 0 RXD2 MODE[1] Mode select bit 1 0 RX_CLK MODE[2] Mode select bit 2 0 RXD3 MODE[3] Mode select bit 3 0 An external 10 k pull-down resistor is required 1 LED_LINK1000 INT SELECT NOTE: 0 = Pull-down, 1 = Pull-up. NOTE: Power-on strapping pins are latched during power-up reset or warm hardware reset. NOTE: Since the MAC device input pins may be driven high or low during power-up or reset, PHY poweron strapping status may be affected by the MAC side. In this case an external 10 k pull-down or pull-up resistor is required to ensure stable status. Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 13 13 1.1.1 Mode Definition Table 1-3 shows the Mode and its Description. Table 1-3. Mode Definition Mode [3:0] Description 0000 1000 BASE-T, RGMII 0001 1000 BASE-T, SGMII 0010 1000 BASE-X, RGMII, 50 0011 1000 BASE-X, SGMII, 75 0100 Converter mode between 1000 BASE-X and 1000 BASE-T media, 50 0101 Converter mode between 1000 BASE-X and 1000 BASE-T media, 75 0110 100 BASE-FX, RGMII, 50 0111 Converter mode between 100 BASE-FX and 100 BASE-TX media, 50 1011 RGMII, copper fiber auto-detection 1110 100 BASE-FX, RGMII mode, 75 1111 Converter mode between 100 BASE-FX and 100 BASE-TX media, 75  Others Reserved NOTE: The 50 or 75 is the single end output impedance. 14 14 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 2. Functional Description Media-Independent Interface (RGMII) to connect to a Gigabit-capable MAC. The AR8031 is Atheros's low cost GbE PHY. It is a highly integrated Analog Front End (AFE) and digital signal transceiver, providing high performance combined with substantial cost reduction. The AR8031 provides physical layer functions for half/full-duplex 10 BASE-Te, 100 BASE-TX and 1000 BASE-T Ethernet to transmit and receive high-speed data over standard Category 5 (CAT5) un-shielded twisted pair cable. The AR8031 transceiver combines echo canceller, Near End Cross Talk (NEXT) canceller, feed-forward equalizer, joint Viterbi, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments. See “AR8031 Functional Block Diagram” on page 2. The AR8031 10/100/1000 PHY is fully 802.3ab compliant, and supports Reduced Gigabit Table 2-1 shows a feature comparison across the AR8031, AR8033, and AR8035 family. Table 2-1. AR8031, AR8033, and AR8035 Comparison Feature AR8031 AR8033 AR8035 RGMII yes yes yes SGMII yes yes Cu Ethernet** yes yes yes EEE (802.3az) yes yes yes Wake-on-LAN yes yes yes SERDES/Fiber*** yes yes 1588v2 yes Sync-E yes yes 48-pin 48-pin Packaging 40-pin NOTE: AR8031, AR8033 are pin-to-pin compatible. ** 10 BASE-Te, 100 BASE-TX, 1000 BASE-T are supported *** 100BASE-FX, and 1000BASE-X are supported Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 15 15 2.2 Modes of Operation 2.2.1 Operation Mode, Copper The AR8031 operates in the following modes, as illustrated below: Figure 2-1 shows the copper operating mode for AR8031. SoC or Switch Transformer MAC Interface - RGMII - SGMII RJ-45 Media types: - 10BASE-Te - 100BASE-TX - 1000BASE-T AR8031 Figure 2-1. Operating Modes — Copper SGMII is serial GMII interface which uses only 4 lines to connect with MAC/SOC. When copper-side link is established, SGMII will pass the copper-side link status (link, speed, duplex) to MAC side for building the link. SGMII interface shares the same SerDes with fiber port. 2.2.2 Operation Mode, Fiber Figure 2-2 shows the fiber operating mode for AR8031. SoC or Switch Fiber Optics Fiber I/F - Serial MAC Interface - RGMII Media Types: - 100BASE-FX - 1000BASE-X AR8031 Figure 2-2. Operating Modes — Fiber AR8031 supports both 1000 BASE-X and 100 BASE-FX modes which are configured by power-on strapping pins (see “Power-on Strapping Pins” on page 13) and by register 0x1F [3:0]. In fiber mode, the MDI+/-[3:0] can be left floating. 16 16 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 2.2.3 Operation Mode, Media Converter Figure 2-3 shows the operating mode Media Converter for AR8031. Fiber Interface: SerDes Transformer Media Type: - 100BASE-FX - 1000BASE-X RJ-45 Media Type: - 100BASE-TX - 1000BASE-T AR8031 Figure 2-3. Operating Modes — Media Converter AR8031 supports the following converter modes: 2.2.4 Operation Mode, Auto-Media Detect (Combo) n 100 BASE-FX fiber to 100 BASE-TX copper n 1000 BASE-X fiber to 1000 BASE-T copper AR8031 supports auto-media detect feature which allows MAC to detect active link partners and process data from copper or fiber interface according to the priority setting. The copper and fiber work modes can be enabled simultaneously by setting the mode bit to 1011 by power-on strapping pin or register 0x1F [3:0]. Converter mode can be configured by poweron strapping (see “Power-on Strapping Pins” on page 13). It can also be configured by register 0x1F [3:0]. The register configuration takes effect immediately. Three LEDs are used to indicate fiber interface status. In converter mode, auto-negotiation is running independently on fiber and copper interfaces. Link status can be checked from copper page and fiber page respectively. Set 0x1F [15] to 1 to select copper page, set 0x1F [15] to0 to select fiber page. Offset address 0x0, 0x1, 0x4, 0x5, 0x6, 0x7, 0x8 and 0x11 refers to two register pages respectively. See “Register Descriptions” chapter for details. When the fiber and copper interfaces link up to the same speed, packets can go through the PHY. When 1000M converter mode (BX1000_CONV) is enabled, the copper port can still link to 100M with a 100M link partner. But packets can not go through the PHY. NOTE: Since the two interfaces implement autonegotiation individually, controller is required to ensure the duplex and pause of two remote link partners are matched. n No fiber or cable connection: Both interfaces in power saving mode. n Fiber connected: RGMII fiber mode. The PHY uses external fiber signal detection from the fiber module along with the synchronization state machine to recognize a valid connection. n Copper connected: RGMII copper mode. The PHY recognizes copper connection by power transmitted over the copper line. n Combo mode: When active link partners over both fiber and copper are detected, the PHY operation mode is defined by priority setting. Priority is configured at register 0x1F [10] (0 = copper; 1 = fiber). In auto media detect mode, fiber port can be configured to 1000 BASE-X or 100 BASE-FX by register 0x1F[8] (1 = 1000 BASE-X, default setting; 0 = 100 BASE-FX). In converter mode, the RGMII interface signal can be left floating. Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 17 17 2.3 Transmit Functions 2.4.2 Analog to Digital Converter Table 2-2 describes the transmit function encoder modes. The AR8031 device employs an advanced high speed ADC on each receive channel with high resolution, which results in better SNR and lower error rates. Table 2-2. Transmit Function Encoder Modes Encoder Mode Description 1000 BASE-T In 1000 BASE-T mode, the AR8031 scrambles transmit data bytes from the MAC interfaces to 9-bit symbols and encodes them into 4D five-level PAM signals over the four pairs of CAT5 cable. 100 BASE-TX In 100 BASE-TX mode, 4-bit data from the MII is 4B/5B serialized, scrambled, and encoded to a three-level MLT3 sequence transmitted by the PMA. 10 BASE-Te In 10 BASE-Te mode, the AR8031 transmits and receives Manchester-encoded data. 2.4 Receive Functions 2.4.1 Decoder Modes Table 2-3 describes the receive function decoder modes. Table 2-3. Receive Function Decoder Modes Decoder Mode Description 1000 BASE-T In 1000 BASE-T mode, the PMA recovers the 4D PAM signals after accounting for the cabling conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs. The resulting code group is decoded into 8-bit data values. Data stream delimiters are translated appropriately and data is output to the MAC interfaces. 100 BASE-TX In 100 BASE-TX mode, the receive data stream is recovered and descrambled to align to the symbol boundaries. The aligned data is then parallelized and 5B/ 4B decoded to 4-bit data. This output runs to the MII receive data pins after data stream delimiters have been translated. 10 BASE-Te 18 18 • • In 10 BASE-Te mode, the recovered 10 BASE-Te signal is decoded from Manchester then aligned. 2.4.3 Echo Canceller A hybrid circuit is used to transmit and receive simultaneously on each pair. A signal reflects back as an echo if the transmitter is not perfectly matched to the line. Other connector or cable imperfections, such as patch panel discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic SNR degradation on the receive signal. The AR8031 device implements a digital echo canceller to adjust for echo and is adaptive to compensate for the varied channel conditions. 2.4.4 NEXT Canceller The 1000 BASE-T physical layer uses all four pairs of wires to transmit data. Because the four twisted pairs are bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. The AR8031 device uses three parallel NEXT cancellers on each receive channel to cancel high frequency crosstalk. The AR8031 cancels NEXT by subtracting an estimate of these signals from the equalizer output. 2.4.5 Baseline Wander Canceller Baseline wander results from Ethernet links that AC-couple to the transceivers and from AC coupling that cannot maintain voltage levels for longer than a short time. As a result, transmitted pulses are distorted, resulting in erroneous sampled values for affected pulses. Baseline wander is more problematic in the 1000 BASE-T environment than in 100 BASETX due to the DC baseline shift in the transmit and receive signals. The AR8031 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizing the impact of DC baseline shift on the overall error rate. 2.4.6 Digital Adaptive Equalizer The digital adaptive equalizer removes intersymbol interference at the receiver. The digital adaptive equalizer takes unequalized signals from ADC output and uses a combination of feedforward equalizer (FFE) and decision AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL crossover algorithm as described in IEEE 802.3 clause 40.4.4 ensures that only one device performs the required crossover. feedback equalizer (DFE) for the bestoptimized signal-to-noise (SNR) ratio. 2.4.7 Auto-Negotiation The AR8031 device supports 10/100/1000 BASE-T Copper auto-negotiation in accordance with IEEE 802.3 clauses 28 and 40. Autonegotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. Auto-negotiation is initiated upon any of the following scenarios: n Power-up reset n Hardware reset n Software reset n Auto-negotiation restart n Transition from power-down to power-up n The link goes down If auto-negotiation is disabled, a 10 BASE-Te or 100 BASE-TX can be manually selected using the IEEE MII registers. 2.4.10 Polarity Correction If cabling has been incorrectly wired, the AR8031 automatically corrects polarity errors on the receive pairs in 1000 BASE-T, 1000BASETX, and 10 BASE-Te modes. 2.5 Loopback Modes 2.5.1 Digital Loopback Digital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the AR8031 device. Figure 24 shows a block diagram of digital loopback. MAC/ Switch RGMII/ SGMII PHY  Digital PHY  AFE NOTE: Smartspeed enable bit requires a software reset to take effect after writing (write register 0x0[15]). Figure 2-4. Digital Loopback 2.4.8 Smartspeed Function The Atheros Smartspeed function is an enhanced feature of auto-negotiation that allows the AR8031 device to fall back in speed based on cabling conditions as well as operate over CAT3 cabling (in 10 BASE-T mode) or two-pair CAT5 cabling (in 100 BASE-TX mode). Followings are the register settings for loopback mode selection: By default, the Smartspeed feature is enabled. Refer to the register “Smart Speed Register” on page 75, which describes how to set the parameters. Set these register bits to control the Smartspeed feature: n Bit [5]: 1 = Enables Smartspeed (default) n Bits [4:2]: Sets the number of link attempts before adjusting n Bit [1]: Timer to determine the stable link condition 2.5.2 External Cable Loopback External cable loopback loops RGMII/SGMII Tx to RGMII/SGMII Rx through a complete digital and analog path and an external cable, thus testing all the digital data paths and all the analog circuits. Figure 2-5 shows a block diagram of external cable loopback. MAC/ Switch RGMII /SGMII PHY  Digital RJ‐45 NOTE: Smartspeed enable bit needs a software reset (write register 0x0[15] = 1’b1 to take effect after writing. n 1000M loopback: register 0x0 = 0x4140 n 100M loopback: register 0x0 = 0x6100 n 10M loopback: register 0x0 = 0x4100 PHY  AFE 2.4.9 Automatic MDI/MDIX Crossover During auto-negotiation, the AR8031 device automatically determines and sets the required MDI configuration, eliminating the need for external crossover cable. If the remote device also implements automatic MDI crossover, the Atheros Communications, Inc. COMPANY CONFIDENTIAL Figure 2-5. External Cable Loopback AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 19 19 To configure external loopback: 1. Plug in an external loopback cable (1-3/2-6/ 4-7/5-8). 2. Set debug register bit 0xB[15] to 0 to disable hibernate (power saving) mode. 3. Set debug register bit 0x11[0] to 1 to enable external loopback. 4. Set register 0x0 to select loopback modes: – 1000M loopback: register 0x0 = 0x8140 – 100M loopback: register 0x0 = 0xA100 – 10M loopback: register 0x0 = 0x8100 NOTE: When cable is removed and then reconnected to 1000M mode, the register 0x0 must be configured again to 0x8140 to establish PHY link. 2.5.3 Remote PHY Loopback Remote PHY loopback connects the MDI receive path to the MDI transmit path, thus the remote link partner can detect the connectivity in the resulting loop. MAC/ Switch RGMII/ SGMII PHY Digital PHY AFE RJ-45 Figure 2-6 shows a block diagram of external cable loopback. Figure 2-6. Remote PHY Loopback To enable remote PHY loopback, set MMD3 register bit 0x805A[0] to 1. NOTE: When remote loopback is enabled, packets from link partner will still appear at RGMII interface. Remote loopback is independent of PHY auto-negotiation. 2.6 Cable Diagnostic Test The Cable Diagnostic Test (CDT) feature in the AR8031 device uses Time Domain Reflectometry (TDR) to identify remote and local PHY malfunctions, bad/marginal cable or patch cord segments, or connectors. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance 20 20 • • mismatch, bad connectors, termination mismatch, and bad magnetics. The CDT can be performed when there is no link partner or when the link partner is auto-negotiating. To perform the cable diagnostic test: 1. Set register bits 0x16[9:8] to select the MDI pair to be tested 2. Set register bit 0x16 to 1 to enable CDT 3. Check register bits 0x1C[9:8] for cable failure status. 4. Check register bits 0x1C[7:0] for delta time. The distance between the falure point and PHY is [delta time] * 0.824. 2.7 Fiber Mode Support Besides standard 10/100/1000 BASE-T copper port support, Both AR8031 and AR8031 provide additional IEEE 1000 BASE-X and 100 BASE-FX support in fiber applications through integrated SERDES. Both the AR8031 and the AR8033 can work in RGMII mode to fiber or 10/100/1000 BASE-T to fiber. Besides 1000 BASE-X and 100 BASE-FX support, Both devices will support IEEE 802.3 remote Fault Indication and fault propagation in fiber application. 2.7.1 IEEE 802.3 Remote Fault Indication Support Remote Fault allows stations on a fiber optic link to know when there is a problem on the link. Without Remote Fault, a station can not detect a problem that affects only one fiber (Transmit, for example). With Remote Fault, the loss of a Receive signal (Link) causes the Transmitter to send a special pattern of data indicating that a fault has occurred. 84 '1's followed by a single '0' is sent three times, in-band, and is readily detectable by the remote station, but is constructed so as to not satisfy the 100BASE-X carrier sense criterion, so the message will not be interpreted as normal traffic. If the remote station has Remote Fault, the link is dropped. If the remote station does not have Remote Fault, the special data pattern is ignored. The AR8031 indicates whether or not a Remote Fault pattern has been received from the remote station using the "Remote Fault Status Bit". This "Remote Fault Status Bit" can be "Propagated" (see below) to the copper links on both ends of a fiber link. In the event of a AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL detected fault, both ends of the link can be notified of the failure in this way. This is particularly useful given the distances fiber links are generally used over. Figure 2-7 shows the Fiber Fault mechanism. TwistedPair Fiber Fiber Far-End-Fault or Re-auto negotiation TwistedPair OFF RX TX RX TX TX RX TX RX 2.7.2 Fault Propagation The AR8031 supports Fault Propagation - this allows the fiber link fault to be propagated to the Twisted-pair copper connections where the "link down" status can be easily and quickly detected. The following steps describe Fault Propagation (for both 100 BASE-FX and 1000 BASE-X): The AR8031 supports Fault Propagation - this allows the fiber link fault to be propagated to the Twisted-pair copper connections where the "link down" status can be easily and quickly detected. The following steps describe Fault Propagation (for both 100 BASE-FX and 1000 BASE-X): n The Twisted-pair transmit path will be OFF n n n n n when the Receive path of the Fiber link has no signal detected or is link down. The two Fiber media types are then handled as described below: The Media Converter (in 100 BASE-FX mode) will transmit Far-End Fault message, on the TX pair, when the Receive path of Fiber has no signal detected or is link down. This alerts the Media Converter on the remote end of the link. The Transmit Twisted-pair will then be switched OFF on the remote end of the link. The Media Converter (in 1000 BASE-X mode) will restart auto-negotiation when the Receive path of the Fiber detects no signal or is link down. Auto-negotiation will carry remote fault indications from the Transmit fiber and the local station will restart auto-negotiation when its' Receive path has no detected signal or is link down. The Twisted-pair transmit path will be OFF when the Receive path of a 1000 BASE-X learns of the fault from an AN message. Atheros Communications, Inc. COMPANY CONFIDENTIAL OFF Figure 2-7. Fiber Fault Propagation or ReAuto-negotiation 2.8 LED Interface The LED interface can either be controlled by the PHY or controlled manually, independent of the state of the PHY. The LEDs have three status to indicate operation speed, traffic mode, and link status. The LEDs can be programmed to different status functions from their default value. Figure 2-8 and Figure 2-9 shows the references designs for the LED interface. AR8031 510 LED_ACT 470 pF 10 k  Figure 2-8. Reference Design for LED, Active High AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 21 21 VDDH_REG AR8031 The active status of LED_ACT and LED_LINK1000 depends on power-on strapping mode. When the interface is strapped high, the LED interface are active low; when strapped low, active high. The active status of LED_LINK10_100 depends on LED_LINK1000 power-on strapping mode and thus LED_LINK10_100 and LED_LINK1000 use the same LED reference design. 3.3 V 10 k  510  LED_ACT 470 pF Figure 2-9. Reference Design for LED, Active Low Table 2-4. LED Status Symbol 10M Link 10M Active 100M Link 100M Active 1000M Link 1000M Active LED_LINK10_100 OFF OFF ON ON OFF OFF LED_LINK1000 OFF OFF OFF OFF ON ON LED_ACT ON BLINK ON BLINK ON BLINK NOTE: ON = active; OFF = inactive 2.9 Power Supplies The AR8031 device requires only one 3.3 V external power supply. Internal power rails are 3.3 V, 2.5V, 1.1V and 1.8V/1.5V. AR8031 integrates a switch regulator to convert 3.3V to 1.1V with high efficiency for core power rail, thus external regulator is optional. Two on-chip LDOs are integrated to support 2.5V/1.5V/1.8V RGMII I/O voltages. AR8031 can also work at 2.5 V RGMII I/O voltage and 3.3 V MAC RGMII interface. Since the input can bear 3.3V logic signal, and the output logic VoH and VoL can satisfy the 3.3V LVCMOS/ LVTTL requirement. Refer to “Electrical Characteristics” for parameter details. 22 22 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Figure 2-10 shows the reference design for 2.5V/3.3V RGMII voltage level: AR8031 2.5V/3.3V RGMII Figure 2-10. Reference Design, 2.5 V/ 3.3 V RGMII I/O Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 23 23 Figure 2-11 shows the reference design for 1.5/1.8 V RGMII voltage level. AR8031 1.5/1.8V RGMII Figure 2-11. Reference Design, 1.5/1.8 V RGMII I/O 2.10 Management Interface output bi-directional signal that runs synchronously to MDC. AR8031 integrates an MDC/MDIO management interface in compliance with IEEE802.3u clause 22. MDIO is an OD-gate and requires an external 1.5k pull-up resistor. Table 2-5 shows the structure of the management frame. MDC is input clock reference provided by the MAC. MDIO is the management data input/ Table 2-5. Management Frame Fields PRE ST OP PHYAD REGAD TA DATA IDLE READ 1...1 01 10 AAAA A RRRRR Z0 DDDDDDDDDDDDDDDD Z WRITE 1...1 01 01 AAAA A RRRRR 10 DDDDDDDDDDDDDDDD Z 24 24 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table 2-6. Management Interface Field Definitions Field Definition PRE A sequence of 32 contiguous single logic bits on MDIO with corresponding cycles on MDC to provide PHY with a pattern to for synchronization. ST Start of frame OP Operation code. 10 = read transaction, 01 = write transaction PHYAD PHY address. The 5-bit PHY address is configured by power-on strapping. Three address bits can be configured in AR8031, thus eight PHYs can be connected to a single management interface. The PHYs connected to the same bus has unique PHY addresses. The first PHY address bit transmitted and received is the MSB of the address. REGAD Register address. The 5-bit register address allows 32 registers to be addressed at each PHY. The first register address bit transmitted and received is the MSB of the address. TA 2-bit field to avoid contention during a read operation. In read operation, both MAC and PHY are at high-impedance state for the first bit time. The PHY drives a zero during the second bit time of the turnaround. In write operation, the MAC must drive 10. DATA 16-bit data from accessed register. MSN is transmitted first. IDLE High-impedance without driving state of the MDIO. At least one clocked idle state is required between frames. Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 25 25 2.11 Timing Sychronization IEEE 1588v2 provides a mechanism to synchronize the clocks across an Ethernet network by exchanging the IEEE 1588v2 packets. The slave node can adjust the local clock based on the the timing information calculated from timestamps exchanged. Figure 3-8 shows the top-level use of the AR8031 to build a typical 1588v2 system. The AR8031 provides all the key componets to support an IEEE 1588v2 operation. The IEEE 1588v2 Real Time Clock (RTC) generates and provides time information to other modules and software, timing information includes Time of Day and PPS. IEEE 1588v2 Control accepts control information from software via MDC/MDIO, generates control signals to other modules, and provides status information to software. IEEE1588v2 Timestamp Unit, packet detction and processing, generates timestamps for IEEE 1588v2 event messages and interrupt signals when receiving or transmitting IEEE 1588v2 messages. The AR8031 supports ordinary, boundary and transparent clock modes as defined in IEEE 1588v2 Figure 3-9 shows the top level diagram of AR8031’s IEEE 1588v2 module. Also the AR8031 supports timestamps to be encapsulated into the 1588v2 packet as explained in the following figure. 26 26 • • AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Figure 2-12 Top Level Use of AR8031 in an IEEE 1588v2 system. Hardware AR8031 Line side RTC Software RGMII/ SGMII 1588v2 module OS Controller MAC 1588v2 Software SMI 1588 ref. Local PPS clock 25MHz (optional) Atheros Solution Figure 2-12. Top Level Use of AR8031 in an IEEE 1588v2 System Figure 2-13 shows the Top Level Diagram of the AR8031’s IEEE 1588v2 module. 1588v2 Module Time of Day IEEE 1588 Real Time Clock PPS MDC/MDIO RGMII/SGMII IEEE 1588 Control IEEE 1588 Timestamp Unit Packet Detection and Processing Figure 2-13. Top Level Diagram of the AR8031’s IEEE 1588v2 Module On the transmit side, the PHY will monitor and parse the incoming packet from the top layer, upon the request of sending IEEE 1588v2 packet, it will calculate the accurate time of transmission onto the media and a timestamp accordingly. Atheros Communications, Inc. COMPANY CONFIDENTIAL The AR8031 supports both one-step and twostep clock modes, as defined in IEEE 1588v2. No matter where accurate time information is carried — in the follow-up message (two-step clock mode) or in the single event message (one-step clock mode), the AR8031 will support AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 27 27 correction filed update and CRC recalculation on the fly. n Delay_Req On the receive side, the PHY will monitor and parse the incoming packet from media, and will generate a timestamp upon the reception of IEEE 1588v2 packets. The built-in parser is capable of detecting IEEE 1588v2 on ethernet layer 2 (including untagged, one VLAN tagged and two VLAN tagged), or layer 3 IPv4/UDP, and IPv6/UDP (including PPPoE and SNAP). Messages for the Peer Delay are also supported: The following IEEE 1588v2 packets are used to exchange the timing message for the delay request-response mechanism: n Sync n Delay_Resp n Pdelay_Req n Pdelay_Resp n Pdelay_Resp_Follow_Up The received IEEE 1588v2 packet along with the timestamp will be forwarded to an external CPU/MAC for further processing via accelerated MDC/MDIO interfaces (running up to 25MHz). The AR8031 also supports time-stamp encapsultion into the 1588v2 packet as explained in the following figure 3-10. n Follow_Up Figure 2-14. PTP Timestamp. L2/L3/L4 Header L2/L3/L4 Header PTP Message PTP Message 0 or more Pads 0 or more Pads CRC Remove Old CRC Re-calculate CRC Attached timestamps CRC 1. Event PTP message attach timestamp of itself. 2. General PTP message attach timestamp of associated event PTP message if existed. Figure 2-15. PTP Timestamp AR8031 provides a Pulse Per Second output, which locks onto the 1588v2 clock time of the device. 28 28 • • The AR8031 1588v2 logic allows multiple reference clock sources, including: n Local 25MHz crystal (default) AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL n Recovered clock from Sychronous Ethernet n Dedicated, external 50MHz ~ 125MHz 1588v2 reference clock The AR8031 IEEE 1588v2 module is under Tx FIFO, so the FIFO does not affect time stamping giving improved accuracy. Refer to Figure 3-11 below. Also, the IEEE 1588v2 module can be bypassed by register settings. Figure 2-16. Block Diagram of the AR8031 1588v2 module. Rx Tx RGMII/SGMII Tx FIFO 1588v2 IEEE 1588v2 module miiswitch Block Diagram: IEEE 1588v2 Module PCS Rx Tx Figure 2-17. Block Diagram of the AR8031’s IEEE 1588v2 Module 2.11.1 Synchronous Ethernet — Physical Layer Timing Synchronization Atheros Communications, Inc. COMPANY CONFIDENTIAL The AR8031 supports Synchronous Ethernet for 100BASE-TX and 1000BASE-T applications AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver August 2011 • • 29 29 by offering one recovered clock from the network line-side. This recovered clock output is register configurable to 25MHz (default), 50MHz, 62.5MHz or 125MHz, to meet the ITUT recommendations G.8261/Y.1361. The network node can use this recovered clock to replace local clock sources and drive the local system. Therefore all distributed nodes the network will use the same network clock to support synchronus and timing sensitive services like T1/E1 service over Ethernet. See Table 4.4.77 on page 112 “Clock Select for details. 2.12 Atheros Green EthosTM 2.12.1 Low Power Modes The AR8031 device supports the software power-down low power mode. The standard IEEE power-down mode is entered by setting the POWER_DOWN bit (bit [11]) of the register “Control” on page 18 equal to one. In this mode, the AR8031 ignores all MAC interface signals except the MDC/MDIO. It does not respond to any activity on the CAT 5 cable. The AR8031 cannot wake up on its own. It can only wake up by setting the POWER_DOWN bit of the “Control” register to 0. . 2.12.2 Shorter Cable Power Mode The AR8031 can attain an additional 25% power savings when a cable length is detected that is