AR8035-AL1B-R

Data Sheet March 2011 AR8035 Integrated 10/100/1000 Gigabit Ethernet Transceiver General Description The AR8035 is part of the Arctic family of devices - which includes the AR8031, AR8033, and the AR8035. It is Atheros’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™ The AR8035 provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc. function as the complete 802.3az system. The key features supported by the device are: n 10BASE-Te PHY supports reduced transmit amplitude. n 100BASE-Tx and 1000BASE-T use Low Power Idle (LPI) mode to turn off unused analog and digital blocks to save power while data traffic is in idle. Features n 10BASE-Te/100BASE-Tx/1000 BASE-T n n The AR8035 integrates Atheros latest Green Ethos® power saving technologies and significantly saves power not only during work time, but also during overtime. Atheros Green Ethos® power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length. Furthermore, the AR8035 supports Wake-on-LAN (WoL) feature to be able to help manage and regulate total system power requirements. n The AR8035 embeds CDT (Cable Diagnostics Test) technology on-chip which allows customers to measure cable length, detect the cable status, and identify remote and local PHY malfunctions, bad or marginal patch cord segments or connectors. Some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a bad transformer. n The AR8035 also integrates a voltage regulator on chip. It reduces the termination R/C circuitry on both the MAC interface (RGMII) and line side. n n n n n n n The AR8035 supports IEEE 802.3az Energy Efficient Ethernet (EEE) standard and Atheros proprietary SmartEEE, which allows legacy MAC/SoC devices without 802.3az support to n IEEE 802.3 compliant Supports 1000 BASE-T PCS and autonegotiation with next page support Supports RGMII interface to MAC devices with a broad I/O voltage level options including 2.5V, 1.8V and 1.5V, and is compatible with 3.3V I/O RGMII timing modes support internal delay and external delay on Rx path Error-free operation up to 140 meters of CAT5 cable n Supports Atheros latest Green Ethos® n n n n n power saving modes with internal automatic DSP power saving scheme Supports 802.3az (Energy Efficient Ethernet) Fully integrated digital adaptive equalizers, echo cancellers, and near end crosstalk (NEXT) cancellers Supports Wake-on-LAN (WoL) to detect magic packet and notify the sleeping system to wake up A robust Cable Discharge Event (CDE) tolerence of ± 6kV A robust surge protection with ±750V/ differential mode and ±4KV/common mode Jumbo Frame support up to 10KB (full duplex) All digital baseline wander correction Automatic channel swap (ACS) Automatic MDI/MDIX crossover Automatic polarity correction IEEE 802.3u compliant Auto-Negotiation Software programmable LED modes Multiple Loopback modes for diagnostics © 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®, Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, UNav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice. COMPANY CONFIDENTIAL • 1 n Cable Diagnostic Test (CDT) n Single power supply: 3.3V n 5mm x 5mm. 40-pin QFN package AR8035 Functional Block Diagram Symbol Encoder Waveshape Filter DAC Echo Canceller TRD[0:3] PMA Hybrid Circut PGA ADC Decision Feedback Equalizer Next Canceller Feed Forward Equalizer PCS Symbol Decoder Deskewer RGMII RGMII Trellis Decoder AGC Timing and Phase Recovery AutoNegotiation 2 2 • • MII Management Registers DLL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table of Contents General Description ........................................ 1 Features ............................................................ 1 AR8035 Functional Block Diagram .............. 2 3.4 MDIO Characteristics ............................ 22 1 Pin Descriptions ............................ 3 3.7 Typical Power Consumption Parameters 25 2 Functional Description ................. 9 3.8 Power-on Sequence, Reset and Clock . 26 3.8.1 Power-on Sequence .................... 26 3.8.2 Reset and Clock Timing ............. 26 2.1 Transmit Functions ................................ 10 2.2 Receive Functions .................................. 10 2.2.1 Decoder Modes ........................... 10 2.2.2 Analog to Digital Converter ...... 10 2.2.3 Echo Canceller ............................. 10 2.2.4 NEXT Canceller .......................... 10 2.2.5 Baseline Wander Canceller ....... 10 2.2.6 Digital Adaptive Equalizer ....... 10 2.2.7 Auto-Negotiation ........................ 11 2.2.8 Smartspeed Function ................. 11 2.2.9 Automatic MDI/MDIX Crossover 11 2.2.10 Polarity Correction ..................... 11 2.3 Loopback Modes .................................... 11 2.3.1 Digital Loopback ......................... 11 2.3.2 External Cable Loopback ........... 11 2.3.3 Remote PHY Loopback .............. 12 2.4 Cable Diagnostic Test ............................ 12 2.5 LED Interface .......................................... 12 2.6 Power Supplies ....................................... 14 2.7 Management Interface .......................... 15 2.8 Atheros Green Ethos® .......................... 16 2.8.1 Low Power Modes ...................... 16 2.8.2 Shorter Cable Power Mode ....... 16 2.8.3 Hibernation Mode ...................... 16 2.9 IEEE 802.3az and Energy Efficient Ethernet 17 2.9.1 IEEE 802.3az LPI Mode .............. 17 2.10 Atheros SmartEEE ................................ 18 2.11 Wake On LAN (WoL) ........................... 18 3 Electrical Characteristics ............ 19 3.1 Absolute Maximum Ratings ................ 19 3.2 Recommended Operating Conditions 19 3.3 RGMII Characteristics ........................... 20 Atheros Communications, Inc. COMPANY CONFIDENTIAL 3.5 XTAL/OSC characteristic table ........... 23 3.6 Power Pin Consumption ...................... 24 4 Register Descriptions ..................27 4.1 Register Summary ................................. 27 4.1.1 Control ......................................... 28 4.1.2 Status ............................................ 30 4.1.3 PHY Identifier [18:3] .................. 31 4.1.4 PHY Identifier [19:24] ................ 31 4.1.5 Auto-Negotiation Advertisement 31 4.1.6 Link Partner Ability (Base Page) 33 4.1.7 Auto-Negotiation Expansion .... 34 4.1.8 Next Page Transmit .................... 34 4.1.9 Link Partner Next Page ............. 35 4.1.10 1000 BASE-T Control ................. 35 4.1.11 1000 BASE-T Status .................... 37 4.1.12 MMD Access Address Register 38 4.1.13 MMD Access Control Register . 38 4.1.14 Extended Status .......................... 39 4.1.15 Function Control ......................... 39 4.1.16 PHY-Specific Status .................... 40 4.1.17 Interrupt Enable .......................... 41 4.1.18 Interrupt Status ........................... 42 4.1.19 Smart Speed ................................. 43 4.1.20 Cable Diagnostic Tester Control 43 4.1.21 LED Control ................................ 44 4.1.22 Cable Defect Tester Status ......... 45 4.1.23 Debug Port Address Offset ....... 45 4.1.24 Debug Port Data ......................... 45 4.2 Debug Register Descriptions ............... 46 4.2.25 rgmii rx clock delay control ...... 46 4.2.26 rgmii tx clock delay control ...... 46 4.2.27 Hib ctrl and rgmii gtx clock delay register ......................................... 47 4.2.28 100BASE-TX Test Mode Select . 48 4.2.29 1000BT external loopback AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 1 1 configure ...................................... 48 4.2.30 Rgmii_mode; Test configuration for 10BT .............................................. 49 4.2.31 MMD3 (MDIO Manageable Device Address 3 for PCS) ..................... 49 4.2.32 MMD7 (MDIO Manageable Device Address 7 for Auto-Negotiation) 50 5 MDIO Interface Register ........... 51 5.1 MMD3 - PCS Register ............................ 51 5.1.1 PCS Control 1 .............................. 51 5.1.2 PCS Status 1 ................................. 52 5.1.3 EEE Capability ............................ 53 5.1.4 EEE Wake Error Counter ........... 53 5.1.5 Wake-on-Lan loc_mac_addr_o . 54 5.1.6 Wake-on-Lan loc_mac_addr_o . 54 5.1.7 . Wake-on-Lan loc_mac_addr_o 54 5.1.8 Rem_phy_lpkb ............................ 55 5.1.9 Smart_eee control1 ..................... 55 5.1.10 Smart_eee control2 ..................... 55 5.1.11 Smart_eee control3 ..................... 56 5.1.1 AN status ..................................... 57 5.1.1 AN XNP transmit1 ..................... 57 5.1.1 AN XNP transmit2 ..................... 57 5.1.2 EEE advertisement ..................... 58 5.1.3 EEE LP advertisement ................ 58 6 Package Dimensions ..................... 1 7 Ordering Information ................... 1 8 Top-side Marking ......................... 1 2 2 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 1. Pin Descriptions This section contains a package pinout for the AR8035 QFN 40 pin and a listing of the signal descriptions (see Figure 1-1). The following nomenclature is used for signal types described in Table 1-1: The following nomenclature is used for signal names: D Open drain IA Analog input signal NC No connection to the internal die is made from this pin I Digital input signal n At the end of the signal name, indicates active low signals IH Input signals with weak internal pull-up, to prevent signals from floating when left open P At the end of the signal name, indicates the positive side of a differential signal IL Input signals with weak internal pull-down, to prevent signals from floating when left open N At the end of the signal name indicates he negative side of a differential signal I/O A digital bidirectional signal OA An analog output signal O A digital output signal P A power or ground signal PD Internal pull-down for input PU Internal pull-up for input Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 3 3 TXD0 GTX_CLK TX_EN RX_CLK TXD3 TXD2 TXD1 DVDDL MDC MDIO Figure 1-1 shows the pinout diagram for the AR8035. 40 39 38 37 36 35 34 33 32 31 RSTn 1 30 RX_DV 29 RXD0 LX 2 VDD33 3 XTLO 4 XTLI 5 AVDDL 6 RBIAS 7 VDDH_REG 8 TRXP0 9 28 RXD1 27 VDDIO_REG AR 8035 TOP VIEW EXPOSED GROUND PAD ON BOTTOM 26 RXD2 25 RXD3 24 LED_10_100 23 CLK_25M 22 LED_1000 TRXN0 10 21 LED_ACT INT TRXN3 AVDDL TRXP3 TRXN2 AVDD33 TRXP2 TRXP1 TRXN1 AVDDL 11 12 13 14 15 16 17 18 19 20 Figure 1-1. Pinout Diagram NOTE: There is an exposed ground pad on the back side of the package. 4 4 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Symbol Pin Type Description TRXP0, TRXN0 9, 10 IA, OA Media-dependent interface 0, 100 transmission line TRXP1, TRXN1 12, 13 IA, OA Media-dependent interface 1, 100  transmission line TRXP2, TRXN2 15, 16 IA, OA Media-dependent interface 2, 100  transmission line TRXP3, TRXN3 18, 19 IA, OA Media-dependent interface 3, 100  transmission line GTX_CLK 33 I, PD RGMII transmit clock, 125 MHz digital. Adding a 22 damping resistor is recommended for EMI design near MAC side. RX_CLK 31 I/O, PD 125MHz digital, adding a 22 damping resistor is recommended for EMI design near PHY side. RX_DV 30 I/O, PD RGMII receive data valid RXD0 29 I/O, PD RGMII received data 0 RXD1 28 I/O, PD RGMII received data 1 RXD2 26 I/O, PD RGMII received data 2 RXD3 25 I/O, PD RGMII received data 3 TX_EN 32 I, PD RGMII transmit enable TXD0 34 I, PD RGMII transmit data 0 TXD1 35 I, PD RGMII transmit data 1 TXD2 36 I, PD RGMII transmit data 2 TXD3 37 I, PD RGMII transmit data 3 MDI RGMII Management Interface and Interrupt MDC 40 I, PU Management data clock reference MDIO 39 I/O, D, PU Management data, 1.5K pull-up to 3.3V/2.5V INT 20 I/O, D, PD Interrupt Signal to System; default OD-gate, needs an external 10K pull-up, active low; can be configured to I/O by register, active high. LED LED_ACT 21 I/O, PU Parallel LED output for 10/100/1000 BASE-T activity, active blinking. LED active based upon power-on strapping. If pulled up — active low, if pulled down — active high LED_1000 22 I/O, PU Parallel LED output for 1000 BASE-T link, LED active based upon power-on strapping. If pulled up — active low, if pulled down — active high Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 5 5 Symbol Pin Type LED_10_100 24 I/O, PU Description Parallel LED output for 10/100 BASE-T link. LED active based upon power-on strapping of LED_1000. If LED_1000 is pulled up,this pin is active low; If LED_1000 is pulled-down, active high. High, external PU 10 Mbps Low, external PU 100 Mbps System Signal Group/Reference CLK_25M 23 O, PD 25 MHz clock output (default). It can be 125, 62.5 or 50 MHz clock output RSTn 1 I XTLI 5 IA Crystal oscillator input. Requries a 27 pF capacitor to GND. Support external 25 MHz, 1.2V swing clock input through this pin. XTLO 4 OA Crystal oscillator output; 27 pF to GND RBIAS 7 OA External 2.37 k 1% to GND to set bias current LX 2 OA Power inductor pin. Add an external 4.7 uH power inductor between this pin and pin 38. VDDH_REG 8 OA 2.5 V regulator output. A 1uF capacitor connected to this pin VDDIO_REG 27 OA 1.5V/1.8V regulator output.If RGMII interface voltage level is 2.5V, connect this pin to pin 8 directly. AVDDL 6, 11, 17 P 1.1 V analog power input. Connect to Pin 38 through a bead DVDDL 38 P 1.1 V digital core power input. Connect to power inductor and 10uF+0.1uF ceramic capacitors to GND VDD33 3 P 3.3 V power for switching regulator AVDD33 14 P Analog 3.3 V power input for PHY, from VDD33 through a bead System reset, active low. Requires an external pull-up resistor Power - 6 6 • • - Exposed ground pad on back of the chip, tie to ground AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL PHY Pin PHY Core Config Signal RXD0 PHYADDRESS0 RXD1 PHYADDRESS1 LED_ACT PHYADDRESS2 Description Default Internal Weak Pullup/Pulldown LED_ACT, RXD[1:0] sets the lower three bits of the physical address. The upper two bits of the physical address are set to the default, “00” 0 0 1 RX_DV MODE0 mode select bit 0 0 RXD2 MODE1 mode select bit 1 0 LED_1000 MODE2 mode select bit 2 1 RXD3 MODE3 mode select bit 3 0 Select the RGMII/RMII I/O voltage level 1: 1.8V I/O 0: 1.5V I/O 0 RX_CLK 1.8V/1.5V NOTE: 0=Pull-down, 1=Pull-up NOTE: Power on strapping pins are latched during power-up reset or warm hardware reset. NOTE: Some MAC devices input pins may drive high/low during power-up or reset. So PHY power on strapping status may be affected by the MAC side. In this case an external 10k pull-down or pull-high resistor is needed to ensure a stable expected status. NOTE: When using 2.5V RGMII I/O voltage level, RX_CLK can be pull-up or pull-down. Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 7 7 MODE[3:0] Description 1100 RGMII, PLLOFF, INT; 1110 RGMII, PLLON, INT; Others Reserved NOTE: PLLOFF means AR8035 can shut down internal PLL in power saving mode; In PLLOFF mode, when the AR8035 enters power saving mode (hibernation), CLK_25m output drops periodically, which saves more power. In PLLON mode, CLK_25M outputs continuously. 8 8 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 2. Functional Description The AR8035 is Atheros's low cost GbE PHY. It is a highly integrated analog front end (AFE) and digital signal transceiver, providing high performance combined with substantial cost reduction. The AR8035 provides physical layer functions for half/full -duplex 10 BASE-Te, 100 BASE-Tx and 1000 BASE-T Ethernet to transmit and receive high-speed data over standard category 5 (CAT5) unshielded twisted pair cable. The AR8035 10/100/1000 PHY is fully 802.3ab compliant, and supports the reduced Gigabit Media-Independent Interface (RGMII) to connect to a Gigabit-capable MAC. The AR8035 transceiver combines echo canceller, near end cross talk (NEXT) canceller, feed-forward equalizer, joint Viterbi, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments. The AR8035 is a part of the Arctic family of devices — which includes the AR8031, the AR8033, and the AR8035. A comparison of these is shown below. Table 2-1 shows a feature comparison across the AR8031, AR8033, and AR8035 family. Table 2-1. AR8031, AR8033, AR8035 Comparison Feature AR8031 AR8033 AR8035 RGMII yes yes yes SGMII yes yes Cu Ethernet** yes yes yes EEE (802.3az) yes yes yes Wake-on-LAN yes yes yes SERDES/Fiber yes*** yes*** 1588v2 yes Sync-E yes yes 48-pin 48-pin Packaging 40-pin NOTE: AR8031, AR8033 is pin-to-pin compatible NOTE: ** 10BASE-Te, 100BASE-TX, 1000BASE-T will be supported NOTE: *** 100BASE-FX, and 1000BASE-X will be supported Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 9 9 2.1 Transmit Functions 2.2.2 Analog to Digital Converter Table 2-2 describes the transmit function encoder modes. The AR8035 device employs an advanced high speed ADC on each receive channel with high resolution, which results in better SNR and lower error rates. Table 2-2. Transmit Encoder Modes Encoder Mode Description 1000 BASE-T In 1000 BASE-T mode, the AR8035 scrambles transmit data bytes from the MAC interfaces to 9-bit symbols and encodes them into 4D five-level PAM signals over the four pairs of CAT5 cable. 100 BASE-TX In 100 BASE-TX mode, 4-bit data from the MII is 4B/5B serialized, scrambled, and encoded to a three-level MLT3 sequence transmitted by the PMA. 10 BASE-Te In 10 BASE-Te mode, the AR8035 transmits and receives Manchester-encoded data. 2.2 Receive Functions 2.2.1 Decoder Modes Table 2-3 describes the receive function decoder modes. Table 2-3. Receive Decoder Modes Decoder Mode Description 1000 BASE-T In 1000 BASE-T mode, the PMA recovers the 4D PAM signals after accounting for the cabling conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs. The resulting code group is decoded into 8-bit data values. Data stream delimiters are translated appropriately and data is output to the MAC interfaces. 100 BASE-TX In 100 BASE-TX mode, the receive data stream is recovered and descrambled to align to the symbol boundaries. The aligned data is then parallelized and 5B/ 4B decoded to 4-bit data. This output runs to the MII receive data pins after data stream delimiters have been translated. 10 BASE-Te 10 10 • • In 10 BASE-Te mode, the recovered 10 BASE-Te signal is decoded from Manchester then aligned. 2.2.3 Echo Canceller A hybrid circuit is used to transmit and receive simultaneously on each pair. A signal reflects back as an echo if the transmitter is not perfectly matched to the line. Other connector or cable imperfections, such as patch panel discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic SNR degradation on the receive signal. The AR8035 device implements a digital echo canceller to adjust for echo and is adaptive to compensate for the varied channel conditions. 2.2.4 NEXT Canceller The 1000 BASE-T physical layer uses all four pairs of wires to transmit data. Because the four twisted pairs are bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. The AR8035 device uses three parallel NEXT cancellers on each receive channel to cancel high frequency crosstalk. The AR8035 cancels NEXT by subtracting an estimate of these signals from the equalizer output. 2.2.5 Baseline Wander Canceller Baseline wander results from Ethernet links that AC-couple to the transceivers and from AC coupling that cannot maintain voltage levels for longer than a short time. As a result, transmitted pulses are distorted, resulting in erroneous sampled values for affected pulses. Baseline wander is more problematic in the 1000 BASE-T environment than in 100 BASETX due to the DC baseline shift in the transmit and receive signals. The AR8035 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizing the impact of DC baseline shift on the overall error rate. 2.2.6 Digital Adaptive Equalizer The digital adaptive equalizer removes intersymbol interference at the receiver. The digital adaptive equalizer takes unequalized signals from ADC output and uses a combination of feedforward equalizer (FFE) and decision AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL feedback equalizer (DFE) for the bestoptimized signal-to-noise (SNR) ratio. on the receive pairs in 1000 BASE-T, 100 BASETX and 10 BASE-Te modes. 2.2.7 Auto-Negotiation 2.3 Loopback Modes 2.3.1 Digital Loopback The AR8035 device supports 10/100/1000 BASE-T Copper auto-negotiation in accordance with IEEE 802.3 clauses 28 and 40. Autonegotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. Auto-negotiation is initiated upon any of the following scenarios: n Power-up reset n Hardware reset n Software reset n Auto-negotiation restart n Transition from power-down to power-up n The link goes down If auto-negotiation is disabled, a 10 BASE-Te or 100 BASE-TX can be manually selected using the IEEE MII registers. Digital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the AR8035 device. Figure 21 shows a block diagram of a digital loopback. MAC/ Switch RGMII PHY Digital PHY AFE Figure 2-1. Digital Loopback n 1000M loopback: write register 0x0 = 0x4140 to enable 1000M digital loopback. n 100M loopback: write register 0x0 = 0x6100 to enable 100M digital loopback. The Atheros Smartspeed function is an enhanced feature of auto-negotiation that allows the AR8035 device to fall back in speed based on cabling conditions as well as operate over CAT3 cabling (in 10 BASE-T mode) or two-pair CAT5 cabling (in 100 BASE-TX mode). By default, the Smartspeed feature is enabled. Refer to the register “Smart Speed” on page 43, which describes how to set the parameters. Set these register bits to control the Smartspeed feature: n Bit [5]: 1 = Enables Smartspeed (default) n Bits [4:2]: Sets the number of link attempts before adjusting n Bit [1]: Timer to determine the stable link condition n 10M loopback: write register 0x0 = 0x4100 to enable 10M digital loopback. 2.3.2 External Cable Loopback External cable loopback loops Tx to Rx through a complete digital and analog path and an external cable, thus testing all the digital data paths and all the analog circuits. Figure 2-2 shows a block diagram of external cable loopback. MAC/ Switch RGMII/ SGMII PHY Digital PHY AFE RJ-45 2.2.8 Smartspeed Function 2.2.9 Automatic MDI/MDIX Crossover During auto-negotiation, the AR8035 device automatically determines and sets the required MDI configuration, eliminating the need for external crossover cable. If the remote device also implements automatic MDI crossover, the crossover algorithm as described in IEEE 802.3 clause 40.4.4 ensures that only one device performs the required crossover. Figure 2-2. External Cable Loopback 1. Plug in an external loopback cable (1-3/2-6/ 4-7/5-8) 2. Write debug register 0xB[15] = 0 to disable hibernate (power-saving mode) 2.2.10 Polarity Correction 3. Write debug register 0x11[0] = 1 to enable external loopback If cabling has been incorrectly wired, the AR8035 automatically corrects polarity errors 4. Select wire speed, as follows: Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 11 11 n 1000M loopback: write register 0x0 = 0x8140 to set 1000M external loopback n 100M loopback: write register 0x0 = 0xA100 to set 100M external loopback n 10M loopback: write register 0x0 = 0x0x8100 to set 10M external loopback 5. When the cable in 1000M mode is replugged, need to write 0x0 = 0x8140 again to make the PHY link. 2. Write register 0x16[0]=1 to enable CDT 3. Check register 0x1C[9:8] for fail status 4. Check register 0x1C[7:0] to get delta time. The distance between the fail point and PHY is delta time *0.842 2.5 LED Interface The Remote loopback connects the MDI receive path to the MDI transmit path, near the RGMII interface, thus the remote link partner can detect the connectivity in the resulting loop. Figure 2-3, below, shows the path of the remote loopback. The LED interface can either be controlled by the PHY or controlled manually, independent of the state of the PHY. Three status LEDs are available. These can be used to indicate operation speed, duplex mode, and link status. The LEDs can be programmed to different status functions from their default value. They can also be controlled directly from the MII register interface. Figure 2-3 shows a block diagram of external cable loopback. The reference design schematics for the AR8035’s LEDs are shown 2.3.3 Remote PHY Loopback MAC/ Switch RGMII/ SGMII PHY Digital PHY AFE RJ-45 Figure 2-4 Reference Design Schematic — Active Low Figure 2-3. Remote PHY Loopback n Write MMD3 register 0x805A[0]= 1 to Figure 2-4. Reference Design Schematic — enable remote PHY loopback. Please note: The packets from link partner will still appear at RGMII interface when remote loopback is enabled. Active Low Also, remote loopback is independant of PHY auto-negotiation. Figure 2-5 Reference Design Schematic — Active High 2.4 Cable Diagnostic Test The Cable Diagnostic Test (CDT) feature in the AR8035 device uses Time Domain Reflectometry (TDR) to identify remote and local PHY malfunctions, bad/marginal cable or patch cord segments, or connectors. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and bad magnetics. The CDT can be performed when there is no link partner or when the link partner is auto-negotiating. 1. Set register 0x16[9:8] to select MDI pair under test 12 12 • • Figure 2-5. Reference Design Schematic — Active High LED_ACT/LED_1000 active states depend on power on strapping mode. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL So LED_10_100 and LED_1000 should have the same LED design. When strapped high, active low. When strapped low, active high. LED_10_100 depends on LED_1000 power on strapping mode. Symbol 10M 10M 100M link 100M active 1000M link 1000M active link active LED_10_10 0 off off on on off off LED_1000 off off off off on on LED_ACT on blink on blink on blink NOTE: Notes: on=active off=inactive Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 13 13 2.6 Power Supplies voltage. Also with 2.5V RGMII I/O voltage configuration AR8035 can work with a 3.3V MAC RGMII interface — because the input can bear 3.3V logic signal, and the output logic VoH and VoL can satisfy the 3.3V LVCMOS/ LVTTL requirement. The parameter details are in the Electrical Characteristics chapter. The AR8035 device requires only one external power supply: 3.3 V. Inside the chip there is a 3.3V rail, 2.5V rail, 1.1V rail and a 1.8V/1.5V rail. AR8035 integrates a switch regulator which converts 3.3V to 1.1V at a high-efficiency for core power rail. (It is optional for an external regulator to provide this core voltage). Reference design for 2.5V RGMII voltage level is shown below: The AR8035 integrates two on chip LDOs which can support 2.5V; 1.5V/1.8V RGMII I/O Figure 2-6 shows the AR8035 reference design for a 2.5V RGMII voltage level. 4.7uH 0.1uF 10uF DVDDL 0.1uF LX VDD33 Arctic 2.5V RGMII Bead 10uF0.1uF AVDDL 0.1uF VDDIO_REG 0.1uF VDDH_REG 0.1uF AVDDL AVDDL AVDD33 1uF 0.1uF 3.3V input Bead 0.1uF 1uF Figure 2-6. AR8035 reference design for a 2.5V RGMII voltage level Reference design for 1.5/1.8V RGMII voltage level is shown below: 14 14 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Figure 2-7 shows the AR8035 reference design for a 1.5/1.8V RGMII voltage level. 4.7uH 0.1uF 10uF DVDDL 0.1uF LX VDD33 VDDIO_REG Arctic 1.5/1.8V RGMII Bead 10uF0.1uF AVDDL 0.1uF 1uF VDDH_REG 0.1uF AVDDL AVDDL AVDD33 0.1uF 0.1uF 3.3V input 0.1uF Bead 1uF Figure 2-7. AR8035 reference design for a 1.5/1.8V RGMII voltage level 2.7 Management Interface The AR8035 integrates an MDC/MDIO management interface which is compliant with IEEE802.3u clause 22. MDC is an input clock reference provided by the MAC. MDIO is the management data input/output bi-directional signal that runs synchronously to MDC. MDIO is an OD-gate, needs an external 1.5k pull-up resistor. Definition of the management frame is shown below. Figure 2-8 shows the AR8035 Management frame fields. Figure 2-8. AR8035 Management Frame Fields Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 15 15 1. PRE is a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use to establish synchronization. MMD register access: 2. ST is start of frame 1. Write 0x3 to register 0xD: 0xD=0x0003;(function= address; set the device address) 3. OP is the operation code. The operation code for a read transaction is , while the operation code for a write transaction is . 4. PHYAD is 5 bits PHY address. PHY address of AR8035 is configured by power on strapping. There are three address bits can be configured in AR8035 which means 8 PHYs can be connected to the same management interface. Each PHY connected to the same bus line should have a unique PHY address. The first PHY address bit transmitted and received is the MSB of the address. 5. The Register Address is five bits, allowing 32 individual registers to be addressed within each PHY. The first Register Address bit transmitted and received is the MSB of the address. 6. TA is 2 bits to avoid contention during a read operation. For a read operation, both the MAC and PHY shall remain in a highimpedance state for the first bit time. The PHY shall drive a zero during the second bit time of the turnaround. During a write transaction, the MAC must drive 10. 7. Data is the 16 bits data from accessed register. MSB is transmitted first. 8. Idle is a high-impedance without driving state of the MDIO. At least one clocked idle state is required between frames. There are three kinds of registers in AR8035. All can be accessed using the management frames. See detail in register description example: Write 0x8000 to Register 0 of MMD3 2. Write 0x0 to register 0xE: 0xE=0x0; (set the register offset address) 3. Write 0x4003 to register 0xD:0xD=0x4003;(function=data; keep the device address) 4. Read register 0xE:0xE==(data from register 0x0 of MMD3) 5. Write 0x8000 to register 0xE :0xE=0x8000(write 0x8000 to register 0x0 of MMD3) Please Note: Read operation please refers to process 1 ~ 4 2.8 Atheros Green Ethos® 2.8.1 Low Power Modes The AR8035 device supports the software power-down low power mode. The standard IEEE power-down mode is entered by setting the POWER_DOWN bit (bit [11]) of the register “Control” equal to one. In this mode, the AR8035 ignores all MAC interface signals except the MDC/MDIO. It does not respond to any activity on the CAT 5 cable. The AR8035 cannot wake up on its own. It can only wake up by setting the POWER_DOWN bit of the “Control” register to 0, or a Hardware Reset See Table 4.1.15 on page 39. 2.8.2 Shorter Cable Power Mode MII register can be access directly through the frame defined above. With Atheros latest propriatary Green Ethos® power saving technology, the AR8035 can attain an additional 25% power savings when a cable length is detected that is < 30M vs. stantard power consumption for a 100M Cat5 cable. The equals and additional 100mW power savings and less than 350mW total power for 1000BASE-T mode in a typical home application. Debug register access: 2.8.3 Hibernation Mode 1. Write the debug offset address to 0x1D The AR8035 supports hibernation mode. When the cable is unplugged, the AR8035 will enter hibernation mode after about 10 seconds. The 1. IEEE defined 32 MII registers. 2. Atheros defined Debug registers. 3. IEEE defined MDIO Manageable Device (MMD) register 2. Read/ Write the data from/to 0x1E 16 16 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL power consumption in this mode can go as low as 10mW only when compared to the normal mode of aperation. When the cable is reconnected, the AR8035 wakes up and normal functioning is restored. 2.9 IEEE 802.3az and Energy Efficient Ethernet At the link start up, both link partners exchange information via auto neg to determine if both parties are capable of entering LPI mode. Legacy Ethernet products are supported, and this is made transparent to the user. 2.9.1 IEEE 802.3az LPI Mode IEEE 802.3az provides a mechanism to greatly save the power consumption between data packets bursts. The link partners enter Low Power Idle state by sending short refresh signals to maintain the link. AR8035 works in the following modes when 802.3 az feature is turned on: There are two operating states, Active state for normal data transfer, and Low-power state between the data packet bursts. n Quiet: No signal transmitted on media, n Active: the regular mode to transfer data n Sleep: send special signal to inform remote link of entry into low-power state most of the analog and digital blocks are turned off to reduce energy. n Refresh: send periodically special training signal to maintain timing recovery and equalizer coefficients n Wake: send special wakup signal to remote link to inform of the entry back into Active. In the low-power state, PHY shuts off most of the analog and digital blocks to reserve energy. Due to the bursty traffic nature of Ethernet, system will stay in low-power mode in the most of time, thus the power saving can be more than 90%. Figure 2-9 shows the 802.3az operating states for the AR8035. O perating States Td Active Existing state used for data transm ission . Data packets or IPG /Idle sym bols are transm itted Active Quiet Tw Quiet Quiet Wake Tr Refresh Sleep Tq Refresh Ts New state used during periods of no data transm ission to allow system power reduction between data packet bursts Low-Power Figure 2-9. Operating States — 802.3az LPI Mode Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 17 17 Figure 2-10 shows the 802.3az operating power modes — 802.3az for the AR8035. Ts Active Quiet Quiet Low-Power Active Quiet Tw Wake Tr Refresh Sleep Active Tq Refresh Td Active Figure 2-10. Operating Power Modes — 802.3az LPI Mode The AR8035 supports both 100BASE-TX EEE and 1000BASE-T EEE. 100BASE-TX EEE allows asymmetrical operation, which allows each link partner to enter the LPI mode independent of the other partner. 1000BASE-T EEE requires symmetrical operation, which means that both link partners must enter the LPI mode simultaneously. 2.10 Atheros SmartEEE AR8035 SmartEEE is compatible with normal 802.3az standard. It helps legacy MAC without EEE ability to work as a complete EEE power saving system. AR8035 SmartEEE will detect egress data flow, if there are no packets to transfer after a defined time which are cofigurable based on system design, it will enter EEE mode. If there are packets need to transfer, AR8035 will wait typically 16.5us to wake up as 802.3az defined and send out datas after the timer configuration in register. It provides a 2048*20bit buffer for egress data before waking up to ensure no packet loss. AR8035 default mode enables smart EEE after power on or hardware reset. Working in smartEEE, AR8035 RX side will not generate MDI LPI pattern. So only normal packets and idle packets will appear on the RGMII inteface. There is no TX LPI pattern at all if MAC has no EEE capability. LPI is generated inside PHY according to smartEEE mechanism. Please Note: 1. Wait time before entering EEE mode is in register MMD3 0x805c,0x805d[7:0]; 2. Adjustable wait time before sending out data is in register MMD3 0x805b, To cooperate with link partner for special requirement. 2.11 Wake On LAN (WoL) Originally Wake-on-LAN (WoL) was an Ethernet networking standard that allowed a computer to be turned on (or woken up) by a network message for Adminstrator attention, etc. However as part of the latest industry trend towards energy savings, WoL gets wide interest to be adopted across networking systems as a mechanism to help to manage and regulate the total power consumed by the network. The AR8035 supports Wake-on-LAN (WoL): n Able to enter the sleep/isolate state (PHY’s all TX bus (including clock) are in High-Z state, but PHY can still receive packets) by ISOLATE bit in MII register configuration n Consumes less than 50mW when in sleep/ isolate mode n Supports automatic detection of magic packets (a specific frame containing anywhere within its payload: 6 bytes of ones (resulting in hexadecimal FF FF FF FF FF FF), followed by sixteen repetitions of the target computer's MAC address) and notification via hardware interrupt. n Supports exit from the sleep state, by register configuration If the MAC has EEE capability, can write SmartEEE control register to bypass SmartEEE function. 18 18 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 3. Electrical Characteristics 3.1 Absolute Maximum Ratings Table 3-1 summarizes the absolute maximum ratings and Table 3-2 lists the recommended operating conditions for the AR8035. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. Table 3-1. Absolute Maximum Ratings Symbol Parameter Max Rating Unit VDD33 3.3V analog supply voltage 3.8 V AVDD 1.1V analog supply voltage 1.6 V DVDD 1.1V digital core supply voltage 1.6 V Tstore Storage temperature –65 to 150 °C HBM Electrostatic discharge tolerance - Human Body Model ±2kV V MM Machine Model ±200V V CDM Charge Device Model ±500V V 3.2 Recommended Operating Conditions Table 3-2. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD33/AVDD33 3.3V supply voltage 3.14 3.3 3.47 V AVDDL/DVDDL 1.1V digital core supply voltage 1.04 1.1 1.17 V TA Ambient temperature for normal opteraiton - Commercial chip version 0 — 70 C TA Ambient temperature for normal opteraiton - Industrial chip version -40 — 85 C TJ Junction temperature -40 — 125 C JT Thermal Dissipation Coefficient — 4 — C/W NOTE: The following condition must be satisfied: TJmax > TCmax + JT x PTypical Where: TJmax = maximum allowable temperature of the Junction TCmax = Maximum allowable case temperature JT = Thermal Dissipation Coefficient PTypical = Typical power dissapation Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 19 19 3.3 RGMII Characteristics Table 3-3 shows the RGMII DC characteristics with 2.5/3.3V I/O supply. Table 3-3. RGMII DC Characteristics — 2.5/3.3V I/O Supply Symbol Parameter Min Max Unit IIH Input high current — 15 A IIL Input low current –15 — A VIH Input high voltage 1.7 3.5 V VIL Input low voltage — 0.7 V VOH Output high voltage 2.4 2.8 V VOL Output low voltage GND – 0.3 0.4 V Table 3-4 shows the RGMII DC characteristics with 1.8V I/O supply. Table 3-4. RGMII DC Characteristics — 1.8V I/O Supply Symbol Parameter Min Max Unit VIH Input high voltage 1.4 — V VIL Input low voltage — 0.4 V VOH Output high voltage 1.5 — V VOL Output low voltage — 0.3 V Table 3-5 shows the RGMII DC characteristics with 1.5V I/O supply. Table 3-5. RGMII DC Characteristics — 1.5 I/O Supply 20 20 • • Symbol Parameter Min Max Unit VIH Input high voltage 1.2 — V VIL Input low voltage — 0.3 V VOH Output high voltage 1.3 — V VOL Output low voltage — 0.2 V AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Figure 3-1 shows the RGMII AC timing diagram — no internal delay. RX_CLK, GTX_CLK TskewT TXD[3:0], RXD[3:0] RX_DV, TX_EN RX_CLK, GTX_CLK TskewR Figure 3-1. RGMII AC Timing Diagram — no Internal Delay Table 3-6 shows the RGMII AC characteristics. Table 3-6. RGMII AC Characteristics — no Internal Delay Symbol Parameter Min Typ Max Unit -500 0 500 ps 1 — — ns Clock cycle duration 7.2 8.0 8.8 ns Duty_G Duty cycle for Gigabit 45 50 55 % Duty_T Duty cycle for 10/100T 40 50 60 % Rise/Fall time (20 - 80%) — — 0.75 ns TskewT Data to clock output skew (at Transmitter) TskewR Data to clock output skew (at Receiver) Tcyc Tr/Tf Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 21 21 Figure 3-2 shows the RGMII AC timing diagram with internal delay added (default RGMII timing). RXC with internal delay added RX_CLK RXD[3:0], RX_DV TsetupT TholdT TXD[3:0], TX_EN TholdR GTX_CLK TsetupR Figure 3-2. RGMII AC Timing Diagram — With Internal Delay Added (Default) Table 3-7 shows the RGMII AC characteristics with delay added. Table 3-7. RGMII AC Characteristics — with internal delay added (Default) Symbol Parameter Min Typ Max Unit TsetupT Data to Clock output Setup (at Transmitter — integrated delay) 1.65 2.0 2.2 ns TholdT Clock to Data output Hold (at Transmitter — integrated delay) 1.65 2.0 2.2 ns TsetupR Data to Clock input setup Setup (at Receiver — integrated delay) 1.0 2.0 ns TholdR Data to Clock output setup Setup (at Reciever — integrated delay) 1.0 2.0 ns 3.4 MDIO Characteristics MDIO is OD-gate, and can be pulled-up to 2.5/3.3V. Table 3-8 shows the MDIO DC characteristics. Table 3-8. MDIO DC Characteristics 22 22 • • Symbol Parameter Min Max Unit IIH Input high current — 0.4 mA IIL Input low current 0.4 — mA VOH Output high voltage 2.4 — V VOL Output low voltage — 0.4 V VIH Input high voltage 2.0 — V VIL Input low voltage — 0.8 V AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Table 3-9 shows the MDIO AC Characteristics. Table 3-9. MDIO AC Characteristics Symbol Parameter Min Typ Max Unit tmdc MDC Period 40 ns tmdcl MDC Low Period 16 ns tmdch MDC High Period 16 ns tmdsu MDIO to MDC rising setup time 10 ns tmdhold MDIO to MDC rising hold time 10 ns tmdelay MDC to MDIO output delay 10 30 ns 3.5 XTAL/OSC characteristic table Table 3-10. XTAL/OSC Characteristic Symbol Parameter Min Typ Max Unit T_XI_PER XI/OSCI Clock Period 40.0 50ppm 40.0 40.0 + 50ppm ns T_XI_HI XI/OSCI Clock High 14 20.0 ns T_XI_LO XI/OSCI Clock Low 14 20.0 ns T_XI_RISE XI/OSCI Clock Rise Time, VIL (max) to VIH (min) 4 ns T_XI_FALL XI/OSCI Clock Fall time, VIL (max) TO VIH (min) 4 ns V_IH_XI The XI input high level 0.8 1.2 1.5 V V_IL_XI The XI input low level voltage - 0.3 0 0.15 V Cin Load capacitance 1 2 pF Jitter_rms Period broadband rms jitter 15 ps Jitter_pk-pk Period broadband PK-PK jitter 200 ps Table 3-11. CLK_25M Output Characteristics Symbol Min Typ Max Unit Frequency -50ppm 20, 50, 62.5, 125 +50ppm MHz Output high voltage 2.3 2.62 2.8 V Output low voltage GND-0.3 0 0.4 V JitterRMS 15 ps JitterPK-PK 125 ps Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 23 23 NOTE: CLK_25M default outputs 25MHz, can be configured to 50MHz, 62.5MHz, or 125MHz by register MMD7 8016[4:3]. NOTE: The jitter result is broadband period jitter with 100000 samples. 3.6 Power Pin Consumption Table 3-12. Power Pin Characteristic Symbol Voltage Range Current AVDDL 1.1V ±5% 50.8 mA DVDDL 1.1V ±5% 113.7 mA AVDD33 3.3V ±5% 63.8 mA VDDIO_REG Connect VDDH_REG 2.5V 20.9 mA NOTE: Data for components selection and layout guide 24 24 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 3.7 Typical Power Consumption Parameters The following conditions apply to the typical characteristics unless otherwise specified: VCC = 3.3V (1.1V switching regulator integrated. 1.8V RGMII power included). Table 3-13. Total System Power Total Current (mA) LED Consumption (mA) Total Power Consumption w/o LED (mW) Symbol Condition PLDPS Link Down, Power Saving Mode 3.0 0 9.9 PPWD Power Down Mode 2.5 0 8.25 P1000F 1000BASE Full Duplex 119 2.7 392.7 P1000F 1000BASE Idle 109 4 359.5 P100F 100BASE Full Duplex 33.9 3.5 111.9 P100F 100BASE Idle 32.6 4 107.6 P10F 10BASE-Te Full Duplex 31.5 1 104.0 P10IDLE 10BASE-Te Idle 9.4 1.5 31.0 PLPI 1000M Idle 20.0 4.0 66.0 PLPI 100M Idle 14.7 4.0 48.5 802.3az Enabled Atheros Proprietary Green Ethos®Power Savigns Per Cable Length P1000F 20m P1000F 20m P1000F 100m P1000F 100m P1000F 140m P1000F 140m 1000BASE Full Duplex 20m cable 92.0 2.7 303.6 1000BASE Idle 20m cable 85.0 4 280.5 1000BASE Full Duplex 100m cable 119.0 2.7 392.7 1000BASE Idle 100m cable 109 4 359.7 1000BASE Full Duplex 140m cable 137.0 2.7 452.1 1000BASE Idle 140m cable 128.0 4 422.4 NOTE: power consumption test results are based on Atheros demo board. Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 25 25 3.8 Power-on Sequence, Reset and Clock 3.8.1 Power-on Sequence The AR8035 only needs a single 3.3V power supply input. The 1.1V core and 2.5V, 1.8V/1.5V voltages are generated by AR8035's internal regulators. So the AR8035’s power-on sequence to establish the power rails stability is met internally. 3.8.2 Reset and Clock Timing The AR8035 hardware reset needs the clock to take effect. Input clock including the crystal and external input clock should be stable for at least 1ms before RESET can be deasserted. For chip reliability, an external clock must be input after the power-on sequence. Figure 3-3 shows the Reset Timing diagram. 3.3V XI clock >0ms Reset >/=1ms >/= 1ms Figure 3-3. Reset Timing Diagram When using crystal, the clock is generated internally after power is stable. For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied. 26 26 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4. Register Descriptions Table 4-1 shows the reset types used in this document. Type Description Table 4-1. Reset Types Retain Value written to a register field takes effect without a software reset. Type Description LH LL Table 4-1. Reset Types (continued) Register field with latching high function. If status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs. Register field with latching low function. If status is low, then the register is cleared to a zero and remains cleared until a read operation is performed through the management interface or a reset occurs. SC Self-Clear. Writing a one to this register causes the desired function to execute immediately, and the register field clears to zero when the function is complete. Update The value written to the register field does not take effect until a software reset is executed. The value can still be read after it is written. 4.1 Register Summary Table 4-2 summarizes the registers for the AR8035. Table 4-2. Register Summary Offset Register 0x00 Control 0x01 Status 0x02 PHY identifier [18:3] 0x03 PHY identifier [19:24] 0x04 Auto-negotiation advertisement 0x05 Link partner ability (base page) 0x06 Auto-negotiation expansion 0x07 Next page transmit 0x08 Link partner next page 0x09 1000 Base-T control 0x0A 1000 Base-T status 0x0B Reserved 0x0C Reserved 0x0D MMD Access Control 0x0E MMD Access Control Data 0x0F Extended status 0x10 Function control 0x11 PHY-specific status 0x12 Interrupt enable 0x13 Interrupt status 0x14 Smart Speed 0x15 Reserved Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 27 27 Table 4-2. Register Summary (continued) Offset Register 0x16 Cable defect tester control 0x17 Reserved 0x18 LED control 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C Cable defect tester status 0x1D Debug port address offset 0x1E Debug port data 0x1F Reserved 4.1.1 Control Offset: 0x00 Mode: Read/Write Hardware Reset: 0x3100 Software Reset: See field descriptions Bit Name 15 RESET SC 14 LOOPBACK 0 13 SPEED_SELECTION (LSB) Retain 12 AUTO_ NEGOTIATION Retain POWER_DOWN 0 11 28 28 • • SW Reset Description PHY software reset 0 Normal operation 1 PHY reset Writing a 1 to this bit causes immediate PHY reset. Once the operation is done, this bit clears to 0 automatically. When loopback is active, the transmitter data on TXD loops back to RXD internally. The link breaks when loopback is enabled. 0 Disable loopback 1 Enable loopback Force_speed = {register 0.6, this bit}: 2’b00 = 10Mbps 2’b01 = 100Mbps 2’b10 = 1000Mbps 2’b11 = Reserved 0 Disable auto-negotiation process 1 Enable auto-negotiation process When the port is switched from power down to normal operation, software reset and restart Auto-Negotiation are performed even when bit Reset (0.15)and Restart Ato-Negotiation (0.9) are not set by the user. IEEE power down shuts down the chip except for the MAC interface if 16.3 is set to 1. If 16.3 is set to 0, then the MAC interface also shuts down. Power-downalos has no effect on the 125clk output if 16.4 is set to 0. 0 Normal operation 1 Power-down AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Bit Name 10 ISOLATE 0 9 RESTART_AUTO_ NEGOTIATION SC 8 DUPLEX MODE Retain 7 COLLISION TEST 0 6 5:0 SPEED SELECTION (MSB) RES Atheros Communications, Inc. COMPANY CONFIDENTIAL SW Reset Description The RGMII/Rmii output pins are tri-statedwhen thei bit is set to 1. The RGMII/RMII inputs are ignored. 1 = Isolate 0 = Normal operation Auto-Negotiation automatically restarts after hardware or software reset regardless of whether or not this bit is set. 0 Normal operation 1 Restart auto-negotiation process . 0 Half-duplex 1 Full-duplex Retain 0 Disable COL signal test 1 Enable COL signal test See description in bit ["13"] 00000 Reserved. Always set to 00000. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 29 29 4.1.2 Status Offset: 0x01 Mode: Read-Only Hardware Reset: 0x7949 Software Reset: See field descriptions Bit Name 15 100BASE-T4 SW Reset Description 0 100 BASE-T4 This protocol is not available 0 14 100BASE-X FULL-DUPLEX 1 Capable of 100-Tx Full Duplex operation 13 100BASE-X HALF-DUPLEX 1 Capable of 100-Tx Half Duplex operation 12 10 MBPS FULLDUPLEX 1 Capable of 10 BASE-T full duplex operation 11 10 MBS HALF-DUPLEX 1 Capable of 10 BASE-T half duplex operation 10 100BASE-T2 FULL-DUPLEX 0 Not able to perform 100 BASE-T2 9 100BASE-T2 HALF-DUPLEX 0 Not able to perform 100 BASE-T2 8 EXTENDED STATUS 1 7 RESERVED 0 Always 0 6 MF PREAMBLE SUPPRESSION 1 PHY accepts management frames with preamble suppressed 5 AUTONEGOTIATION COMPLETE 0 REMOTE FAULT 0 4 Extended status information in the register “Extended Status” on page 39 0 Auto negotiation process not complete 1 Auto negotiation process complete This bit clears after read “SC”. 0 Remote fault condition not detected. 1 Remote fault condition detected 3 AUTONEGOTIATION ABILITY 1 PHY able to perform auto negotiation 2 LINK STATUS 0 Indicates whether the link was lost since the last read. For the current link status, read LINK_REAL_TIME (bit [10]) of the register “PHY-Specific Status” on page 40. Latching low function. 1 JABBER DETECT 0 30 30 PHY not able to perform 100 BASE-T4 EXTENDED CAPABILITY • • 0 1 0 Link is down 1 Link is up This bit clears after read “SC”. 0 Jabber condition not detected 1 Jabber condition detected Extended register capabilities AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.3 PHY Identifier [18:3] Offset: 0x02 Mode: Read-Only Hardware Reset: 0x004D Software Reset: 0x004D Bit 15:0 Name Description Unique Identifier Bit Organizationally unique identifier bits [18:3]. Always 16’h004D 4.1.4 PHY Identifier [19:24] Offset: 0x03 Mode: Read-Only Hardware Reset: 0xD072 Software Reset: 0xD072 Bit Name 15:0 OUI LSB Model Revision Description Organizationally unique identifier bits [19:24]. Always 16’hD072 4.1.5 Auto-Negotiation Advertisement Offset: 0x04 Mode: Read/Write Hardware Reset: 0x1DE1 Software Reset: See field descriptions Bit Name 15 NEXT_PAGE SW Reset Description Retain 14 ACK 0 13 REMOTE FAULT Retain 12 xnp_able 1 11 ASYMMETRIC PAUSE Retain Atheros Communications, Inc. COMPANY CONFIDENTIAL The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down If 1000BASE-T is advertised then the required next pages are automatically transmitted. Register 4.15 should be set to 0 if no additional next pages are needed. 0 Not advertised 1 Advertise Must be set to 0 Write a 1 to set remote fault Extended next page enable control bi: 1 = Local device supports transmission of extended next pages; 0 = Local device does not support transmission of extended next pages. Upon hardware reset , this bit depends on ASYM_PAUSE_PAD. The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Asymmetric Pause 0 = No asymmetric Pause AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 31 31 Bit Name 10 PAUSE SW Reset Description Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = MAC PAUSE implemented 0 = MAC PAUSE not implemented 9 100BASE-T4 0 8 100BASE-TX FULL DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised Not able to perform 100 BASE-T4 7 100BASE-TX HALF DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised 6 10BASE-TX FULL DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised 5 10BASE-TX HALF DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised 4:0 SELECTOR FIELD 00001 Selector field mode 00001 32 32 • • 802.3 AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.6 Link Partner Ability (Base Page) Offset: 0x05 Mode: Read-Only Hardware Reset: 0 Software Reset: 0 Bit Name 15 NEXT PAGE 14 13 ACK REMOTE FAULT Description Received code word bit [15] 0 Link partner not capable of next page 1 Link partner capable of next page Acknowledge; received code word bit [14] 0 Link partner does not have next page ability 1 Link partner received link code word Received code word bit [13] 0 Link partner has not detected remote fault 1 Link partner detected remote fault 12 RESERVED Technology Ability Field Received Code Word Bit [12] 11 ASYMMETRIC PAUSE Received code word bit [11] 10 9 8 7 6 5 4:0 PAUSE 100BASE-T4 100BASE-TX FULL DUPLEX 100BASE-TX HALF DUPLEX 10BASE-TX FULL DUPLEX 10BASE-TX HALF DUPLEX SELECTOR FIELD Atheros Communications, Inc. COMPANY CONFIDENTIAL 0 Link partner does not request asymmetric pause 1 Link partner requests asymmetric pause Received code word bit [10] 0 Link partner is not capable of pause operation 1 Link partner is capable of pause operation Received code word bit [9] 0 Link partner is not 100 BASE-T4 capable 1 Link partner is 100 BASE-T4 capable Received code word bit [8] 0 Link partner is not 100 BASE-TX full-duplex capable 1 Link partner is 100 BASE-TX full-duplex capable Received code word bit [7] 0 Link partner is not 100 BASE-TX half-duplex capable 1 Link partner is 100 BASE-TX half-duplex capable Received code word bit [6] 0 Link partner is not 10 BASE-T full-duplex capable 1 Link partner is 10 BASE-T full-duplex capable Received code word bit [5] 0 Link partner is not 10 BASE-T half-duplex capable 1 Link partner is 10 BASE-T half-duplex capable Received code word bit [4:0] AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 33 33 4.1.7 Auto-Negotiation Expansion Offset: 0x06 Mode: Read-Only Hardware Reset: 0x0004 Software Reset: Decided by the PHY inner state Bit Name 15:5 RES 4 PARALLEL DETECTION FAULT 3 LINK PARTNER NEXT PAGE ABLE 2 Description Reserved. Must be set to 0. Software resets this bit to 0; clear after read 0 No fault has been detected 1 A fault has been detected Software resets this bit to 0; clear after read 0 Link partner is not next page capable 1 Link partner is next page capable 0 Local device is not next page capable 1 Local device is next page able LOCAL NEXT PAGE ABLE 1 PAGE RECEIVED 0 LINK PARTNER AUTONEGOTIATION ABLE On software reset, this bit value is reserved; LH; cleared after a read. 0 No new page has been received 1 A new page has been received Software reset to 0. 0 Link partner is not auto-negotiation capable 1 Link partner is auto-negotiation capable 4.1.8 Next Page Transmit Offset: 0x07 Mode: Read/Write Reset: See field descriptions Bit Name Reset 15 NEXT PAGE 0 Transmit code word bit [15] 14 RES 0 Transmit code word bit [14] 13 MESSAGE PAGE MODE 1 Transmit code word bit [13] 12 ACK2 0 Transmit code word bit [12] 11 TOGGLE 1 Transmit code word bit [11] 10:0 MESSAGE/ UNFORMATTED FIELD 0x001 34 34 • • Description Transmit code word bits [10:0] AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.9 Link Partner Next Page Offset: 0x08 Mode: Read-Only Hardware Reset: 0 Software Reset: 0 Bit Name 15 NEXT PAGE Description Receive code word bit [15] 14 ACK Receive code word bit [14] 13 MESSAGE PAGE MODE Receive code word bit [13] 12 ACK2 Receive code word bit [12] 11 TOGGLE Receive code word bit [11] 10:0 MESSAGE/ UNFORMATTED FIELD Receive code word bits [10:0] 4.1.10 1000 BASE-T Control Offset: 0x09 Mode: Read/Write Hardware Reset: 0x0200 Software Reset: See field descriptions Bit Name 15:13 TEST MODE SW Reset Description Retain Hardware reset or software reset (see RESET (bit [15]) of the register “Function Control” on page 39) should be issued to ensure normal operation after exiting the test mode. 000 Normal Mode 001 Test mode 1: Transmit waveform test 010 Test mode 2: Transmit jitter test (MASTER mode) 011 Test mode 3: Transmit jitter test (SLAVE mode) 100 Test mode 4: Transmit distortion test 101, 110, 111 Reserved 12 11 MASTER/SLAVE MANUAL CONFIGURATION ENABLE MASTER/SLAVE CONFIGURATION Atheros Communications, Inc. COMPANY CONFIDENTIAL Retain Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Manual MASTER/SLAVE configuration 0 = Automatic MASTER/SLAVE configuration 0 Automatic MASTER/SLAVE configuration 1 Manual MASTER/SLAVE configuration The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down Register 9.11 is ignored if register 9.12 is equal to 0. 1 = Manual configure as MASTER 0 = Manual configure as SLAVE 0 Manual configure as SLAVE 1 Manual configure as MASTER AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 35 35 36 36 Bit Name 10 PORT TYPE SW Reset Description Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down Register 9.10 is ignored if register 9.12 is equal to 1. 0 Prefer single port device (SLAVE) 1 Prefer multi-port device (MASTER) 9 1000BASE-T FULL DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised When giga_dis_qual(register20.8) is high, this bit is forced to be low. 8 1000BASE-T HALF-DUPLEX Retain The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs: o Software reset is asserted (register 0.15) o Restart Auto-Negotiation is asserted (register 0.9) o Power down (register 0.11) transitions from power down to normal operation o Link goes down 1 = Advertise 0 = Not advertised Note: the default setting is no 1000 baset/half duplex advertised When giga_dis_qual(register20.8) is high, this bit is forced to be low. 7:0 RES 0 • • Reserved AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.11 1000 BASE-T Status Offset: 0x0A Mode: Read-Only Hardware Reset: 0 Software Reset: 0 Note: Contents of this register clear after a read operation has occurred. Bit Name Description 15 MASTER/SLAVE This register bit will clear on read CONFIGURATION 0 No fault detected FAULT 1 Master/slave configuration fault detected 14 MASTER/SLAVE This register bit is not valid until PAGE_RECEIVED (bit [1]) of the register CONFIGURATION “Auto-Negotiation Expansion” on page 34 is 1 RESOLUTION 0 Local PHY configuration resolved to Slave 13 12 11 10 1 Local PHY configuration resolved to Master LOCAL RECEIVER STATUS 0 Local Receiver Not OK 1 Local Receiver OK REMOTE RECEIVER STATUS 0 Remote Receiver Not OK 1 Remote Receiver OK LINK PARTNER 1000BASE-T FULL DUPLEX CAPABILITY LINK PARTNER 1000BASE-T HALF DUPLEX CAPABILITY 9:8 RES 7:0 IDLE ERROR COUNT Atheros Communications, Inc. COMPANY CONFIDENTIAL This register bit is not valid until PAGE_RECEIVED (bit [1]) of the register “Auto-Negotiation Expansion” on page 34 is 1 0 Link Partner is not capable of 1000 BASE-T half duplex 1 Link Partner is capable of 1000 BASE-T half duplex This register bit is not valid until PAGE_RECEIVED (bit [1]) of the register “Auto-Negotiation Expansion” on page 34 is 1 0 Link Partner is not capable of 1000 BASE-T full duplex 1 Link Partner is capable of 1000 BASE-T full duplex Reserved. Reports the idle error count since the last time this register was read. The counter stops at 11111111 and does not roll over. These bits clear on a read. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 37 37 4.1.12 MMD Access Address Register Offset: 0x0E Mode: Read-Only Hardware Reset: 0 Software Reset: 0 Bit Name 15:0 Address Data Type Description Mode R/W HW Rst 00 SW Rst Retain If register13.15:14=00, MMD DEVAD's address register. Otherwise, MMD DEVAD's data register as indicated by the contents of its address register 4.1.13 MMD Access Control Register Offset: 0x0D Mode: Read-Only NOTE: Contents of this register clear after a read operation has occurred. Bit Name 15:14 Function Type Mode HW Rst SW Rst 13:5 4:0 Reserved DEVAD Description R/W 00=address 01=data,no post increment 00 10=data,post increment on reads and writes Retain 11=data,post increment on writes only; Mode RO HW Rst 0 SW Rst 0 Mode R/W HW Rst 00 Device address SW Rst Update 38 38 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.14 Extended Status Offset: 0x0F Mode: Read-Only Hardware Reset: 0x2000 Software Reset: 0 Bit Name 15 1000BASE-X FULL DUPLEX Description PHY not able to perform 1000 BASE-X Full Duplex 14 1000BASE-X HALF DUPLEX PHY not able to perform 1000 BASE-X Half Duplex 13 1000BASE-T FULL-DUPLEX PHY able to perform 1000 BASE-T Full Duplex 12 1000BASE-T HALF-DUPLEX PHY not able to perform 1000 BASE-T Half Duplex 11:0 RES Reserved 4.1.15 Function Control Offset: 0x10 Mode: Read/Write Hardware Reset: 0x0862 Software Reset: See field descriptions Bit Name 15:12 RESERVED 11 ASSERT_CRS_ON_ TRANSMIT 10 RESERVED 9:7 RESERVED 6:5 MDI_CROSSOVER_ MODE Atheros Communications, Inc. COMPANY CONFIDENTIAL SW Reset Description Retain Update This bit has effect in 10BT half-duplex mode and 100BT mode: 0 Never assert on transmit 1 Assert on transmit Changes to these bits are disruptive to the normal operation; therefore any changes to this register must be followed by a software reset to take effect. 00 Manual MDI configuration 01 Manual MDIX configuration 10 Reserved 11 Enable automatic crossover for all modes AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 39 39 Bit Name 4:3 RES 0 2 SQE_TEST Retain 1 POLARITY_ REVERSAL 0 DISABLE_JABBER SW Reset Description Retain Retain Reserved SQE Test is automatically disabled in full-duplex mode regardless of the state of this bit 0 SQE test disabled 1 SQE test enabled If polarity is disabled, then the polarity is forced to be normal in 10 BASE-T 0 Polarity reversal enabled 1 Polarity reversal disabled 0 Enable jabber function 1 Disable jabber function 4.1.16 PHY-Specific Status Offset: 0x11 Mode: Read-Only Hardware Reset: 0x0010 Software Reset: 0 Bit Name 15:14 SPEED 13 12 11 10 9:7 6 5 40 40 • • Description Valid only after resolved bit [11] of this register = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled. 00 10 Mbps 01 100 Mbps 10 1000 Mbps 11 Reserved DUPLEX Valid only after resolved bit [11] of this register = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled. 0 Half-duplex 1 Full-duplex PAGE_RECEIVED 0 Page not received (real-time) 1 Page received SPEED_DUPLEX_ When Auto-Negotiation is not enabled, this bit = 1 for force speed RESOLVED 0 Not resolved 1 Resolved LINK (real-time) 0 Link down 1 Link up RES Reserved. Always set to 0. MDI_CROSSOVER_ Valid only after resolved bit [11] of this register = 1. The resolved bit is set when STATUS Auto-Negotiation is completed or Auto-Negotiation is disabled. This bit is 0 or 1 depending on what is written to bits [6:5] of the register “Function Control” on page 39 in manual configuration mode. “Function Control” bits [6:5] are updated with software reset. 0 MDI 1 MDIX SMARTSPEED_ 0 Smartspeed downgrade does not occur DOWNGRADE 1 Smartspeed downgrade occurs AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Bit Name 4 RESERVED 3 2 1 0 Description TRANSMIT_PAUSE Valid only after resolved bit [11] of this register = 1. The resolved bit is set when _ENABLED auto-negotiation is completed or disabled. A reflection of the MAC pause resolution. 0 Transmit pause disabled 1 Transmit pause enabled RECEIVE_ A reflection of the MAC pause resolution. This status bit is valid only after PAUSE_ENABLED resolved bit [11] of this register = 1. The resolved bit is set when auto-negotiation is completed or disabled. 0 Receive pause disabled 1 Receive pause enabled POLARITY 0 Normal (real-time) 1 Reversed JABBER (real-time) 0 No jabber 1 Jabber 4.1.17 Interrupt Enable Offset: 0x12 Mode: Read/Write Hardware Reset: 0 Software Reset: See field descriptions Bit Name 15 Auto-Negotiation Error Interrupt Enable Retain Speed Changed Interrupt Enable Retain Duplex Changed Interrupt Enable Retain Page Received Interrupt Enable Retain Link fail interrupt Retain 14 13 12 11 10 Link success interrupt 9 Reserved 8 Reserved 7 Reserved Atheros Communications, Inc. COMPANY CONFIDENTIAL SW Reset Description Retain 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 41 41 Bit Name 6 Reserved 5 Wirespeeddowngrade Interrupt SW Reset Description Retain 4 Reserved 3:2 RES 0 1 Polarity Changed Interrupt Enable Retain Wake on LAN interrupt enable 0 0 0 Interrupt disable 1 Interrupt enable Reserved. Always set to 00. 0 Interrupt disable 1 Interrupt enable 0 Interrupt disable 1 Interrupt enable 4.1.18 Interrupt Status Offset: 0x13 Mode: Read-Only Hardware Reset: 0 Note: All bits clear on read. Bit Name 15 AUTO _NEGOTIATION_ ERROR 14 13 12 11 10 9:6 5 42 42 An error is said to occur if MASTER/SLAVE does not resolve, parallel detect fault, no common HCD, or link does not come up after negotiation is completed. 0 No Auto-Negotiation Error 1 Auto-Negotiation Error 0 Speed not changed 1 Speed changed DUPLEX_ CHANGED 0 Duplex not changed 1 Duplex changed PAGE_RECEIVED 0 Page not received 1 Page received LINK_FAIL _INTERUPT 0 1 = Link down happened. 1 0 = Link down not happened LINK_SUCESS_INT ERUPT 0 1 = Link up happened. 1 0 = Link up not happened RESERVED 0 No symbol error 1 Symbol error 0 No Smartspeed interrupt detected 1 Smartspeed interrupt detected SPEED_CHANGED WIRESPEED_DOW NGRADE _INTERRUPT • • Description AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Bit Name Description 4:2 RESERVED 0 1 1 0 POLARITY_ CHANGED 0 Polarity not changed 1 Polarity changed INT_WOL_PTP 0 No Wake-on-LAN packet is received 1 Wake-on-LAN packet is received 4.1.19 Smart Speed Offset: 0x14 Mode: Read/Write Hardware Reset: 0x82C Software Reset: See field descriptions Bit Name Reset 15:6 5 RES SMARTSPEED_EN 0 1 4:2 SMARTSPEED_RETRY_LIMIT 011 1 BYPASS_SMARTSPEED_TIMER 0 0 RESERVED 0 Description Reserved. Must be set to 00001000. The default value is one; if this bit is set to one and cable inhibits completion of the training phase, then after a few failed attempts, the device automatically adjusts the highest ability to the next lower speed: from 1000 to 100 to 10. The default value is three; if set to three, then the device attempts five times before adjusting; the number of attempts can be changed through setting these bits. 000 2 retries 001 3 retries 010 4 retries 011 5 retries (default) 100 6 retries 101 7 retries 110 8 retries 111 9 retries 0 The stable link condition is determined 2.5 seconds after the link is established (default) 1 The stable link condition is determined as soon as the link is established Reserved. Must be set to 0. 4.1.20 Cable Diagnostic Tester Control Offset: 0x16 Mode: Read/Write Hardware Reset: 04E8 Software Reset: Retain Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 43 43 Bit Name 15:10 9:8 RES MDI_PAIR_ SELECT 7:1 0 RES ENABLE_TEST Description Reserved Cable Diagnostic Tester (CDT) control registers Use the cable defect tester control registers to select which MDI pair is shown in the register “Cable Defect Tester Status” on page 45. 00 MDI[0] pair 01 MDI[1] pair 10 MDI[2] pair 11 MDI[3] pair Reserved When set, hardware automatically disable this bit when CDT is done 0 Disable CDT Test 1 Enable CDT Test 4.1.21 LED Control Offset: 0x018 Bit Name 15 Reserved 14:12 Led on time Type Mode R/W HW Rst. 0 SW Rst Retain Mode R/W HW Rst. SW Rst 11 10:8 Reserved Led off time R/W HW Rst. 0 SW Rst Retain Mode R/W SW Rst 44 44 • • Reserved 000 = 5 ms 001 = 10ms 011 010 = 21 ms Retain 011 = 42ms 100 = 84 ms 101 = 168ms 110 to 111 = 42ms Mode HW Rst. 7:0 Description Always 0 000 = 21 ms 001 = 42 ms 010 010 = 84 ms Retain 011 =168 ms 100 =330 ms 101 = 670 ms 110 to 111 = 168ms Mode R/W HW Rst. 0 SW Rst Retain AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.1.22 Cable Defect Tester Status Offset: 0x1C Mode: Read-Only Hardware Reset: 0200 Software Reset: Retain Bit Name 15:10 RES 9:8 STATUS 7:0 DELTA_TIME Description Reserved The content of this register applies to the cable pair selected in the register “Cable Diagnostic Tester Control” on page 43. 00 Valid test, normal cable (no short or open in cable) 01 Valid test, short in cable (Impedance < 33 ) 10 Valid test, open in cable (Impedance > 333 ) 11 Test fail Delta time to indicate distance 4.1.23 Debug Port Address Offset Offset: 0x1D Mode: Read/Write Hardware Reset: 0 Software Reset: 0 Bit Name 15:6 RES 5:0 Description Reserved ADDRESS_OFFSET Address index to access the debug registers 4.1.24 Debug Port Data Offset: 0x1E Mode: Read/Write Hardware Reset: 0x82EE Software Reset: 0x82EE Bit Name 15:0 DATA Description Data contents of the debug registers as addressed by the “Debug Register Summary” register Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 45 45 4.2 Debug Register Descriptions Table 4-3 summarizes the debug registers for the AR8035. Table 4-3. Debug Register Summary Offset Register 0x00 Debug register 0 0x05 Debug register 5 0x10 100 BASE-TX test mode select 0x11 Debug register 11 0x12 Test configuration for 10 BASE-T 4.2.25 rgmii rx clock delay control Offset: 0x00 Bit Name 15 Sel_clk125m_dsp 14:0 Reserved Type Description Mode R/W HW Rst. 1 SW Rst. 1 Mode RO HW Rst. 2EE SW Rst. 2EE Control bit for rgmii interface rx clock delay: 1 = rgmii rx clock delay enable 0 = rgmii rx clock delay disable 4.2.26 rgmii tx clock delay control Offset: 0x05 Bit Name 15:9 Reserved 8 rgmii_tx_clk_dly 7:0 46 46 • • Reserved Type Description Mode R/W HW Rst. 1 SW Rst. 1 Mode R/W HW Rst. 0 SW Rst. Retain Mode RO HW Rst. 2EE SW Rst. 2EE Rgmii tx clock delay control bit: 1 = rgmii tx clock delay enable 0 = rgmii tx clock delay disable. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.2.27 Hib ctrl and rgmii gtx clock delay register Offset: 0x0B Bit Name 15 Ps_hib_en 14:13 12 Reseved Hib_pulse_sw Type Mode R/W HW Rst. 1 SW Rst. Retain Mode RO HW Rst. 01 SW Rst. 01 Mode R/W HW Rst. SW Rst. 11:7 6:5 Reseved Gtx_dly_val RO HW Rst. 11000 SW Rst. 11000 Mode R/W SW Rst. Reseved Atheros Communications, Inc. COMPANY CONFIDENTIAL Power hibernate control bit; 1: hibernate enable 0: hibernate disable 1: when hibernate, PHY sends NLP pulse and detects signal from cables. 1 0: when hibernate, PHY doesn't send NLP pulse ,just Retain detects signal from cables. Mode HW Rst. 4:0 Description Select the delay of gtx_clk. 00:0.25ns 2’b10 01:1.3ns Retain 10:2.4ns 11:3.4ns Mode RO HW Rst. 0 SW Rst. 0 AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 47 47 4.2.28 100BASE-TX Test Mode Select Offset: 0x10 Bit Name 15:8 Reserved 7 Jitter_test 6 Os_test 5 Dcd_test 4:0 Reserved Type Description Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. Retain Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. Retain Mode RO HW Rst. 0 SW Rst. 0 Always 0. 100BT jitter test 100BT over shoot test 100BT DCD test 4.2.29 1000BT external loopback configure Offset: 0x11 Bit Name 15:1 Reserved 0 48 48 Ext_lpbk • • Type Description Mode RO HW Rst. 3AA9 SW Rst. 3AA9 Mode RO HW Rst. 0 SW Rst. 0 1: enable the PHY's external loopback, namely channel 0 channel 1, channel 2 channel 3. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 4.2.30 Rgmii_mode; Test configuration for 10BT Offset: 0x12 Bit Name 15:6 Reserved 5 4 3 2 1:0 Test_mode[2] Reserved Reserved Reserved Test_mode[1:0] Type Description Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 1 SW Rst. 1 Mode RO HW Rst. 1 SW Rst. 1 Mode RO HW Rst. 0 SW Rst. 0 The bit2 of test_mode [001]: packet with all ones, 10MHz sine wave, For harmonic test. [010]: pseudo random, for TP_IDLE/Jitter/Differential Voltage test. [011]: normal link pulse only, [100]: 5MHz sin wave. Others: normal mode. 4.2.31 MMD3 (MDIO Manageable Device Address 3 for PCS)  Offset Register 0 PCS Control Register 1 PCS Status Register Atheros Communications, Inc. COMPANY CONFIDENTIAL Description AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 49 49 Offset Register 20 EEE capability 22 EEE wake error counter Description 4.2.32 MMD7 (MDIO Manageable Device Address 7 for Auto-Negotiation)  Offset Register 0 AN control 1 AN status 22 AN XNP transmit 23 AN XNP transmit1 24 AN XNP transmit2 25 AN XNP ability 26 AN XNP ability1 27 AN XNP ability2 60 EEE advertisement 61 EEE LP advertisement 32768 EEE ability autonegotiation result 50 50 • • Description AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 5. MDIO Interface Register 5.1 MMD3 - PCS Register 5.1.1 PCS Control 1 Device Address = 3 Offset: 0x0 (Hex)  Bit Name 15 Pcs_rst 14:11 10 9.0 Reserved Clock_stoppable Reserved Atheros Communications, Inc. COMPANY CONFIDENTIAL Description Mode R/W HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. Retain Mode RO HW Rst. 0 SW Rst. 0 Reset bit, self clear. When write this bit 1 : 1, reset the registers(not vender specific) in MMD3/ MMD7. 2, cause software reset in mii register0 bit15. Always 0. Not implemented. Always 0. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 51 51 5.1.2 PCS Status 1 Device Address = 3 Offset: 0x1 (Hex) Bit Name 15:12 Reserved 11 10 9 Rx lp idle received Tx lp idle indication 8 Rx lp idle indication 7:0 52 52 Tx lp idle received • • Reserved Description Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Always 0. When read as 1, it indicates that the transmit PCS has received low power idle signaling one or more times since the register was last read. Latch High. When read as 1, it indicates that the recive PCS has received low power idle signaling one or more times since the register was last read. Lach High. When read as 1, it indicates that the transmit PCS is currently receiving low power idle signals. When read as 1, it indicates that the receive PCS is currently receiving low power idle signals. Always 0. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 5.1.3 EEE Capability Device Address = 3 Offset: 0x14 (Hex) Bit Name 15:3 Reserved 2 1 0 Description Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 1 SW Rst. 1 Mode RO HW Rst. 1 SW Rst. 1 Mode RO HW Rst. 0 SW Rst. 0 1000BT EEE 100BT EEE Reserved Always 0. EEE is supported for 1000BASE-T. EEE is supported for 100BASE-T. Always 0. 5.1.4 EEE Wake Error Counter Device Address = 3 Offset: 0x16 (Hex) Bit Name 15: EEE wake error counter Atheros Communications, Inc. COMPANY CONFIDENTIAL Description Mode RO HW Rst. 0 SW Rst. 0 Count wake time faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type. This counter is clear after read, and hold at all ones in the case of overflow. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 53 53 5.1.5 Wake-on-Lan loc_mac_addr_o Device Address = 3 Offset: 0x804A (Hex) Bit Name 15:0 Loc_mac_ Addr_o[47:32] Description Mode R/W HW Rst. 0 SW Rst. Retain Bits [47:32] of local MAC address, used in Wake-on-Lan. 5.1.6 Wake-on-Lan loc_mac_addr_o Device Address = 3 Offset: 0x804B (Hex) Bit Name 15:0 Loc_mac_ Addr_o[31:16] Description Mode R/W HW Rst. 0 SW Rst. Retain Bits [31:16] of local MAC address, used in Wake-on-Lan. 5.1.7 Wake-on-Lan loc_mac_addr_o Device Address = 3 Offset: 0x804C (Hex) Bit Name 15:0 Loc_mac_ Addr_o[15:0] 54 54 • • Description Mode R/W HW Rst. 0 SW Rst. Retain Bits [15:0] of local MAC address, used in Wake-on-Lan. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 5.1.8 Rem_phy_lpkb Device Address = 3 Offset: 0x805A (Hex) Bit Name 15:1 Reserved 0 Rem_phy_lpbk Description Mode R/W HW Rst. 0 SW Rst. Retain Mode R/W HW Rst. 0 SW Rst. Retain Loopback received data packets to link partner 5.1.9 Smart_eee control1 Device Address = 3 Offset: 0x805B (Hex) Bit Name 15:8 Lpi_wt Description Mode HW Rst. SW Rst. 7:0 Lpi_wt Mode HW Rst. SW Rst. R/W 1000BT Tw timer. After timer done, buffered data will be send. 8’h11 LSB vs time : 1us Retain Default value: 17us. R/W 100BT Tw timer. After timer done, buffered data will be send. 8’h17 LSB vs time : 1us Retain Default value: 23us. 5.1.10 Smart_eee control2 Device Address = 3 Offset: 0x805C (Hex) Bit Name 15:0 Lpi_time[15:0] Description Mode HW Rst. SW Rst. Atheros Communications, Inc. COMPANY CONFIDENTIAL R/W Lpi_timer will count when no data for transmission. After lpi_timer done, PHY will enter LPI mode. 16’h800 LSB vs time : 163.84us Retain Default value: 335.544ms. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 55 55 5.1.11 Smart_eee control3 Device Address = 3 Offset: 0x805D (Hex) Bit Name 15:14 Reserved 13:12 11:9 8 Lpi_tx_delay_sel Reserved Lpi_en 7:0 lpi_timer[23:16] Description Mode R/W HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 2’b01 SW Rst. Retain Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 1’b01 SW Rst. Retain Mode R/W HW Rst. 0 SW Rst. Retain Select IPG length inserted between packets. It's for debug. Enable smart EEE. 1 = enable, 0 = disable. Lpi_timer will count when no data for transmission. After lpi_timer done, PHY will enter LPI mode. Device address = 7, address ofset = 0x8016 (Hex) 4:3 Select_clk125m Mode HW Rst. SW Rst. R/W CLK_25M output clock select 00=25M 00 01=50M Retain 10=62.5M 11=125M Device Address = 7 Offset: 0x1 (Hex) Bit Name 15:8 Reserved 56 56 • • Description Mode RO HW Rst. 0 SW Rst. 0 AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL Bit Name 7 Xnp_status 6:0 Reserved Description Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 1 = both Local device and link partner have indicated support for extended next page; 0 = extended next page shall not be used. 5.1.1 AN status Device Address = 7 Offset: 0x16 (Hex) Bit Name 15:0 Xnp_22 Description Mode R/W HW Rst. 15’h0 SW Rst. Retain A write to this register set mr_next_page_loaded. 5.1.1 AN XNP transmit1 Device Address = 7 Offset: 0x17 (Hex) Bit Name 15:0 Xnp_23 Description Mode R/W HW Rst. 15’h0 SW Rst. Retain 5.1.1 AN XNP transmit2 Device Address = 7 Offset: 0x18 (Hex) Bit Name 15:0 Xnp_24 Atheros Communications, Inc. COMPANY CONFIDENTIAL Description Mode R/W HW Rst. 15’h0 SW Rst. Retain AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • March 2011 • 57 57 5.1.2 EEE advertisement Device Address = 7 Offset: 0x3C (Hex) Bit Name 15:3 Reserved 2 EEE_1000BT 1 EEE_100BT 0 Reserved Description Mode RO HW Rst. 0 SW Rst. 0 Mode R/W HW Rst. 1’b1 SW Rst. Retain Mode R/W HW Rst. 1’b1 SW Rst. Retain Mode RO HW Rst. 0 SW Rst. 0 Always 0. If Local device supports EEE operation for 1000BT, and EEE operation is desired, this bit shall be set to 1. If Local device supports EEE operation for 100BT, and EEE operation is desired, this bit shall be set to 1. Always 0. 5.1.3 EEE LP advertisement Device Address = 7 Offset: 0x3D (Hex) Bit Name 15:3 Reserved 2 EEE_1000BT 1 EEE_100BT 0 58 58 Reserved • • Description Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Mode RO HW Rst. 0 SW Rst. 0 Always 0. 1 = link partner supports EEE operation for 1000BT, and EEE operation is desired; 0 = link partner does not support EEE operation for 1000BT, or EEE operation is not desired. 1 = link partner supports EEE operation for 100BT, and EEE operation is desired; 0 = link partner does not support EEE operation for 100BT, or EEE operation is not desired. Always 0. AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 6. Package Dimensions The AR8035 is packaged in a 40 pin QFN. The body size is 5 mm x 5 mm. The package drawings and dimensions are provided in Figure 6-1 and the following table. Figure 6-1. Package Views Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 1 1 Table 6-1. Package Dimensions Dimension Label Min Nom Max Unit A 0.70 0.75 0.80 mm A1 0.00 0.02 0.05 mm A3 0.20 REF b 0.15 0.20 0.25 mm D 4.90 5.00 5.10 mm E 4.90 5.00 5.10 mm D2 3.15 3.30 3.50 mm E2 3.15 3.30 3.50 mm e 0.35 0.40 0.45 mm K 0.20 -- -- mm L 0.30 0.40 0.50 mm R 0.09 -- -- mm La 0.12 0.15 0.18 mm Lb 0.23 0.26 0.29 mm Lc 0.30 0.39 0.50 mm Notes: 1. All Dimensions refer to JEDEC Standard MO-220 VHHE-1 2 2 • • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 Atheros Communications, Inc. COMPANY CONFIDENTIAL 7. Ordering Information The order number AR8035-AL1A specifies a current, Commercial version of the AR8035 — delivered by tray pack by default. The order number AR8035-AL1A-R specifies a current, Commercial version of the AR8035 — delivered by tape and reel packing, if required. The order number AR8035-AL1B specifies a current, Industrial version of the AR8035 — delivered by tray pack by default. The order number AR8035-AL1B-R specifies a current, Industrial version of the AR8035 — delivered by tape and reel packing, if required. 8. Top-side Marking The top-side marking of the AR8035-AL1A is AR8035-AL1A The top-side marking of the AR8035-AL1B is AR8035-AL1B Atheros Communications, Inc. COMPANY CONFIDENTIAL AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver March 2011 • • 1 1 © 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®, Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, SignalSustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice. MKG-xxxx Rev. 1 Atheros Communications, Incorporated 5480 Great America Parkway Santa Clara, CA 95054 tel: 408.773.5200 fax: 408.773.9940 www.atheros.com COMPANY CONFIDENTIAL Subject to Change without Notice