FM18L08-70-PG

FM18L08 256Kb Bytewide FRAM Memory Features 256K bit Ferroelectric Nonvolatile RAM • Organized as 32,768 x 8 bits • 45 year Data Retention • Unlimited Read/Write Cycles • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Superior to Battery-Backed SRAM • No Battery Concerns • Monolithic Reliability • True Surface Mount Solution, No Rework Steps • Superior for Moisture, Shock, and Vibration • Resistant to Negative Voltage Undershoots SRAM & EEPROM Compatible • JEDEC 32Kx8 SRAM & EEPROM pinout • 70 ns Access Time • 140 ns Cycle Time Low Power Operation • 3.0V to 3.65V Operation • 15 mA Active Current • 15 µA Standby Current Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 32-pin “Green” TSOP Package • 28-pin SOIC or DIP Package • “Green” Packaging Options Pin Configurations NC OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 NC Description The FM18L08 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and reads and writes like a RAM. It provides data retention for 45 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make FRAM superior to other types of nonvolatile memory. In-system operation of the FM18L08 is very similar to other RAM based devices. Read cycle and write cycle times are equal. The FRAM memory, however, is nonvolatile due to its unique ferroelectric memory process. Unlike BBSRAM, the FM18L08 is a truly monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the FM18L08 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The availability of a surface-mount package improves the manufacturability of new designs, while the DIP package facilitates simple design retrofits. Device specifications are guaranteed over a temperature range of -40°C to +85°C. TSOP-I Ordering Information FM18L08-70-TG FM18L08-70-S FM18L08-70-P FM18L08-70-SG FM18L08-70-PG 70 ns access, 32-pin “Green” TSOP 70 ns access, 28-pin SOIC 70 ns access, 28-pin DIP 70 ns access, 28-pin “Green” SOIC 70 ns access, 28-pin “Green” DIP This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Rev. 3.4 July 2007 1 of 13 A10-A14 Block Decoder A0-A14 Address Latch A0-A7 Row Decoder 32,768 x 8 FRAM Array CE A8-A9 Column Decoder WE OE Control Logic I/O Latch Bus Driver DQ0-7 Figure 1. Block Diagram Pin Description Pin Name A0-A14 DQ0-7 /CE Type Input I/O Input /OE /WE VDD VSS Input Input Supply Supply Pin Description Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The address value is latched on the falling edge of /CE. Data: 8-bit bi-directional data bus for accessing the FRAM array. Chip Enable. /CE selects the device when low. Asserting /CE low causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated. Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the data bus to the address location latched by the falling edge of /CE. Supply Voltage Ground Functional Truth Table /CE /WE H X X ↓ L H L ↓ Function Standby/Precharge Latch Address (and Begin Write if /WE=low) Read Write Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 Note: The /OE pin controls only the DQ output buffers. This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. http://www.ramtron.com Rev. 3.4 July 2007 2 of 13 FM18L08 Overview The FM18L08 is a bytewide FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the FRAM memory is the same as SRAM type devices, except the FM18L08 requires a falling edge of /CE to start each memory cycle. The FM18L08 drives the data bus when /OE is asserted to a low state. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will be driven when valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive the data bus will remain tri-stated. Write Operation Writes operations require the same time as reads. The FM18L08 supports both /CE- and /WE-controlled write cycles. In all cases, the address is latched on the falling edge of /CE. In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the device begins the memory cycle as a write. The FM18L08 will not drive the data bus regardless of the state of /OE. In a /WE-controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls after the falling edge of /CE. Therefore, the memory cycle begins as a read. The data bus will be driven according to the state of /OE until /WE falls. The timing of both /CE- and /WE-controlled write cycles is shown in the electrical specifications. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever is first. Data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Precharge Operation The precharge operation is an internal condition where the state of the memory is prepared for a new access. All memory cycles consist of a memory access and a precharge. The precharge is user initiated by taking the /CE signal high or inactive. It 3 of 13 Memory Operation Users access 32,768 memory locations each with 8 data bits through a parallel interface. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When /CE is deasserted high, a precharge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. Note that the FM18L08 contains a limited low voltage write protection circuit. This will prevent access when VDD is much lower than the specified operating range. It is still the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. The FM18L08 is designed to operate in a manner similar to other bytewide memory products. For users familiar with SRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the obvious differences result from the higher write performance of FRAM technology including NoDelay writes and from unlimited write endurance. Read Operation A read operation begins on the falling edge of /CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a full memory cycle must be completed internally regardless of the state of /CE. Data becomes available on the bus after the access time has been satisfied. After the address has been latched, the address value may be changed upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. Rev. 3.4 July 2007 FM18L08 must remain high for at least the minimum precharge timing specification. The user dictates the beginning of this operation since a precharge will not begin until /CE rises. However, the device has a maximum /CE low time specification that must be satisfied. FRAM Design Considerations When designing with FRAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide FRAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use FRAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM18L08. The reason for /CE to strobe for each address is twofold: it latches the new address and creates the necessary precharge period while /CE is high. Valid Memory Signaling Relationship CE FRAM signaling Address Address 1 Address 2 Data Data 1 Data 2 Invalid Memory Signaling Relationship CE SRAM signaling Address Address 1 Address 2 Data Data 1 Data 2 Figure 2. Memory Address Relationships Rev. 3.4 July 2007 4 of 13 FM18L08 A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are forced to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to prevent loading the battery with current demand from an active SRAM. The user can be abruptly cut off from access to the memory in a power down situation without warning. FRAM memories do not need this system overhead. The memory will not block access at any VDD level. The user, however, should prevent the processor from accessing memory when VDD is out-of-tolerance. The common design practice of holding a processor in reset during powerdown may be sufficient. It is recommended that Chip Enable is pulled high and allowed to track VDD during powerup and powerdown cycles. It is the user’s responsibility to ensure that chip enable is high to prevent accesses below VDD min. (3.0V). Figure 3 shows an external pullup resistor on /CE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /CE pin tracks VDD yet a high enough value that the current drawn when /CE is low is not an issue. VDD R FM18L08 CE MCU/ MPU WE OE A(14:0) DQ Figure 3. Use of Pullup Resistor on /CE Rev. 3.4 July 2007 5 of 13 FM18L08 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD VESD Storage temperature Lead temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Machine Model (JEDEC Std JESD22-A115-A) Package Moisture Sensitivity Level Ratings -1.0V to +5.0V -1.0V to +5.0V and VIN < VDD+1V -55°C to +125°C 300° C 4kV 400V MSL-1 (SOIC/DIP) MSL-2 (TSOP) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 3.0V to 3.65V) Symbol Parameter Min Typ Max VDD Power Supply 3.0 3.65 IDD VDD Supply Current – Active 7 15 ISB1 Standby Current – TTL 400 ISB2 Standby Current – CMOS 7 15 ILI Input Leakage Current 10 ILO Output Leakage Current 10 VIH Input High Voltage 2.0 VDD + 0.5 VIL Input Low Voltage -0.5 0.8 VOH Output High Voltage (IOH = -1.0 mA) 2.4 VOL Output Low Voltage (IOL = 3.2 mA) 0.4 Notes 1. VDD = 3.65V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded. 2. VDD = 3.65V, /CE at VIH, All other pins at TTL levels. 3. VDD = 3.65V, /CE at VDD, All other pins at CMOS levels. 4. VIN, VOUT between VDD and VSS. Units V mA µA µA µA µA V V V V Notes 1 2 3 4 4 Rev. 3.4 July 2007 6 of 13 FM18L08 Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 3.0V to 3.65V) Symbol Parameter Min tCE Chip Enable Access Time ( to data valid) tCA Chip Enable Active Time 70 tRC Read Cycle Time 140 tPC Precharge Time 70 tAS Address Setup Time 0 tAH Address Hold Time 15 tOE Output Enable Access Time tHZ Chip Enable to Output High-Z tOHZ Output Enable to Output High-Z Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 3.0V to 3.65V) Symbol Parameter Min tCA Chip Enable Active Time 70 tCW Chip Enable to Write High 70 tWC Write Cycle Time 140 tPC Precharge Time 70 tAS Address Setup Time 0 tAH Address Hold Time 15 tWP Write Enable Pulse Width 40 tDS Data Setup 40 tDH Data Hold 0 tWZ Write Enable Low to Output High Z tWX Write Enable High to Output Driven 10 tHZ Chip Enable to Output High-Z tWS Write Setup 0 tWH Write Hold 0 Notes 1 2 Max 70 2,000 10 15 15 Units ns ns ns ns ns ns ns ns ns Notes 1 1 Max 2,000 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 2 2 This parameter is periodically sampled and not 100% tested. The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing specification associated with this relationship. Data Retention (VDD = 3.0V to 3.65V) Parameter Data Retention Min 45 Units Years Notes 1 Power Cycle Timing (TA = -40° C to + 85° C, VDD = 3.0V to 3.65V) Symbol Parameter Min tPU VDD (min.) to First Access Start 1 tPD Last Access Complete to VDD (min.) 0 Capacitance (TA = 25° C , f=1 MHz, VDD = 3.3V) Symbol Parameter CI/O Input/Output Capacitance (DQ) CIN Input Capacitance Units µS µS Notes Max 8 6 Units pF pF Notes Rev. 3.4 July 2007 7 of 13 FM18L08 AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels 0.1 VDD to 0.9 VDD 5 ns 1.5V Equivalent AC Load Circuit 1.3V 3300Ω Output 50 pF Read Cycle Timing t RC t CA t PC CE t AS t AH A0-14 t OE OE t OHZ DQ0-7 t CE t HZ Write Cycle Timing - /CE Controlled Timing t WC t CA t PC CE t AS t AH A0-14 t WS t WH WE OE t DS t DH DQ0-7 Rev. 3.4 July 2007 8 of 13 FM18L08 Write Cycle Timing - /WE Controlled Timing t WC t CA t PC tC W t AH CE t AS A0-14 t WS t WH t WP WE OE t WZ t WX DQ0-7 out t DS t DH DQ0-7 in Power Cycle Timing VDD min t PD t PC t PU VDD VDD min CE Rev. 3.4 July 2007 9 of 13 FM18L08 Mechanical Drawing 28-pin SOIC (JEDEC MS-013D Variation AE) All dimensions in millimeters 7.50 ±0.10 10.30 ±0.30 Pin 1 17.90 ±0.20 2.35 2.65 45 ° 0? 8? 1.27 typ 0.33 0.51 0.10 0.30 0.10 0.25 0.75 0.23 0.32 0.40 1.27 SOIC Package Marking Scheme Legend: XXXX= part number, S=speed (-70), P= package type (-SG) R=rev code, YY=year, WW=work week, LLLLLL= lot code Example: FM18L08, 70ns speed, “Green” SOIC package, B rev., Year 2006, Work Week 30, Lot code 50013G RAMTRON FM18L08-70-SG B063050013G RAMTRON XXXXXXX-S-P RYYWWLLLLLLL Rev. 3.4 July 2007 10 of 13 FM18L08 28-pin 600-mil DIP (JEDEC MS-011) All dimensions in inches 0.485 0.580 PIN 1 1.380 1.565 0.125 0.195 0.250 max 0.015 min. 0.600 0.625 0.005 min. 0.100 BSC 0.030 0.070 0.014 0.022 0.115 0.200 0.600 BSC 0.700 max. DIP Package Marking Scheme Legend: XXXX= part number, S=speed (-70), P= package type (-PG) R=rev code, YY=year, WW=work week, LLLLLL= lot code Example: FM18L08, 70ns speed, “Green” DIP package, B rev., Year 2006, Work Week 30, Lot code 50013G RAMTRON FM18L08-70-PG B063050013G RAMTRON XXXXXXX-S-P RYYWWLLLLLLL Rev. 3.4 July 2007 11 of 13 FM18L08 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters TSOP Package Marking Scheme Legend: XXXXXX= part number, SP= speed/package (-70TG) R=rev code, YY=year, WW=work week, LLLLLL= lot code Example: FM18L08-70-TG, “green” TSOP package, B rev., Year 2006, Work Week 51, Lot 60012T2 RAMTRON FM18L08-70TG B065160012T2 RAMTRON XXXXXXX-SP YYWWLLLLLL Rev. 3.4 July 2007 12 of 13 FM18L08 Revision History Revision 0.1 0.2 0.3 Date 3/23/01 9/28/01 3/18/02 Summary Initial Release Changed Data Retention table. Modified temperature range to commercial. Changed temperature range to industrial and Vdd range to 3V – 3.65V. Changed precharge time to 70ns. Added note for 2.7V operation. Updated package drawings. Updated to Preliminary status, changed storage temperature. Updated to Production status, removed ref to 2.7V operation. Changed tCA (max) value. Reworded notes 2 and 3 in DC Operating Conditions table. Added “green” packaging options. Added ESD and package MSL ratings. Updated rev numbering and footer. Added recommendation on CE pin during power cycles. Added TSOP packaging option. Updated TSOP MSL rating. Redraw package outlines, added marking scheme to SOIC/DIP. Extended data retention to 45 years based on recent test results. 1.0 2.0 2.1 2.2 3.0 3.1 3.2 3.3 3.4 6/15/02 12/10/02 5/1/03 7/14/04 6/12/06 11/27/06 2/20/07 5/15/07 7/30/07 Rev. 3.4 July 2007 13 of 13