FM18W08

Pre-Production FM18W08 256Kb Wide Voltage Bytewide F-RAM Features 256Kbit Ferroelectric Nonvolatile RAM  Organized as 32,768 x 8 bits  High Endurance 100 Trillion (1014) Read/Writes  38 year Data Retention  NoDelay™ Writes  Advanced High-Reliability Ferroelectric Process Superior to BBSRAM Modules  No Battery Concerns  Monolithic Reliability  True Surface Mount Solution, No Rework Steps  Superior for Moisture, Shock, and Vibration  Resistant to Negative Voltage Undershoots SRAM & EEPROM Compatible  JEDEC 32Kx8 SRAM & EEPROM pinout  70 ns Access Time  130 ns Cycle Time Low Power Operation  Wide Voltage Operation 2.7V to 5.5V  12 mA Active Current  20 A (typ.) Standby Current Industry Standard Configuration  Industrial Temperature -40 C to +85 C  28-pin “Green”/RoHS SOIC Package Description The FM18W08 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides data retention for 38 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make F-RAM superior to other types of nonvolatile memory. In-system operation of the FM18W08 is very similar to other RAM devices. Minimum read- and writecycle times are equal. The F-RAM memory, however, is nonvolatile due to its unique ferroelectric memory process. Unlike BBSRAM, the FM18W08 is a truly monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the FM18W08 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The availability of a true surface-mount package improves the manufacturability of new designs. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Ordering Information FM18W08-SG 28-pin “Green” SOIC This is a product in the pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Rev. 2.0 Dec. 2011 Page 1 of 11 FM18W08 A(14:0) Address Latch & Decoder A(14:0) 32,768 x 8 FRAM Array CE WE OE Control Logic I/O Latch Bus Driver DQ(7:0) Figure 1. Block Diagram Pin Description Pin Name A(14:0) DQ(7:0) /CE Type Input I/O Input /OE Input /WE VDD VSS Input Supply Supply Description Address: The 15 address lines select one of 32,768 bytes in the F-RAM array. The address value is latched on the falling edge of /CE. Data: 8-bit bi-directional data bus for accessing the F-RAM array. Chip Enable: /CE selects the device when low. Asserting /CE low causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. Output Enable: Asserting /OE low causes the FM18W08 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri stated. Write Enable: Asserting /WE low causes the FM18W08 to write the contents of the data bus to the address location latched by the falling edge of /CE. Supply Voltage Ground Functional Truth Table /CE /WE H X X  L H L  Function Standby/Precharge Latch Address (and Begin Write if /WE=low) Read Write Note: The /OE pin controls only the DQ output buffers. Rev. 2.0 Dec. 2011 Page 2 of 11 FM18W08 Overview The FM18W08 is a bytewide F-RAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the F-RAM memory is the same as SRAM type devices, except the FM18W08 requires a falling edge of /CE to start each memory cycle. /CE goes inactive. Data becomes available on the bus after the access time has been satisfied. After the address has been latched, the address value may be changed upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. The FM18W08 will drive the data bus when /OE is asserted low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive the data bus will remain tri-stated. Write Operation Writes occur in the FM18W08 in the same time interval as reads. The FM18W08 supports both /CEand /WE-controlled write cycles. In all cases, the address is latched on the falling edge of /CE. In a /CE controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the part begins the memory cycle as a write. The FM18W08 will not drive the data bus regardless of the state of /OE. In a /WE controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls after the falling edge of /CE. Therefore, the memory cycle begins as a read. The data bus will be driven according to the state of /OE until /WE falls. The timing of both /CE- and /WE-controlled write cycles is shown in the electrical specifications. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever is first. Data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page 3 of 11 Memory Architecture Users access 32,768 memory locations each with 8 data bits through a parallel interface. The complete 15-bit address specifies each of the 32,768 bytes uniquely. Internally, the memory array is organized into 4092 rows of 8-bytes each. This block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance characteristics as explained on page 4. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When /CE is deasserted high, a precharge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. It is the user’s responsibility to ensure that VDD remains within datasheet tolerances to prevent incorrect operation. Also proper voltage level and timing relationships between VDD and /CE must be maintained during power-up and power-down events. See Power Cycle Timing diagram on page 9. Memory Operation The FM18W08 is designed to operate in a manner similar to other bytewide memory products. For users familiar with BBSRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the obvious differences result from the higher write performance of F-RAM technology including NoDelay writes and much higher write endurance. Read Operation A read operation begins on the falling edge of /CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a full memory cycle must be completed internally even if Rev. 2.0 Dec. 2011 FM18W08 Precharge Operation The precharge operation is an internal condition that prepares the memory for a new access. All memory cycles consist of a memory access and a precharge. The precharge is initiated by deasserting the /CE pin high. It must remain high for at least the minimum precharge time tPC. The user determines the beginning of this operation since a precharge will not begin until /CE rises. However, the device has a maximum /CE low time specification that must be satisfied. 150,000 accesses per second to the same row for over 20 years. F-RAM Design Considerations When designing with F-RAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide F-RAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use FRAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM18W08. The reason for /CE to strobe for each address is two fold: it latches the new address and creates the necessary precharge period while /CE is high. Endurance Internally, a F-RAM operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM18W08, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 1014 cycles will allow Valid Strobing of /CE CE FRAM Signaling Address A1 A2 Data D1 D2 Invalid Strobing of /CE CE SRAM Signaling Address A1 A2 Data D1 D2 Figure 2. Chip Enable and Memory Address Relationships Rev. 2.0 Dec. 2011 Page 4 of 11 FM18W08 A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are forced to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to prevent loading the battery with current demand from an active SRAM. The user can be abruptly cut off from access to the nonvolatile memory in a power down situation with no warning or indication. F-RAM memories do not need this system overhead. The memory will not block access at any VDD level that complies with the specified operating range. The user should take measures to prevent the processor from accessing memory when VDD is out-oftolerance. The common design practice of holding a processor in reset during powerdown may be sufficient. It is recommended that Chip Enable is pulled high and allowed to track VDD during powerup and powerdown cycles. It is the user’s responsibility to ensure that chip enable is high to prevent accesses below VDD min. (2.7V). Figure 3 shows a pullup resistor on /CE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /CE pin tracks VDD yet a high enough value that the current drawn when /CE is low is not an issue. VDD R FM18W08 CE MCU/ MPU WE OE A(14:0) DQ Figure 3. Use of Pullup Resistor on /CE Rev. 2.0 Dec. 2011 Page 5 of 11 FM18W08 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.0V -55C to + 125C 260 C 4kV 1.25kV 300V MSL-2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above thos e listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max VDD Power Supply 2.7 3.3 5.5 IDD VDD Supply Current 12 ISB Standby Current 20 50 ILI Input Leakage Current 1 ILO Output Leakage Current 1 VIH Input High Voltage 0.7*VDD VDD+0.3 VIL Input Low Voltage -0.3 0.3*VDD VOH1 Output High Voltage (IOH = -1 mA, VDD=2.7V) 2.4 VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 VOL1 Output Low Voltage (IOL = 2 mA, VDD=2.7V) 0.4 VOL2 Output Low Voltage (IOL = 150 A) 0.2 Notes 1. VDD = 5.5V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded. 2. /CE at VIH, All other pins at CMOS levels (0.2V or VDD-0.2V). 3. VIN, VOUT between VDD and VSS. Units V mA A A A V V V V V V Notes 1 2 3 3 Rev. 2.0 Dec. 2011 Page 6 of 11 FM18W08 Read Cycle AC Parameters (TA = -40C to + 85C, CL = 30 pF, unless otherwise specified) VDD 2.7 to 3.0V VDD 3.0 to 5.5V Symbol Parameter Min Max Min Max tCE Chip Enable Access Time (to data valid) 80 70 tCA Chip Enable Active Time 80 70 tRC Read Cycle Time 145 130 tPC Precharge Time 65 60 tAS Address Setup Time 0 0 tAH Address Hold Time 15 15 tOE Output Enable Access Time 15 12 tHZ Chip Enable to Output High-Z 15 15 tOHZ Output Enable to Output High-Z 15 15 Write Cycle AC Parameters (TA = -40C to + 85C, unless otherwise specified) VDD 2.7 to 3.0V VDD 3.0 to 5.5V Symbol Parameter Min Max Min Max tCA Chip Enable Active Time 80 70 tCW Chip Enable to Write High 80 70 tWC Write Cycle Time 145 130 tPC Precharge Time 65 60 tAS Address Setup Time 0 0 tAH Address Hold Time 15 15 tWP Write Enable Pulse Width 50 40 tDS Data Setup 40 30 tDH Data Hold 0 0 tWZ Write Enable Low to Output High Z 15 15 tWX Write Enable High to Output Driven 10 10 tHZ Chip Enable to Output High-Z 15 15 tWS Write Enable Setup 0 0 tWH Write Enable Hold 0 0 Units ns ns ns ns ns ns ns ns ns Notes 1 1 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 2 2 Notes 1 This parameter is periodically sampled and not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing specification associated with this relationship. Data Retention Symbol Parameter TDR @ +85ºC @ +80ºC @ +75ºC Min 10 19 38 Max - Units Years Years Years Notes Rev. 2.0 Dec. 2011 Page 7 of 11 FM18W08 Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter CI/O Input/Output Capacitance (DQ) CIN Input Capacitance AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Min - Max 8 6 Units pF pF Notes Equivalent AC Load Circuit 10% and 90% of VDD 5 ns 0.5 VDD Read Cycle Timing t RC t CA t PC CE t AS t AH A0-14 t OE OE t OHZ DQ0-7 t CE t HZ Write Cycle Timing - /CE Controlled Timing t WC t CA t PC CE t AS t AH A0-14 t WS t WH WE OE t DS t DH DQ0-7 Rev. 2.0 Dec. 2011 Page 8 of 11 FM18W08 Write Cycle Timing - /WE Controlled Timing t WC t CA t PC tC W t AH CE t AS A0-14 t WS t WH t WP WE OE t WZ t WX DQ0-7 out t DS t DH DQ0-7 in Power Cycle Timing VDD VDD (min) t PD t PC VDD (min) t PU VIH (min) VIL (max) CE VIH (min) Power Cycle Timing (TA = -40C to + 85C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units tPU VDD(min) to First Access Start 10 ms tPD Last Access Complete to VDD(min) 0 s tVR VDD Rise Time 30 s/V tVF VDD Fall Time 100 s/V Notes 1. Slope measured at any point on V DD waveform. Notes 1 1 Rev. 2.0 Dec. 2011 Page 9 of 11 FM18W08 28-pin SOIC (JEDEC MS-013 variation AE) All dimensions in millimeters 7.50 ±0.10 10.30 ±0.30 Pin 1 17.90 ±0.20 2.35 2.65 45 0? 8? 1.27 typ 0.33 0.51 0.10 0.30 0.10 0.25 0.75 0.23 0.32 0.40 1.27 SOIC Package Marking Scheme Legend: XXXXXX= part number, P= package type (-SG) R=rev code, YY=year, WW=work week, LLLLLL= lot code Example: FM18W08, 70ns speed, “Green”/RoHS SOIC package, A die rev., Year 2010, Work Week 37, Lot code 00002G RAMTRON FM18W08-SG A103700002G RAMTRON XXXXXXX-P RYYWWLLLLLL Rev. 2.0 Dec. 2011 Page 10 of 11 FM18W08 Revision History Revision 1.0 1.1 1.2 2.0 Date 11/22/2010 12/20/2010 3/10/2011 12/20/2011 Summary Initial Release Updated MSL rating. Changed tPU and tVF spec limits. Changed to Pre-Production status. Rev. 2.0 Dec. 2011 Page 11 of 11