FM24VN10-G

Preliminary FM24V10 1Mb Serial 3V F-RAM Memory Features 1M bit Ferroelectric Nonvolatile RAM • Organized as 131,072 x 8 bits • High Endurance 100 Trillion (1014) Read/Writes • 10 year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface • Up to 3.4 MHz maximum bus frequency • Direct hardware replacement for EEPROM • Supports legacy timing for 100 kHz & 400 kHz Device ID and Serial Number • Device ID reads out Manufacturer ID & Part ID • Unique Serial Number (FM24VN10) Low Voltage, Low Power Operation • Low Voltage Operation 2.0V – 3.6V • Active Current < 150 µA (typ. @ 100KHz) • 90 µA Standby Current (typ.) • 5 µA Sleep Mode Current (typ.) Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 8-pin “Green”/RoHS SOIC Package available in industry standard 8-pin SOIC package using a familiar two-wire (I2C) protocol. The FM24VN10 is offered with a unique serial number that is read-only and can be used to identify a board or system. Both devices incorporate a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The devices are guaranteed over an industrial temperature range of -40°C to +85°C. Description The FM24V10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24V10 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM24V10 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24V10 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The devices are Pin Configuration NC A1 A2 VSS 1 2 3 4 8 7 6 5 VDD WP SCL SDA Pin Name A1, A2 SDA SCL WP VDD VSS Function Device Select Address Serial Data/address Serial Clock Write Protect Supply Voltage Ground This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.1 Feb. 2009 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 15 FM24V10 - 1Mb I2C FRAM Counter Address Latch 16K x 64 FRAM Array 8 SDA Serial to Parallel Converter Data Latch 8 Control Logic Device ID and Serial Number SCL WP A1, A2 Figure 1. FM24V10 Block Diagram Pin Description Pin Name A1, A2 Type Input Pin Description Device Select Address 1, 2: These pins are used to select one of up to 4 devices of the same type on the same two-wire bus. To select the device, the address value on the two pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of the part on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. Write Protect: When tied to VDD, addresses in the entire memory map will be writeprotected. When WP is connected to ground, all addresses may be written. This pin is pulled down internally. Supply Voltage Ground SDA I/O SCL WP VDD VSS Input Input Supply Supply Rev. 1.1 Feb. 2009 Page 2 of 15 FM24V10 - 1Mb I2C FRAM Overview The FM24V10 is a family of serial F-RAM memory devices. The memory array is logically organized as a 131,072 x 8 bit memory array and is accessed using an industry standard two-wire (I2C) interface. Functional operation of the F-RAM is similar to serial EEPROM. The major difference between the FM24V10 and serial EEPROM is F-RAM’s superior write performance. Two-wire Interface The FM24V10 employs a bi-directional two-wire bus protocol using few pins or board space. Figure 2 illustrates a typical system configuration using the FM24V10 in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24V10 always is a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including start, stop, data bit, or acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. VDD Memory Architecture When accessing the FM24V10, the user addresses 131,072 locations each with 8 data bits. These data bits are shifted serially. The 131,072 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other non-memory devices), a page select bit, and a 2-byte address. The 17-bit address consists of a page select bit followed by 16-bits. The complete address of 17 bits specifies each byte address uniquely. The access time for memory operation is essentially zero beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24V10 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that it is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. Microcontroller Rmin = 1.1 Kohm Rmax = tR/Cbus SDA SCL SDA SCL FM24V10 A1 A2 FM24V10 A1 A2 Figure 2. Typical System Configuration Rev. 1.1 Feb. 2009 Page 3 of 15 FM24V10 - 1Mb I2C FRAM SCL SDA Stop (Master) Start (Master) 7 6 0 Data bit Acknowledge (Transmitter) (Receiver) Data bits (Transmitter) Figure 3. Data Transfer Protocol Second and most common, the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24V10 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24V10 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. Slave Address The first byte that the FM24V10 expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type or slave ID, the device select address bits, a page select bit, and a bit that specifies if the transaction is a read or a write. Bits 7-4 are the device type (slave ID) and should be set to 1010b for the FM24V10. These bits allow other function types to reside on the 2-wire bus within an identical address range. Bits 3 and 2 are the device select address bits. They must match the corresponding value on the external address pins to select the device. Up to four FM24V10 devices can reside on the same two-wire bus by assigning a different address to each. Bit 1 is the page select bit and is effectively the address MSB, A16. It specifies the 64K-byte block of memory that is targeted for the current operation. Bit 0 is the read/write bit. R/W=1 indicates a read operation and R/W=0 indicates a write operation. High Speed Mode (HS-mode) The FM24V10 supports a 3.4MHz high speed mode. A master code (0000 1XXXb) must be issued to place the device into high speed mode. Communication between master and slave will then be enabled for speeds up to 3.4MHz. A stop condition will exit HSmode. Single- and multiple-byte reads and writes are supported. See Figures 10 and 11 for HS-mode timings. Stop Condition A stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations using the FM24V10 should end with a stop condition. If an operation is in progress when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a stop condition. Start Condition A start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All commands should be preceded by a start condition. An operation in progress can be aborted by asserting a start condition at any time. Aborting an operation using the start condition will ready the FM24V10 for a new operation. If during operation the power supply drops below the specified VDD minimum, the system should issue a start condition prior to performing another operation. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Acknowledge The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a no-acknowledge and the operation is aborted. The receiver would fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the no-acknowledge ceases the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Rev. 1.1 Feb. 2009 Page 4 of 15 FM24V10 - 1Mb I2C FRAM Memory Operation Slave ID Device Select Page Select 1 7 0 6 1 5 0 4 A2 3 A1 2 A16 1 R/W 0 Figure 4. Slave Address Addressing Overview After the FM24V10 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires a 1-bit page select and two bytes. Since the device uses 17 address bits, the page select bit is the MSB of the address followed by the remaining 16 address bits. The complete 17-bit address is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch -- either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24V10 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (1FFFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After the address information has been transmitted, data transfer between the bus master and the FM24V10 can begin. For a read operation the FM24V10 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24V10 will transfer the next sequential byte. If the acknowledge is not sent, the FM24V10 will end the read operation. For a write operation, the FM24V10 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. The FM24V10 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of F-RAM technology. These improvements result in some differences between the FM24V10 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address, then a memory address. The bus master indicates a write operation by setting the LSB of the slave address (R/W bit) to a ‘0’. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 1FFFFh to 0000h. Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8th data bit. The FM24V10 uses no page buffering. The memory array can be write-protected using the WP pin. This feature is available only on FM24V10 and FM24VN10 devices. Setting the WP pin to a high condition (VDD) will write-protect all addresses. The FM24V10 will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a low state (VSS) will deactivate this feature. WP is pulled down internally. Figures 5 and 6 below illustrate a single-byte and multiple-byte write cycles. Rev. 1.1 Feb. 2009 Page 5 of 15 FM24V10 - 1Mb I2C FRAM By Master Start P 0 S Address & Data Stop S Slave Address A Address MSB A Address LSB A Data Byte A P By FM24V10 Acknowledge Figure 5. Single Byte Write Start By Master S By FM24V10 Slave Address P 0 S Address & Data Stop A Address MSB A Address LSB A Data Byte A Data Byte A P Acknowledge Figure 6. Multiple Byte Write There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24V10 attempts to read out additional data onto the bus. The four valid methods are: 1. The bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clock cycle. This is illustrated in the diagrams below. This is preferred. The bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. The bus master issues a stop in the 9th clock cycle. The bus master issues a start in the 9th clock cycle. Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V10 uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned above the FM24V10 uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to a ‘1’. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V10 will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM24V10 should read out the next sequential byte. 2. 3. 4. If the internal address reaches 1FFFFh, it will wrap around to 0000h on the next read cycle. Figures 7 and 8 below show the proper operation for current address reads. Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24V10 acknowledges the address, the bus master Rev. 1.1 Feb. 2009 Page 6 of 15 FM24V10 - 1Mb I2C FRAM issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a ‘1’. The operation is now a current address read. By Master Start Address No Acknowledge Stop S By FM24V10 Slave Address X 1 A Data Byte 1 P Acknowledge Data Figure 7. Current Address Read By Master Start Address Acknowledge No Acknowledge Stop S By FM24V10 Slave Address X1 A Data Byte A Data Byte 1P Acknowledge Data Figure 8. Sequential Read Start By Master S Slave Address P 0 S Address Start Address No Acknowledge Stop A Address MSB A Address LSB A S Slave Address X 1 A Data Byte 1P By FM24V10 Acknowledge Data Figure 9. Selective (Random) Read Start By Master S HS-mode command Start & Enter HS-mode Address No Acknowledge Stop & Exit HS-mode Data Byte 1 P 0 0 0 0 1 X X X 1 S Slave Address X 1 A By FM24V10 No Acknowledge Acknowledge Data Figure 10. HS-mode Current Address Read Start By Master S HS-mode command Start & Enter HS-mode Address & Data Stop & Exit HS-mode 0 0 0 0 1 X X X 1 S Slave Address P 0A S Address MSB A Address LSB A Data Byte AP By FM24V10 No Acknowledge Acknowledge Figure 11. HS-mode Byte Write Rev. 1.1 Feb. 2009 Page 7 of 15 FM24V10 - 1Mb I2C FRAM Sleep Mode A low power mode called Sleep Mode is implemented on both FM24V10 and FM24VN10 devices. The device will enter this low power state when the Sleep command 0x86 is clocked-in. Sleep Mode entry can be entered as follows: 1. 2. 3. The master sends a START command. The master sends Reserved Slave ID 0xF8 The master sends the I2C-bus slave address of the slave device it needs to identify. The last two bits are ‘Don’t care’ values (Page Select and R/W bits). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. 5. 6. 7. The master sends a Re-START command. The master sends Reserved Slave ID 0x86 The FM24V10 sends an ACK. The master sends STOP to ensure the device enters sleep mode. Once in sleep mode, the device draws IZZ current, but the device continues to monitor the I2C pins. Once the master sends a Slave Address that the FM24V10 identifies, it will “wakeup” and be ready for normal operation within tREC (400 µs max.). As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. While the device is waking up, it will NACK the master until it is ready. Start By Master S Rsvd Slave ID (F8) Address Start Address Stop A Slave Address X X A S Rsvd Slave ID (86) A P By FM24V10 Acknowledge Figure 12. Sleep Mode Entry Rev. 1.1 Feb. 2009 Page 8 of 15 FM24V10 - 1Mb I2C FRAM Device ID The FM24V10 and FM24VN10 devices incorporate a means of identifying the device by providing three bytes of data, which are manufacturer, product ID, and die revision. The Device ID is read-only. It can be accessed as follows: 1. 2. 3. The master sends a START command. The master sends Reserved Slave ID 0xF8 The master sends the I2C-bus slave address of the slave device it needs to identify. The last two bits are ‘Don’t care’ values (Page Select and R/W bits). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). Start By Master S Rsvd Slave ID (F8) Address Start Address Acknowledge 4. 5. 6. 7. The master sends a Re-START command. The master sends Reserved Slave ID 0xF9 The Device ID Read can be done, starting with the 12 manufacturer bits, followed by the 9 part identification bits, and then the 3 die revision bits. The master ends the Device ID read sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Note: The reading of the Device ID can be stopped anytime by sending a NACK command. No Acknowledge Stop A Slave Address X X A S Rsvd Slave ID (F9) A Data Byte A Data Byte A Data Byte 1 P By FM24V10 Acknowledge Data Figure 13. Read Device ID Manufacturer ID 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0 0 8 0 7 1 6 0 Product ID 5 0 4 N 3 V 2 V 1 V 0 0 Die Rev. 2 0 1 0 0 0 Ramtron Density Variation Figure 14. Manufacturer and Product ID Density: 02h=256Kb, 03h=512Kb, 04=1Mb Variation: Product ID bit 4 = S/N, Product ID bits 3-1 = VTP option, Product ID bit 0 = reserved The 3-byte hex code for an FM24V10 will be: The 3-byte hex code for an FM24VN10 will be: The 3-byte hex code for an FM24VR10-G1 will be: The 3-byte hex code for an FM24VR10-G2 will be: The 3-byte hex code for an FM24VRN10-G1 will be: The 3-byte hex code for an FM24VRN10-G2 will be: 0x00 0x00 0x00 0x00 0x00 0x00 0x44 0x44 0x44 0x44 0x44 0x44 0x00 0x80 0x10 0x20 0x90 0xA0 Rev. 1.1 Feb. 2009 Page 9 of 15 FM24V10 - 1Mb I2C FRAM Unique Serial Number (FM24VN10 only) The FM24VN10 device also incorporates a read-only 8-byte serial number. It can be used to uniquely identify a pc board or system. The serial number includes a 40-bit unique number, an 8-bit CRC, and a 16-bit number that can be defined upon request by the customer. If a customer-specific number is not requested, the 16-bit Customer Identifier is 0x0000. The 8 bytes of data are accessed via a Slave Address sequence similar to the Device ID. The serial number can be read by the system as follows: 1. 2. 3. The master sends a START command The master sends Reserved Slave ID 0xF8 The master sends the I2C-bus slave address of the slave device it needs to identify. The last two bits are ‘Don’t care’ values. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). The master sends a Re-START command The master sends Reserved Slave ID 0xCD to read the serial number. The master ends the serial number read sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. 4. 5. 6. The 8-bit CRC value can be used to compare to the value calculated by the controller. If the two values match, then the communication between slave and master was performed without errors. CUSTOMER IDENTIFIER * 40-bit UNIQUE NUMBER 8-bit CRC SN(63:56) SN(55:48) SN(47:40) SN(39:32) SN(31:24) * Contact factory for requesting a customer identifier number. SN(23:16) SN(15:8) SN(7:0) Figure 15. 8-Byte Serial Number (read-only) Start By Master S Rsvd Slave ID (F8) Address Start Address Acknowledge No Acknowledge Stop A Slave Address XX A S Rsvd Slave ID (CD) A Data Byte 7 A A Data Byte 0 1 P By FM24VN10 Acknowledge Data Figure 16. Read Serial Number Rev. 1.1 Feb. 2009 Page 10 of 15 FM24V10 - 1Mb I2C FRAM Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) Package Moisture Sensitivity Level Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1.0V * -55°C to +125°C 300° C TBD TBD TBD MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Main Power Supply 2.0 3.6 V IDD VDD Supply Current @ SCL = 100 kHz 175 µA @ SCL = 1 MHz 400 µA @ SCL = 3.4 MHz 1000 µA ISB Standby Current 90 150 µA IZZ Sleep Mode Current 5 8 µA ILI Input Leakage Current ±1 µA ILO Output Leakage Current ±1 µA VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL1 Output Low Voltage (IOL = 2 mA, VDD ≥ 2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 µA) 0.2 V RIN Address Input Resistance (WP, A2-A1) 50 For VIN = VIL (max) KΩ 1 For VIN = VIH (min) MΩ VHYS Input Hysteresis 0.05 VDD V Notes 1 2 2 3 3 5 4 Notes 1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A1 pins. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is stronger (50KΩ) when the input voltage is below VIL and weak (1MΩ) when the input voltage is above VIH. Rev. 1.1 Feb. 2009 Page 11 of 15 FM24V10 - 1Mb I2C FRAM AC Parameters (TA = -40° C to + 85° C, VDD =2.0V to 3.6V unless otherwise specified) F/S-mode HS-mode (CL