FM25640-S

FM25640 64Kb FRAM Serial Memory Features 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 45 Year Data Retention • NoDelay™ Writes • Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SPI • Up to 5 MHz maximum bus frequency • Direct hardware replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme • Hardware Protection • Software Protection Low Power Consumption • 10 µA Standby Current Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 8-pin SOIC • “Green” 8-pin SOIC Description The FM25640 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25640 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25640 is capable of supporting up to 1012 read/write cycles -- far more than most systems will require from a serial memory. These capabilities make the FM25640 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25640 provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25640 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration CS SO WP VSS 1 2 3 4 8 7 6 5 VDD HOLD SCK SI Pin Names /CS /HOLD /WP SCK SI SO VDD VSS Function Chip Select Hold Write Protect Serial Clock Serial Data Input Serial Data Output 5V Ground Ordering Information FM25640-S FM25640-G 8-pin SOIC “Green” 8-pin SOIC This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Rev. 3.0 Mar. 2005 1 of 13 FM25640 WP CS HOLD SCK Instruction Decode Clock Generator Control Logic Write Protect 2,048 x 32 FRAM Array Instruction Register ` Address Register Counter 13 8 Data I/O Register 3 Nonvolatile Status Register SO Figure 1. Block Diagram Pin Description Pin Name /CS I/O Input Pin Description Chip Select: Enables and disables the device. When /CS is high, the output pin SO is hiZ, all other inputs are ignored, and the device remains in a low-power standby mode. When /CS is low, the part will respond to the SCK signal. A falling edge on /CS must occur for every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. The device is static so the clock frequency may be any value between 0 and 5 MHz and may be interrupted at any time. Hold: The /HOLD signal is used when the host CPU must interrupt a memory operation for another task. Asserting the /HOLD signal low pauses the current operation. The device ignores SCK and /CS. All transitions on /HOLD must occur while SCK is low. Write Protect: This pin prevents write operations to the status register. This is critical since other write protection features are controlled through the status register. A complete explanation of write protection is provided below. *Note that the function of /WP is different from the FM25040 where it prevents all writes to the part. Serial Input: SI is the data input pin. It is sampled on the rising edge of SCK and is ignored otherwise. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. Serial Output: SO is the data output pin. It is driven during read cycles and remains hi-Z at all other times including when HOLD\ is low. Data transitions are driven on the falling edge of the serial clock. * SO can be connected to SI for a single pin data interface since the part communicates in half-duplex. Supply Voltage: 5V Ground SCK /HOLD /WP Input Input Input SI Input SO Output VDD VSS Supply Supply Rev. 3.0 Mar. 2005 2 of 13 FM25640 Overview The FM25640 is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25640 and a serial EEPROM with the same pinout relates to its superior write performance. Serial Peripheral Interface – SPI Bus The FM25640 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 5 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25640 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. It is possible to connect the two data lines together. Figure 2 illustrates a typical system configuration using the FM25640 with a microcontroller that offers an SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the SPI bus. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25640 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock, and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25640 supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. In both cases, data is clocked into the FM25640 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The FM25640 is controlled by SPI op-codes. These op-codes specify the commands to the part. After /CS is asserted, the first byte transferred from the bus master is the op-code. Following the op-code, addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. Memory Architecture When accessing the FM25640, the user addresses 8,192 locations of 8 data bits each. These data bits are shifted in and out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code and a two-byte address. The upper 3 bits of the address range are ignored by the device. The complete address of 13-bits specifies each byte address uniquely. Most functions of the FM25640 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25640 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25640 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Rev. 3.0 Mar. 2005 3 of 13 FM25640 SPI Microcontroller FM25640 FM25640 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Figure 2. System Configuration with SPI port P1.0 P1.1 Microcontroller FM25640 P1.2 Figure 3. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 7 6 5 4 3 2 1 0 SPI Mode 3: CPOL=1, CPHA=1 7 6 5 4 3 2 1 0 Figure 4. SPI Modes 0 & 3 Rev. 3.0 Mar. 2005 4 of 13 FM25640 Data Transfer All data transfers to and from the FM25640 occur in 8-bit groups. They are synchronized to the clock signal (SCK) and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. The SO output is driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25640. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by an address and one or more bytes of data. Table 1. Op-code Commands Name Description WREN WRDI RDSR WRSR READ WRITE Set Write Enable Latch Write Disable Read Status Register Write Status Register Read Memory Data Write Memory Data WREN - Set Write Enable Latch The FM25640 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Op-code value 0000_0110b 0000_0100b 0000_0101b 0000_0001b 0000_0011b 0000_0010b Figure 5. WREN Bus Configuration Figure 6. WRDI Bus Configuration Rev. 3.0 Mar. 2005 5 of 13 FM25640 RDSR - Read Status Register The RDSR command allows the bus master to verify the contents of the Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR opcode, the FM25640 will return one byte with the contents of the Status register. The Status register is described in detail below. WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Note that on the FM25640, /WP only prevents writing to the Status register, not the memory array. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus configuration of RDSR and WRSR in the timing diagrams below. Figure 7. RDSR Bus Configuration Figure 8. WRSR Bus Configuration Status Register & Write Protection The write protection features of the FM25640 are multi-tiered. First, a WREN op-code must be issued prior to any write operation. Assuming that writes are enabled using WREN, writes to memory are controlled by the Status register. As described above, writes to the status register are performed using the WRSR command and subject to the /WP pin. The Status Register is organized as follows. Table 2. Status Register Bit Name 7 WPEN 6 0 5 0 4 0 3 BP1 2 BP0 1 WEL 0 0 Latch. This bit is internally set by the WREN command and is cleared by terminating a write cycle (/CS high) or by using the WRDI command. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are writeprotected as shown in the following table. Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 1800h to 1FFFh (upper ¼) 1 0 1000h to 1FFFh (upper ½) 1 1 0000h to 1FFFh (all) Bits 0 and 4-6 are fixed at 0 and cannot be modified. Note that bit 0 (Ready in EEPROMs) is unnecessary as the FRAM writes in real-time and is never busy. The WPEN, BP1 and BP0 control write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Rev. 3.0 Mar. 2005 6 of 13 FM25640 The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /WP pin. When WPEN is low, the /WP pin is ignored. When WPEN is high, the /WP pin controls write access to the status register. Thus the Status register is write protected if WPEN=1 and /WP=0. This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions. Table 4. Write Protection WEL WPEN /WP 0 X X 1 0 X 1 1 0 1 1 1 Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Unprotected Unprotected Unprotected Status Register Protected Unprotected Protected Unprotected Memory Operation The SPI interface, with its relatively high maximum clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25640 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8th clock). The rising edge of /CS terminates a WRITE op-code operation. Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. Following this instruction is a twobyte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first byte of the read operation. After the op-code and address are complete, the SI line is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation. The bus configuration for read and write operations is shown below. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. Rev. 3.0 Mar. 2005 7 of 13 FM25640 CS 0 SCK op-code SI SO 0 0 0 0 0 0 1 0 X MSB X X 13-bit Address 12 11 10 Data 54 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 4 3 2 1 0 7 6 3 2 1 0 LSB LSB MSB Figure 9. Memory Write CS 0 SCK op-code SI 0 0 0 0 0 0 1 1 X MSB SO X 13-bit Address X 12 11 10 4 3 2 1 0 LSB MSB 7 6 5 Data 43 2 1 LSB 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 10. Memory Read be located within the same row. In the FM25640, there are 2048 rows each 32 bits wide. Each 4 bytes in the address mark the beginning of a new row. Regardless, FRAM read and write endurance is effectively unlimited at the 5MHz clock speed. Even at 2000 accesses per second to the same row, 15 years time will elapse before 1012 endurance cycles occur. Endurance Internally, a FRAM operates with a read and restore mechanism similar to a DRAM. Therefore, endurance cycles are applied for each access: read or write. The FRAM architecture is based on an array of rows and columns. Each access causes a cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not Rev. 3.0 Mar. 2005 8 of 13 FM25640 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) Package Moisture Sensitivity Level Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.0V -55°C to + 125°C 300° C 4.5kV 1.25kV MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 4.5 5.0 5.5 V IDD VDD Supply Current mA 1 0.6 0.45 @ SCK = 1.0 MHz 1.2 0.9 @ SCK = 2.0 MHz 3.0 2.2 @ SCK = 5.0 MHz ISB Standby Current 1 10 2 µA ILI Input Leakage Current 3 ±1 µA ILO Output Leakage Current 3 ±1 µA VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL Output Low Voltage 0.4 V @ IOL = 2 mA VOH Output High Voltage V VDD - 0.8 @ IOH = -2 mA VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD. 4. This parameter is characterized but not 100% tested. Rev. 3.0 Mar. 2005 9 of 13 FM25640 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max fCK SCK Clock Frequency 0 5.0 tCH Clock High Time 90 tCL Clock Low Time 90 tCSU Chip Select Setup 90 tCSH Chip Select Hold 90 tOD Output Disable 100 tODV Output Data Valid 60 tOH Output Data Hold 0 tD Deselect Time 100 tR Data In Rise Time 1 tF Data In Fall Time 1 tH Data In Hold Time 30 tSU Data In Setup Time 20 tHS /HOLD Input Setup Time 70 tHH /HOLD Input Hold Time 40 tHZ /HOLD Low to Data Out Hi-Z 100 tLZ /HOLD High to Data Out Lo-Z 50 Notes 1. 2. 3. Rise and fall times measured between 10% and 90% of waveform. This parameter is characterized but not 100% tested. For Clock High Time tCH ≤ 100 ns, the parameter tODV is extended such that tCH + tODV ≤ 160 ns. Units MHz ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns Notes 2 3 1,2 1,2 2 2 Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter CO Output Capacitance (SO) CI Input Capacitance Notes 1. This parameter is characterized and not 100% tested. Max 8 6 Units pF pF Notes 1 1 AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance 10% and 90% of VDD 10 ns 0.5 VDD 100 pF Rev. 3.0 Mar. 2005 10 of 13 FM25640 Serial Data Bus Timing tD tCSH tF tCSU tH 1/fCK tR tCL tCH tSU tODV tOH tOD /HOLD Timing Data Retention (VDD = 4.5V to 5.5V, +85°C) Parameter Data Retention Min 45 Units Years Notes Rev. 3.0 Mar. 2005 11 of 13 FM25640 Mechanical Drawing (8-pin SOIC - JEDEC MS-012, Variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 6.00 ±0.20 2.00 3.70 P in 1 1.27 0.65 4.90 ±0.10 1.35 1.75 0.25 0.50 45° 0.19 0.25 1.27 0.33 0.51 0.10 0.25 0.10 mm 0°- 8° 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25640, Standard SOIC package, Year 2004, Work Week 39 FM25640-S A40003S RIC0439 XXXXXXX-P LLLLLLL RICYYWW Rev. 3.0 Mar. 2005 12 of 13 FM25640 Revision History Revision 1.0 2.0 2.1 2.2 2.3 3.0 Date 10/23/00 10/21/02 8/5/03 11/10/03 3/17/04 3/31/05 Summary Changed status to Preliminary. Changed status to Production. Changed endurance from 1010 to 1012 cycles. Extended storage temperature limits. Removed DIP packaging option. Changed IDD limits. Changed Input & Output Leakage limits. Added note to Output Data Valid spec. Added “green” package. Updated package drawing. Changed Data Retention spec. Added ESD and package MSL ratings. Updated package drawing, added pcb footprint. Added note about powering down with /CS active (pg 3). Rev. 3.0 Mar. 2005 13 of 13