FM25V01

Preliminary FM25V01 128Kb Serial 3V F-RAM Memory Features 128K bit Ferroelectric Nonvolatile RAM  Organized as 16,384 x 8 bits  High Endurance 100 Trillion (1014) Read/Writes  10 Year Data Retention  NoDelay™ Writes  Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI  Up to 40 MHz Frequency  Direct Hardware Replacement for Serial Flash  SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme  Hardware Protection  Software Protection Device ID  Device ID reads out Manufacturer ID & Part ID Low Voltage, Low Power  Low Voltage Operation 2.0V – 3.6V  Active Current 120 A (typ. @ 1MHz)  Standby Current 90 A (typ.)  Sleep Mode Current 5 A (typ.) Industry Standard Configurations  Industrial Temperature -40C to +85C  8-pin “Green”/RoHS SOIC Package Description The FM25V01 is a 128-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories. Unlike Serial Flash, the FM25V01 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers very high write endurance, orders of magnitude more endurance tha n Serial Flash. Also, F-RAM exhibits lower power consumption than Serial Flash. These capabilities make the FM25V01 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of Serial Flash can cause data loss. The FM25V01 provides substantial benefits to users of Serial Flash as a hardware drop-in replacement. The device uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The device incorporates a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The device is guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration S Q W VSS 1 2 3 4 8 7 6 5 VDD HOLD C D Pin Name /S /W /HOLD C D Q VDD VSS Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage Ground This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.1 Sept. 2011 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 15 FM25V01 - 128Kb SPI FRAM W S HOLD C Instruction Decode Clock Generator Control Logic Write Protect 2K x 64 FRAM Array Instruction Register Address Register Counter D 14 8 Q Data I/O Register 3 Nonvolatile Status Register Figure 1. Block Diagram Pin Descriptions Pin Name /S I/O Input Description Chip Select: This active-low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the C signal. A falling edge on /S must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 40 MHz and may be interrupted at any time. Hold: The /HOLD pin is used when the host CPU must interrupt a memory o peration for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on C or /S. All transitions on /HOLD must occur while C is low. This pin has a weak internal pull-up (see RIN spec, pg 11). However, if it is not used, the /HOLD pin should be tied to VDD. Write Protect: This active-low pin prevents write operations to the Status Register only. A complete explanation of write protection is provided on pages 6 and 7. If not used, the /W pin should be tied to VDD. Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of C and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * D may be connected to Q for a single pin data interface. Serial Output: This is the data output pin. It is driven during a read and remains tri stated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * Q may be connected to D for a single pin data interface. Power Supply Ground C Input /HOLD Input /W Input D Input Q Output VDD VSS Supply Supply Rev. 1.1 Sept. 2011 Page 2 of 15 FM25V01 - 128Kb SPI FRAM Overview The FM25V01 is a serial F-RAM memory. The memory array is logically organized as 16,384 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to Serial Flash. The major differences between the FM25V01 and a Serial Flash with the same pinout are the F-RAM’s superior write performance, very high endurance, and lower power consumption. Memory Architecture When accessing the FM25V01, the user addresses 16K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a twobyte address. The complete address of 14-bits specifies each byte address uniquely. Most functions of the FM25V01 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike Serial Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25V01 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than Serial Flash since it is completed quickly. By contrast, Serial Flash requiring milliseconds to write is vulnerable to noise during much of the cycle. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25V01 will begin monitoring the clock and data lines. The relationship between the falling edge of /S, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25V01 supports only modes 0 and 3. Figure 2 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25V01 on the rising edge of C and data is expected on the first rising edge after /S goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /S is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Certain op-codes are commands with no subsequent data transfer. The /S must go inactive after an operation is complete and before a new op -code can be issued. There is one valid op-code only per active chip select. SPI Mode 0: CPOL=0, CPHA=0 S C D 7 MSB 6 5 4 3 2 1 0 LSB Serial Peripheral Interface – SPI Bus The FM25V01 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 40MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25V01 operates in SPI Mode 0 and 3. SPI Mode 3: CPOL=1, CPHA=1 S C D 7 MSB 6 5 4 3 2 1 0 LSB Figure 2. SPI Modes 0 & 3 Rev. 1.1 Sept. 2011 Page 3 of 15 FM25V01 - 128Kb SPI FRAM System Hookup The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25V01 devices with a microcontroller that has a dedicated SPI port, as Figure 3 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25V01 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 4 shows a configuration that uses only three pins. SCK MOSI MISO Q D C Q D C SPI Microcontroller SS1 SS2 HOLD1 HOLD2 FM25V01 S HOLD FM25V01 S HOLD MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Figure 3. 256Kbit (32KB) System Configuration with SPI port P1.0 P1.1 Microcontroller Q D C FM25V01 S P1.2 HOLD Vdd Figure 4. System Configuration without SPI port Rev. 1.1 Sept. 2011 Page 4 of 15 FM25V01 - 128Kb SPI FRAM Power Up to First Access The FM25V01 is not accessible for a period of time (tPU) after power up. Users must comply with the timing parameter tPU, which is the minimum time from VDD (min) to the first /S low. Data Transfer All data transfers to and from the FM25V01 occur in 8-bit groups. They are synchronized to the clock signal (C), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of C. Outputs are driven from the falling edge of clock C. Command Structure There are ten commands called op-codes that can be issued by the bus master to the FM25V01. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function, such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the Status Register. The third group includes commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description Set Write Enable Latch WREN Write Disable WRDI Read Status Register RDSR Write Status Register WRSR Read Memory Data READ FSTRD Fast Read Memory Data WRITE Write Memory Data Enter Sleep Mode SLEEP Read Device ID RDID without another WREN command. Figure 5 below illustrates the WREN command bus configuration. S 0 C 1 2 3 4 5 6 7 D Q 0 0 0 0 0 Hi-Z 1 1 0 Figure 5. WREN Timing WRDI – Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. S 0 C 1 2 3 4 5 6 7 Op-code 0000 0000 0000 0000 0000 0000 0000 1011 1001 0110b 0100b 0101b 0001b 0011b 1011b 0010b 1001b 1111b D Q 0 0 0 0 0 Hi-Z 1 0 0 Figure 6. WRDI Timing RDSR – Read Status Register The RDSR command allows the bus master to verify the contents of the Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR op-code, the FM25V01 will return one byte with the contents of the Status Register. The Status Register is described in detail in the section below. WREN – Set Write Enable Latch The FM25V01 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register (WRSR) and writing the memory (WRITE). Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes Rev. 1.1 Sept. 2011 Page 5 of 15 FM25V01 - 128Kb SPI FRAM WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /W pin must be high or inactive. Prior S C to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus configuration of RDSR and WRSR are shown below. D Q Figure 7. RDSR Timing S C D Q Figure 8. WRSR Timing (WREN not shown) Status Register & Write Protection The write protection features of the FM25V01 are multi-tiered. Taking the /W pin to a logic low state is the hardware write-protect function. Status Register write operations are blocked when /W is low. To write the memory with /W high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /W, writes to memory are controlled by the Status Register. As described above, writes to the Status Register are performed using the WRSR command and subject to the /W pin. The Status Register is organized as follows. Table 2. Status Register Bit Name 7 WPEN 6 0 5 0 4 0 3 BP1 2 BP0 1 WEL 0 0 state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are writeprotected as shown in the following table. Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 3000h to 3FFFh (upper ¼) 1 0 2000h to 3FFFh (upper ½) 1 1 0000h to 3FFFh (all) The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /W pin. When WPEN is low, the /W pin is ignored. When WPEN is high, the /W pin controls write access to the Status Register. Thus the Status Register is write protected if WPEN=1 and /W=0. This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and Page 6 of 15 Bits 0 and 4-6 are fixed at 0, and cannot can be modified. Note that bit 0 (“Ready” in Serial Flash) is unnecessary as the F-RAM writes in real-time and is never busy, so it reads out as a ‘0’. There is an exception to this when the device is waking up from Sleep Mode, which is described on the following page. The BP1 and BP0 control software write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its Rev. 1.1 Sept. 2011 FM25V01 - 128Kb SPI FRAM BP0 bits are set to 1, the WPEN bit is set to 1, and the /W pin is low. This occurs because the block protect bits prevent writing memory and the /W signal in hardware prevents altering the block protect Table 4. Write Protection WEL WPEN 0 X 1 0 1 1 1 1 bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions. /W X X 0 1 Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Unprotected Unprotected Unprotected Status Register Protected Unprotected Protected Unprotected Memory Operation The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike Serial Flash, the FM25V01 can perform sequential writes at bus speed. No page buffer is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value, which specifies the 14-bit address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 3FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in Figure 9. Unlike Serial Flash, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8th clock). The rising edge of /S terminates a WRITE op-code operation. Asserting /W active in the middle of a write operation will have no effect until the next falling edge of /S. Read Operation After the falling edge of /S, the bus master can issue a READ op-code. Following this instruction is a twobyte address value (A13-A0), specifying the address of the first data byte of the read operation. After the op-code and address are complete, the D pin is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 3FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /S terminates a READ opcode operation and tri-states the Q pin. A read operation is shown in Figure 10. Fast Read Operation The FM25V01 supports the FAST READ op-code (0Bh) that is found on Serial Flash devices. It is implemented for code compatibility with Serial Flash devices. Following this instruction is a two-byte address (A13-A0), specifying the address of the first data byte of the read operation. A dummy byte follows the address. It inserts one byte of read latency. The D pin is ignored after the op -code, 2byte address, and dummy byte are complete. The bus master issues 8 clocks, with one bit read out for each. The Fast Read operation is otherwise the same as an ordinary READ. If the last address of 3FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /S terminates a FAST READ op-code operation and tri-states the Q pin. A Fast Read operation is shown in Figure 11. Hold The FM25V01 device has a /HOLD pin that can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while C is low, the current operation will pause. Taking the /HOLD pin high while C is low will resume an operation. The transitions of /HOLD must occur while C is low, but the C and /S pins can toggle during a hold state. Rev. 1.1 Sept. 2011 Page 7 of 15 FM25V01 - 128Kb SPI FRAM S 0 C 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 4 5 6 7 0 1 2 3 4 5 6 7 op-code D 14-bit Add ress 0 1 0 X X 13 12 11 10 9 8 3 2 1 0 0 0 0 0 0 7 6 Data 54 3 2 1 0 LSB MSB Q LSB MSB Figure 9. Memory Write with 2-Byte Address (WREN not shown) S 0 C 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 4 5 6 7 0 1 2 3 4 5 6 7 op-code D 14-bit Address 0 1 1 X X 13 12 11 10 9 8 3 2 1 0 0 0 0 0 0 MSB Q LSB MSB 7 6 5 Data 4 3 2 1 LSB 0 Figure 10. Memory Read with 2-Byte Address S 0 C 1 2 3 4 5 6 7 0 1 2 3 5 6 7 4 5 6 7 0 1 2 3 4 5 6 7 op-code D 14-bit Address 0 1 1 X X 13 12 2 1 0 Dummy byte X X X X 0 0 0 0 1 MSB Q LSB MSB 7 6 5 Data 4 3 2 1 LSB 0 Figure 11. Fast Read with 2-Byte Address and Dummy Byte Rev. 1.1 Sept. 2011 Page 8 of 15 FM25V01 - 128Kb SPI FRAM Sleep Mode A low power mode called Sleep Mode is implemented on the FM25V01 device. The device will enter this low power state when the SLEEP opcode B9h is clocked-in and a rising edge of /S is applied. Once in sleep mode, the C and D pins are ignored and Q will be high-Z, but the device continues to monitor the /S pin. On the next falling edge of /S, the device will return to normal operation within tREC (400 s max.). The Q pin remains in a hiZ state during the wakeup period. The device will not necessarily respond to an opcode within the wakeup period. To start the wakeup procedure, the controller may send a “dummy” read, for example, and wait the remaining tREC time. It is not recommended to start the wakeup by asserting /S low, leaving /S low, and issuing clocks since the device wakeup is an asynchronous event and could misinterpret the opcodes. It is recommended that the controller deassert /S after each polled read opcode. Polling is the process of looking for expected data and allows the system to determine if the device has returned to a normal operating condition. Enter Sleep Mode S C D Q Figure 12. Sleep Mode Entry Device ID The FM25V01 device can be interrogated for its manufacturer, product identification, and die revision. The RDID op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are read -only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes a Family code, a Density code, a Sub code, and Product Revision code. Table 6. Manufacturer and Product ID 7 0 0 0 0 0 0 1 6 1 1 1 1 1 1 1 5 1 1 1 1 1 1 0 Bit 43 11 11 11 11 11 11 00 2 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 Hex 7F 7F 7F 7F 7F 7F C2 Hex 21h 00h Manufacturer ID Continuation code Continuation code Continuation code Continuation code Continuation code Continuation code JEDEC assigned Ramtron C2h in bank 7 Device ID (1st Byte) Device ID (2nd Byte) Family Density 00100001 Sub Rev. Rsvd 00000000 Density: 01h=128K, 02h=256K, 03h=512K, 04=1M 00h=FM25V01 S C ....... 9Fh 7Fh 1 D Q … 7Fh 6 C2h 21h 00h Six bytes of continuation code 7Fh Figure 13. Read Device ID Rev. 1.1 Sept. 2011 Page 9 of 15 FM25V01 - 128Kb SPI FRAM Endurance The FM25V01 device is capable of being accessed at least 1014 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A13-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 2K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op -code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 40MHz clock rate. Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop SCK Freq Endurance Endurance Years to Reach (MHz) Cycles/sec. Cycles/year 1014 Cycles 12 40 74,620 2.35 x 10 4 2 .6 85.1 20 37,310 1.18 x 1012 10 18,660 5.88 x 1011 1 7 0 .2 5 9,330 2.94 x 1011 340.3 Rev. 1.1 Sept. 2011 Page 10 of 15 FM25V01 - 128Kb SPI FRAM Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1.0V -55C to + 125C 260 C TBD 1.25kV 200V MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational sectio n of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reli ability. DC Operating Conditions (TA = -40C to + 85C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 2.0 3.3 3.6 V IDD Power Supply Operating Current 1 @ C = 1 MHz 0.12 0.22 mA @ C = 40 MHz 1 .3 2.5 mA ISB Standby Current 90 150 A 2 IZZ Sleep Mode Current 5 8 A 3 ILI Input Leakage Current A 4 1 ILO Output Leakage Current A 4 1 VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOH1 Output High Voltage (IOH = -1 mA, VDD=2.7V) 2.4 V VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 V VOL1 Output Low Voltage (IOL = 2 mA, VDD=2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 A) 0.2 V RIN Input Resistance (/HOLD pin) 5 For VIN = VIH (min) 40 K For VIN = VIL (max) 1 M Notes 1. C toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. 2. /S=VDD. All inputs VSS or VDD. 3. In Sleep mode and /S=VDD. All inputs VSS or VDD. 4. VSS  VIN  VDD and VSS  VOUT  VDD. 5. The input pull-up circuit is stronger (> 40K) when the input voltage is above VIH and weak (> 1M) when the input voltage is below VIL. Data Retention (TA = -40C to + 85C) Parameter Data Retention Min 10 Max - Units Years Notes Rev. 1.1 Sept. 2011 Page 11 of 15 FM25V01 - 128Kb SPI FRAM AC Parameters (TA = -40C to + 85C, CL = 30pF, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max fC C Clock Frequency 0 25 0 40 tCH Clock High Time 20 11 tCL Clock Low Time 20 11 tCSU Chip Select Setup 12 10 tCSH Chip Select Hold 12 10 tOD Output Disable Time 20 12 tODV Output Data Valid Time 18 9 tOH Output Hold Time 0 0 tD Deselect Time 60 40 tR Data In Rise Time 50 50 tF Data In Fall Time 50 50 tSU Data Setup Time 8 5 tH Data Hold Time 8 5 tHS /HOLD Setup Time 12 10 tHH /HOLD Hold Time 12 10 tHZ /HOLD Low to Hi-Z 25 20 tLZ /HOLD High to Data Active 25 20 Notes 1. Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 2 2,3 2,3 2 2 2. 3. tCH + tCL = 1/fC. This parameter is characterized but not 100% tested. Rise and fall times measured between 10% and 90% of waveform. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter CO Output Capacitance (Q) CI Input Capacitance Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance Serial Data Bus Timing Min - Max 8 6 Units pF pF Notes 1 1 10% and 90% of VDD 3 ns 0.5 VDD 30 pF tD S tCSU C 1/tCK tH tF tR tCL tCH tCSH tSU D tODV Q tOH tOD Rev. 1.1 Sept. 2011 Page 12 of 15 FM25V01 - 128Kb SPI FRAM /HOLD Timing S tHS tHH C tHH tHS HOLD Q tHZ tLZ Power Cycle Timing VDD min. tVR tPU tPD tVF VDD S Power Cycle & Sleep Timing (TA = -40 C to + 85 C, VDD = 2.0V to 3.6V, unless otherwise specified) Symbol Parameter Min Max Units Notes tVR VDD Rise Time 50 s/V 1,2 tVF VDD Fall Time 100 s/V 1,2 tPU Power Up (VDD min) to First Access (/S low) 250 s 3 tPD Last Access (/S high) to Power Down (VDD min) 0 s tREC Recovery Time from Sleep Mode 400 s Notes 1. This parameter is characterized and not 100% tested. 2. Slope measured at any point on VDD waveform. 3. Applies to VDD > 2.7V. When powering up to VDD < 2.7V, the tPU limit is 500 s. Rev. 1.1 Sept. 2011 Page 13 of 15 FM25V01 - 128Kb SPI FRAM Mechanical Drawing 8-pin SOIC (JEDEC MS-012 variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 6.00 ±0.20 2.00 3.70 Pin 1 1.27 0.65 4.90 ±0.10 1.35 1.75 0.25 0.50 45  0.19 0.25 1.27 0.33 0.51 0.10 0.25 0.10 mm 0- 8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXXX= part number, P=package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25V01, “Green”/RoHS SOIC package, Rev. A, Lot 9646447, Year 2010, Work Week 21 FM25V01-G A9646447 RIC1021 XXXXXX-P RLLLLLLL RICYYWW Rev. 1.1 Sept. 2011 Page 14 of 15 FM25V01 - 128Kb SPI FRAM Revision History Revision 1.0 1.1 Date 10/20/2010 9/22/2011 Summary Initial release. Removed S/N ordering option. Added note to tPU timing parameter when VDD powers up to < 2.7V. Ordering Information Part Number FM25V01-G FM25V01-GTR Features Device ID Device ID Operating Voltage 2.0-3.6V 2.0-3.6V Package 8-pin “Green”/RoHS SOIC 8-pin “Green”/RoHS SOIC, Tape & Reel Rev. 1.1 Sept. 2011 Page 15 of 15