R1610

RDC® R1610 RISC DSP Communication FAST ETHERNET RISC PROCESSOR FAST ETHERNET RISC PROCESSOR R1610 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 4 REV 1.0 Nov. 25 2005 RDC® 1. Features l l l R1610 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Five-stage pipeline RISC architecture Bus interface - Multiplexed address and data bus - Supports non-multiplexed address bus A[19:0] - 8-bit or 16-bit external bus dynamic access - 1M-byte memory address space - 64K-byte I/O space - Supports an independent bus for the slower I/O device l l Three independent 16-bit timers and one independent programmable watchdog timer The Interrupt controller with five maskable external interrupts and one non-maskable external interrupt l l l l l l l l Two independent DMA channels Programmable chip-select logic for memory or I/O bus cycle decoder Programmable wait-state generators With 8-bit or 16-bit boot ROM bus size 1-port Fast Ethernet MAC with MII interface With 25MHz input frequency and up to 4x25MHz maximum internal frequency Compatible with 3.3V I/O With 128-pin PQFP package type l l l l l Software is compatible with the 80C186 microprocessor Supports two 16550 UART serial channels with 16-byte FIFO Supports CPU ID Supports 18 PIO pins SDRAM control Interface Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 4 REV 1.0 Nov. 25 2005 RDC® R1610 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 2. Block Diagram INT2/INTA0_n CLKOUTA INT[6:5] INT1/SELECT_n INT0 NMI TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Managemen t Interrupt Control Unit Timer Control Unit DMA Unit RST_n MAC MII UCS_n PCS5_n PCS[3:0]_n Chip Select Unit Instruction Queue (64bits) Instruction Decoder Control Signal Micro ROM PIO Unit EA / LA Address 16550 UART Serial Port0 DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n DCD1_n SIN1 DSR1_n CTS1_n RTS1_n SOUT1 DTR1_n ARDY Refresh Control Unit Register File General, Segment, Eflag Register SD_CLK WE_n CAS_n RAS_n SDRAM/Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit 16550 UART Serial Port1 A[19:0] AD[15:0] RD_n ALE WR_n/BWSEL Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 4 REV 1.0 Nov. 25 2005 RDC® 3. R1610 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Package Information PQFP 128 pins 23.2 ± 0.2mm 20.0 ± 0.1mm 102 65 103 64 RDC R1610 XXXX-B-QF XX-XXXXX 128 17.2 ± 0.2mm 14.0 ± 0.1mm 39 Pin 1 Identifier 1 0.22 ± 0.05mm 38 0.5mm BSC 3.40mm (Max.) 2.85 ± 0.12mm 0.145 ± 0.055mm 0.25mm (Min.) Seating Plane Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 4 REV 1.0 Nov. 25 2005