R2010

RDC® R2010 RISC DSP Communication FAST ETHERNET RISC PROCESSOR FAST ETHERNET RISC PROCESSOR R2010 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 4 REV 1.0 Nov. 28 2005 RDC® 1. Features l l l R2010 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Five-stage pipeline RISC architecture Bus interface - Multiplexed address and Data bus - Supports non-multiplexed address bus A [20:0] - 16-bit external bus dynamic access - 16M-byte memory address space - 64K-byte I/O space - Supports an independent data/address bus for external I/O device - Supports a glueless and simplified 16-bit PCMCIA bus interface l l l l l l l l l l l Three independent 16-bit timers and one independent programmable watchdog timer The Interrupt controller with five maskable external interrupts Two independent DMA channels Programmable chip-select logic for Memory or I/O bus cycle decoder Programmable wait-state generator With 8-bit or 16-bit Boot ROM bus size 1-Port Fast Ethernet MAC with MII interface Supports an 8K-byte Uniform cache With 25MHz input frequency and up to 100MHz maximum internal frequency. Compatible with 3.3V I/O and 2.5V core voltage. Package Type includes 128-pin PQFP. l l l Supports two compatible UART serial channels with 16-byte FIFO and hardware flow-control. Supports CPU ID SDRAM control Interface Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 4 REV 1.0 Nov. 28 2005 RDC® R2010 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 2. Block Diagram INT2 CLKOUTA INT6-INT5 INT1 INT0 TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST_n Cache MCS_n UCS_n PCS5_n, PCS3_n, PCS2_n, PCS0_n Chip Select Unit Instruction Decoder Control Signal Register File General, ARDY Refresh Control SD_CLK WE_n CAS_n RAS_n BA[1:0] SDRAM/Bus Interface Unit Unit Segment, Eflag Register Micro ROM Instruction Queue (64bits) MAC MII PIO Unit EA / LA Address 16550 UART Serial Port0 DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n SIN1 ALU (Special, Logic, Adder, BSF) 16550 UART Execution Unit Serial Port1 CTS1_n RTS1_n SOUT1 A[20:0] D[15:0] RD_n WHB_n WLB_n ALE WR_n/BWSEL Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 4 REV 1.0 Nov. 28 2005 RDC® 3. R2010 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Package Information PQFP 128 pins 23.2 ± 0.2mm 20.0 ± 0.1mm 102 65 103 64 RDC R2010 XXXX-C-QF XX-XXXXX 128 17.2 ± 0.2mm 14.0 ± 0.1mm 39 Pin 1 Identifier 1 38 0.22 ± 0.05mm 0.5mm BSC 3.40mm (Max.) 2.85 ± 0.12mm 0.145 ± 0.055mm 0.25mm (Min.) Seating Plane Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 4 REV 1.0 Nov. 28 2005