R2020

RDC® R2020 RISC DSP Communication FAST ETHERNET RISC PROCESSOR FAST ETHERNET RISC PROCESSOR R2020 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 4 REV 1.0 Sep. 20 2006 RDC® 1. Features l l l R2020 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Five-stage pipeline RISC architecture Bus interface - Multiplexed address and Data bus - Supports non-multiplexed address bus A[23:0] - 8-bit or 16-bit external bus dynamic access - 16M-byte memory address space - 64K-byte I/O space - Supports an independent data/address bus for external I/O device l l Three independent 16-bit timers and one independent programmable watchdog timer The Interrupt controller with six maskable external interrupts and two non-maskable external interrupt l l l l l l l l l Two independent DMA channels Programmable chip-select logic for Memory or I/O bus cycle decoder Programmable wait-state generator With 8-bit or 16-bit Boot ROM bus size 2-Port Fast Ethernet MAC with MII interface Supports an 8K-byte Uniform cache With 25MHz input frequency and up to 100MHz maximum internal frequency. Compatible with 3.3V I/O and 2.5V core voltage. Package Type includes 160-pin PQFP. l l l l l Supports two compatible UART serial channels with 16-byte FIFO and hardware flow-control. Supports CPU ID Supports a glueless and simplified 16-bit PCMCIA bus interface Supports 32 PIO pins SDRAM control Interface Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 4 REV 1.0 Sep. 20 2006 RDC® R2020 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 2. Block Diagram INT2 INT1 CLKOUTA INT3 INT6-INT5 INT0 NMI TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST_n MAC1 MII 1 Cache MCS_n UCS_n PCS[6:5]_n, PCS[3:0]_n Chip Select Unit Instruction Decoder Control Signal Register File General, ARDY DT/R_n DEN_n HOLD HLDA Refresh Control Unit Segment, Eflag Register Micro ROM PIO Unit EA / LA Address 16550 UART Serial Port0 Instruction Queue (64bits) MAC0 MII 0 DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n DCD1_n SIN1 DSR1_n CTS1_n RI1_n RTS1_n SOUT1 DTR1_n SDRAM/Bus SD_CLK WE_n CAS_n RAS_n BA[1:0] Interface Unit ALU (Special, Logic, Adder, BSF) 16550 UART Execution Unit Serial Port1 A[23:0] D[15:0] RD_n WHB_n WLB_n ALE WR_n/BWSEL Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 4 REV 1.0 Sep. 20 2006 RDC® 3. R2020 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Package Information PQFP 160 pins 31.2 ± 0.25mm 28.0 ± 0.1mm 120 81 1 21 80 RDC R2020 XXXX-C-QF XX-XXXXX 31.2 ± 0.25mm 28 ± 0.1mm 160 PIN 1 IDENTIFIER 1 0.65mm BSC 0.30 ± 0.05mm 15° REF A2 = 3.22 ± 0.07mm A = 4.07mm (max.) A2 40 41 0.18 ± 0.05mm A1 = 0.25mm (min.) 10° REF Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 4 REV 1.0 Sep. 20 2006