1339-31DVGI8

DATASHEET Real-Time Clock with Serial I2C Interface Description 1339 Features • Real-Time Clock (RTC) counts seconds, minutes, hours, The 1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially through an I2C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The 1339 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. day, date, month, and year with leap-year compensation valid up to 2100 • Packaged in 8-TSSOP, 8-SOIC, or 16-SOIC (surface-mount package with an integrated crystal) • • • • • • • • Applications • Handhelds (GPS, POS terminals) • Consumer Electronics (Set-Top Box, Digital Recording, Fast mode I2C Serial interface Two time-of-day alarms Programmable square-wave output Oscillator stop flag Automatic power-fail detect and switch circuitry Trickle-charge capability Industrial temperature range (-40°C to +85°C) Underwriters Laboratory (UL) recognized Network Applications) • • • • Office (Fax/Printers, Copiers) Medical (Glucometer, Medicine Dispensers) Telecomm (Routers, Switches, Servers) Other (Thermostats, Vending Machines, Modems, Utility Meters) Block Diagram Crystal inside package for 16-pin SOIC ONLY 1Hz / 4.096kHz / 8.192kHz / 32.768kHz X1 32.768 kHz Oscillator and Divider MUX/ Buffer SQW/INT X2 GND VCC Trickle Charger Power Control Clock, Calendar Counter Control Logic SCL SDA ©2007-2023 Renesas Electronics Corporation I2C Interface Trickle Charger Byte VBACKUP 1 1 Byte Control 7 Bytes Buffer 7 Bytes Alarm 1 Byte Status April 4, 2023 1339 Datasheet Pin Assignment (8-TSSOP/8-SOIC) X1 1 X2 2 VBACKUP 3 GND 4 1339 8 VCC 7 SQW/INT 6 5 Pin Assignment (16-SOIC) SCL 1 16 SDA SQW/INT 2 15 GND SCL VCC 3 14 VBACKUP SDA NC 4 13 NC NC 5 12 NC NC 6 11 NC NC 7 10 NC NC 8 9 NC 1339C Pin Descriptions Pin Number TSSOP SOIC Pin Name Pin Description/Function 1 — X1 Connections for standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 7pF. An external 32.768kHz oscillator can also drive the 1339. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left floating. 2 — X2 3 14 VBACKUP 4 15 GND Connect to ground. DC power is provided to the device on these pins. 5 16 SDA Serial data input/output. SDA is the input/output pin for the I2C serial interface. The SDA pin is an open-drain output and requires an external pull-up resistor (2k typical). 6 1 SCL Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an open-drain output and requires an external pull-up resistor (2k typical). 7 2 8 3 VCC Primary power supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. — 4 - 13 NC No connect. These pins are unused and must be connected to ground. Backup supply input. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap that can be charged using the trickle charger circuit. Diodes placed in series between the backup source and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be connected to ground. UL recognized to ensure against reverse charged current when used with a lithium cell. SQW/INT Square-Wave/Interrupt output. Programmable square-wave or interrupt output signal. The SQW/INT pin is an open-drain output and requires an external pull-up resistor (10k typical). ©2007-2023 Renesas Electronics Corporation 2 April 4, 2023 1339 Datasheet Typical Operating Circuit RPU 2k CPU RPU 2k VCC CRYSTAL VCC VCC 1 2 X1 6 5 10k VCC X2 SQW/INT SCL SDA 8 1339 GND 4 V BACKUP 7 3 + - Detailed Description The following sections discuss in detail the Oscillator block, Power Control block, Clock/Calendar Register, Alarms, trickle Charger, and Serial I2C block. Oscillator Block Selection of the right crystal, correct load capacitance and careful PCB layout are important for a stable crystal oscillator. Due to the optimization for the lowest possible current in the design for these oscillators, losses caused by parasitic currents can have a significant impact on the overall oscillator performance. Extra care needs to be taken to maintain a certain quality and cleanliness of the PCB. Crystal Selection The key parameters when selecting a 32kHz crystal to work with 1339 RTC are: In the above figure, X1 and X2 are the crystal pins of our device. Cin1 and Cin2 are the internal capacitors which include the X1 and X2 pin capacitance. Cex1 and Cex2 are the external capacitors that are needed to tune the crystal frequency. Ct1 and Ct2 are the PCB trace capacitances between the crystal and the device pins. CS is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). • Recommended Load Capacitance • Crystal Effective Series Resistance (ESR) • Frequency Tolerance Effective Load Capacitance Please see diagram below for effective load capacitance calculation. The effective load capacitance (CL) should match the recommended load capacitance of the crystal in order for the crystal to oscillate at its specified parallel resonant frequency with 0ppm frequency error. ©2007-2023 Renesas Electronics Corporation Note: The 1339CSRI integrates a standard 32.768kHz (±20ppm) crystal in the package and contributes an additional frequency error of 10ppm at nominal VCC (+3.3V) and TA=+25°C. 3 April 4, 2023 1339 Datasheet ESR (Effective Series Resistance) PCB Layout Choose the crystal with lower ESR. A low ESR helps the crystal to start up and stabilize to the correct output frequency faster compared to high ESR crystals. 1339 Frequency Tolerance The frequency tolerance for 32kHz crystals should be specified at nominal temperature (+25°C) on the crystal manufacturer datasheet. The crystals used with 1339 typically have a frequency tolerance of ±20ppm at +25°C. Specifications for a typical 32kHz crystal used with our device are shown in the table below. Parameter Symbol Nominal Freq. fO Series Resistance ESR Load Capacitance CL Min Typ Max 32.768 PCB Assembly, Soldering and Cleaning Board-assembly production process and assembly quality can affect the performance of the 32kHz oscillator. Depending on the flux material used, the soldering process can leave critical residues on the PCB surface. High humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. These process residuals cause the insulation of the sensitive oscillator signal lines towards each other and neighboring signals on the PCB to decrease. High humidity can lead to moisture condensation on the surface of the PCB and, together with process residuals, reduce the surface resistivity of the board. Flux residuals on the board can cause leakage current paths, especially in humid environments. Thorough PCB cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. In general, reduction of losses in the oscillator circuit leads to better safety margin and reliability. Unit kHz 50 7 k pF PCB Design Consideration • Signal traces between Renesas device pins and the crystal must be kept as short as possible. This minimizes parasitic capacitance and sensitivity to crosstalk and EMI. Note that the trace capacitances play a role in the effective crystal load capacitance calculation. • Data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. Crosstalk from these signals may disturb the oscillator signal. • Reduce the parasitic capacitance between X1 and X2 Power Control signals by routing them as far apart as possible. • The oscillation loop current flows between the crystal and The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed after tREC (see the “Power-Up/Down Timing” diagram). the load capacitors. This signal path (crystal to CL1 to CL2 to crystal) should be kept as short as possible and ideally be symmetric. The ground connections for both capacitors should be as close together as possible. Never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and EMI. • To reduce the radiation / coupling from oscillator circuit, an isolated ground island on the GND layer could be made. This ground island can be connected at one point to the GND layer. This helps to keep noise generated by the oscillator circuit locally on this separated island. The ground connections for the load capacitors and the oscillator should be connected to this island. ©2007-2023 Renesas Electronics Corporation 4 April 4, 2023 1339 Datasheet Table 1. Power Control Supply Condition Read/Write Access Powered By VCC < VPF, VCC < VBACKUP No VBACKUP VCC < VPF, VCC > VBACKUP No VCC VCC > VPF, VCC < VBACKUP Yes VCC VCC > VPF, VCC > VBACKUP Yes VCC Power-up/down Timing Table 2. Power-up/down Characteristics Ambient Temperature -40 to +85C Parameter Symbol Conditions Recovery at Power-up tREC (see note 1) VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF (see note 2) VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR Min. Typ. Max. Unit 2 ms 3 ms 0 µs Note 1: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs. Note 2: Measured at typ VBAT level. ©2007-2023 Renesas Electronics Corporation 5 April 4, 2023 1339 Datasheet Address Map Table 3 (Timekeeper Registers) shows the address map for the 1339 registers. During a multi-byte access, when the address pointer reaches the end of the register space (10h), it wraps around to location 00h. On an I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. Table 3. Timekeeper Registers Address Bit 7 Bit 6 00h 0 10 seconds 01h 0 10 minutes 02h 0 12/24 03h 0 0 04h 0 0 05h Century 0 06h Bit 5 AM/PM 10 hour Bit 4 Bit 3 Bit 2 Function Range Seconds Seconds 00 - 59 Minutes Minutes 00 - 59 Hour Hours 1 - 12 + AM/PM 00 - 23 Day 1-7 Date Date 01 - 31 Month Month/Century 01 - 12 + Century Year Year 00 - 99 10 hour 0 0 Bit 1 0 Day 10 date 0 Bit 0 10 month 10 year 07h A1M1 10 seconds Seconds Alarm 1 Seconds 00 - 59 08h A1M2 10 minutes Minutes Alarm 1 Minutes 00 - 59 09h A1M3 12/24 Hour Alarm 1 Hours 0Ah A1M4 DY/DT Day, Date Alarm 1 Day, Alarm 1 Date 1 - 7, 1 - 31 0Bh A2M2 Minutes Alarm 2 Minutes 00 - 59 0Ch A2M3 12/24 Hour Alarm 2 Hours 0Dh A2M4 DY/DT Day, Date Alarm 2 Day, Alarm 2 Date 0Eh EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Control 0Fh OSF 0 0 0 0 0 A2F A1F Status 10h TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Trickle Charger AM/PM 10 hour 10 hour 10 date 10 minutes AM/PM 10 hour 10 hour 10 date 1 - 12 + AM/PM 00 - 23 1 - 12 + AM/PM 00 - 23 1 - 7, 1 - 31 Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC and VBACKUP falls below the VBACKUP(min). ©2007-2023 Renesas Electronics Corporation 6 April 4, 2023 1339 Datasheet Time and Date Operation Alarms The time and date information is obtained by reading the appropriate register bytes. Table 3 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The 1339 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined operation. The 1339 contains two time of day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the Alarm Enable and INTCN bits of the Control Register) to activate the SQW/INT output on an alarm match condition. Bit 7 of each of the time of day/date alarm registers are mask bits (Table 4). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 4 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to a logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop, and when the address pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already running. ©2007-2023 Renesas Electronics Corporation The device checks for an alarm match once per second. When the RTC register values match alarm register settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is set to logic 1. If the corresponding Alarm Interrupt Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT signal. If the BBSQI bit is set to 1, the INT output activates while the part is being powered by VBACKUP. The alarm output remains active until the alarm flag is cleared by the user. 7 April 4, 2023 1339 Datasheet Table 4. Alarm Mask Bits DY/DT Alarm 1 Register Mask Bits (Bit 7) Alarm Rate A1M4 A1M3 A1M2 A1M1 X 1 1 1 1 Alarm once per second. X 1 1 1 0 Alarm when seconds match. X 1 1 0 0 Alarm when minutes and seconds match. X 1 0 0 0 Alarm when hours, minutes, and seconds match. 0 0 0 0 0 Alarm when date, hours, minutes, and seconds match. 1 0 0 0 0 Alarm when day, hours, minutes, and seconds match. DY/DT Alarm 2 Register Mask Bits (Bit 7) Alarm Rate A2M4 A2M3 A2M2 X 1 1 1 Alarm once per minute (00 sec. of every min.). X 1 1 0 Alarm when minutes match. X 1 0 0 Alarm when hours and minutes match. 0 0 0 0 Alarm when date, hours, and minutes match. 1 0 0 0 Alarm when day, hours, and minutes match. Special-Purpose Registers The 1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave output. Control Register (0Eh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Bit 7: Enable Oscillator (EOSC). This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the square wave or interrupt output when VCC is absent and the 1339 is being powered by the VBACKUP pin. When BBSQI is a logic 0, the SQW/INT pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied. ©2007-2023 Renesas Electronics Corporation 8 April 4, 2023 1339 Datasheet Table 5. SQW/INT Output INTCN RS2 RS1 SQW/INT Output A2IE A1IE 0 0 0 1Hz X X 0 0 1 4.096kHz X X 0 1 0 8.192kHz X X 0 1 1 32.768kHz X X 1 X X A1F 0 1 1 X X A2F 1 0 1 X X A2F + A1F 1 1 Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied. Status Register (0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSF 0 0 0 0 0 A2F A1F Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage on both VCC and VBACKUP are insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. ©2007-2023 Renesas Electronics Corporation 9 April 4, 2023 1339 Datasheet Trickle Charger Register (10h) Programmable Trickle Charger The simplified “Programmable Trickle Charger” schematic shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 on the TCS bits enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. The ROUT bits (bits 0 and 1) select the value of the resistor connected between VCC and VBACKUP. Table 6 shows the bit values. Table 6. Trickle Charger Register (10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT 1 ROUT 0 X X X X 0 0 X X Disabled X X X X 1 1 X X Disabled X X X X X X 0 0 Disabled 1 0 1 0 0 1 0 1 No diode, 250 resistor 1 0 1 0 1 0 0 1 One diode, 250 resistor 1 0 1 0 0 1 1 0 No diode, 2k resistor 1 0 1 0 1 0 1 0 One diode, 2k resistor 1 0 1 0 0 1 1 1 No diode, 4k resistor 1 0 1 0 1 0 1 1 One diode, 4k resistor 0 0 0 0 0 0 0 0 Initial power-up values Function Warning: The ROUT value of 250 must not be selected whenever VCC is greater than 3.63 V. ©2007-2023 Renesas Electronics Corporation 10 April 4, 2023 1339 Datasheet The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3V system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2k 1.3mA As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases. I2C Serial Data Bus The 1339 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The 1339 operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast mode (400kHz cycle rate) are defined. The 1339 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The following bus protocol has been defined (see the “Data Transfer on I2C Serial Bus” figure): A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Timeout: Timeout is where a slave device resets its interface whenever Clock goes low for longer than the timeout, which is typically 35mSec. This added logic deals with slave errors and recovering from those errors. When timeout occurs, the slave interface should re-initialize itself and be ready to receive a communication from the master, but it will expect a Start prior to any new communication. Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on ©2007-2023 Renesas Electronics Corporation 11 April 4, 2023 1339 Datasheet Data Transfer on I2C Serial Bus Depending upon the state of the R/W bit, two types of data transfer are possible: byte contains the 7-bit 1339 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the 1339 acknowledges the slave address + write bit, the master transmits a register address to the 1339. This sets the register pointer on the 1339, with the 1339 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the 1339 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the 1339 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see the “Data Read–Slave Transmitter Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit 1339 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The 1339 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The 1339 must receive a “not acknowledge” to end a read. The 1339 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see the “Data Write–Slave Receiver Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address ©2007-2023 Renesas Electronics Corporation 12 April 4, 2023 1339 Datasheet Data Write – Slave Receiver Mode Data Read (from current Pointer location) – Slave Transmitter Mode Data Read (Write Pointer, then Read) – Slave Receive and Transmit ©2007-2023 Renesas Electronics Corporation 13 April 4, 2023 1339 Datasheet Handling, PCB Layout, and Assembly The 1339 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning equipment should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All NC (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 1339. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Symbol Rating All Inputs and Outputs -0.3V to +6.0V Junction Temperature 125C Storage Temperature -55 to +125C Soldering Temperature 260C Recommended DC Operating Conditions Parameter Symbol Min. TA -40 VBACKUP 1.3 Ambient Operating Temperature Backup Supply Voltage Typ. 3.0 Max. Unit +85 C 3.7 V 5.5 V Pull-up Resistor Voltage (SQW/INT, SDA, SCL), VPU Logic 1 VIH 0.8VCC VCC + 0.3 V Logic 0 VIL -0.3 0.2VCC V VCC = 0V Supply Voltage 1339-2, Note A VCC 1339-31, Note A VPF 2.0 5.5 VPF 3.3 5.5 1.40 1.70 1.80 2.45 2.70 2.97 V Power Fail Voltage 1339-2, Note B VPF 1339-31, Note B V Note A: Operating voltages without a back up supply connected. Note B: When a back up supply voltage is connected choose proper part number 1339-2 or 1339-31 depending upon the back up supply voltage. ©2007-2023 Renesas Electronics Corporation 14 April 4, 2023 1339 Datasheet DC Electrical Characteristics Unless stated otherwise, VCC = MIN to MAX, Ambient Temperature -40 to +85C, Note 1 Parameter Symbol Conditions Min. Typ. Max. Unit Input Leakage ILI Note 2 1 µA I/O Leakage ILO Note 3 1 µA Logic 0 Out VCC > 2.0V IOL 1339-2, Note 3 3 mA Logic 0 Out VOL = 0.4; VCC > VCC Min. VCC > 2.0V IOL 1339-31, Note 3 3 mA Logic 0 Out VOL = 0.2V (VCC); 1.8V < VCC < 2.0V IOL Note 3 3 mA Logic 0 Out VOL = 0.2V (VCC); 1.3V < VCC < 1.8V IOL Note 3 250 µA VCC Active Current ICCA Note 4 450 µA VCC Standby Current, Note 5 ICCS VCC < 3.63V 150 µA 80 3.63V < VCC < 5.5V Trickle-charger Resistor Register 10h = A5h, VCC = Typ, VBACKUP = 0V R1 Trickle-charger Resistor Register 10h = A6h, VCC = Typ, VBACKUP = 0V Trickle-charger Resistor Register 10h = A7h, VCC = Typ, VBACKUP = 0V VBACKUP Leakage Current 200 Note 6 250  R2 2000  R3 4000  IBKLKG 25 100 nA Typ. Max. Unit DC Electrical Characteristics Unless stated otherwise, VCC = 0V, Ambient Temperature -40 to +85C, Note 1 Parameter Symbol VBACKUP Current EOSC = 0, SQW Off IBKOSC Note 7 800 1200 nA VBACKUP Current EOSC = 0, SQW On IBKSQW Note 7 1025 1400 nA IBKDR Note 7 120 300 nA VBACKUP Current EOSC = 1 ©2007-2023 Renesas Electronics Corporation Conditions 15 Min. April 4, 2023 1339 Datasheet AC Electrical Characteristics Unless stated otherwise, VCC = MIN to MAX, Ambient Temperature -40 to +85C, Note 13 Parameter SCL Clock Frequency Symbol fSCL Conditions Min. Fast Mode Typ. 100 Standard Mode Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition, Note 8 Low Period of SCL Clock High Period of SCL Clock tBUF tHD:STA tLOW tHIGH Setup Time for a Repeated START Condition tSU:STA Data Hold Time, Notes 9, 10 tHD:DAT Data Setup Time, Note 11 tSU:DAT Rise Time of Both SDA and SCL Signals, Note 12 tR Fall Time of Both SDA and SCL Signals, Note 12 tF Setup Time for STOP Condition tSU:STO Max. Unit 400 kHz 100 Fast Mode 1.3 Standard Mode 4.7 Fast Mode 0.6 Standard Mode 4.0 Fast Mode 1.3 Standard Mode 4.7 Fast Mode 0.6 Standard Mode 4.0 Fast Mode 0.6 Standard Mode 4.7 Fast Mode 0 Standard Mode 0 Fast Mode 100 Standard Mode 250 µs µs µs µs µs 0.9 ns Fast Mode 20 + 0.1CB 300 Standard Mode 20 + 0.1CB 1000 Fast Mode 20 + 0.1CB 300 Standard Mode 20 + 0.1CB 300 Fast Mode 0.6 Standard Mode 4.0 Capacitive Load for Each Bus Line, Note 12 CB I/O Capacitance (SDA, SCL) CI/O Note 13 Oscillator Stop Flag (OSF) Delay tOSF Note 14 µs ns ns µs 100 400 pF 10 pF ms WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: SCL only. Note 3: SDA and SQW/INT. Note 4: ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled. Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled. Note 6: VCC must be less than 3.63V if the 250 resistor is selected. ©2007-2023 Renesas Electronics Corporation 16 April 4, 2023 1339 Datasheet Note 7: Using recommended crystal on X1 and X2. Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released. Note 12: CB—total capacitance of one bus line in pF. Note 13: Guaranteed by design. Not production tested. Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V < VCC < VCCMAX and 1.3V < VBACKUP < 3.7V. Timing Diagram ©2007-2023 Renesas Electronics Corporation 17 April 4, 2023 1339 Datasheet Typical Operating Characteristics (VCC=3.3V, TA=25C) IBACKUP vs VBACKUP (1339-31) Icc vs Vcc 1339-31 (IDT1339-31) RS1=RS0=00 SDA=GND 20 425 16 415 410 INTC=1 405 Vcc (V) Supply Current (nA) 420 INTC=0 400 12 SCL=400kHz SCL=0Hz 8 395 4 390 385 0 380 1.3 1.8 2.3 2.8 2.7 3.3 3.2 3.7 4.2 4.7 5.2 Supply current (uA) VBACKUP (V) IBACKUP vs Temperature 1339-31 (IDT1339-31) Oscillator Frequency vs Supply Voltage 1339-31 (IDT1339-31) RS1=RS0=00 32768.1 Oscillator Supply Voltage (V) Supply Current (nA) 500 460 420 INTC=1 INTC=0 380 340 32768.05 Freq 32768 300 -40 -20 0 20 40 60 2.8 80 3.8 4.3 4.8 5.3 Frequency (Hz) Temperature (C) ©2007-2023 Renesas Electronics Corporation 3.3 18 April 4, 2023 1339 Datasheet Thermal Characteristics for 8-TSSOP Parameter Symbol Thermal Resistance Junction to Ambient JA Thermal Resistance Junction to Case JC Conditions Min. Still air Typ. Max. Unit 95 C/W 48 C/W Thermal Characteristics for 8-SOIC Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Unit JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W 40 C/W JC Thermal Characteristics for 16-SOIC Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case ©2007-2023 Renesas Electronics Corporation Symbol Conditions Min. Typ. Max. Unit JA Still air 120 C/W JA 1 m/s air flow 115 C/W JA 3 m/s air flow 105 C/W 58 C/W JC 19 April 4, 2023 1339 Datasheet Marking Diagram (8-TSSOP) Marking Diagram (16-SOIC) 16 31GI YYWW$ 92GI YYWW$ 1339-31DVGI 1339-2DVGI IDT 1339AC-31 SRGI YYWW**$ 1 Marking Diagram (8-SOIC) 8 5 4 1339-31DCGI 8 1339AC-31SRI 8 IDT1339 -31DCGI #YYWW$ 1 9 5 16 IDT1339 -2DCGI #YYWW$ 1 9 IDT 1339AC-2 SRGI YYWW**$ 4 1339-2DCGI 1 8 1339AC-2SRI Notes: 1. ‘#’ is the lot number. 2. ‘$’ is the assembly mark code. 3. ‘**’ is the lot sequence. 4. YYWW is the last two digits of the year and week that the part was assembled. 5. “G” denotes RoHS compliant package. 6. “I” denotes industrial grade. 7. Bottom marking: country of origin if not USA. ©2007-2023 Renesas Electronics Corporation 20 April 4, 2023 1339 Datasheet Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document. Ordering Information Part Number 1339-2DVGI 1339-2DVGI8 1339-2DCGI 1339-2DCGI8 1339AC-2SRGI 1339AC-2SRGI8 1339-31DVGI 1339-31DVGI8 1339-31DCGI 1339-31DCGI8 1339AC-31SRGI 1339AC-31SRGI8 Marking see page 20 Carrier Type Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 8-TSSOP 8-TSSOP 8-SOIC 8-SOIC 16-SOIC 16-SOIC 8-TSSOP 8-TSSOP 8-SOIC 8-SOIC 16-SOIC 16-SOIC Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C The 1339 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS requirements. The lead finish is JESD91 category e3. “A” is the device revision designator and will not correlate to the datasheet revision. ©2007-2023 Renesas Electronics Corporation 21 April 4, 2023 1339 Datasheet Revision History Date June 26, 2007 Description of Change New device. Preliminary release. November 1, 2007 Updated ordering info for 16-pin SOIC package. January 17, 2008 Added 8-pin SOIC package; updated “Power-up/down Characteristics” table; updates to “Absolute Maximum Ratings” table. February 11, 2008 Combined part numbers for 1339-3 and 1339-33 into one part number: 1339-31. March 28, 2008 May 18, 2008 August 4, 2008 Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices. Changed the part number for the 16PIN SOIC package from 1339C-31SOGI to 1339C-31SRI and the 1339C-2SOGI changed to 1339C-2SRI Removed “Preliminary”; removed UL statement from pin 3 description. November 20, 2008 Updated Block Diagram, Detailed description section(s), Operating Circuit diagram, and Typical Operating Characteristics diagrams. December 3, 2008 Updated Block Diagram, Features bullets, Pin descriptions, Typical Operating Characteristics diagrams; added marking diagrams. November 10, 2009 Added “Handling, PCB Layout, and Assembly” section. March 29, 2010 Added “Timeout” paragraph on page 11. July 30, 2010 Added Underwriters Laboratory recognition. April 13, 2011 Updated Supply Current specifications. June 3, 2011 Updated package drawing and dimensions for 8MSOP. June 5, 2012 1. Updated top-side marking for DVG package from 'YWW$' to 'YYWW$' September 20, 2012 1. Moved all from Fab4 to TSMC. QA requested change in the marking of only the 16-pin SOIC device with internal crystal to add “A” due to the fact that TSMC uses a different crystal than Fab4. Notification of a change in orderables was initiated with PCN A1208-06. 2. Updated 16-pin SOIC marking diagram and ordering information to include “A”. December 10, 2012 Updated orderable parts - added “G” to 16-pin SOIC parts with SRI/SRI8. New part numbers for 16-pin SOIC will read as SRGI and SRGI8. July 1, 2013 March 10, 2014 April 4, 2023 Updated Typ. and Max. values for Vbackup parameters in DC char table per latest TSMC data. Updated tVCCF from 300 µs to 3 ms. Added associated note. • Added Junction Temperature specification to the Absolute Maximum Ratings table. • Updated Package Outline Drawings section; removed embedded drawings and added links to PODs in Ordering Information section. ©2007-2023 Renesas Electronics Corporation 22 April 4, 2023 Package Outline Drawing Package Code: DCG8D1 8-SOIC 4.82 x 3.81 x 1.72 mm Body, 1.27mm Pitch PSC-4068-01, Revision: 02, Date Created: Jun 21, 2022 0.010 CA B -A5.00 4.80 See Detail A 8 4.00 3.81 6.30 5.79 -B0.48 x45° 0.25 Index Area 1 A A Side View Top View 15° 5° 1.75 1.50 0° Min R0.07 Min R0.07 Min 1.80 1.24 0.25 0.10 -CSeating Plane Gage Plane 0.004 C 1.27 0.51 0.30 0.254 1.27 0.41 1.04 Ref Side View Detail A (Rotated 90° CW) 3.81 0.61 0.38 1.27 0.51 0.30 0.25 0.10 8 7.16 6.96 0.25 0.10 0.48 0.28 3.81 3.61 With Plating Base Metal Section A-A 1 NOTES: RECOMMENDED LAND PATTERN (PCB Top View, SMD Design) © Renesas Electronics Corporation 1. 2. 3. 4. JEDEC compatible. All dimensions are in mm and angles are in degrees. Use ±0.05 mm for the non-toleranced dimensions. Foot length is measured at gauge plane 0.25 mm above seating plane. 16-TSSOP Package Outline Drawing 4.4mm Body, 0.65mm Pitch PGG16T1, PSC-4749-01, Rev 00, Page 1 16-TSSOP Package Outline Drawing 4.4mm Body, 0.65mm Pitch PGG16T1, PSC-4749-01, Rev 00, Page 2 Package Revision History Date Created Rev No. Jan 26, 2018 Rev 00 Description Revised from PSC-4056-02 PGG16 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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