16C26

M16C/26 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ09B0176-0100Z Rev.1.00 2004.6.10 1. Overview The M16C/26 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 48-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 Applications Audio, cameras, office/communications/portable/industrial equipment, etc Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 1 of 37 M16C/26 Group 1. Overview 1.2 Performance Outline Table 1.1 lists performance outline of M16C/26 group. Table 1.1. Performance outline of M16C/26 group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 50 ns (f(BCLK)= 20MHZ, VCC1= 3.0V to 5.5V) 100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V) Memory ROM (See the product list) capacity RAM (See the product list) I/O port P15 to P17, P6, P7, P80 to P83, 8bit x 3, 7bit x 1, 4bit x 1, 3bit x 1 P85 to P87, P90 to P93, P10 Multifunction timer Timer A:16 bits x 5 channels (TA0, TA1, TA2, TA3, TA4) Timer B:16 bits x 3 channels (TB0, TB1, TB2) Three-phase Motor Control Timer Serial I/O 2 channels (UART0, UART1) UART, clock synchronous 1 channels (UART2) UART, clock synchronous, I2C bus1, or IEBus2 A/D converter 10 bits x 8 channels DMAC 2 channels (trigger: 20 sources) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 20 internal and 7 external sources, 4 software sources, 7 levels  (These circuits contain a built-in feedback Clock generation circuit 3 circuits  • Main clock  resistor and external ceramic/quartz oscillator) • Sub-clock • On-chip oscillator(main-clock oscillation stop detect function) Power supply voltage VCC=3.0V to 5.5V (f(BCLK)=20MHZ) VCC=2.7V to 5.5V (f(BCLK)=10MHZ) Flash memory Program/erase voltage VCC=2.7V to 5.5V Number of program/erase 100 times (all area) 1000times (program area) /10000 times3 (data area) Power consumption 16mA (VCC=3V, f(BCLK)=20MHZ) 25µA (f(BCLK)=f(XCIN)=32kHZ on RAM) 1.8µA (VCC=3V, f(XCIN)=32kHZ, when wait mode) 0.7µA (VCC=3V, when stop mode) I/O I/O withstand voltage 5.0V characteristics Output current 5mA Operating ambient temperature -20 to 85°C -40 to 85°C 3 Device configuration CMOS high performance silicon gate Package 48-pin plastic mold QFP Notes: 1. I2C bus is a trademark of Koninklijke Philips Electronics N.V. 2. IEBus is a trademark of NEC Electronics Corporation. 3. See Table 1.3 for the number of program/erase and the operating ambient temperatue. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 2 of 37 M16C/26 Group 1. Overview 1.3 Block Diagram Figure 1.1 is a block diagram of the M16C/26 group. 3 8 8 7 4 8 Port P1 Port P6 Port P7 Port P8 Port P9 Port P10 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit A/D converter (10 bits X 8 channels ) System clock generator XIN-XOUT XCIN-XCOUT On-Chip Oscillator UART or clock synchronous serial I/O (8 bits X 3 channels) Watchdog timer (15 bits) M16C/60 series16-bit CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (Note 1) RAM (Note 2) DMAC (2 channels) Multiplier Note 1: ROM size depends on microcomputer type. Note 2: RAM size depends on microcomputer type. Figure 1.1. Block Diagram Rev.1.00 2004.6.10 REJ09B0176-0100Z page 3 of 37 M16C/26 Group 1. Overview 1.4 Product List Table 1.2 lists the M16C/26 group products, Figure 1.2 shows the type numbers, memory sizes and packages, Table 1.3 lists the product code, and Figure 1.3 shows the marking. Table 1.2. Product List Type No. ROM capacity M30262F3GP 24K + 4K byte M30262F4GP 32K + 4K byte M30262F6GP 48K + 4K byte M30262F8GP 64K + 4K byte RAM capacity 1K byte 1K byte 2K byte 2K byte Package type As of May 2004 Remarks 48P6Q-A Flash ROM Version Type No. M 3 0 2 6 2 F 4 GP – D3 Product code: Refer to Table 1.3 Package type: GP : Package 48P6Q-A ROM capacity: 3: (24K + 4K) bytes 4: (32K + 4K) bytes 6: (48K + 4K) bytes 8: (64K + 4K) bytes Memory type: F: Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/26 Group M16C Family Figure 1.2. Type No., Memory Size, and Package Rev.1.00 2004.6.10 REJ09B0176-0100Z page 4 of 37 M16C/26 Group 1. Overview Table 1.3. Product code Internal ROM (Program area) Product Code D3 D5 D7 D9 U3 U5 U7 U9 100 Lead-free 1,000 100 Lead-included 1,000 0°C to 60°C Package Internal ROM (Data area) Temperature Range 0°C to 60°C -40°C to 85°C 10,000 100 10,000 -20°C to 85°C 0°C to 60°C -40°C to 85°C -20°C to 85°C Operating Ambient Temperature -40°C to 85°C 100 -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C Program and Temperature Program and Erase Endurance Range Erase Endurance 0262F8 A D3 XXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Chip version and product code A : Shows chip version. First version is blank. Henceforth, whenever it changes a version, it continues with A, B, and C. D3 : Shows Product code. (See table 1.3 Product Code) Data code five digits Figure 1.3. Marking Diagram of Flash Memory versionfor M16C/26 (Top View) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 5 of 37 M16C/26 Group 1. Overview 1.5 Pin Configuration Figures 1.4 showd the pin configurations (top view). PIN CONFIGURATION (top view) P70/TA0out/TXD2/SDA (Note 1) 25 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RXD1 29 30 28 27 P15/INT3/ADtrg P16/INT4 P17/INT5 P60/CTS0/RTS0 P61/CLK0 P62/RXD0 35 36 33 32 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVss P100/AN0 Vref AVcc P93 34 31 26 P67/TXD1 37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 4 7 3 6 2 5 8 9 24 23 22 21 20 19 18 17 16 15 14 13 P71/TA0in/RXD2/SCL(Note 1) P72/CLK2/TA1out/V P73/CTS2/RTS2/TA1in/V P74/TA2out/W P75/TA2in/W P76/TA3out P77/TA3in P80/TA4out/U P81/TA4in/U P82/INT0 P83/INT1 IVCC (Note 2) P92/TB2in P91/TB1in P90/TB0in CNVSS P87/Xcin P86/Xcout RESET Xout VSS Xin VCC Note 1. this pin is N channel open-drain output pins. Note 2. Leave this pin open. Figure 1.4. Pin Configuration (Top View) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 6 of 37 P85/NMI/SD Package: 48P6Q M16C/26 Group 1. Overview 1.6 Pin Description Table 1.4 and 1.5 describe the available pins. Table 1.4. Pin Description(1) Pin name Signal name I/O type VCC,VSS Power supply input CNVSS CNVSS Input IVCC IVCC ____________ RESET Reset input Input XIN Clock input Input XOUT Clock output Output Function Apply 2.7V to 5.5V to the VCC pin, and 0V to the Vss pin. Connect this pin to Vss. Leave this pin open. "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A/D converter. Connect this pin to VCC. This pin is a power supply input for the A/D converter. Connect this pin to VSS. This pin is a reference voltage input for the A/D converter. This is an 3-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input, a pull-up resister option can be selected for the entire group of three pins. Additional software selectable secondary ______ functions are: 1) P15 to P17 can be configured as external INT interrupt pins, and; 2) P15 can input a trigger for the A/D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input, a pull-up resister option can be selected for the entire group of four pins. Pins in this port also function as UART0 and UART1 I/O. This is an 8-bit I/O port equivalent to P6. (P70 and P71 are N channel open-drain output) P7 can also function as I/O for timer A0 to A3, as selected by software. Additional programming options are: P70 to P73 can assume UART2 I/O capabilities, and P72 to P75 can function as output pins for the three-phase motor control timer. P80 to P83 and P85 to P87 are an 7-bit I/O port equivalent to P6.When used for input, a pull-up resister option can be selected for the entire group of four pins or three pins. Additional software-selectable secondary functions are: 1) P80 and P81 can act as either I/O for Timer A4, or as output pins for the three-phase motor control timer; 2) P82 to P83 can be ______ _______ _____ configured as external INT interrupt pins; 3) P85 can be used as NMI/SD. P85 can not be used as I/O port while the three-phase motor control is enabled. Apply a stable "H" to P85 after setting the direction register for P85 to "0" when the three-phase motor control is enabled, and; 4) P86 and P87 can serve as I/O pins for the sub-clock generation circuit. In this latter case, a quartzoscillator must be connented between P86 (XCOUT pin) and P87 (XCIN pin). AVCC AVSS VREF P15~P17 Analog power supply input Analog power supply input Reference Voltage input I/O port P1 Input Input/ output P60~P67 I/O port P6 Input/ output P70~P77 I/O port P7 Input/ output P80~P83, I/O port P8 P85~P87 Input/ output Rev.1.00 2004.6.10 REJ09B0176-0100Z page 7 of 37 M16C/26 Group 1. Overview Table 1.7. Pin Description(2) Pin name Signal name P90~P93 I/O port P9 I/O type Input/ output Input/ output Function This is an 4-bit I/O port equivalent to P6. Additional software-selectable secondary functions are: 1) P90 to P92 can act as Timer B0~B2 input pins. This is an 8-bit I/O port equivalent to P6. This port can also function as A/D converter input pins, as selected by software. Furthermore, P104 to P107 can also function as input pins for the key input interrupt function. P100~P107 I/O port P10 Rev.1.00 2004.6.10 REJ09B0176-0100Z page 8 of 37 M16C/26 Group 2. CPU 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note) Frame base registers (Note) b0 Data registers (Note) b19 b15 INTBH INTBL Interrupt table register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC b15 b0 Program counter USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OB SZ DC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: These registers comprise a register bank. There are two register banks. Figure 2.1. Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.1.00 2004.6.10 REJ09B0176-0100Z page 9 of 37 M16C/26 Group 2. CPU 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”. 2.8.3 Zero Flag (Z Flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”. 2.8.4 Sign Flag (S Flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. 2.8.6 Overflow Flag (O Flag) This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is cleared to “0” when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 10 of 37 M16C/26 Group 3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/26 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example, a 32-Kbyte internal ROM is allocated to the addresses from F800016 to FFFFF16. The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 1-Kbytes internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual.” 0000016 SFR 0040016 Internal RAM XXXXX16 Reserved area Internal RAM Size 1K bytes 2K bytes Address XXXXX16 007FF16 00BFF16 Size 24K bytes 32K bytes 48K bytes 64K bytes Internal ROM Address YYYYY16 FA00016 F800016 F400016 F000016 FFE0016 Special page vector table 0F00016 0FFFF16 Internal ROM (Data area)(Note 1) FFFDC16 Reserved area Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset YYYYY16 Internal ROM (Program area) FFFFF16 FFFFF16 Note 1: Shown here is a Block A (2K bytes) and Block B (2K bytes). Figure 3.1. Memory Map Rev.1.00 2004.6.10 REJ09B0176-0100Z page 11 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP 4. Special Function Register (SFR) Map Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register Symbol After reset Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 (Note 2) PM0 PM1 CM0 CM1 AIER PRCR 0016 000010002 010010002 001000002 XXXXXX002 XX0000002 0X0000002 XX16 00XXXXXX2(Note 4) 0016 0016 X016 0016 0016 X016 (Note 3) CM2 WDTS WDC RMAD0 Address match interrupt register 1 RMAD1 Voltage detection register 1 Voltage detection register 2 (Note 5) (Note 5) VCR1 VCR2 000010002 0016 Processor mode register 2 Voltage down detection interrupt register DMA0 source pointer PM2 D4INT SAR0 XXX000002 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 DMA0 destination pointer DAR0 DMA0 transfer counter TCR0 DMA0 control register DM0CON 00000X002 DMA1 source pointer SAR1 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 DMA1 destination pointer DAR1 DMA1 transfer counter TCR1 DMA1 control register DM1CON 00000X002 Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. Note 4: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable). X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 12 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 Register Symbol After reset INT3 interrupt control register INT3IC XX00X0002 INT5 interrupt control register INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A/D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT5IC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC XX00X0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 Note :The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 13 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP Address 008016 008116 008216 008316 008416 008516 008616 Register Symbol After reset ~ 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 ~ Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 (Note 2) (Note 2) (Note 2) FMR4 FMR1 FMR0 010000002 0100XX0X2 XX0000012 ~ 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 ~ Peripheral clock select register PCLKR 000000112 ~ 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 ~ Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: This register is included in the flash memory version. X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 14 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Register Symbol After reset Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 XX16 XX16 Interrupt cause select register IFSR 0016 UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 0016 000X0X0X2 X00000002 X00000002 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 Note : The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 15 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 transmit/receive mode register Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON After reset 0016 0XXXXXXX2 0016 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX00002 00XX00002 00XX00002 XXXXXX002 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 0016 XX16 XXXXXXXX2 XXXXXXXX2 000010002 000000102 XXXXXXXX2 XXXXXXXX2 X00000002 UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2 DMA0 request cause select register DMA1 request cause select register DM0SL DM1SL 0016 0016 Note : The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 16 of 37 M16C/26 Group 4. Special Function Register (SFR) MAP Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 A/D register 7 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After reset XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 XXXXXXXX2 A/D control register 2 A/D control register 0 A/D control register 1 ADCON2 ADCON0 ADCON1 0016 00000XXX2 0016 Port P1 register Port P1 direction register P1 PD1 XX16 0016 Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XX16 XX16 0016 0016 XX16 XX16 00X000002 0016 XX16 0016 Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register PUR0 PUR1 PUR2 PCR 0016 0016 0016 0016 Note 1: The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.1.00 2004.6.10 REJ09B0176-0100Z page 17 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 16.1. Absolute Maximum Ratings Symbol VCC AVCC Supply voltage Parameter Analog supply voltage Input voltage RESET, CNVSS, P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, VREF, XIN P70, P71 Output voltage P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, XOUT P70, P71 Condition VCC=AVCC VCC=AVCC Rated value -0.3 to 6.5 -0.3 to 6.5 Unit V V VI -0.3 to VCC+0.3 V -0.3 to 6.5 V VO -0.3 to VCC+0.3 V V mW C C -0.3 to 6.5 Topr=25 C 300 -20 to 85 / -40 to 85 -65 to 150 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature Rev.1.00 2004.6.10 REJ09B0176-0100Z page 18 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.2 Recommended Operating Conditions Table 1.26.2. Recommended Operating Conditions (Note 1) Symbol VCC AVcc Vss AVss Supply voltage Analog supply voltage Supply voltage Analog supply voltage RESET, CNVSS, XIN, HIGH input P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, voltage P90 to P93, P100 to P107 P70 , P71 VIL I OH (peak) I OH (avg) I OL (peak) I OL (avg) f (XIN) f (XCIN) f (Ring) f (BCLK) LOW input voltage RESET, CNVSS, XIN, P15 to P17, P60 to P67, P70 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 VCC=3.0 to 5.5V VCC=2.7 to 3.0V 0 0 32.768 1 0 20 Parameter Min. 2.7 Standard Typ. VCC 0 0 Max. 5.5 Unit V V V V 0.8VCC 0.8VCC 0 VCC 6.5 0.2VCC V V V VIH HIGH peak output current HIGH average output current LOW peak output current LOW average output current -10.0 - 5 .0 10.0 5.0 20 33.33 X VCC-80 50 mA mA mA mA MHz MHz kHz MHz MHz Main clock input oscillation frequency (Note 4) Sub-clock oscillation frequency On-chip oscillation frequency CPU operation clock Note 1: Referenced to VCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified. Note 2: The mean output current is the mean value within 100ms. Note 3: The total IOL (peak) for all ports must be 80mA max. The total IOL (peak) for all ports must be -80mA max. Note 4: Relationship between main clock oscillation frequency and supply voltage. f(XIN) operating maximum frequency [MHZ] Main clock input oscillation frequency 33.33 x VCC-80MHZ 20.0 10.0 0.0 2.7 3.0 5.5 VCC[V] (main clock: no division) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 19 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.3 A/D Conversion Characteristics Table 16.3. A/D Conversion Characteristics (Note 1) Symbol – INL Resolution Integral non-linearity error 10 bit 8 bit 10 bit Parameter Measuring condition VREF =VCC VREF=VCC=5V VREF=VCC=3.3V VREF =VCC=3.3V VREF=VCC=5V VREF=VCC=3.3V VREF =VCC=3.3V AN0 to AN7 input AN0 to AN7 input AN0 to AN7 input AN0 to AN7 input Standard Unit Min. Typ. Max. 10 ±3 ±5 ±2 ±3 ±5 ±2 ±1 ±3 ±3 40 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB kΩ µs µs µs V V – DNL – – RLADDER tCONV tCONV tSAMP VREF VI A 8 bit Differential non-linearity error Offset error Gain error Ladder resistance Conversion time(10bit), Sample & hold function available Conversion time(8bit), Sample & hold function available Sampling time Reference voltage Analog input voltage Absolute accuracy VREF =VCC VREF =VCC=5V, øAD=10MHz VREF =VCC=5V, øAD=10MHz 10 3.3 2.8 0.3 2.0 0 VCC VREF Note 1: Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified. Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V, and make ØAD frequency equal to or lower than fAD/2. Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 2. A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 2. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 20 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.4 Flash Memory Version Electrical Characteristics Table 16.4. Flash Memory Version Electrical Characteristics (Note 1) 100E/W cycle products (D3, D5, U3, U5)) Symbol – – – Parameter Erase/Write cycle (Note 3) Word program time (Vcc=5.0V, Topr=25°C) Block erase time 2Kbyte block 8Kbyte block 16Kbyte block 32Kbyte block Min. 100(Note 4) Standard Typ. (Note 2) 75 0.2 0.4 0.7 1.2 Max Unit cycle 600 9 9 9 9 8 µs s s s s ms year td(SR-ES) Tim e delay from S uspend R equest until E rase S uspend – Data retention time (Note 5) 20 Table 16.5. Flash Memory Version Electrical Characteristics (Note 6) 10000 E/W cycle products (D7, D9, U7, U9) [blockA and block B(Note 7)] Symbol – – – Parameter Erase/Write cycle (Note 3, 8, 9) Word program time (Vcc=5.0V, Topr=25°C) Block erase time(Vcc=5.0V, Topr=25°C) (2Kbyte block) Min. 10000(Note 4,10) Standard Typ. (Note 2) 100 0.3 Max Unit cycle µs s td(SR-ES) Tim e delay from S uspend R equest until E rase S uspend 8 ms Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C. Note 2: VCC = 5V; TOPR = 25 °C. Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total number of distinct word addresses - for every block erase. Performing multiple writes to the same address before an erase operation is prohibited. Note 4: Maximum number of E/W cycles for which opration is guaranteed. Note 5: Topr = 55°C. Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -40 to 85°C (D7, U7) / -20 to 85°C (D9, U9). Note 7: Table18.5 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.4. Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different word addresses (only one time each) as possible. It is important to track the total number of block erases. Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. Note 10: When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access. When FMR 17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of the setting of FMR17. Note 11: Customers desiring E/W failure rate information should contact their Renesas technical support representative. Erase suspend request (interrupt request) FMR46 td(SR-ES) Table 16.6. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics Flash program, erase voltage VCC = 2.7 V to 5.5 V Rev.1.00 2004.6.10 REJ09B0176-0100Z page 21 of 37 Flash read operation voltage VCC=2.7 to 5.5 V (at Topr = 0 to 60oC) M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.5 Low Voltage Detection Circuit Electrical Charactristics Table 16.7. Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 4) Symbol Vdet4 Vdet3 Vdet3s Vdet3r Parameter Voltage down detection voltage (Note 1) Reset level detection voltage (Notes 1, 2) Low voltage reset retention voltage Low voltage reset release voltage (Note 3) Measuring condition Min. 3 .3 2 .2 Standard Typ. 3 .8 2 .8 Max. 4 .4 3 .6 Unit V V V VCC1=0.8 to 5.5V 0 .8 2 .2 2 .9 4 .0 V Note 1: Vdet4 > Vdet3 Note 2: Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the operation at f(BCLK) ≤ 10MHz is guaranteed. Note 3: Vdet3r > Vdet3 is not guaranteed. Note 4: The low voltage detection circuit is designed to use when VCC is set to 5V. Table 16.8. Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) td(M-L) td(S-R) td(E-A) Parameter Time for internal power supply stabilization during powering-on STOP release time Low power dissipation mode wait mode release time Time for internal power supply stabilization when main clock oscillation starts Hardware reset 2 release wait time Low voltage detection circuit operation start time Measuring condition Min. Standard Typ. Max. 2 150 150 50 Unit ms µs µs µs ms µs VCC1=2.7 to 5.5V VCC1=Vdet3r to 5.5V VCC1=2.7 to 5.5V 6 (Note) 20 20 Note : When VCC = 5V VCC Vdet3r td(S-R) Interrupt for stop mode release CPU clock td(R-S) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 22 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.6 Electrical Charactristics (VCC=5V) VCC = 5V Table 16.9. Electrical Characteristics (Note 1) Symbol VOH VOH Parameter HIGH output P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 voltage HIGH output P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 voltage HIGH output voltage XOUT XCOUT HIGHPOWER LOWPOWER Measuring condition IOH=-5mA IOH=-200µA IOH=-1mA IOH=-0.5mA With no load applied With no load applied IOL=5mA IOL=200µA IOL=1mA IOL=0.5mA With no load applied With no load applied Min. VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0 Standard Typ. Max. VCC VCC VC C VC C Unit V V V V VOH HIGH output voltage VOL VOL HIGHPOWER LOWPOWER 2.5 1.6 2 .0 0.45 2 .0 2 .0 0 0 LOW output P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 voltage LOW output P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 voltage LOW output voltage XOUT XCOUT HIGHPOWER LOWPOWER V V V V VOL LOW output voltage Hysteresis VT+-VT- HIGHPOWER LOWPOWER TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT1,INT3 to INT5,NMI, ADTRG, SCL, SDA, RxD0 to RxD2, CTS0 to CTS2, CLK0 to CLK2, TA2OUT to TA4OUT, KI0 to KI3 RESET P15 to P17, P60 to P67, P70 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, XIN, RESET, CNVss P15 to P17, P60 to P67, P70 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, XIN, RESET, CNVss P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 XIN XCIN At stop mode VI=5V 0 .2 1 .0 V VT+-VTIIH Hysteresis HIGH input current 0 .2 2 .5 5.0 V µA II L LOW input current VI=0V -5.0 µA RPULLUP RfXIN RfXCIN VRAM Pull-up resistance VI=0V 30 50 1 .5 15 170 kΩ MΩ MΩ V Feedback resistance Feedback resistance RAM retention voltage 2.0 Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 23 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) VCC = 5V Table 16.10. Electrical Characteristics (2) (Note 1) Symbol Parameter In single-chip mode, the output pins are open and other pins are VSS Mask ROM Measuring condition f(BCLK)=20MHz, No division No division, On-chip oscillation Flash memory Program Flash memory Erase Flash memory Min. Standard Typ. 16 T.B.D T.B.D T.B.D Max. 19 Unit mA mA mA mA f(BCLK)=10MHz, VCC=5.0V f(BCLK)=10MHz, VCC=5.0V f(BCLK)=32kHz, Low power dissipation mode, RAM(Note 3) f(BCLK)=32kHz Low power dissipation mode, Flash memory(Note 3) On-chip oscillation, Wait mode f(BCLK)=32kHz, Wait mode (Note 2), 25 µA ICC Power supply current (VCC=3.0 to 5.5V) 420 µA T.B.D 7.5 µA µA Flash memory Oscillation capacity High f(BCLK)=32kHz, Wait mode(Note 2), Oscillation capacity Low Stop mode, Topr=25°C 2.0 0.8 3.0 µA µA Note 1: Referenced to VCC==4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified. Note 2: With one timer operated using fC32. Note 3: This indicates the memory in which the program to be executed exists. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 24 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) 5.7 Timing Requirements (VCC=5V) VCC = 5V (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.11. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 50 25 25 15 15 Unit ns ns ns ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 25 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.12. Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 16.13. Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 16.14. Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. Standard Max. Unit ns ns ns 200 100 100 Table 16.15. Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns Table 16.16. Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Max. Min. 2000 1000 1000 400 400 Unit ns ns ns ns ns Table 16.17. Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time Parameter Standard Max. Min. 800 200 200 Unit ns ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 26 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=5V) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.18. Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 16.19. Timer B Input (Pulse Period Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 16.20. Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 16.21. A/D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 16.22. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 200 100 100 80 0 30 90 Max. Unit ns ns ns ns ns ns ns Table 16.23. External Interrupt INTi Input Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 27 of 37 M16C/26 Group 5. Timing (VCC=5V) VCC = 5V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode TAiIN input tsu(TAIN-TAOUT) TAiOUT input tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 16.1. Timing Diagram (1) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 28 of 37 M16C/26 Group 5. Timing (VCC=5V) VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 16.2. Timing Diagram (2) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 29 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=3V) VCC = 3V 5.8 Electrical Charactristics (VCC=3V) Table 16.24. Electrical Characteristics (Note) Symbol VOH HIGH output voltage Parameter P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER Measuring condition IOH=-1mA IOH=-0.1mA IOH=-50µA With no load applied With no load applied IOL=1mA IOL=0.1mA IOL=50µA With no load applied With no load applied Min. VCC-0.5 VCC-0.5 VCC-0.5 Standard Typ. Max. VC C VC C VC C 2.5 1 .6 0 .5 0 .5 0 .5 0 0 Unit V V V V V V VOH HIGH output voltage HIGH output voltage VOL VOL LOW output voltage P15 to P17, P60 to P67, P72 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107 XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER LOW output voltage LOW output voltage Hysteresis VT+-VT- VT+-VTII H Hysteresis HIGH input current IIL LOW input current TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT1,INT3 to INT5,NMI, ADTRG, SCL, SDA, RxD0 to RxD2, CTS0 to CTS2, CLK0 to CLK2, TA2OUT to TA4OUT, KI0 to KI3 RESET P15 to P17, P60 to P67, P70 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, XIN, RESET, CNVss P15 to P17, P60 to P67, P70 to P77, P80 to P83, P85 to P87, P90 to P93, P100 to P107, XIN, RESET, CNVss P15 to P17, P60 to P67,P72 to P77,P80 to P83, P85 to P87,P90 to P93, P100 to P107 XIN XCIN 0.2 0 .8 V 0.2 VI=3V 1 .8 4.0 V µA VI=0V -4.0 50 100 3.0 25 500 µA RPULLUP RfXIN RfXCIN VRAM Pull-up resistance VI=0V kΩ MΩ MΩ V Feedback resistance Feedback resistance RAM retention voltage At stop mode 2.0 Note 1 : Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 30 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=3V) VCC = 3V Table 16.25. Electrical Characteristics (2) (Note 1) Symbol Parameter In single-chip mode, the output pins are open and other pins are VSS Flash memory Measuring condition f(BCLK)=10MHz, No division No division, On-chip oscillation Flash memory Program Flash memory Erase Flash memory Min. Standard Typ. 8 T.B.D T.B.D T.B.D 25 Max. 13 Unit mA mA mA mA µA f(BCLK)=10MHz, Vcc1=3.0V f(BCLK)=10MHz, Vcc1=3.0V f(BCLK)=32kHz, Low power dissipation mode, RAM(Note 3) f(BCLK)=32kHz, Low power dissipation mode, Flash memory(Note 3) On-chip oscillation, Wait mode f(BCLK)=32kHz, Wait mode (Note 2), ICC Power supply current (VCC=2.7 to 3.6V) 420 µA T.B.D 6 .0 µA µA Flash memory Oscillation capacity High f(BCLK)=32kHz, Wait mode (Note 2), Oscillation capacity Low Stop mode, Topr=25°C 1.8 0.7 3 .0 µA µA Note 1: Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified. Note 2: With one timer operated using fC32. Note 3: This indicates the memory in which the program to be executed exists. Rev.1.00 2004.6.10 REJ09B0176-0100Z page 31 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=3V) VCC = 3V 5.9 Timing Requirements (VCC=3V) Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.26. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 100 40 40 18 18 Unit ns ns ns ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 32 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=3V) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.27. Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 60 60 Unit ns ns ns Table 16.28. Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 16.29. Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 300 150 150 Max. Unit ns ns ns Table 16.30. Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 150 Unit ns ns Table 16.31. Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Max. Min. 3000 1500 1500 600 600 Unit ns ns ns ns ns Table 1.6.32. Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol tc(TA) tsu(TAIN -TAOUT ) tsu(TAOUT -TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time Parameter Standard Min. Max. 2 500 500 Unit µs ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 33 of 37 M16C/26 Group 5. Electrical Characteristics (VCC=3V) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 16.33. Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns Table 16.34. Timer B Input (Pulse Period Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 16.35. Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 16.36. A/D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 16.37. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 16.38. External Interrupt INTi Input Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns Rev.1.00 2004.6.10 REJ09B0176-0100Z page 34 of 37 M16C/26 Group 5. Timing (VCC=3V) VCC = 3V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode TAiIN input tsu(TAIN-TAOUT) TAiOUT input tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 16.3. Timing Diagram (1) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 35 of 37 M16C/26 Group 5. Timing (VCC=3V) VCC = 3V tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 16.4. Timing Diagram (2) Rev.1.00 2004.6.10 REJ09B0176-0100Z page 36 of 37 M16C/26 Group 6. Package 6. Package 48P6Q-A EIAJ Package Code LQFP48-P-77-0.50 Recommended JEDEC Code – Weight(g) – Lead Material Cu Alloy Plastic 48pin 7✕7mm body LQFP MD e HD D 48 37 1 36 b2 I2 Recommended Mount Pad Symbol HE 12 25 13 24 A F e A2 L1 A A1 A2 b c D E e HD HE L L1 Lp A3 y b L Detail F Lp x y b2 I2 MD ME x M Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 – – 1.4 0.17 0.22 0.27 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.5 – – 8.8 9.0 9.2 8.8 9.0 9.2 0.35 0.5 0.65 1.0 – – 0.6 0.75 0.45 0.25 – – – – 0.08 – – 0.1 – 0° 8° – – 0.225 1.0 – – – – 7.4 – – 7.4 E A1 Rev.1.00 2004.6.10 REJ09B0176-0100Z page 37 of 37 c A3 ME REVISION HISTORY Rev. Date Page 1.00 Jun/10/ 04 First edition M16C/26 Hardware Manual Description Summary C-1 M16C/29 Group Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.