2510CGT-CQ0

ICS2510C 3.3V Phase-Lock Loop Clock Driver General Description Features The ICS2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2510C operates at 3.3V VCC and drives up to ten clock loads. • One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Outputs can be enabled or disabled via control (OE) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state. • • • • • • • Meets or exceeds PC133 registered DIMM specification1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs Operating frequency 25MHz to 175MHz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plastic 24-pin 173mil TSSOP package The ICS2510C does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer. This test mode, the ICS2510C can be use as low skew fanout clock buffer device. The ICS2510C comes in 24 pin 173mil Thin Shrink SmallOutline package (TSSOP) package. Pin Configuration Block Diagram FBOUT AGND 1 24 CLKIN VCC 2 23 AVCC CLK1 CLK0 3 22 VCC CLK2 CLK1 4 21 CLK9 CLK2 5 20 CLK8 GND 6 19 GND GND 7 18 GND CLK0 FBIN PLL CLK3 CLKIN CLK4 CLK3 8 17 CLK7 CLK5 CLK4 9 16 CLK6 CLK6 VCC 10 15 CLK5 OE 11 14 VCC FBOUT 12 13 FBIN AVCC CLK7 CLK8 CLK9 OE 0010G—09/22/09 24 Pin TSSOP 4.40 mm. Body, 0.65 mm. pitch ICS2510C Pin Descriptions PIN NUMBER 1 2, 10, 14 3 4 5 6, 7, 18, 19 8 9 PIN NAME AGND VCC CLK0 CLK1 CLK2 GND CLK3 CLK4 TYPE PWR PWR OUT OUT OUT PWR OUT OUT DESCRIPTION Analog Ground Power Supply (3.3V) Buffered clock output. Buffered clock output. Buffered clock output. Ground Buffered clock output. Buffered clock output. Output enable (has internal pull_up). When high, normal operation. When low, clock outputs are disabled to a logic low state. 11 OE1 12 13 15 16 17 20 21 22 FBOUT FBIN CLK5 CLK6 CLK7 CLK8 CLK9 VCC OUT IN OUT OUT OUT OUT OUT PWR 23 AVCC IN 24 CLKIN IN IN Feedback output Feedback input Buffered clock output. Buffered clock output. Buffered clock output. Buffered clock output. Buffered clock output. Power Supply (3.3V) digital supply. Analog power supply (3.3V). When input is ground PLL is off and bypassed. Clock input Note: 1. Weak pull-ups on these inputs Functionality OUTPUTS INPUTS OE AVCC CLK (9:0) FBOUT Source PLL Shutdown 0 1 3.33 3.33 0 Driven Driven Driven PLL PLL N N CLKIN CLKIN Y Y Buffer Mode 0 0 0 Driven Driven 1 0 Driven Test mode: When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers 0010G—09/22/09 2 ICS2510C Absolute Maximum Ratings Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . AVCC < (V cc + 0.7V) 4.3 V GND –0.5 V to Vcc +0.5 V 0°C to +70°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - OUTPUT TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF; RL = 470 Ohms (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage SYMBOL RDSP RDSN VOH VOL CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 8 mA VOH = 2.4 V VOH = 2.0 V VOL = 0.8 V VOL = 0.55 V MIN 19 13 TYP 36 32 2.9 0.25 -26 -37 25 17 Output High Current IOH Output Low Current IOL Rise Time1 Fall Time1 Tr VOL = 0.8 V, VOH = 2.0 V 0.5 1.4 2.1 ns Tf VOH = 2.0 V, VOL = 0.8 V 0.5 1.5 2.7 ns Duty Cycle Dt 45 Tcyc-cyc 55 100 75 Absolute Jitter1 Tjabs 50 52 39 57 % Cycle to Cycle jitter1 VT = 1.5 V;CL=30 pF at 66-100 MHz ; loaded outputs at 133 MHz ; loaded outputs 10000 cycles; CL = 30 pF 80 150 ps 40 150 ps 1 1 Skew 1 Phase error Phase error Jitter1 Delay Input-Output1 1 2.4 Tsk VT = 1.5 V (Window) Output to Output Tpe VT = Vdd/2; CLKIN-FBIN -150 VT = Vdd/2; CLKIN-FBIN; Delay Jitter VT = 1.5 V; PLL_EN = 0 -50 3 Tpe DR1 Guaranteed by design, not 100% tested in production. 0010G—09/22/09 3 MAX UNITS Ω Ω V 0.4 V -13.6 mA -22 mA ps ps 35 50 ps 3.3 3.7 ns ICS2510C Electrical Characteristics - Input & Supply TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating current Input Capacitance Output Capacitance SYMBOL CONDITIONS VIH V IL VIN = VDD IIH VIN = 0 V; IIL CL = 0 pF; FIN @ 66M IDD1 CIN1 CO1 MIN 2 VSS - 0.3 TYP 0.1 19 140 MAX UNITS VDD + 0.3 V 0.8 V 100 uA 50 uA 170 mA Logic Inputs 4 pF Logic Outputs 8 pF 1 Guaranteed by design, not 100% tested in production. Timing requirements over recommended ranges of supply voltage and operating free-air temperature Symbol Parameter Test Conditions Min. Max. Unit Input clock Fclk 25 175 MHz frequency Input clock 40 60 % frequency duty cycle After power up 1 ms Stabilization time Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal Until phase lock is obtained, the specifications for parameters given in the switching 0010G—09/22/09 4 ICS2510C PARAMETER MEASUREMENT INFORMATION From Output Under Test 3V 50% VCC 0V Input 30pF 500Ω tPD 2V Output 0.4V tR Figure 1. Load Circuit for Outputs VOH 2V 0.4V VOL 50% VCC tF Notes: Figure 2. Voltage Waveforms 1. CL includes probe and jig capacitance. Propagation Delay Times 2. All input pulses are supplied by generators having the following characteristics: PRR ≤133 MHz, Z O = 5 0 Ω , Tr ≤1.2 ns, Tf ≤1.2 ns. 3. The outputs are measured one at a time with one transition per measurement. CLKIN FBIN tPE (PHASE ERROR) FBOUT Any CLKOUT tSK(o) Any CLKOUT Any CLKOUT tSK(o) Figure 3. Phase Error and Skew Calculations 0010G—09/22/09 5 ICS2510C General Layout Precautions: An ICS2509C is used as an example. It is similar to the ICS2510C. The same rules and methods apply. 1) Use copper flooded ground on the top signal layer under the clock buffer The area under U1 in figure 1 on the right is an example. Every ground pin goes to a ground via. The vias are not visible in figure 1. 2) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 3) Make all power and ground traces are as wide as the via pad for lower inductance. 4) VAA for pin 23 has a low pass RC filter to decouple the digital and analog supplies. C9-12 may be replaced with a single low ESR (0.8 ohm or less) device with the same total capacitance. R2 may be replaced with a ferrite bead. The bead should have a DC resistance of at least 0.5 ohms. 1 ohm is better. It should have an impedance of at least 300 ohms at 100MHz. 600 ohms at 100MHz is better. 5) Notice that ground vias are never shared. 6) All VCC pins have a decoupling capacitor. Power is always routed from the plane connection via to the capacitor pad to the VCC pin on the clock buffer. 7) Component R1 is located at the clock source. 8) Component C1, if used, has the effect of adding delay. 9) Component C7 , if used, has the effect of subtracting delay. Delaying the FBIn clock will cause the output clocks to be earlier. A more effective method is to use the propagation time of a trace between FBOut and FBIn. Figure 1. Component Values: C1,C7= As necessary for delay adjust C[6:2]=.01uF C8,C13=0.1uF C[12:9]=4.7Uf R1=10 ohm. Locate at driver R2=10 ohm. 0010G—09/22/09 6 ICS2510C N In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 SEE VARIATIONS D 6.40 BASIC E E1 4.30 4.50 0.65 BASIC e L 0.45 0.75 SEE VARIATIONS N α 0° 8° aaa -0.10 C L E1 E H INDEX AREA 1 2 α D A A2 A1 e b VARIATIONS -CSEATING PLANE aaa In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 N 24 C D mm. MIN 7.70 D (inch) MAX 7.90 MIN .303 MAX .311 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information 2510CGLFT Example: XXXX y G (LF) PPP T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 0010G—09/22/09 7 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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