251PMLF

Field Programmable SS VersaClock® Synthesizer ICS251 DATASHEET Description Features The ICS251 is a low cost, single-output, field programmable clock synthesizer. The ICS251 can generate an output frequency from 314kHz to 200MHz and may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). • • • • • • • • • • • Using IDT’s VersaClock software to configure the PLL and output, the ICS251 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 4 selectable configuration registers. The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. 8-pin SOIC package Four addressable registers Input crystal frequency of 5 to 27MHz Clock input frequency of 3 to 150MHz Output clock frequencies up to 200MHz Configurable spread spectrum modulation Operating voltage of 3.3V Replaces multiple crystals and oscillators Controllable output drive levels Advanced, low-power CMOS process RoHS compliant packaging The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS251 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD S1:0 2 OTP ROM with PLL Divider Values Crystal or clock input PLL Clock Synthesis, Spread Spectrum and Control Circuitry CLK X1/ICLK Crystal Oscillator X2 External capacitors are required with a crystal input. ICS251 OCTOBER 10, 2017 GND PDTS (output and PLL) 1 ©2017 Integrated Device Technology, Inc. ICS251 DATASHEET Pin Assignment Output Clock Selection Table S0 1 8 PDTS VDD 2 7 GND X1/ICLK 3 6 S1 X2 4 5 CLK S1 S0 CLK (MHz) Spread Percentage 0 0 User Configurable User Configurable 0 1 User Configurable User Configurable 1 0 User Configurable User Configurable 1 1 User Configurable User Configurable 8-pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 S0 Input Select pin 0 for frequency selection on CLK. Internal pull-up resistor. 2 VDD Power Connect to +3.3 V. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. Connect this pin to a crystal, or float for clock input. 4 X2 XO 5 CLK Output 6 S1 Input 7 GND Power 8 PDTS Input Clock output. Weak internal pull-down when tri-state. Select pin 1 for frequency selection on CLK. Internal pull-up resistor. Connect this to ground. Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up resistor. The pin must be tied either directly or through the external resistor to VDD or GND. External resistor value must be less than 15kOhm. External Components capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The ICS251 requires a minimum number of external components for proper operation. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. The value (in pF) of these crystal caps should equal (CL -6pF) × 2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16pF load capacitance, each crystal capacitor would be 20pF [(16-6) x 2] = 20. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS251 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER 2 OCTOBER 10, 2017 ICS251 DATASHEET PCB Layout Recommendations IDT VersaClock Software For optimum device performance and lowest output phase noise, the following guidelines should be observed. IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. Spread Spectrum Modulation The ICS251 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electro-magnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS251. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. ICS251 Configuration Capabilities The architecture of the ICS251 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS251 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between ±0.125% to ±2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. The ICS251 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Each output frequency can be represented as: OutputFreq = REFFreq -------------------------------------OutputDivide Spread Spectrum Modulation Rate ----M N The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30–33kHz. For other applications, a 120kHz modulation option is available. Output Drive Control The ICS251 has two output drive settings. Low drive should be selected when outputs are less than 100MHz. High drive should be selected when outputs are greater than 100MHz. (Consult the AC Electrical Characteristics for output rise and fall times for each drive option.) OCTOBER 10, 2017 3 FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER ICS251 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS251. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND. Inputs Clock Outputs Max. Units -0.5 4.6 V Referenced to GND. -0.5 VDD + 0.5 V Referenced to GND. -0.5 VDD + 0.5 V -65 150 C 260 C 125 C Storage Temperature Soldering Temperature Typ. Max 10 seconds. Junction Temperature Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS251M) 0 +70 C Ambient Operating Temperature (ICS251MI) -40 +85 C Power Supply Voltage (measured in respect to GND) +3.15 Power Supply Ramp Time FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER 4 +3.3 +3.45 V 4 ms OCTOBER 10, 2017 ICS251 DATASHEET DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, ambient temperature -40 to +85C Parameter Operating Voltage Symbol Conditions VDD Min. Typ. Max. Units 3.15 3.3 3.45 V Configuration dependent see VersaClock estimates. mA Operating Supply Current Input High Voltage IDD 33.3333 MHz output, PDTS = 1, no load. Note 1. Input High Voltage VIH S1:S0. Input Low Voltage VIL S1:S0. Input High Voltage, PDTS VIH Input Low Voltage, PDTS VIL Input High Voltage VIH ICLK. Input Low Voltage VIL ICLK. Output High Voltage (CMOS High) VOH IOH = -4mA. VDD - 0.4 V Output High Voltage VOH IOH = -8mA (Low Drive); IOH = -12mA (High Drive). 2.4 VDD - 0.4 V Output Low Voltage VOL IOL = 8mA (Low Drive); IOL = 12mA (High Drive). Short Circuit Current IOS ±70 mA Nominal Output Impedance ZO 20  PDTS = 0. 14 mA 500 A VDD/2 + 1 V 0.4 VDD - 0.5 V V 0.4 VDD/2 + 1 V V VDD/2 - 1 0.4 V V Internal Pull-up Resistor RPUP S1:S0, PDTS. 190 k Internal Pull-down Resistor RPD CLK output. 120 k Input Capacitance CIN Inputs. 4 pF Note 1: Example with 25MHz crystal input with output of 33.3MHz, no load, and VDD = 3.3V. OCTOBER 10, 2017 5 FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER ICS251 DATASHEET AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, ambient temperature -40 to +85C Parameter Symbol Input Frequency FIN Conditions tOR Output Fall Time tOF Max. Units 5 27 MHz Input clock. 3 150 MHz 0.314 200 MHz 20% to 80%, Note 1. 1 80% to 20%, Note 1. Duty Cycle Typ. Fundamental crystal. Output Frequency Output Rise Time Min. Note 2. ns 1 ns 49–51 60 % PLL lock time from power-up. 4 10 ms PDTS goes high until stable CLK output, spread spectrum off. .6 2 ms PDTS goes high until stable CLK output, spread spectrum on. 4 7 ms PDTS goes high until spread spectrum is stable, spread spectrum on. 10 50 ms One Sigma Clock Period Jitter Configuration dependent. 50 ps Maximum Absolute Jitter Deviation from Mean. Configuration dependent. +200 ps Power-up Time tja 40 Note 1: Measured with 15pF load. Note 2: Duty cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER Symbol Conditions Min. Typ. Max. Units JA Still air. 150 C/W JA 1 m/s air flow. 140 C/W JA 3 m/s air flow. 120 C/W 40 C/W JC 6 OCTOBER 10, 2017 ICS251 DATASHEET Marking Diagrams 8 5 251PMLF LOT YYWW 1 4 8 5 251PMILF LOT YYWW 1 4 Notes: 1. “LOT” is the lot number. 2. “YYWW” is the last two digits of the year and week that the part was assembled. 3. “I” denotes industrial temp. range (if applicable). 4. “LF” denotes RoHS compliant package. 5. Bottom marking: country of origin. OCTOBER 10, 2017 7 FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER ICS251 DATASHEET 8 Package Drawings (DCG8, 8-SOIC, 150 Mil. Body) FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER OCTOBER 10, 2017 9 Package Drawings (DCG8, 8-SOIC, 150 Mil. Body), cont. OCTOBER 10, 2017 ICS251 DATASHEET FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 251PMLF 251PMILF 251M-XXLF 251MI-XXLF 251M-XXLFT 251MI-XXLFT See page 7 Tubes Tubes Tubes Tubes Tape and Reel Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 251MXXLF 251MIXXLF 251MXXLF 251MIXXLF Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 251M-XXLF and 251MI-XXLF are factory programmed versions of the ICS251PMLF and ICS251PMILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. Revision History Date October 10, 2017 May 19, 2014 Description of Change 1. Updated marking diagrams. 2. Added legal disclaimer 3. Updated package outline drawings. 4. Updated ordering information. 1. Updated Supply Voltage max rating from 7V to 4.6V 2. Updated datasheet with latest version of template. Corporate Headquarters Sales 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. 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