2SJ244JYTR-E

2SJ244 Silicon P Channel MOS FET REJ03G0853-0200 (Previous: ADE-208-1187) Rev.2.00 Sep 07, 2005 Description High speed power switching Low voltage operation Features • Very Low on-resistance • High speed switching • Suitable for camera or VTR motor drive circuit, power switch, solenoid drive and etc. Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) D 3 2 1 G 4 1. Gate 2. Drain 3. Source 4. Drain S Note: Marking is “JY”. *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SJ244 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID ID (pulse) Note 2 Pch Tch Tstg Note 1 Value –12 ±7 ±2 ±4 1 150 –55 to +150 Unit V V A A W °C °C Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10% 2. Value on the alumina ceramic board (12.5 × 20 × 0.7 mm) Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Turn-off delay time Body to drain diode forward voltage Note: 3. Pulse test Symbol V (BR) DSS V (BR) GSS IGSS IDSS VGS (off) RDS (on) 1 RDS (on) 2 |yfs| Ciss Coss Crss td (on) td (off) VDF Min –12 ±7 — — –0.4 — — — — — — — — — Typ — — — — — 0.65 0.5 1.8 100 168 35 365 1450 — Max — — ±5 –1 –1.4 0.9 — — — — — — — 7 Unit V V µA µA V Ω Ω S pF pF pF ns ns V Test Conditions ID = –1 mA, VGS = 0 IG = ±10 µA, VDS = 0 VGS = ±6 V, VDS = 0 VDS = –8 V, VGS = 0 ID = –100 µA, VDS = –5 V Note 3 ID = –0.5 A, VGS = –2.5 V ID = –1 A, VGS = –4 V Note 3 ID = –1 A, VDS = –5 V VDS = –5 V VGS = 0 f = 1 MHz ID = –0.2 A Vin = –4 V, RL = 51 Ω IF = 4 A Note 3 Note 3 Note 3 , VGS = 0 Rev.2.00 Sep 07, 2005 page 2 of 6 2SJ244 Main Characteristics Maximum Channel Power Dissipation Curve Channel Power Dissipation Pch (W) (on the alumina ceramic board) 2.0 –10 PW = 1 ms (1 shot) Maximum Safe Operation Area 1.5 ID (A) –3 –1 –0.3 –0.1 –0.03 Operation in this area is limited by RDS (on) –1 –3 DC n tio ra pe O 1.0 Drain Current a (T = ) °C 25 0.5 0 0 50 100 150 200 –0.01 –0.1 –0.3 –10 –30 –100 Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V) (on the alumina ceramic board) Typical Forward Transfer Characteristics –5 Tc = –25°C 25°C 75°C Typical Output Characteristics –5 –5 V –4.5 V –4 V –3.5 V ID (A) –4 –3 V –3 ID (A) Drain Current Pulse Test –4 –3 –2.5 V Drain Current –2 –2 V –1 VGS = –1.5 V 0 0 –2 –4 –6 –8 –10 –2 –1 VDS = –5 V Pulse Test 0 0 –1 –2 –3 –4 –5 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source on State Resistance RDS (on) (Ω) 20 10 5 25°C 2 1 0.5 VDS = –5 V Pulse Test 0.2 –0.1 –0.2 –0.5 –1 –2 –5 –10 75°C Tc = –25°C 10 Drain to Source on State Resistance vs. Drain Current Pulse Test 5 2 1 0.5 –2 V –3 V VGS = –4 V 0.2 0.1 –0.1 –0.2 –0.5 –1 –2 –5 10 Drain Current ID (A) Drain Current ID (A) Rev.2.00 Sep 07, 2005 page 3 of 6 2SJ244 Drain to Source Saturation Voltage vs. Gate to Source Voltage Pulse Test –0.8 Drain to Source Saturation Voltage VDS (on) (V) Drain to Source on State Resistance vs. Temperature Drain to Source on State Resistance RDS (on) (Ω) 1.0 ID = –1 A 0.8 VGS = –2.5 V –0.5 A 0.6 –0.5 A ID = –1 A VGS = –4 V –1.0 –0.6 ID = –1 A –0.4 –0.5 A –0.2 A –0.1 A 0.4 –0.2 0.2 Pulse Test 0 –25 0 25 50 75 100 0 0 –1 –2 –3 –4 –5 Gate to Source Voltage VGS (V) Case Temperature Tc (°C) Body-Drain Diode Reverse Recovery Time 2000 2000 1000 500 Switching Time vs. Drain Current Reverse Recovery Time trr (ns) Switching Time t (ns) 1000 500 td(off) tf tr 200 100 50 di / dt = 10 A / µs PW = 10 µs 20 –0.1 –0.2 –0.5 –1 –2 –5 –10 200 100 50 VGS = –4 V, VDD = –10 V PW = 2 µs, Duty Cycle = 1 % 20 –0.1 –0.2 –0.5 –1 –2 –5 –10 td(on) Reverse Drain Current IDR (A) Drain Current ID (A) Dynamic Input Characteristics VDS (V) ID = –4 A Pulse Test –20 –5 V VDD = –10 V –8 Typical Capacitance vs. Drain to Source Voltage VGS (V) –10 1000 500 Coss –25 Drain to Source Voltage Gate to Source Voltage Capacitance C (pF) –15 VDS –10 VGS –6 200 100 50 Ciss –4 VDD = –10 V Crss VGS = 0 f = 1 MHz –0.5 –1 –2 –5 –10 –5 –5 V –2 20 10 –0.1 –0.2 0 0 2 4 6 8 10 0 Gate Charge Qg (nc) Drain to Source Voltage VDS (V) Rev.2.00 Sep 07, 2005 page 4 of 6 2SJ244 Reverse Drain Current vs. Source to Drain Voltage –4 Reverse Drain Current IDR (A) Pulse Test –3 –4 V –2 –2.5 V –1 VGS = 0 0 0 –0.5 –1.0 –1.5 –2.0 Source to Drain Voltage VSD (V) Rev.2.00 Sep 07, 2005 page 5 of 6 2SJ244 Package Dimensions JEITA Package Code SC-62 RENESAS Code PLZZ0004CA-A Package Name UPAK / UPAKV MASS[Typ.] 0.050g Unit: mm 4.5 ± 0.1 0.4 1.8 Max φ1 1.5 ± 0.1 0.44 Max (1.5) 2.5 ± 0.1 4.25 Max 1.5 1.5 3.0 Ordering Information Part Name 2SJ244JYTL-E 2SJ244JYTR-E 1000 pcs 1000 pcs Quantity Taping Taping Shipping Container Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 0.8 Min 0.44 Max (0.4) 0.53 Max 0.48 Max (2.5) (0.2) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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