2SJ505STL-E

2SJ505(L), 2SJ505(S) Silicon P Channel MOS FET REJ03G0872-0500 Rev.5.00 Jun 05, 2006 Description High speed power switching Features • Low on-resistance RDS (on) = 0.017 Ω typ. • Low drive current. • 4 V gate drive devices. • High speed switching. Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) 4 4 G 1 1 2 3 S 2 1. Gate 2. Drain 3. Source 4. Drain RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) D 3 Rev.5.00 Jun 05, 2006 page 1 of 8 2SJ505(L), 2SJ505(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Ta = 25°C, Rg ≥ 50 Ω Symbol VDSS VGSS ID ID (pulse) Note 1 IDR IAP Note 3 EAR Note 3 Pch Note 2 Tch Tstg Value –60 ±20 –50 –200 –50 –50 214 75 150 –55 to +150 Unit V V A A A A mJ W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 4. Pulse test Symbol V (BR) DSS V (BR) GSS IDSS IGSS VGS (off) RDS (on) RDS (on) |yfs| Ciss Coss Crss td (on) tr td (off) tf VDF trr Min –60 ±20 — — –1.0 — — 27 — — — — — — — — — Typ — — — — — 0.017 0.024 39 4100 2100 450 32 225 530 330 –1.1 110 Max — — –10 ±10 –2.0 0.022 0.036 — — — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns Test Conditions ID = –10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VDS = –60 V, VGS = 0 VGS = ±16 V, VDS = 0 ID = –1 mA, VDS = –10 V ID = –25 A, VGS = –10 V Note 4 ID = –25 A, VGS = –4 V Note 4 ID = 25 A, VDS = 10 V Note 4 VDS = –10 V VGS = 0 f = 1 MHz VGS = –10 V ID = –25 A RL = 1.2 Ω IF = –50 A, VGS = 0 IF = –50 A, VGS = 0 diF/dt = 50 A/µs Rev.5.00 Jun 05, 2006 page 2 of 8 2SJ505(L), 2SJ505(S) Main Characteristics Power vs. Temperature Derating 80 –1000 –300 Maximum Safe Operation Area Pch (W) ID (A) 10 µ =1 1 m s 0m s Op s( era 1s tio ho n( t) Tc =2 Operation in 5° C) this area is limited by RDS (on) DC 60 –100 PW 10 µs 0 Channel Dissipation –30 –10 –3 –1 –0.3 40 20 Drain Current 200 0 0 50 100 150 Ta = 25°C –0.1 –0.1 –0.3 –1 –3 –10 –30 –100 Case Temperature Tc (°C) Drain to Source Voltage VDS (V) Typical Output Characteristics –100 –10 V –8 V –5 V Pulse Test –4 V –100 Typical Transfer Characteristics VDS = –10 V Pulse Test ID (A) –80 ID (A) Drain Current –4.5 V –80 –60 –60 –3.5 V Drain Current –40 –3 V –20 VGS = –2.5 V 0 0 –4 –8 –12 –16 –20 –40 –20 75°C 25°C Tc = –25°C –3 –4 –5 0 0 –1 –2 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage VDS (on) (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage –2.0 Pulse Test –1.6 Static Drain to Source on State Resistance vs. Drain Current Static Drain to Source on State Resistance RDS (on) (Ω) 100 50 VGS = –4 V 20 10 5 –10 V –1.2 ID = –50 A –0.8 –20 A –10 A –16 –20 –0.4 –5 A 0 0 –4 –8 –12 2 Pulse Test 1 –1 –3 –10 –30 –100 –300 –1000 Gate to Source Voltage VGS (V) Drain Current ID (A) Rev.5.00 Jun 05, 2006 page 3 of 8 2SJ505(L), 2SJ505(S) Static Drain to Source on State Resistance vs. Temperature Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (Ω) 50 Pulse Test 40 VGS = –4 V 30 –10 A ID = –50 A –20 A 100 30 10 3 1 0.3 0.1 –0.1 75°C Tc = –25°C 25°C Forward Transfer Admittance vs. Drain Current 20 –50 A –10 A, –20 A 10 –10 V VDS = –10 V Pulse Test –0.3 –1 –3 –10 –30 –100 0 –40 0 40 80 120 160 Case Temperature Tc (°C) Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 50000 20000 VGS = 0 f = 1 MHz Body-Drain Diode Reverse Recovery Time 1000 Reverse Recovery Time trr (ns) 500 Capacitance C (pF) 10000 5000 2000 1000 500 200 100 0 –10 –20 Crss –30 –40 –50 Ciss 200 100 50 Coss 20 10 –0.1 di / dt = 50 A / µs VGS = 0, Ta = 25°C –0.3 –1 –3 –10 –30 –100 Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V) Dynamic Input Characteristics VDS (V) VDD = –50 V –25 V –10 V Switching Characteristics VGS (V) 0 1000 td(off) 500 tf 200 100 50 tr td(on) VGS = –10 V, VDD = –30 V PW = 10 µs, duty ≤ 1 % –1 –3 –10 –30 –100 0 –20 –4 Drain to Source Voltage –40 VDS VDD = –50 V –25 V –10 V VGS –8 –60 –12 –80 ID = –50 A 0 40 80 120 160 –16 Gate to Source Voltage Switching Time t (ns) 20 10 –0.1 –0.3 –100 –20 200 Gate Charge Qg (nc) Drain Current ID (A) Rev.5.00 Jun 05, 2006 page 4 of 8 2SJ505(L), 2SJ505(S) Reverse Drain Current vs. Source to Drain Voltage –100 Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) 250 IAP = –50 A VDD = –25 V duty < 0.1 % Rg ≥ 50 Ω Reverse Drain Current IDR (A) –80 200 –60 –5 V –40 –10 V VGS = 0 150 100 –20 Pulse Test 0 0 –0.4 –0.8 –1.2 –1.6 –2.0 50 0 25 50 75 100 125 150 Source to Drain Voltage VSD (V) Channel Temperature Tch (°C) Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 0.05 0.02 θch – c (t) = γ s (t) • θch – c θch – c = 1.67°C/W, Tc = 25°C PDM p ot uls e D= PW T 0.03 0.0 1 h PW T 1s 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit Avalanche Waveform 1 • L • IAP2 • 2 VDSS VDSS – VDD V(BR)DSS IAP VDD ID VDS VDS Monitor L IAP Monitor EAR = Rg D.U.T Vin –15 V 50 Ω VDD 0 Rev.5.00 Jun 05, 2006 page 5 of 8 2SJ505(L), 2SJ505(S) Switching Time Test Circuit Vin Vin Monitor D.U.T. RL 90% Vin –10 V 50 Ω VDD = –30 V Vout td(on) 10% tr td(off) 10% tf 90% 90% Vout Monitor 10% Waveform Rev.5.00 Jun 05, 2006 page 6 of 8 2SJ505(L), 2SJ505(S) Package Dimensions Package Name LDPAK(L) JEITA Package Code  RENESAS Code PRSS0004AE-A Previous Code LDPAK(L) / LDPAK(L)V MASS[Typ.] 1.40g Unit: mm (1.4) 4.44 ± 0.2 10.2 ± 0.3 1.3 ± 0.15 11.3 ± 0.5 0.3 10.0 + 0.5 – 8.6 ± 0.3 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 11.0 ± 0.5 0.2 0.86 + 0.1 – 2.49 ± 0.2 0.4 ± 0.1 Package Name LDPAK(S)-(1) JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V MASS[Typ.] 1.30g Unit: mm 4.44 ± 0.2 10.2 ± 0.3 (1.4) 8.6 ± 0.3 + 0.3 – 0.5 10.0 (1.5) (1.5) 2.49 ± 0.2 0.2 0.1 + 0.1 – 7.8 7.0 2.2 1.37 ± 0.2 1.3 ± 0.2 2.54 ± 0.5 0.3 3.0 + 0.5 – 0.2 0.86 + 0.1 – 0.4 ± 0.1 2.54 ± 0.5 Rev.5.00 Jun 05, 2006 page 7 of 8 1.7 1.3 ± 0.15 7.8 6.6 2SJ505(L), 2SJ505(S) Ordering Information Part Name 2SJ505L-E 2SJ505STL-E Quantity 500 pcs 1000 pcs Box (Sack) Taping Shipping Container Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.5.00 Jun 05, 2006 page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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