2SK2315

2SK2315 Silicon N Channel MOS FET REJ03G1006-0200 (Previous: ADE-208-1354) Rev.2.00 Sep.07,2005 Application High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current 2.5 V gate drive device can be driven from 3 V source. Suitable for DC-DC converter, motor drive, power switch, solenoid drive Outline RENESAS RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) 3 21 G 4 D 1. Gate 2. Drain 3. Source 4. Drain S Note: Marking is “TY” *UPAK *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep. 07, 2005 page 1 of 5 2SK2315 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Channel dissipation Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. When using the alumina ceramic board (12.5 × 20 × 0.7mm) Symbol VDSS VGSS ID ID(pulse)*1 IDR Pch*2 Tch Tstg Ratings 60 ±20 2 4 2 1 150 –55 to +150 Unit V V A A A W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate Gate to source breakdown voltage Gate Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on time Turn-off time Note: 3. Pulse Test Symbol V(BR)DSS V(BR)GSS IGSS IDSS VGS(off) RDS(on) |y |yfs| Ciss Coss Coss Crss ton toff Min 60 ±20 — — 0.5 — — 1.5 — — — — — Typ — — — — — 0.4 0.4 0.35 1.8 173 85 23 21 85 Max — — ±5 5 1.5 0.6 0.45 — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns Test Conditions ID = 10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 50 V, VGS = 0 ID = 1 mA, VDS = 10 V ID = 0.3 A, VGS = 3 V*3 ID = 1 A, VGS = 4 V*3 ID = 1 A, VDS = 10 V*3 VDS = 10 V, VGS = 0, f = 1 MHz ID = 1 A, RL = 30 Ω, VGS = 10 V Rev.2.00 Sep. 07, 2005 page 2 of 5 2SK2315 Main Characteristics Power vs. Temperature Derating Channel Dissipation Pch** (W) (** on the almina ceramic board) 1.6 5 100 µs Maximum Safe Operation Area ID (A) 2 1 0.5 PW 1 1.2 = m s 10 m Drain Current s C D 0.8 0.2 0.1 0.05 0.02 0.01 Operation in this area is limited by RDS(on) O pe t ra n io 0.4 Ta = 25°C 1 shot pulse 0.5 1 2 5 10 20 50 100 200 0 50 100 150 200 0.005 0.2 Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V) Typical Output Characteristics 5 5 10 V 5V 4V 3.5 V Ta = 25°C Pulse Test 3V Typical Transfer Characteristics ID (A) 4 ID (A) 4 Tc = 75°C 25°C –25°C Drain Current 2 2.5 V Drain Current 3 3 2 1 2V VGS = 1.5 V 1 VDS = 10 V Pulse Test 0 2 4 6 8 10 0 1 2 3 4 5 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage VDS(on) (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source On State Resistance RDS(on) (Ω) 1.0 Pulse Test Ta = 25°C 5 2 1 0.5 Static Drain to Source State Resistance vs. Drain Current 0.8 Ta = 25°C Pulse Test 0.6 ID = 2 A VGS = 3 V 0.4 1A 0.2 0.5 A 10 V 0.2 0.1 0.05 0.1 0 4 8 12 16 20 0.2 0.5 1 2 5 10 Gate to Source Voltage VGS (V) Drain Current ID (A) Rev.2.00 Sep. 07, 2005 page 3 of 5 2SK2315 Static Drain to Source on State Resistance vs. Temperature 1.0 Static Drain to Source on State Resistance RDS(on) (Ω) Forward Transfer Admittance |yfs| (S) Forward Transfer Admittance vs. Drain Current 10 5 2 1 0.5 VDS = 10 V Pulse Test 0.8 ID = 2 A 0.6 VGS = 3 V Tc = –25°C 25°C 75°C 1A 0.4 0.5 A 0.2 0 –40 VGS = 10 V 1A 0.5 A ID = 2 A 0.2 0.1 0.1 0 40 80 120 160 0.2 0.5 1 2 5 10 Case Temperature Tc (°C) Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage VDS (V) 1000 100 Dynamic Input Characteristics VDD = 50 V 25 V 10 V VGS 20 Capacitance C (pF) Ciss 100 Coss 80 16 Drain to Source Voltage 60 VDS 12 Crss 10 VGS = 0 f = 1 MHz 40 ID = 2 A VDD = 50 V 25 V 10 V 8 20 4 0 10 1 0 10 20 30 40 50 0 2 4 6 8 Drain to Source Voltage VDS (V) Gate Charge Qg (nc) Switching Characteristics Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 200 5 Pulse Test 4 Switching Time t (ns) 100 td(off) 50 tf tr 3 10 V 2 5V VGS = 0 20 10 5 td(on) 2 0.05 VGS = 10 V, PW = 2 µs VDD = 30 V, duty < 1 % 1 0.1 0.2 0.5 1 2 5 0 0.4 0.8 1.2 1.6 2.0 Drain Current ID (A) Source to Drain Voltage VSD (V) Rev.2.00 Sep. 07, 2005 page 4 of 5 Gate to Source Voltage VGS (V) 2SK2315 Package Dimensions JEITA Package Code SC-62 RENESAS Code PLZZ0004CA-A Package Name UPAK / UPAKV MASS[Typ.] 0.050g Unit: mm 4.5 ± 0.1 1.5 1.5 1.5 3.0 Ordering Information Part Name 2SK2315TYTL-E 2SK2315TYTR-E Quantity 1000 pcs 1000 pcs Taping Taping Taping Taping Shipping Container Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of contact production before ordering the product. Rev.2.00 Sep. 07, 2005 page 5 of 5 0.8 Min 0.44 Max (0.4) 0.53 Max 0.48 Max (2.5) φ1 2.5 ± 0.1 4.25 Max 0.4 1.8 Max 1.5 ± 0.1 0.44 Max (1.5) (0.2) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember placement Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme of substitutive, auxiliary circuits, circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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