32171

REJ09B0015-0200Z 32 32171 Group User’s Manual RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 2.00 Revision date: Sep 19, 2003 www.renesas.com Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. • Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. • All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). • When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. • Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. • If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. • Please contact Renesas Technology Corporation for further details on these materials or t he products contained therein. REVISION HISTORY Rev. 0.1 1.0 Date Page Apr 8, 2000 Nov 1, 2002 all all P1-6 32171 Group User’s Manual Description Summary – First edition issued Explanation of the M32171F2 added Designation of M32R/E changed to M32R/ECU Description in Section 1.1.6, Built-in Full-CAN Function, corrected Incorrect: Compliant with CAN Specification V2.0B Correct: Compliant with CAN Specification V2.0B active P1-7 P1-8 P1-10 P1-11 M32171F2 added to the internal flash memory in Figure 1.2.1 M32171F2 added to the internal flash memory in Table 1.2.2 Table 1.2.4, List of Type Name added Note 1 in Figure 1.3.1 corrected Incorrect: Operates with a 5 V power supply Correct: Operates with a 3.3 V or 5 V power supply P1-12 Functional description of pin names VCCE and OSC-VCC in Table 1.3.1corrected Explanation of WR added to the functional description of clock in Table 1.3.1 P1-13 P1-17 P3-5 P3-6 Explanation of the A-D converter in Table 1.3.1 corrected Figure 1.4.1 corrected Figure 3.1.3, "M32171F2 address space," added Table 3.2.1 corrected Note 1 in Table 3.2.1 corrected P3-7 P3-8 P4-25 P5-13 P5-17 P5-19 P6-2 Figure 3.2.3 "M32171F2 operation mode and internal ROM/external extended areas," added M32171F2 added to Table 3.3.1 Section 4.13, "Precautions on EIT," added Relevant names of causes added to Table 5.4.1 Relevant names of causes added to Table 5.5.1 Explanation added to (4) "Enabling multiple interrupts" in Section 5.5.2, "Processing of Internal Peripheral I/O Interrupts by Handler" Description in Section 6.1, "Outline of the Internal Memory," corrected Precautions added to Table 6.2.1 P6-3 P6-5 P6-7 P6-8 P6-13 P6-22 P6-25 M32171F2 added to Table 6.3.1 Precautions added Precautions (Note 2) added Precautions added Figure 6.4.4, “FCNT4 Register Usage Example 2,” added Table 6.5.1 corrected Precautions (Note 2, 3, 4) added to Table 6.5.2 (1/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P6-27 P6-30 P6-38 P6-40 P6-43 P6-46 32171 Group User’s Manual Description Summary Table 6.5.5, “M32171F2’s relevant block and specificaion address,” added Table 6.5.9, “Block configuration of M32171F2 flash memory,” added Figure 6.5.15, Figure 6.5.16 and Figure 6.5.17 corrected (3) M32171F2 added to Section 6.5.4, “Flash Programming Time (Reference Value)” Precautios (Notes 2, 3, 4) added Figure 6.7.6, “Virtual-flash emulation area of the M32171F2 divided in 8 Kbyte units,” added Figure 6.7.7, “Virtual-flash emulation area of the M32171F2 divided in 4 Kbyte units,” added P6-47, P6-48 P6-49 Incorrect register names in Figures 6.7.8 through 6.7.11 corrected Incorrect: LBAKNKAD Correct: LBANKAD Figure 6.7.12, “Virtual-flash bank register setup values for the M32171F2 when divided in 8 Kbyte units,” added Figure 6.7.13, “Virtual-flash bank register setup values for the M32171F2 when divided in 4 Kbyte units,” added P6-55 P6-56 P7-3 P7-4 to P7-7 P8-4 Section 6.9, “Internal Flash Memory Protect Functions,” added Explanation in Section 6.10, ”Precautions to Be Taken when Reprogramming Flash Memory,” changed Table 7.3.1 corrected Tables 7.3.2 to 7.3.5, “ Pin Status When Reset,” added or corrected Table 8.2.1 corrected Precautions in Table 8.2.1 corrected P8-22 to P8-25 P8-26 P9-4 P10-1 to P10-142 P10-4 P10-5 P10-12 P10-31 P10-47 P10-55 P10-66 Figures 8.4.1 to 8.4.4 corrected Section 8.5, “Precautions on Input/output Ports,” added Figure 9.1.2, “Causes of DMAC Requests Connection Diagram,” added Chapter 10 overall, designation of the prescaler unified to PRS Port numbers added to Figure 10.1.1 Port numbers added to Figure 10.1.2 Port numbers added to Figure 10.2.2 Figure 10.2.5 changed Port numbers added to Figure 10.3.1 Port number added to Figure 10.3.5 Figure 10.3.8 corrected (2/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P10-84 P10-93 P10-96 P10-124 P10-130 P10-133 P10-141 P11-3 32171 Group User’s Manual Description Summary Port numbers added to Figure 10.4.1 Port numbers added to Figure 10.4.5 Port numbers added to Figure 10.4.6 Port numbers added to Figure 10.5.1 Figure 10.5.3 corrected Port numbers added to Figure 10.6.1 Note 1 in Figure 10.6.3 corrected Table 11.1.1 corrected Precautions in Table 11.1.1 corrected P11-4 P11-35 Register names in Figure 11.1.1 corrected Method for calculating the conversion time during A-D conversion mode and that for conversion time during comparate mode explained separately Table 11.3.1 and precausions corrected Figure 11.3.4, “Conceptual Diagram of Conversion Time in Comparate Mode,” added Table 11.3.2, “Conversion Clock Cycles in Comparate Mode,” added P11-37 to P11-38 P11-40 P12-12 P12-24 Explanation in Section 11.3.5, “Definition of the A-D Conversion Accuracy,” changed A section “Regarding the analog input pins” added to Section 11.4, “Precautions on Using Figure 12.2.4 corrected Description of the last line in Section 12.2.8, “SIO Baud Rate Register,” corrected Incorrect: 7 or less Correct: greater than 7 to P11-42 A-D Converters” P12-58 Figure 12.7.5, “Detecting the Start Bit, added Figure 12.7.6, “Example of an Invalid Start Bit (Not Received),” added Figure 12.7.7, “Delay when Receiving,” added P13-2 Description in Section 13.1, “Outline of the CAN Module,” corrected Incorrect: Compliant with CAN (Controller Area Network) Specification V2.0B Correct: Compliant with CAN (Controller Area Network) Specification V2.0B active Protocol explanation in Table 13.1.1 corrected Incorrect: CAN Specification V2.0B Correct: CAN Specification V2.0B active Explanation of acceptance filters in Table 13.1.1 changed Precautions in Table 13.1.1 changed P13-3 P13-19 P13-20 Figure 13.1.1 corrected Table 13.2.2, “Example for Setting Bit Timing when CPU Clock: 32 MHz,” added Note 3 added (3/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P13-28 P13-29 P13-30 P13-35 Figure 13.2.5 corrected Figure 13.2.6 corrected Figure 13.2.7 corrected 32171 Group User’s Manual Description Summary Figure 13.2.8, “Relationship between Mask Registers and the Controlled Slots,” added Figure 13.2.9, “ Operation of the Acceptance Filter,” added P13-61 P13-64 P13-65 P13-68 P13-71 P13-75 P13-78 P13-82 P15-6 P15-12 P16-6 P18-2 P19-7 P19-14 P19-14 P19-15 P19-16 Explanation in (2) Confirming that transmission is idle corrected Figure 13.5.2 corrected Explanation in (2) Confirming that reception is idle corrected Figure 13.6.2 corrected Explanation in (2) Confirming that transmission is idle corrected Figure 13.7.2 corrected Explanation in (2) Confirming that reception is idle corrected Figure 13.8.2 corrected Figures 15.2.1 to 15.2.6 corrected (Address signals A12 to A30 and chip select signals Figures 15.3.1 and 15.3.2 corrected (Address signals A12 to A30 and chip select signals Figures 16.3.1 to 16.3.14 corrected (Address signals A12 to A30 and chip select signals Precautions added to Figure 18.1.1 Figure 19.4.2 corrected Precautions added to Section 19.5, “Boundary Scan Description Language” BSDL description language for the 32171 (Figures 19.5.1 to 19.5.14) deleted Precautions added to Figure 19.6.1 Precautions added to Section 19.7, “Processing Pins when Not Using JTAG” Figure 19.7.1, “Processing Pins when Not Using JTAG,” added to P15-11 CS0, CS1 separately shown) to P15-13 CS0, CS1 separately shown) to P16-19 CS0, CS1 separately shown) P20-1 In Chapter 20, explanation of power supply turn-on/turn-off sequences during Chapter 20 overall, designations of “5V system” and “3.3V system” changed to “external I/O” and “internal,” respectively to P20-16 VCCE=3.3V added P20-12 P20-13 P20-15 P21-3, P21-4 P21-5 Figure 20.3.6 corrected Figure 20.3.8, “CPU Reset State” deleted Figure 20.3.12, “SRAM Data Backup State” deleted Recommended operating conditions corrected (minimum value of analog reference voltage added) (1) Electrical characteristics when f(XIN) = 10 MHz corrected (4/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P21-7 P21-10 P21-11 to P21-18 P21-19 P21-22 P21-32 32171 Group User’s Manual Description Summary (3) Electrical characteristics when f(XIN) = 8 MHz corrected Section 21.1.4, “A/D Conversion Characteristics,” corrected Section 21.2, “Electrical Characteristics (when VCCE = 3.3V),” added Explanation in Section 21.3.1, “Timing Requirements,” corrected (9) Table of rated RTD timings corrected Figure 21.3.12 corrected Appendix 3 Appendix 3, “Processing Unused Pins,” added Appendix 4 Appendix 4, “Summary of Precautions,” added “Precautions about Noise” in Appendix 3 moved to Appendix 4, “Summary of Precautions” 2.00 Sep 19, 2003 all P1-4 P2-14 P3-8 The word “Mitsubishi” deleted or replaced by “Renesas” Figure 1.1.1 and Table 1.1.1 newly added Section 2.7, “Precautions on CPU” added Addresses in the third line of Section 3.3 corrected Incorrect: Correct: H’0000 0000 to H’0003 FFFF H’0000 0000 to H’003F FFFF H’0080 4000 through H’0080 3FFF H’0080 4000 through H’0080 7FFF ← ← P3-9 Addresses in Section 3.4.1 corrected Incorrect: Correct: P4-20 Designation in (2), “Updating SM, IE and C bits” in the Section [EIT processing] corrected Incorrect: Correct: SM SM 0 Unchanged P5-end Section 5.2 and 5.3 placed in reversed Title of Section 5.3 (former 5.2) changed Before: After: Interrupt Sources of Internal Peripheral Interrupt Request Sources in Internal Peripheral total of 31 total of 22 P5-2 Description in the fourth line of Section 5.1 corrected Incorrect: Correct: Note added to Table 5.1.1 P5-3 P5-5, P5-6 P5-7 P5-9 P5-10 Description in Section 5.2.3 altered Description in (1), “IREQ (Interrupt Request) bit (D3 or D11)”, altered Figures 5.2.2, “Configuration of the Interrupt Control Register (Edge-recognized Type)”, and 5.2.3, “Configuration of the Interrupt Control Register (Level-recognized Type)”, changed Figure 5.1.1 altered Note (former CAUTION) altered (5/8) REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P5-17 P5-19, P5-20 P5-21 P6-43 P6-44 P6-50 P7-1 to P7-7 P7-3 P10-end P10-19, P10-20 P10-49 P10-72 P10-82 P10-122 P10-87 P10-96 P10-103 P10-115 P10-119 P10-124 Table 5.5.1 corrected 32171 Group User’s Manual Description Summary Description in (2) to (4), Section 5.5.2 changed Figure 5.5.2 changed Note 3 for Section 6.7.1 corrected Notes in Figures 6.7.2 and 6.7.3 corrected Figure, “Virtual-Flash Emulation Mode to Normal Mode Return Sequence” deleted Chapter 7 overall, The phrase “reset release” changed to “ exiting reset” Registers R0-R15 added to Table 7.3.1 Sections 10.7 to 10.9 deleted Note added Figure 10.3.2, “Count Clock Dependent Delay”, newly added Figure (former 10.3.13), “Prescaler Delay”, deleted Figure 10.3.22 deleted Description of DMA transfer request generation (for only the TIO8) newly added Description of “Count clock-dependent delay” along with Figure 10.4.2 newly added Figure 10.4.7, “Outline Diagram of TIO5-9 Clock/Enable Inputs”, altered Description of W= corrected P10-83 to Section 10.4 overall, (3), “Precautions on using TIO PWM output mode”, newly added Last item of Section 10.4.13. (2) added Figure 10.5.1 corrected Description of “Count clock-dependent delay” along with Figure 10.5.2 newly added P10-141 P11-6 P11-16 P11-36 Second paragraph of Section 10.6.7. (1) corrected Description added to Section 11.1.2 Note 1 added Conversion time for Comparator mode in Table 11.3.3 corrected Incorrect: Correct: 27 29 P11-39 P11-41, P11-42 “AD1CSTP” is deleted from the explanation of “Forcible termination during scan operation” in Section 11.14 Equations altered (6/8) REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P12-3 32171 Group User’s Manual Description Summary Baud rate for UART mode in Table 12.1.1 changed Before: 156K bits/sec After: 1.25M bits/sec Note in Section 12.2.3. (1) corrected Last paragraph of Section 12.2.8 changed Figure 12.4.1 corrected Note deleted Figure 12.6.3 corrected Note deleted P12-14 P12-24 P12-34 P12-42 P12-46 P12-53 Figure 12.7.1 corrected Note deleted P12-60 P13-9 P13-77 P15-16 P17-4 P17-6 P18-5 P19-13 P19-14 P21-5, P21-7 P21-9 P21-11 P21-18 Description in “Setting of Baud Rate (BRG) Regiser” partly deleted Notes and Explanation added for 13.2.1. (4), “RFST (Forcible Reset) bit” Figure 13.7.3 altered Figure 5.4.3 corrected Note 4 for Figure 17.2.3 corrected Note 2 for Figure 17.3.2 altered Figure 18.2.1 altered TAP states for (2) continuous access to the same datagister in Figure 19.4.5 corrected Note in Section 19.5 altered Note 3 changed Figures of ICCI-3V temperature characteristics newly added Descriptions of IIAN in the tables, Section 21.1.4 addedd (2) Electrical characteristics of each power supply pin when f(XIN)=10 MHz corrected to (4) Electrical characteristics of each power supply pin when f(XIN)= 8 MHz “A-D conversion characteristics (Referenced to AVCC=VREF=VCCE=3.3V, Ta=25°C, f(XIN) = 8.0 MHz Unless Otherwise Noted)” corrected to “A-D conversion characteristics (Referenced to AVCC=VREF=VCCE=3.3V, Ta = -40 to 85°C, f(XIN) = 8.0 MHz Unless Otherwise Noted)” Descriptions of IIAN in the tables, Section 21.2.4 added P21-19 P21-23 P21-25 P21-26 P21-27 P22-2 Maximum rated value for td(RTDCLKH-RTDRXD) corrected “tv(BCLKL-BHWL)” corrected to “td(BCLKL-D)” Parameter, “Byte enable delay time after write” corrected to “Valid Byte enable timer after write” Figure 21.3.1 altered Normal mode added to (1) Test conditions (7/8) REVISION HISTORY Rev. Date Page 3-2, 3-3 4-11 Note 3 altered 32171 Group User’s Manual Description Summary 2.00 Sep 19, 2003 Appendix Processing for Input/output ports in Table A3.1.1 alterd Appendix Last item of Appendix 4.8.6 added Appendix Last line of the 1st paragraph deleted 4-24 Appendix Description in (2), “Wiring of clock input/output pins”, altered 4-25 4-26 Figure A4.13.2 changed newly added Figure A4.13.7, “Exmple Wiring of the MOD0 and MOD1 Pins”, altered Appendix Description in (1), “Avoidance from large-current signal lines”, altered 4-29 Figure A4.13.7, “Example Wiring of Large-current Signal Lines”, changed Appendix (3), “Wiring of the VCNT pin”, and Figure A4.13.3, “Example Wiring of the VCNT Pin”, Appendix Figure A.4.13.8, “Example Wiring of Rapidly Level-changing Signal Lines”, changed 4-30 Appendix (3), “Protection against signal lines that are the source of strong noise”, and Figures 4-31,32 A4.13.9, “Example Processing of a Noise-laden Pin”, and A4.13.10, “Example Processing of Pins Adjacent to the Oscillator and VCNT Pins”, newly added (8/8) How to read internal I/O register tables ➀ Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. ➁ State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column ➂.) ➂ A t read: ... read enabled ? ... read disabled (read value invalid) 0 ... Read always as 0 1 ... Read always as 1 : Write enabled : Write enable conditionally (include some conditions at write) : Write disabled (Written value invalid) { A t write: - Not implemented in the shaded portion. 1 D0 1 Abit 2 Bbit 3 Cbit Registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes). 4 2 D 0 1 Bit name Not assigned. Abit (...................) 2 Bbit (...................) 3 Cbit (...................) 0: ----1: ----0: ----1: ----0: ----1: ----Function 6 P86DT D7 P87DT MOD0DT MOD1DT D 0 Bit Name MOD0DT (MOD0 data) 1 MOD1DT (MOD1 data) 2 P82DT (Port P82 data) 3 P83DT (Port P83 data) 4 P84DT (Port P84 data) 5 P85DT (Port P85 data) 6 P86DT (Port P86 data) 7 P87DT (Port P87 data) Function 0 : MOD0 pin = low 1 : MOD0 pin = high 0 : MOD1 pin = low 1 : MOD1 pin = high Depending on how the Port Direction Register is set • When direction bit = 0 (input mode) 0: Port input pin = low 1: Port input pin = high • When direction bit = 1 (output mode) 0: Port output latch = low 1: Port output latch = high — R W — 6-23 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Enter one of the following modes: • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode • External extension mode + flash E/W enable mode FMOD(H'0080 07E0) FPMOD P8DATA(H'0080 0708) MOD0DT MOD1DT MOD0, 1 FP pin levels checked OK NO END Transfer E/W program to internal RAM in each mode Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 0 Switched to flash E/W program Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 1 1 µs wait (by hardware timer or software timer) Execute flash E/W command and various read commands (Note 1) Jump to flash memory or apply reset Switched to normal mode END Note 1: For details about each command, refer to Section 6.5.3, "Programming Procedure to Internal Flash Memory." Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode 6-24 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.3 Programming Procedure to the Internal Flash Memory To program to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write/erase program that has already been transferred from the flash memory into the internal RAM. In flash E/W enable mode, no data can be read out from the internal flash memory as in normal mode, so you cannot execute a program that exists in the internal flash memory. Therefore, the flash write/erase program must be prepared in the internal RAM before entering flash E/W enable mode. (Once you've entered flash E/W enable mode, you cannot use any command except flash commands to access the flash memory.) To access the internal flash memory in flash memory E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash memory E/W enable mode. Note: • During flash E/W enable mode, the flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash Memory E/W Enable Mode Command Name Read Array command Page Program command Lock Bit Program command Block Erase command Erase All Unlock Block command Read Status Register command Clear Status Register command Read Lock Bit Status command Verify command (Note1 - 4) Issued Command Data H'FFFF H'4141 H'7777 H'2020 H'A7A7 H'7070 H'5050 H'7171 H'D0D0 Note 1: This command is used in conjunction with Lock Bit Program, Block Erase, and Erase All Unlock Block operations. Note 2: Always issue this command successively after the Lock Bit Program, Block Erase, or Erase All Unlock Block command. Note 3: If the Read Array command (H’FFFF) is issued after the Lock Bit Program, Block Erase, or Erase All Unlock Block command, each of those preceding commands is canceled. Note 4: If other than the Verify command (H’D0D0) and Read Array command (H’FFFF) are issued after the Lock Bit Program, Block Erase, or Erase All Unlock Block command, each of those preceding commands terminates in an error without ever being executed. 6-25 32171 Group User's Manual (Rev.2.00) 6 (1) Read Array command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Read mode is entered by writing command data H'FFFF to any address of the internal flash memory. Then read the flash memory address you want to read out, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. (2) Page Program command Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write. With the Page Program command, you cannot program to the protected blocks. Page Program is automatically performed by the internal control circuit, and the completion of programming can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, the next programming can not be performed. (3) Lock Bit Program command Flash memory can be protected against program/erase one block at a time. The Lock Bit Program command is provided for protecting memory blocks. Write the Lock Bit Program command data H'7777 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the block you want to protect, and this memory block is protected against program/erase. To remove protection, disable lock bit-effectuated protection using the Flash Control Register 2 (FCNT2) FPROT bit (see Section 6.4.3, "Flash Control Registers") and erase the block whose protection you want to remove. (The content of this memory block is also erased.) The tables 6.5.3 to 6.5.5 list the target blocks and their specified addresses when writing the Verify command data. 6-26 32171 Group User's Manual (Rev.2.00) 6 Target Block 0 1 2 3 4 5 6 7 8 9 10 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.3 M32171F4 Target Blocks and Specified Addresses Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE Table 6.5.4 M32171F3 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE Table 6.5.5 M32171F2 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE 6-27 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F4's Internal Flash Memory Area (512KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF H'0004 0000 64KB H'0004 FFFF H'0005 0000 64KB H'0005 FFFF H'0006 0000 64KB H'0006 FFFF H'0007 0000 64KB H'0007 FFFF Block 10 Block 9 Block 8 Block 7 Even blocks Block 6 Block 5 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB Block 4 Figure 6.5.7 Block Configuration of the M32171F4 Flash Memory 6-28 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F3’s Internal Flash Memory Area (384KB) H’0000 0000 H’0000 3FFF H’0000 4000 H’0000 5FFF H’0000 6000 H’0000 7FFF H’0000 8000 H’0000 FFFF H’0001 0000 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H’0001 FFFF H’0002 0000 64KB H’0002 FFFF H’0003 0000 64KB H’0003 FFFF H’0004 0000 64KB H’0004 FFFF H’0005 0000 64KB H’0005 FFFF Block 4 Block 5 Even blocks Block 6 Block 7 Block 8 Figure 6.5.8 Block Configuration of the M32171F3 Flash Memory 6-29 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F2's Internal Flash Memory Area (256KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF Block 4 Block 5 Even blocks Block 6 Figure 6.5.9 Block Configuration of the M32171F2 Flash Memory 6-30 32171 Group User's Manual (Rev.2.00) 6 (4) Block Erase command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to erase (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"). The content of this memory block is erased. With the Block Erase command, you cannot erase the protected blocks. Block Erase is automatically performed by the internal control circuit, and the completion of Block Erase can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, you cannot erase the next block. (5) Erase All Unlock Block command The Erase All Unlock Block command erases all memory blocks that are not protected. To erase all unlock blocks, write the command data H'A7A7 to any address of the internal flash memory. Next, write the command data H'D0D0 to any address of the internal flash memory, and all of unprotected memory blocks are erased. (6) Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory write or erase operation has terminated normally or not. To read Flash Status Register 2, write the command data H'7070 to any address of the internal flash memory. Next, read any address of the internal flash memory, and the content of Flash Status Register 2 (FSTAT2) is read out. (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to 0. Write the command data H'5050 to any address of the internal flash memory, and Flash Status Register 2 is cleared to 0. If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) bit is set to 1, you cannot perform the next program or erase operation unless ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) is cleared to 0. 6-31 32171 Group User's Manual (Rev.2.00) 6 (8) Read Lock Bit Status command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory. Next, read the last even address of the block you want to check (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"), and the data you read shows whether or not the target block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit of the data you read are 0s, it means that the target memory block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit are 1s, it means that the target memory block is not protected. s Lock Bit Status Register (FLBST) FLBST0 FLBST1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D 0 1 Bit Name No functions assigned FLBST0 (Lock bit 0) 2-8 9 No functions assigned FLBST1 (Lock bit 1) 0 : Protected 1 : Not protected (Same content as FLBST0 is output.) 10 - 15 No functions assigned ? — 0 : Protected 1 : Not protected ? — — Function R ? W — — The Lock Bit Status Register is a read-only register, which contains said lock bits independently for each block. 6-32 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command (H'A7A7) to erase the memory block you want to unprotect. This is the only way to unprotect a memory block. You cannot set the lock bit alone to 1. c) Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit. (9) Execution flow of each command The diagrams below show an execution flow of each command. START Write Read Array command (H'FFFF) to any address of internal flash memory Read the internal flash memory address you want to read END Figure 6.5.10 Read Array 6-33 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Page Program command (H'4141) to any address of internal flash memory. Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address. NO Programmed for one page ? YES Written to the internal flash memory by Page Program (Note 2) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES Read any address of internal flash memory to check for program error. (Note 3) TIME OUT ? 0.5s YES Forcibly terminated NO Last address ? YES NO Go to next page END Note 1: Start writing from the beginning of a 256-byte boundary of the flash memory (lower address H'00). Note 2: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 3: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.11 Page Program 6-34 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 0.5s Read any address of internal flash memory to check for program error. (Note 2) YES Forcibly terminated NO END Note 1: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.12 Lock Bit Program 6-35 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 1s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.13 Block Erase 6-36 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 10s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.14 Erase All Unlock Block 6-37 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any address of internal flash memory. END Figure 6.5.15 Read Status Register START Write Clear Status command (H'5050) to any address of internal flash memory. END Figure 6.5.16 Clear Status Register START Write Read Lock Bit Status command (H'7171) to any address of internal flash memory. Read the last even address of the block whose status you want to read. END Figure 6.5.17 Read Lock Bit Status Register 6-38 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.4 Flash Program Time (for Reference) The time required for programming to the internal flash memory is shown below for your reference. (1) M32171F4 a) Transfer time by SIO (for a transfer data size of 512 KB) . 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 512 KB = 100.1 [s] . b) Flash program time . 512 KB/256-byte block × 8 ms = 16.4 [s] . c) Erase time (entire area) . 50 ms × number of blocks = 550 [ms] . d) Total flash program time (entire 512 KB area) • When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 101 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: . . b + c = 17 [s] (2) M32171F3 a) Transfer time by SIO (for a transfer data size of 384 KB) . . 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 384 KB = 75.1 [s] b) Flash program time . 384 KB/256-byte block × 8 ms = 12.3 [s] . c) Erase time (entire area) . 50 ms × number of blocks = 450 [ms] . d) Total flash program time (entire 384 KB area) • When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 76 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: . . b + c = 13 [s] 6-39 32171 Group User's Manual (Rev.2.00) 6 (3) M32171F2 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory a) Transfer time by SIO (for a transfer data size of 256 KB) . 1/57600 bps ¥ 1 (frame) ¥ 11 (number of transfer bits) ¥ 256 KB = 50.1 [s] . b) Flash program time 256 KB/256-byte block ¥ 8 ms .. 8.2 [s] = c) Erase time (entire area) . 50 ms ¥ number of blocks = 350 [ms] . d) Total flash program time (entire 256 KB area) • When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 50.5 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: = b + c .. 8.6 [s] 6-40 32171 Group User's Manual (Rev.2.00) 6 6.6 Boot ROM The table below shows boot memory specifications of the 32171. Table 6.6.1 Boot Memory Specifications Item Capacity Location address Wait insertion Internal bus connection Read Specification 8 Kbytes H'8000 0000 - H'8000 1FFF INTERNAL MEMORY 6.6 Boot ROM Operates with no wait states (with 40 MHz internal CPU memory clock) Connected by 32-bit bus Can only be read when FP = 1, MOD0 = 1, and MOD1 = 0. When read in other modes, indeterminate values are read out. Cannot be accessed for write. Other Because the boot ROM area is a reserved area that can only be used in boot mode, the program cannot be modified. 6-41 32171 Group User's Manual (Rev.2.00) 6 6.7 Virtual-Flash Emulation Function INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can map up to two 4-Kbyte blocks of internal RAM beginning with address H’0080 6000 into one of 4-Kbyte areas (S banks) of the internal flash memory. This capability is referred to as the “virtual-flash emulation” function. This function allows the data located in an 8-Kbyte block or one or two 4-Kbyte blocks of the internal RAM to be switched for use to or from the L or S bank of flash memory specified by the Virtual-Flash Bank Register. Therefore, applications that require changes of data during program operation can have data dynamically changed using 8 or 4 Kbytes of RAM area. The RAM used for virtual-flash emulation can be accessed for read and write from both the internal RAM and the internal flash memory areas. When this function is used in combination with the internal Real Time Debugger (RTD), the data tables created in the internal flash memory can be referenced or rewritten from outside, thus facilitating data table tuning. Before programming to the internal flash memory, always be sure to terminate this virtualflash emulation mode. H'0080 4000 RAM bank L block 0 (FELBANK0) 8Kbytes H'0080 6000 RAM bank S block 0 (FESBANK0) 4Kbytes RAM bank S block 1 (FESBANK1) 4Kbytes H'0080 7000 H'0080 7FFF Figure 6.7.1 Internal RAM Bank Configuration of the 32171 6-42 32171 Group User's Manual (Rev.2.00) 6 6.7.1 Virtual-Flash Emulation Areas INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The following shows the areas effective for the virtual-flash emulation function. Select one of 8-Kbyte blocks or L banks of flash memory using the Virtual-Flash L Bank Register (FELBANK0) (by setting the seven address bits A12–A18 of the start address of the desired L bank in the Virtual-Flash L Bank Register LBANKAD bits). Then set the Virtual-Flash L Bank Register MODENL bit (MODENL0 bit) to 1. The selected L bank area can be rewritten with the 8-Kbyte content of the internal RAM beginning with its start address. Also, select one or two of 4-Kbyte blocks or S banks of flash memory using the Virtual-Flash S Bank Registers (FESBANK0 and FESBANK1) (by setting the eight address bits A12–A19 of the start address of each desired S bank in the Virtual-Flash S Bank Register SBANKAD bits). Then set the Virtual-Flash S Bank Register MODENS0 and MODENS1 bits to 1. The selected S bank areas can be replaced with 4 Kbytes of the internal RAM, for up to two blocks, beginning with the address H’0080 6000. In this way, one 8-Kbyte block or L bank and two 4-Kbyte blocks or S banks for up to a total of three banks can be selected. Notes: • If the virtual-flash emulation enable bit is enabled after setting the same bank area in multiple virtual-flash bank registers, the corresponding internal RAM area (8 or 4 Kbytes) is allocated in order of priority FELBANK0 > FESBANK0 > FESBANK1. • During virtual-flash emulation mode, RAM can be accessed for read and write from the internal RAM area and virtual-flash setup area. • When performing virtual-flash read after setting Flash Control Register 1's Virtual-Flash Emmulation Mode bit to 1, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the said bit to 1. • Before performing virtual-flash read after setting the Virtual-flash Bank Register(L Bank and S Bank Registers)’s virtual-flash emulation enable and bank address bits, be sure to insert wait states equal to or greater than three CPU clock periods. 6-43 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) 8Kbytes 4Kbytes 4Kbytes H'0080 4000 H'0007 C000 H'0007 E000 L bank 62 (8Kbytes) L bank 63 (8Kbytes) Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.2 Virtual-Flash Emulation Areas of the M32171F4 Divided in Units of 8 Kbytes H’0000 0000 H’0000 1000 H’0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) 8Kbytes 4Kbytes 4Kbytes H’0080 4000 H’0080 6000 H’0080 7000 H’0007 E000 H’0007 F000 S bank 126 (4Kbytes) S bank 127 (4Kbytes) Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0,1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.3 Virtual-Flash Emulation Areas of the M32171F4 Divided in Units of 4 Kbytes 6-44 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) 8Kbytes 4Kbytes 4Kbytes H'0080 4000 H'0005 C000 H'0005 E000 L bank 46 (8Kbytes) L bank 47 (8Kbytes) Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.4 Virtual-Flash Emulation Areas of the M32171F3 Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) 8Kbytes 4Kbytes 4Kbytes H'0080 4000 H'0080 6000 H'0080 7000 H'0005 E000 H'0005 F000 S bank 94 (4Kbytes) S bank 95 (4Kbytes) Notea: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0,1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.5 Virtual-Flash Emulation Areas of the M32171F3 Divided in Units of 4 Kbytes 6-45 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) 8Kbytes 4Kbytes 4Kbytes H'0080 4000 H'0003 C000 H'0003 E000 L bank 30 (8Kbytes) L bank 31 (8Kbytes) Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.6 Virtual-Flash Emulation Areas of the M32171F2 Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) 8Kbytes 4Kbytes 4Kbytes H'0080 4000 H'0080 6000 H'0080 7000 H'0003 E000 H'0003 F000 S bank 62 (4Kbytes) S bank 63 (4Kbytes) Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. • When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0, 1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtualflash memory areas. Figure 6.7.7 Virtual-Flash Emulation Areas of the M32171F2 Divided in Units of 4 Kbytes 6-46 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 62 L bank 63 H'0007 C000 H'0007 E000 H'7C H'7E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.8 Values Set in the M32171F4's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 126 S bank 127 H'0007 E000 H'0007 F000 H'7E H'7F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.9 Values Set in the M32171F4's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-47 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 46 L bank 47 H'0005 C000 H'0005 E000 H'5C H'5E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.10 Values Set in the M32171F3's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 94 S bank 95 H'0005 E000 H'0005 F000 H'5E H'5F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.11 Values Set in the M32171F3's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-48 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 30 L bank 31 H'0003 C000 H'0003 E000 H'3C H'3E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.12 Values Set in the M32171F2's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 62 S bank 63 H'0003 E000 H'0003 F000 H'3E H'3F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.13 Values Set in the M32171F2's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-49 32171 Group User's Manual (Rev.2.00) 6 6.7.2 Entering Virtual Flash Emulation Mode INTERNAL MEMORY 6.7 Virtual Flash Emulation Function To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function. Even during virtual-flash emulation mode, the internal RAM area (H’0080 4000 through H’0080 7FFF) can be accessed as internal RAM. Setup start Write flash data to RAM Go to Virtual Flash Emulation Mode FEMMOD ← 1 Set RAM location address in Virtual Flash Bank Register LBANKAD ← Address A12-A18 SBANKAD ← Address A12-A19 Enable Virtual Flash Emulation Function MODENL ← 1 MODENS ← 1 End of Setting Figure 6.7.14 Virtual-flash Emulation Mode Sequence 6-50 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.3 Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx Initial value Replace area RAM block 0 RAM block 1 Data write to RAM0 (2) Program operation using RAM block 0 Flash Replace Bank xx Initial value RAM block 0 Bank xx specified RAM block 0 RAM block 1 Data write to RAM1 (3) Program operation changed from RAM block 0 to RAM block 1 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified (settings invalid) Bank xx specified RAM block 0 RAM block 1 Figure 6.7.15 Application Example of Virtual Flash Emulation (1/2) 6-51 32171 Group User's Manual (Rev.2.00) 6 (4) Program operation using RAM block 1 Flash INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 RAM block 1 Data write to RAM0 (5) Program operation changed from RAM block 1 to RAM block 0 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified (settings invalid) Bank xx specified RAM block 0 RAM block 1 (6) Go to item (2) NOTE : valid area Figure 6.7.16 Application Example of Virtual Flash Emulation (2/2) 6-52 32171 Group User's Manual (Rev.2.00) 6 6.8 Connecting to A Serial Programmer INTERNAL MEMORY 6.8 Connecting to A Serial Programmer When you reprogram the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32171 shown below to make them suitable for the serial programmer. Table 6.8.1 Processing the 32171 Pins when Using a Serial Programmer Pin Name SCLKI1 RXD1 Pin Number 71 70 Function Transfer clock input Serial data input (receive data) Serial data output (transmit data) Transmit/receive enable output Flash memory protect Operation mode 0 Operation mode 1 Reset Clock input Clock output PLL circuit control input PLL circuit power supply PLL circuit ground A-D converter reference voltage input Remark Need to be pulled high Need to be pulled high TXD1 P84 FP MOD0 MOD1 RESET XIN XOUT VCNT OSC-VCC OSC-VSS VREF0 AVCC0 AVSS0 FVCC VDD VCCE VCCI VSS 69 68 94 92 93 91 4 5 7 6 3 42 43 60 73 108 20, 65, 95, 132 61, 123, 137 21, 62, 72, 96, 138 Need to be pulled high Connect to ground Connect to 3.3 V power supply Connect to ground Connect to 5 V power supply Connect to 5 V power supply Connect to ground Connect to 3.3 V power supply Connect to 3.3 V power supply Analog power supply Analog ground Flash memory power supply RAM backup power supply 5 V power supply 3.3 V power supply Ground Note: All other pins do not need to be processed. 6-53 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer programs to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur. If the system uses any 32171 pins which will connect to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H'0000 0084 through H'0000 0093 as an area to check ID for flash memory protection. User system circuit board Connects to 5 V power supply AVCC0 VCCE VREF0 Connects to 3.3 V power supply FVCC Connects to 5 V power supply VCCI OSC-VCC VDD Various signals on flash programmer 5V(Input) RxD(Input) TxD(Output) SCLKO(Output) BUSY(Input) MOD0(Output) FP(Output) RESET(Output) GND(Output) P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET VSS AVSS0 OSC-VSS To system circuit about 2KΩ MOD1 JTRST Connector Set microcomputer operating conditions XIN XOUT VCNT 32171 Notes: • Turn on the power to the user system before you program to the flash memory. • If the system circuit uses P84-P87, consideration must be taken for connection of a serial programmer. • P64/SBI must be fixed high or low to ensure that interrupts will not be generated. • The pullup resistances of P84, P86, and P87 must be set to suit system design conditions. • The typical pullup resistances of P84, P86, and P87 are 4.7 to 10 kΩ. • All other ports, whether high or low, do not affect flash memory programming. Figure 6.8.1 Pin Connection Diagram 6-54 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.9 Internal Flash Memory Protect Functions 6.9 Internal Flash Memory Protect Functions The 32171’s internal flash memory has the following four protect functions to prevent unintended reprogramming by an erratic operation or unauthorized copying or reprogramming of its contents. (1) Flash memory protect ID When using flash memory reprogramming tools such as a general-purpose serial programmer or an emulator, the ID entered from the keyboard is checked against the flash memory’s internal ID. In no case can reprogramming be executed unless the correct ID is entered. (For some tools, erasing of the entire area only can be executed.) (2) Protection by FP pin The flash memory is protected in hardware against E/W by pulling the FP (Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in a flash write program, the flash memory can also be protected in software. For systems that do not require protection by external pin settings, holding the FP pin high will help to simplify operation while reprogramming the flash memory. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered unless Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to 1. Furthermore, the FENTRY bit can only be set to 1 by writing 0 and 1 in succession while the FP pin is high. (4) Protection by a lock bit Each block of flash memory has a lock bit, so that any memory block can be protected against E/W by setting this bit to 0. 6-55 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.10 Precautions to Be Taken When Reprogramming Flash Memory 6.10 Precautions to Be Taken When Reprogramming Flash Memory The following describes precautions to be taken when you reprogram the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. • When reprogramming the flash memory, a high voltage is generated inside the chip. Because this high voltage could cause the chip to break down, be careful about mode pin and power supply management not to move from one mode to another while reprogramming. • If the system uses any pin that is to be used by a general-purpose reprogramming tool, take appropriate measures to prevent adverse effects when connecting the tool. • If flash memory protection is needed when using a general-purpose reprogramming tool, set any ID in the flash memory protect ID check area (H’0000 0084–H’0000 0093). • If flash memory protection is not needed when using a general-purpose reprogramming tool, set H’FF in the entire flash memory protect ID check area (H’0000 0084–H’0000 0093). • Before using a reset by Flash Control Register 4 (FCNT4)’s FRESET bit to clear each error status in Flash Status Register 2 (FSTAT2) (initialized to H’80), check to see that Flash Status Register 1 (FSTAT1)’s FSTAT bit = 1 (Ready). • Before changing Flash Control Register 1 (FCNT1)’s FENTRY bit from 1 to 0, check to see that Flash Status Register 1 (FSTAT1)’s FSTAT bit = 1 (Ready) or Flash Status Register 2 (FSTAT2)’s FBUSY bit = 1 (Ready). • If Flash Control Register 1 (FCNT1)’s FENTRY bit = 1 and Flash Status Register 1 (FSTAT1)’s FSTAT bit = 0 (Busy) or Flash Status Register 2 (FSTAT2)’s FBUSY bit = 0 (program/erase in progress), do not clear the FENTRY bit. 6-56 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State after Exiting Reset 7.4 Things To Be Considered after Exiting Reset 7 7.1 Outline of Reset _____ RESET 7.1 Outline of Reset The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out _____ of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry. 7.2 Reset Operation 7.2.1 Reset at Power-on _____ When powering on the device, hold the RESET input low until its internal multiply-by-4 clock generator becomes oscillating stably. 7.2.2 Reset during Operation _____ To reset the device during operation, hold the RESET input low for more than four clock periods of XIN signal. 7.2.3 Reset Vector Relocation during Flash Reprogramming When placed in boot mode, the reset vector entry address is moved to the start address of the boot program space (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." 7-2 32171 Group User's Manual (Rev.2.00) 7 7.3 Internal State after Exiting Reset RESET 7.3 Internal State after Exiting Reset The table below lists the register state of the device after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described. Table 7.3.1 Internal State after Exiting Reset Register PSW CBR SPI SPU BPC PC R0–R15 (CR0) (CR1) (CR2) (CR3) (CR6) State after Exiting Reset B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = indeterminate) H'0000 0000 (C bit = 0) Indeterminate Indeterminate Indeterminate H'0000 0000 (Executed beginning with address H'0000 0000) (Note 1) Indeterminate ACC (accumulator) Indeterminate RAM Indeterminate at power-on reset (However, if the device is reset and placed out of reset while the VDD pin has 2.0 V to 3.6 V being applied to it, the RAM content before a reset is retained.) Note 1: When in boot mode, this changes to the start address of the boot program space (H'8000 0000). 7-3 32171 Group User's Manual (Rev.2.00) 7 RESET 7.3 Internal State after Exiting Reset The pins that were set for input when reset go to a high-impedance state (Hi-Z). Here, “when reset” means that the RESET# pin input is held low (the device being reset) and is released back high (the device being placed out of reset). Table 7.3.2 Pin Status When Reset (1/4) Function PIN NO. 1 2 3 4 5 6 7 8 Pin Name Port P221/CRX (Note 1) P225/A12 OSC-VSS XIN XOUT OSC-VCC VCNT P30/A15 P221 P225 P30 Other than Other than port port CRX A12 OSC-VSS XIN XOUT OSC-VCC VCNT A15 Input/output Input Condition Pin status when reset function Input/output Status during Status after exiting reset reset P221 Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Hi-z Hi-z Hi-z Indeterminate XOUT P225 During single-chip mode Input/output During external extension or A12 processor mode OSC-VSS Input Output During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode XIN XOUT OSC-VCC VCNT P30 A15 P31 A16 P32 A17 P33 A18 P34 A19 P35 A20 P36 A21 P37 A22 P20 A23 P21 A24 P22 A25 P23 A26 VCCE VSS P24 A27 P25 A28 P26 A29 P27 A30 P00 DB0 9 P31/A16 P31 A16 - 10 P32/A17 P32 A17 - 11 P33/A18 P33 A18 - 12 P34/A19 P34 A19 - 13 P35/A20 P35 A20 - 14 P36/A21 P36 A21 - 15 P37/A22 P37 A22 - 16 P20/A23 P20 A23 - 17 P21/A24 P21 A24 - 18 P22/A25 P22 A25 - 19 20 21 22 P23/A26 VCCE VSS P24/A27 P23 P24 A26 VCCE VSS A27 - 23 P25/A28 P25 A28 - 24 P26/A29 P26 A29 - 25 P27/A30 P27 A30 - 26 P00/DB0 P00 DB0 - Note 1: P221 is used exclusively for CAN input 7-4 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.3 Pin Status When Reset (2/4) Pin NO. Pin Name Port P01 Function Other than Other than Input/output port port DB1 - RESET 7.3 Internal State after Exiting Reset Pin status when reset Condition Function Input/output Status during Status after exiting reset reset P01 DB1 P02 DB2 P03 DB3 P04 DB4 P05 DB5 P06 DB6 P07 DB7 P10 DB8 P11 DB9 P12 DB10 P13 DB11 P14 DB12 P15 DB13 P16 DB14 P17 DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - 27 P01/DB1 28 P02/DB2 P02 DB2 - 29 P03/DB3 P03 DB3 - 30 P04/DB4 P04 DB4 - 31 P05/DB5 P05 DB5 - 32 P06/DB6 P06 DB6 - 33 P07/DB7 P07 DB7 - 34 P10/DB8 P10 DB8 - 35 P11/DB9 P11 DB9 - 36 P12/DB10 P12 DB10 - 37 P13/DB11 P13 DB11 - 38 P14/DB12 P14 DB12 - 39 P15/DB13 P15 DB13 - 40 P16/DB14 P16 DB14 - 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 P17/DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI P17 - DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI - During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input - 7-5 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.4 Pin Status When Reset (3/4) Function Pin NO. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 VSS P174/TXD2 P175/RXD2 VCCE P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS FVCC P61 P62 P63 P64/SBI (Note 1) P70/BCLK/WR P71/WAIT P72/HREQ P73/HACK P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK P93/TO16 P94/TO17 P95/TO18 P96/TO19 P97/TO20 RESET MOD0 MOD1 FP VCCE VSS P110/TO0 P111/TO1 Pin Name Port P174 P175 P82 P83 P84 P85 P86 P87 P61 P62 P63 P64 P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 P103 P104 P105 P106 P107 P124 P125 Other than Other than port port VSS TXD2 RXD2 VCCE TXD0 RXD0 SCLKI0 TXD1 RXD1 SCLKI1 VSS FVCC SBI BCLK WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK TO16 TO17 TO18 TO19 TO20 RESET MOD0 MOD1 FP VCCE VSS TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO8 TO9 TO10 VDD JTMS JTCK JTRST JTDO JTDI TO11 TO12 TO13 TO14 TO15 TCLK0 TCLK1 ______ RESET 7.3 Internal State after Exiting Reset Pin status when reset Input/output Input/output Input/output Condition Function Input/output Status during Status after reset exiting reset VSS P174 P175 VCCE P82 P83 P84 P85 P86 P87 VSS FVCC P61 P62 P63 SBI P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 RESET MOD0 MOD1 FP VCCE VSS P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 VDD JTMS JTCK JTRST JTDO JTDI P103 P104 P105 P106 P107 P124 P125 input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input Output input input input input input input input input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - Input/output Input/output SCLKO0 Input/output Input/output Input/output SCLKO1 Input/output Input/output WR Input/output Input/output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output 99 P112/TO2 100 P113/TO3 101 P114/TO4 102 P115/TO5 103 P116/TO6 104 P117/TO7 105 P100/TO8 106 P101/TO9 107 P102/TO10 108 VDD 109 JTMS (Note 2) 110 JTCK (Note 2) 111 JTRST (Note 2) 112 JTDO (Note 2) 113 JTDI (Note 2) 114 P103/TO11 115 P104/TO12 116 P105/TO13 117 P106/TO14 118 P107/TO15 119 P124/TCLK0 120 P125/TCLK1 Note 1: P64 is used exclusively for SBI input. ____________ Note 2: The JTCK, JTDI, JTDO, and JTMS pins are reset by the JTRST pin, and not by the RESET pin. All of these pins are placed in the high-impedance state while the JTRST pin input is held low. 7-6 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.5 Pin Status When Reset (4/4) Function Pin NO. Pin Name Port 121 P126/TCLK2 122 P127/TCLK3 123 VCCI 124 P130/TIN16 125 P131/TIN17 126 P132/TIN18 127 P133/TIN19 128 P134/TIN20 129 P135/TIN21 130 P136/TIN22 131 P137/TIN23 132 VCCE 133 P150/TIN0 134 P153/TIN3 135 P41/BLW/BLE P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P150 P153 P41 Other than Other than port Port TCLK2 TCLK3 VCCI TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 VCCE TIN0 TIN3 BLW BLE Input/output RESET 7.3 Internal State after Exiting Reset Pin status when reset Condition Function Input/output Status during Status after exiting reset reset P126 P127 VCCI P130 P131 P132 P133 P134 P135 P136 P137 VCCE P150 P153 P41 BLW P42 BHW VCCI VSS P43 RD P44 CS0 P45 CS1 P46 A13 P47 A14 P220 Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z Indeterminate Hi-z Indeterminate Hi-z Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode Input/output 136 P42/BHW/BHE 137 VCCI 138 VSS 139 P43/RD P42 P43 BHW VCCI VSS RD BHE - 140 P44/CS0 P44 CS0 - 141 P45/CS1 P45 CS1 - 142 P46/A13 P46 A13 - 143 P47/A14 144 P220/CTX P47 P220 A14 CTX - 7-7 32171 Group User's Manual (Rev.2.00) 7 RESET 7.4 Things To Be Considered after Exiting Reset 7.4 Things To Be Considered after Exiting Reset • Input/output ports After exiting reset, the 32171's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit. For details, refer to Section 8.3, "Input/ Output Port Related Registers." 7-8 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits 8.5 Precautions on Input/output Ports 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32171 has a total of 97 input/output ports consisting of P0–P13, P15, P17, and P22 (with P5 reserved for future use, however). These input/output ports can be used as input ports or output ports by setting up the direction registers. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or external extension bus signal line. Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. (If any internal peripheral I/O has still another function, you need to set the register provided for that peripheral I/O.) As a new function, the 32171 internally contains a Port Input Function Enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite. To use any ports in input mode, you need to set the Port Input Function Enable bit accordingly. The input/output ports are outlined in the next pages. 8-2 32171 Group User's Manual (Rev.2.00) 8 Item Number of ports Specification Total 97 lines P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P15 P17 : : : : : : : : : : : : : : : INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of Input/Output Ports P00 - P07 P10 - P17 P20 - P27 P30 - P37 P41 - P47 P61 - P64 P70 - P77 P82 - P87 P93 - P97 P100 - P107 P110 - P117 P124 - P127 P130 - P137 P150 , P153 P174, P175 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (4 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (2 lines) (2 lines) P22 : Port function P220, P221, P225 (3 lines) The input/output ports can individually be set for input or output mode using the Direction Control Register provided for each input/output port. (However, P64 is a ___ SBI input-only port and P221 is a CAN input-only port.) Pin function Shared with peripheral I/O or external extension signals to serve dual functions (or with two or more peripheral I/O functions to serve multiple functions) Pin function switchover P0 - P4, P225 : Depends on CPU operation mode (determined by setting MOD0 and MOD1 pins) P6 - P22 : As set by each input/output port's Operation Mode Register (However, peripheral I/O pin functions are selected by peripheral I/O registers.) Note: • P14, P16, and P18–P21 are nonexistent. 8-3 32171 Group User's Manual (Rev.2.00) 8 8.2 Selecting Pin Functions INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Each input/output port serves dual purposes along with other internal peripheral I/Os or external extension bus signal lines (or triple purposes along with multiple functions of peripheral I/O). Pin functions are selected according to the operation modes set or using the input/output port operation mode registers. When the selected CPU operation mode is external extension mode or processor mode, P0–P4 and P225 all are switched to signal pins for external access. The operation mode is determined depending on how MOD0 and MOD1 pins are set. (See the table below.) Table 8.2.1 CPU Operation Modes and P0–P4 and P225 Pin Functions MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCC Operation Mode Single-chip mode External extension mode External extension signal pin Processor mode Reserved (Use inhibited) — Pin Functions of P0-P4, P225 input/output port pin Note: • VCCE = 5 V or 3.3 V and VSS = GND. Ports P6–P13, P15, P17, and P22 (except for P64, P221, P225) have their pin functions switched between input/output ports and internal peripheral I/Os by setting up the input/output port operation mode registers. If any internal peripheral I/O has multiple functions, select the desired pin function using the relevant internal peripheral I/O register. Operation on FP and MOD1 pins during write to the internal flash memory does not affect the pin functions. 8-4 32171 Group User's Manual (Rev.2.00) 8 0 P0 P1 Settings of CPU operation mode P2 (Note 1) P3 P4 (Reserved) DB0 DB8 A23 A15 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 DB9 A24 A16 BLW/ BLE 2 DB2 DB10 A25 A17 BHW/ BHE 3 DB3 DB11 A26 A18 RD 4 DB4 DB12 A27 A19 CS0 5 DB5 DB13 A28 A20 CS1 6 DB6 DB14 A29 A21 A13 7 DB7 DB15 A30 A22 A14 P5 P6 P7 P8 P9 P10 P11 P12 TO8 TO0 TO9 TO1 TO10 TO2 BCLK/ WR (P61) WAIT (P62) HREQ TXD0 (P63) HACK RXD0 TO16 TO11 TO3 SBI RTDTXD RTDRXD RTDACK RTDCLK SCLKI0/ SCLKO0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 RXD1 TO19 TO14 TO6 TCLK2 TIN22 SCLKI1/ SCLKO1 TO17 TO12 TO4 TCLK0 TO20 TO15 TO7 TCLK3 TIN23 P13 Settings of input/ output port Operation Mode P14 Register P15 P16 P17 P18 P19 P20 P21 P22 TIN16 TIN17 TIN18 TIN19 TIN20 TIN0 TIN3 TXD2 RXD2 CTX CRX A12 (Note 2) Note 1: Pin functions are switched over by setting MOD0 and MOD1 pins. Note 2: Pin functions are switched over by setting MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. Note: • P14, P16, P18, P19, P20 and P21 have no functions assigned in M32171. Figure 8.2.1 Input/Output Ports and Pin Function Assignments 8-5 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The input/output port related registers consist of the Port Data Register, Port Direction Register, and Port Operation Mode Register. Of these, the Port Operation Mode Register is available for only P7–P22. Ports P0–P4 and P225 have their pin functions determined depending on CPU operation mode (selected by FP, MOD0, and MOD1 pins). Port P5 is reserved for future use. An input/output port related register map is shown below. Address +0 Address +1 Address D0 D7 D8 D15 H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P22 Data Register (P22DATA) H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P22 Direction Register (P22DIR) Blank addresses are reserved. Note : • The Data Register, Direction Register, and Operation Mode Register for P14, P16, and P18-P21 are not included. Figure 8.3.1 Input/Output Port Related Register Map (1/2) 8-6 32171 Group User's Manual (Rev.2.00) 8 Address H'0080 0744 H'0080 0746 D0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +0 Address D8 +1 Address D15 Port Input Function Enable Register (PIEN) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) H'0080 0748 P8 Operation Mode Register (P8MOD) H'0080 074A P10 Operation Mode Register (P10MOD) H'0080 074C P12 Operation Mode Register (P12MOD) H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 P22 Operation Mode Register (P22MOD) Blank addresses are reserved. 8.3.2 Input/Output Port Related Register Map (2/2) 8-7 32171 Group User's Manual (Rev.2.00) 8 8.3.1 Port Data Registers s P0 Data Register (P0DATA) s P1 Data Register (P1DATA) s P2 Data Register (P2DATA) s P3 Data Register (P3DATA) s P4 Data Register (P4DATA) s P6 Data Register (P6DATA) s P7 Data Register (P7DATA) s P8 Data Register (P8DATA) s P9 Data Register (P9DATA) s P10 Data Register (P10DATA) s P11 Data Register (P11DATA) s P12 Data Register (P12DATA) s P13 Data Register (P13DATA) s P15 Data Register (P15DATA) s P17 Data Register (P17DATA) s P22 Data Register (P22DATA) D0 ( D8 Pn0DT 1 9 Pn1DT 2 10 Pn2DT INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 3 11 Pn3DT 4 12 Pn4DT 5 13 Pn5DT 6 14 Pn6DT D7 D15 ) Pn7DT Note: • n = 0-13, 15, 17, and 22 (not including P5). D 0 (8) 1 (9) 2 (10) 3 (11) 4 (12) 5 (13) 6 (14) 7 (15) Bit Name Pn0DT (Port Pn0 data) Pn1DT (Port Pn1 data) Pn2DT (Port Pn2 data) Pn3DT (Port Pn3 data) Pn4DT (Port Pn4 data) Pn5DT (Port Pn5 data) Pn6DT (Port Pn6 data) Pn7DT (Port Pn7 data) Function Depending on how the Port Direction Register is set • When direction bit = 0 (input mode) 0: Port input pin = low 1: Port input pin = high • When direction bit = 1 (output mode) 0: Port output latch = low 1: Port output latch = high R W Notes: • The bits listed below have no functions assigned. (They show a 0 when read; writing to these bits has no effect.) P40, P60, P65-P67, P90-P92, P120-P123, P151, P152, P154-P157, P170-P173, P176, P177, P222P224, P226, P227 : • Port P64 is available for only input mode. Writing to P64DT bit has no effect. : • Ports P80 and P81 are available for only input mode. Writing to P80DT and P81DT bits has no effect. When read, P80 and P81 show the MOD0 and MOD1 pin levels, respectively. : • Port P221 is available for only input mode. Writing to P221DT bit has no effect. : • P14, P16, and P18-P21 do not have data registers. 8-8 32171 Group User's Manual (Rev.2.00) 8 8.3.2 Port Direction Registers INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P0 Direction Register (P0DIR) s P1 Direction Register (P1DIR) s P2 Direction Register (P2DIR) s P3 Direction Register (P3DIR) s P4 Direction Register (P4DIR) s P6 Direction Register (P6DIR) s P7 Direction Register (P7DIR) s P8 Direction Register (P8DIR) s P9 Direction Register (P9DIR) s P10 Direction Register (P10DIR) s P11 Direction Register (P11DIR) s P12 Direction Register (P12DIR) s P13 Direction Register (P13DIR) s P15 Direction Register (P15DIR) s P17 Direction Register (P17DIR) s P22 Direction Register (P22DIR) D0 ( D8 Pn0DIR 1 9 Pn1DIR 2 10 Pn2DIR 3 11 Pn3DIR 4 12 Pn4DIR 5 13 Pn5DIR 6 14 Pn6DIR D7 D15 ) Pn7DIR Note: • n = 0-13, 15, 17, and 22 (not including P5). D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 __ R W 1 : BCLK / WR 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK 8-10 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P8 Operation Mode Register (P8MOD) D 0, 1 2 Bit Name No functions assigned P82MOD (Port P82 operation mode) 3 P83MOD (Port P83 operation mode) 4 P84MOD (Port P84 operation mode) 5 P85MOD (Port P85 operation mode) 6 P86MOD (Port P86 operation mode) 7 P87MOD (Port P87 operation mode) Note : • Ports P80 and P81 are nonexistent. 0 : P82 1 : TXD0 0 : P83 1 : RXD0 0 : P84 1 : SCLKI0 / SCLKO0 0 : P85 1 : TXD1 0 : P86 1 : RXD1 0 : P87 1 : SCLKI1 / SCLKO1 Function R 0 W — 8-11 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P9 Operation Mode Register (P9MOD) D 8 - 10 11 Bit Name No functions assigned P93MOD (Port P93 operation mode) 12 P94MOD (Port P94 operation mode) 13 P95MOD (Port P95 operation mode) 14 P96MOD (Port P96 operation mode) 15 P97MOD (Port P97 operation mode) Note : • Ports P90 - P92 are nonexistent. 0 : P93 1 : TO16 0 : P94 1 : TO17 0 : P95 1 : TO18 0 : P96 1 : TO19 0 : P97 1 : TO20 Function R 0 W — 8-12 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P10 Operation Mode Register (P10MOD) D 0 Bit Name P100MOD (Port P100 operation mode) 1 P101MOD (Port P101 operation mode) 2 P102MOD (Port P102 operation mode) 3 P103MOD (Port P103 operation mode) 4 P104MOD (Port P104 operation mode) 5 P105MOD (Port P105 operation mode) 6 P106MOD (Port P106 operation mode) 7 P107MOD (Port P107 operation mode) Function 0 : P100 1 : TO8 0 : P101 1 : TO9 0 : P102 1 : TO10 0 : P103 1 : TO11 0 : P104 1 : TO12 0 : P105 1 : TO13 0 : P106 1 : TO14 0 : P107 1 : TO15 R W 8-13 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P11 Operation Mode Register (P11MOD) D 8 Bit Name P110MOD (Port P110 operation mode) 9 P111MOD (Port P111 operation mode) 10 P112MOD (Port P112 operation mode) 11 P113MOD (Port P113 operation mode) 12 P114MOD (Port P114 operation mode) 13 P115MOD (Port P115 operation mode) 14 P116MOD (Port P116 operation mode) 15 P117MOD (Port P117 operation mode) Function 0 : P110 1 : TO0 0 : P111 1 : TO1 0 : P112 1 : TO2 0 : P113 1 : TO3 0 : P114 1 : TO4 0 : P115 1 : TO5 0 : P116 1 : TO6 0 : P117 1 : TO7 R W 8-14 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P12 Operation Mode Register (P12MOD) D 0-3 4 Bit Name No functions assigned P124MOD (Port P124 operation mode) 5 P125MOD (Port P125 operation mode) 6 P126MOD (Port P126 operation mode) 7 P127MOD (Port P127 operation mode) Note : • Ports P120 - P123 are nonexistent. 0 : P124 1 : TCLK0 0 : P125 1 : TCLK1 0 : P126 1 : TCLK2 0 : P127 1 : TCLK3 Function R 0 W — 8-15 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P13 Operation Mode Register (P13MOD) D 8 Bit Name P130MOD (Port P130 operation mode) 9 P131MOD (Port P131 operation mode) 10 P132MOD (Port P132 operation mode) 11 P133MOD (Port P133 operation mode) 12 P134MOD (Port P134 operation mode) 13 P135MOD (Port P135 operation mode) 14 P136MOD (Port P136 operation mode) 15 P137MOD (Port P137 operation mode) Function 0 : P130 1 : TIN16 0 : P131 1 : TIN17 0 : P132 1 : TIN18 0 : P133 1 : TIN19 0 : P134 1 : TIN20 0 : P135 1 : TIN21 0 : P136 1 : TIN22 0 : P137 1 : TIN23 R W 8-16 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P15 Operation Mode Register (P15MOD) D 8 Bit Name P150MOD (Port P150 operation mode) 9, 10 11 No functions assigned P153MOD (Port P153 operation mode) 12 - 15 No functions assigned 0 : P153 1 : TIN3 0 – Function 0 : P150 1 : TIN0 0 – R W Note: • Ports P151, P152, and P154-157 are nonexistent. 8-17 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P17 Operation Mode Register (P17MOD) D 8 - 11 12 Bit Name No functions assigned P174MOD (Port P174 operation mode) 13 P175MOD (Port P175 operation mode) 14, 15 No functions assigned 0 : P174 1 : TXD2 0 : P175 1 : RXD2 0 — Function R 0 W — Note : • Ports P170-P173, and P176, P177 are nonexistent. 8-18 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P22 Operation Mode Register (P22MOD) D 0 Bit Name P220MOD (Port P220 operation mode) 1-4 5 No functions assigned P225MOD (Port P225 operation mode) 6-7 No functions assigned 0 : P225 1 : Use inhibited 0 — Function 0 : P220 1 : CTX 0 — R W Notes: • P221 is a CAN input-only pin. : • The pin function of P225 changes depending on how MOD0 and MOD1 pins are set. Also, because it has a debug event function, be careful when using this port. : • P222-224, P226, and P227 are nonexistent. 8-19 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s Port Input Function Enable Register (PIEN) D 8 - 14 15 Bit Name No functions assigned PIEN0 (Port input function enable bit) 0 : Disables input (to prevent current from flowing in) 1 : Enables input Function R 0 W — This register is provided to prevent current from flowing into the port input pin. Because after reset this register is set to disable input, it must be set to 1 before input can be processed. During boot mode, all pins shared with serial I/O function are enabled for input, so that when rewriting the flash memory via serial communication, you can set this register to 0 to prevent current from flowing in from any pins other than serial I/O function. The next page lists the pins that can be controlled by the Port Input Function Enable Register in each mode. 8-20 32171 Group User's Manual (Rev.2.00) 8 Mode Name INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Table 8.3.1 Controllable Pins by Port Function Enable Bit Controllable Pins P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 Single chip P70 - P77, P82 - P87, P93 - P97 P100 - P107, P110 - P117, P124 - P127 P130 - P137, P150, P153, P174, P175 P220, P225 P61 - P63, P70 - P77, P82 - P87 External extension Microprocessor P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137 P150, P153, P174, P175, P220 P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 Boot (single chip) P67, P70 - P77, P93 - P97 P100 - P107, P110 - P117, P124 - P127 P130 - P137, P150, P153, P220, P225 P00 - P07, P10 - P17 P20 - P27, P30 - P37 P41 - P47, P64, P221 P225, FP P64, P82 - P87 P174, P175, P221, FP Noncontrollable Pins P64, P221, FP 8-21 32171 Group User's Manual (Rev.2.00) 8 8.4 Port Peripheral Circuits INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) P20 - P27 (A23-A30) P30 - P37 (A15-A22) ___ ___ P41 (BLW / BLE) ___ ___ P42 (BHW / BHE) __ P43 (RD) ___ P44 (CS0) ___ P45 (CS1) P46 - P47 (A13-A14) P61 - P63 P225(A12) Direction register Data bus (DB0 - DB15) Port output latch Input function enable Note: • Although P00-07, P10-17, P20-27, P30-37, P41-47, and P225 serve as external bus interface control signal pins during external extension mode and processor mode, functional description is eliminated in this block diagram. Direction register P75 (RTDRXD) Data bus P77 (RTDCLK) (DB0 - DB15) P83 (RXD0) P86 (RXD1) P124 - P127 (TCLK0-TCLK3) P130 - P137 (TIN16-TIN23) P150, P153 (TIN0, TIN3) Peripheral P175 (RXD2) function input Port output latch Operation mode register Input function enable Notes: • :• denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : • The input capacitance of each pin is approximately 10 pF. Figure 8.4.1 Port Peripheral Circuit Diagram (1) 8-22 32171 Group User's Manual (Rev.2.00) 8 ___ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P64 (SBI) P221 / CRX Data bus (DB0 - DB15) SBI, CRX ____ P72 (HREQ) Data bus (DB0 - DB15) Direction register Port output latch Operation mode register HREQ Input function enable Notes: • :• denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : • The input capacitance of each pin is approximately 10 pF. Figure 8.4.2 Port Peripheral Circuit Diagram (2) 8-23 32171 Group User's Manual (Rev.2.00) 8 ____ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P71 (WAIT) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register WAIT Input function enable __ P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) P76 (RTDACK) P82 (TXD0) P85 (TXD1) P93 - P97 (TO16-TO20) P100 - P107 (TO8-TO15) P110 - P117 (TO0-TO7) P174 (TXD2) P220 (CTX) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register Peripheral function output Input function enable Notes: • :• denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : • The input capacitance of each pin is approximately 10 pF. Figure 8.4.3 Port Peripheral Circuit Diagram (3) 8-24 32171 Group User's Manual (Rev.2.00) 8 P84 (SCLKI0, SCLKO0) P87 (SCLKI1, SCLKO1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Direction register Data bus (DB0 - DB15) Port output latch Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function enable MOD0 MOD1 MOD0 , MOD1 FP FP _____ RESET XIN JTRST RESET, XIN, JTRST JTDI JTCK JTMS JTDI, JTCK, JTMS JTDO JTDO OSC-VCC VCCI VCCE VDD Notes: • :• OSC-VCC, VCCI, VCCE, VDD denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Figure 8.4.4 Port Peripheral Circuit Diagram (4) 8-25 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/output Ports 8.5 Precautions on Input/output Ports • When using the ports in output mode Because the Port Data Register values immediately after a reset are indeterminate, it is necessary that the initial value be written to the Port Data Register before setting the Port Direction Register for output. Conversely, if the Port Direction Register is set for output before writing to the Port Data Register, indeterminate values will be output for a while until the initial value is set in the Port Data Register. 8-26 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 9 DMAC 9.1 Outline of the DMAC 9.2 DMAC Related Registers 9.3 Functional Description of the DMAC 9.4 Precautions about the DMAC 9 9.1 Outline of the DMAC DMAC 9.1 Outline of the DMAC The 32171 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Number of channel Transfer request Description 10 channels • Software trigger • Request from internal peripheral I/Os: A-D converter, multijunction timer, or serial I/O (reception completed, transmit buffer empty) • Transfer operation can be cascaded between DMA channels (Note) 256 times Maximum number of times transferred Transferable address space • 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, between internal RAMs are supported 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination: • Address fixed • Address incremental • Ring buffered Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Priority is fixed) Transfer data size Transfer method Transfer mode Direction of transfer Channel priority Maximum transfer rate 13.3 Mbytes per second (with 20 MHz internal peripheral clock) Interrupt request Transfer area Group interrupt request can be generated when each transfer count register underflows. 64 Kbytes from H'0080 0000 to H'0080 FFFF (Transferable in the entire internal RAM/SFR area) Note: • Transfer operation can be cascaded between DMA channels as shown below. Completion of one transfer in channel 0 starts DMA transfer in channel 1 Completion of one transfer in channel 1 starts DMA transfer in channel 2 Completion of one transfer in channel 2 starts DMA transfer in channel 0 Completion of one transfer in channel 3 starts DMA transfer in channel 4 Completion of one transfer in channel 5 starts DMA transfer in channel 6 Completion of one transfer in channel 6 starts DMA transfer in channel 7 Completion of one transfer in channel 7 starts DMA transfer in channel 5 Completion of one transfer in channel 8 starts DMA transfer in channel 9 Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer in channel 5 9-2 32171 Group User's Manual (Rev.2.00) 9 Software start One DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) DMA request selector Source address register Destination address register Transfer count register udf Internal bus DMAC 9.1 Outline of the DMAC DMA channel 0 DMA channel 1 Software start MJT (output event bus 0) One DMA0 transfer completed DMA channel 2 Software start MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) DMA request selector Source Destination Transfer count udf Interrupt request DMA start Determination block Software start One DMA7 transfer completed All DMA0 transfers completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 5 DMA request selector Source Destination Transfer count udf Internal bus arbitration DMA channel 6 Software start Serial I/O1 (transmit buffer empty) One DMA5 transfer completed DMA channel 7 Software start Serial I/O2 (transmit buffer empty) One DMA6 transfer completed DMA channel 8 Software start MJT (input event bus 0) DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 9 Software start One DMA8 transfer completed DMA request selector Source Destination Transfer count DMA start Determination block udf Interrupt request Internal bus arbitration Figure 9.1.1 Block Diagram of the DMAC 9-3 32171 Group User's Manual (Rev.2.00) 9 Clock bus Input event bus 3210 3210 DMAC 9.1 Outline of the DMAC Output event bus 0123 AD0 completed TIO8-udf S DMA0 udf end udf end udf end udf end DMAIRQ0 S DMA1 DMAIRQ0 TIN18 S DMA2 DMAIRQ0 TIN0 SIO0-TXD SIO1-RXD S DMA3 DMAIRQ0 SIO0-RXD TIN19 SIO2-RXD S DMA4 udf DMAIRQ0 TIN20 S DMA5 udf end udf end udf end DMAIRQ1 SIO1-TXD S DMA6 DMAIRQ1 SIO2-TXD S DMA7 DMAIRQ1 S DMA8 udf end udf DMAIRQ1 S DMA9 DMAIRQ1 3210 3210 0123 Figure 9.1.2 Causes of DMAC Requests Connection Diagram 9-4 32171 Group User's Manual (Rev.2.00) 9 9.2 DMAC Related Registers DMAC 9.2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers. Address H'0080 0400 D0 +0 Address D7 D8 +1 Address DMA0-4 Interrupt Mask Register (DM04ITMK) D15 DMA0-4 Interrupt Request Status Register (DM04ITST) H'0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) Blank addresses are reserved. Note: • The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.1 DMAC Related Register Map (1/2) 9-5 32171 Group User's Manual (Rev.2.00) 9 Address H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA9 Channel Control Register (DM9CNT) DMA4 Channel Control Register (DM4CNT) DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D0 +0 Address DMA3 Channel Control Register (DM3CNT) D7 D8 +1 Address DMA3 Transfer Count Register (DM3TCT) D15 DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) Blank addresses are reserved. Note: • The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.2 DMAC Related Register Map (2/2) 9-6 32171 Group User's Manual (Rev.2.00) 9 9.2.1 DMA Channel Control Register s DMA0 Channel Control Register (DM0CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL0 (Selects DMA0 transfer mode) 1 TREQF0 (DMA0 transfer request flag) 2, 3 REQSL0 (Selects cause of DMA0 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start or one DMA2 transfer completed 01 : A-D0 conversion completed 10 : MJT (TIO8_udf) 11 : MJT (input event bus 2) 4 TENL0 (Enables DMA0 transfer) 5 TSZSL0 (Selects DMA0 transfer size) 6 SADSL0 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA0 source address direction) 1 : Incremental 7 DADSL0 (Selects DMA0 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-7 32171 Group User's Manual (Rev.2.00) 9 s DMA1 Channel Control Register (DM1CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL1 (Selects DMA1 transfer mode) 1 TREQF1 (DMA1 transfer request flag) 2, 3 REQSL1 (Selects cause of DMA1 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (output event bus 0) 10 : Use inhibited 11 : One DMA0 transfer completed 4 TENL1 (Enables DMA1 transfer) 5 TSZSL1 (Selects DMA1 transfer size) 6 SADSL1 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA1 source address direction) 1 : Incremental 7 DADSL1 (Selects DMA1 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-8 32171 Group User's Manual (Rev.2.00) 9 s DMA2 Channel Control Register (DM2CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL2 (Selects DMA2 transfer mode) 1 TREQF2 (DMA2 transfer request flag) 2, 3 REQSL2 (Selects cause of DMA2 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (output event bus 1) 10 : MJT (TIN18 input signal) 11 : One DMA1 transfer completed 4 TENL2 (Enables DMA2 transfer) 5 TSZSL2 (Selects DMA2 transfer size) 6 SADSL2 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA2 source address direction) 1 : Incremental 7 DADSL2 (Selects DMA2 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-9 32171 Group User's Manual (Rev.2.00) 9 s DMA3 Channel Control Register (DM3CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL3 (Selects DMA3 transfer mode) 1 TREQF3 (DMA3 transfer request flag) 2, 3 REQSL3 (Selects cause of DMA3 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O0 (transmit buffer empty) 10 : Serial I/O1 (reception completed) 11 : MJT (TIN0 input signal) 4 TENL3 (Enables DMA3 transfer) 5 TSZSL3 (Selects DMA3 transfer size) 6 SADSL3 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA3 source address direction) 1 : Incremental 7 DADSL3 (Selects DMA3 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-10 32171 Group User's Manual (Rev.2.00) 9 s DMA4 Channel Control Register (DM4CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL4 (Selects DMA4 transfer mode) 1 TREQF4 (DMA4 transfer request flag) 2, 3 REQSL4 (Selects cause of DMA4 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : One DMA3 transfer completed 10 : Serial I/O0 (reception completed) 11 : MJT (TIN19 input signal) 4 TENL4 (Enables DMA4 transfer) 5 TSZSL4 (Selects DMA4 transfer size) 6 SADSL4 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA4 source address direction) 1 : Incremental 7 DADSL4 (Selects DMA4 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-11 32171 Group User's Manual (Rev.2.00) 9 s DMA5 Channel Control Register (DM5CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL5 (Selects DMA5 transfer mode) 1 TREQF5 (DMA5 transfer request flag) 2, 3 REQSL5 (Selects cause of DMA5 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start or one DMA7 transfer completed 01 : All DMA0 transfers completed 10 : Serial I/O2 (reception completed) 11 : MJT (TIN20 input signal) 4 TENL5 (Enables DMA5 transfer) 5 TSZSL5 (Selects DMA5 transfer size) 6 SADSL5 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA5 source address direction) 1 : Incremental 7 DADSL5 (Selects DMA5 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-12 32171 Group User's Manual (Rev.2.00) 9 s DMA6 Channel Control Register (DM6CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL6 (Selects DMA6 transfer mode) 1 TREQF6 (DMA6 transfer request flag) 2, 3 REQSL6 (Selects cause of DMA6 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O1 (transmit buffer empty) 10 : Use inhibited 11 : One DMA5 transfer completed 4 TENL6 (Enables DMA6 transfer) 5 TSZSL6 (Selects DMA6 transfer size) 6 SADSL6 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA6 source address direction) 1 : Incremental 7 DADSL6 (Selects DMA6 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-13 32171 Group User's Manual (Rev.2.00) 9 s DMA7 Channel Control Register (DM7CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL7 (Selects DMA7 transfer mode) 1 TREQF7 (DMA7 transfer request flag) 2, 3 REQSL7 (Selects cause of DMA7 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O2 (transmit buffer empty) 10 : Use inhibited 11 : One DMA6 transfer completed 4 TENL7 (Enables DMA7 transfer) 5 TSZSL7 (Selects DMA7 transfer size) 6 SADSL7 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA7 source address direction) 1 : Incremental 7 DADSL7 (Selects DMA7 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-14 32171 Group User's Manual (Rev.2.00) 9 s DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL8 (Selects DMA8 transfer mode) 1 TREQF8 (DMA8 transfer request flag) 2, 3 REQSL8 (Selects cause of DMA8 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (input event bus 0) 10 : Use inhibited 11 : Use inhibited 4 TENL8 (Enables DMA8 transfer) 5 TSZSL8 (Selects DMA8 transfer size) 6 SADSL8 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA8 source address direction) 1 : Incremental 7 DADSL8 (Selects DMA8 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-15 32171 Group User's Manual (Rev.2.00) 9 s DMA9 Channel Control Register (DM9CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL9 (Selects DMA9 transfer mode) 1 TREQF9 (DMA9 transfer request flag) 2, 3 REQSL9 (Selects cause of DMA9 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Use inhibited 10 : Use inhibited 11 : One DMA8 transfer completed 4 TENL9 (Enables DMA9 transfer) 5 TSZSL9 (Selects DMA7 transfer size) 6 SADSL9 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA9 source address direction) 1 : Incremental 7 DADSL9 (Selects DMA9 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-16 32171 Group User's Manual (Rev.2.00) 9 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA transfer, and set the transfer size and the source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal mode or ring buffer mode. Normal mode is selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). No interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn transfer request flag) bit (D1) This flag is set to 1 when a DMA transfer request occurs. Reading this flag helps to know DMA transfer requests in each channel. The generated DMA request is cleared by writing a 0 to this bit. If you write a 1, the value you wrote is ignored and the bit retains its previous value. If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1, the next DMA transfer request is not accepted until the transfer under way in that channel is completed. (3) REQSLn (cause of DMAn request select) bits (D2, D3) These bits select the cause of DMA request in each DMA channel. (4) TENLn (DMAn transfer enable) bit (D4) Transfer is enabled by setting this bit to 1, so that the channel is ready for DMA transfer. Conversely, transfer is disabled by setting this bit to 0. However, if a transfer request has already been accepted, transfer in that channel is not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn transfer size select) bit (D5) This bit selects the number of bits to be transferred in one DMA transfer operation (unit of one transfer). The unit of one transfer is 16 bits when TSZSL = 0 or 8 bits when TSZSL = 1. (6) SADSLn (DMAn source address direction select) bit (D6) This bit selects the direction in which the source address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. (7) DADSLn (DAMn destination address direction select) bit (D7) This bit selects the direction in which the destination address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. 9-17 32171 Group User's Manual (Rev.2.00) 9 9.2.2 DMA Software Request Generation Registers s DMA0 Software Request Generation Register (DM0SRI) s DMA1 Software Request Generation Register (DM1SRI) s DMA2 Software Request Generation Register (DM2SRI) s DMA3 Software Request Generation Register (DM3SRI) s DMA4 Software Request Generation Register (DM4SRI) s DMA5 Software Request Generation Register (DM5SRI) s DMA6 Software Request Generation Register (DM6SRI) s DMA7 Software Request Generation Register (DM7SRI) s DMA8 Software Request Generation Register (DM8SRI) s DMA9 Software Request Generation Register (DM9SRI) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SRI - DM9SRI D 0 - 15 Bit Name DM0SRI - DM9SRI Function DMA transfer request is generated R ? W (Generates DMA software request) by writing any data Note: • This register can be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when "Software start" has been selected for the cause of DMA request. DM0SRI - DM9SRI (DMA software request generate) bit A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "Software" is selected as the cause of DMA transfer request (by setting the DMA Channel Control Register D2, D3 bits to "00"). 9-18 32171 Group User's Manual (Rev.2.00) 9 9.2.3 DMA Source Address Registers s DMA0 Source Address Register (DM0SA) s DMA1 Source Address Register (DM1SA) s DMA2 Source Address Register (DM2SA) s DMA3 Source Address Register (DM3SA) s DMA4 Source Address Register (DM4SA) s DMA5 Source Address Register (DM5SA) s DMA6 Source Address Register (DM6SA) s DMA7 Source Address Register (DM7SA) s DMA8 Source Address Register (DM8SA) s DMA9 Source Address Register (DM9SA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SA - DM9SA D 0 - 15 Bit Name DM0SA - DM9SA (DMA source address) Function A16-A31 of the source address (A0-A15 are fixed to H'0080) R W Note: • This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Source Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0SA-DM9SA (A16-A31 of the source address) By setting this register, specify the source address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the source address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the source address (with D0 corresponding to A16, and D15 corresponding to A31). 9-19 32171 Group User's Manual (Rev.2.00) 9 9.2.4 DMA Destination Address Registers s DMA0 Destination Address Register (DM0DA) s DMA1 Destination Address Register (DM1DA) s DMA2 Destination Address Register (DM2DA) s DMA3 Destination Address Register (DM3DA) s DMA4 Destination Address Register (DM4DA) s DMA5 Destination Address Register (DM5DA) s DMA6 Destination Address Register (DM6DA) s DMA7 Destination Address Register (DM7DA) s DMA8 Destination Address Register (DM8DA) s DMA9 Destination Address Register (DM9DA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0DA - DM9DA D 0 - 15 Bit Name DM0DA - DM9DA (DMA destination address) Function A16-A31 of the destination address (A0-A15 are fixed to H'0080) R W Note: • This register must always be accessed in halfwords. The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because access to this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same destination address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Destination Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0DA-DM9DA (A16-A31 of the destination address) By setting this register, specify the destination address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the destination address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the destination address (with D0 corresponding to A16, and D15 corresponding to A31). 9-20 32171 Group User's Manual (Rev.2.00) 9 9.2.5 DMA Transfer Count Registers s DMA0 Transfer Count Register (DM0TCT) s DMA1 Transfer Count Register (DM1TCT) s DMA2 Transfer Count Register (DM2TCT) s DMA3 Transfer Count Register (DM3TCT) s DMA4 Transfer Count Register (DM4TCT) s DMA5 Transfer Count Register (DM5TCT) s DMA6 Transfer Count Register (DM6TCT) s DMA7 Transfer Count Register (DM7TCT) s DMA8 Transfer Count Register (DM8TCT) s DMA9 Transfer Count Register (DM9TCT) D8 9 10 11 12 13 DMAC 9.2 DMAC Related Registers 14 D15 DM0TCT - DM9TCT D 8 - 15 Bit Name DM0TCT - DM9TCT (DMA transfer count) Function DMA transfer count (ignored during 32-channel ring buffer mode) R W The DMA Transfer Count Register is used to set the number of times data is transferred in each channel. However, the value in this register is ignored during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the value you get by reading this register is always the current value. (However, if you read this register in a cycle immediately after transfer, the value you get is the value that was in the count register before the transfer began.) When transfer finishes, this count register underflows, so that the read value you get is H'FF. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts. 9-21 32171 Group User's Manual (Rev.2.00) 9 9.2.6 DMA Interrupt Request Status Registers s DMA0-4 Interrupt Request Status Register (DM04ITST) DMAC 9.2 DMAC Related Registers D 0-2 3 4 5 6 7 W= Bit Name No functions assigned DMITST4 (DMA4 interrupt request status) DMITST3 (DMA3 interrupt request status) DMITST2 (DMA2 interrupt request status) DMITST1 (DMA1 interrupt request status) DMITST0 (DMA0 interrupt request status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt requested Function R 0 W — The DMA0-4 Interrupt Request Status Register lets you know the status of interrupt requests in channels 0-4. If the DMAn interrupt request status bit (n = 0 to 4) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 0 to 4) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: • The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "IREQ bit" of the DMA Interrupt Control Register(IDMA04CR) that the interrupt controller has. When writing to the DMA0-4 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-22 32171 Group User's Manual (Rev.2.00) 9 s DMA5-9 Interrupt Request Status Register (DM59ITST) DMAC 9.2 DMAC Related Registers D 0-2 3 4 5 6 7 W= Bit Name No functions assigned DMITST9 (DMA9 interrupt request status) DMITST8 (DMA8 interrupt request status) DMITST7 (DMA7 interrupt request status) DMITST6 (DMA6 interrupt request status) DMITST5 (DMA5 interrupt request status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt requested Function R 0 W — The DMA5-9 Interrupt Request Status Register lets you know the status of interrupt requests in channels 5-9. If the DMAn interrupt request status bit (n = 5 to 9) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 5 to 9) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: • The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "IREQ bit" of the DMA Interrupt Control Register(IDMA59CR) that the interrupt controller has. When writing to the DMA5-9 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-23 32171 Group User's Manual (Rev.2.00) 9 9.2.7 DMA Interrupt Mask Registers s DMA0-4 Interrupt Mask Register (DM04ITMK) DMAC 9.2 DMAC Related Registers D 8 - 10 11 12 13 14 15 Bit Name No functions assigned DMITMK4 (DMA4 interrupt request mask) DMITMK3 (DMA3 interrupt request mask) DMITMK2 (DMA2 interrupt request mask) DMITMK1 (DMA1 interrupt request mask) DMITMK0 (DMA0 interrupt request mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — The DMA0-4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0-4. DMITMKn (DMAn interrupt request mask) bit (n = 0 to 4) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-24 32171 Group User's Manual (Rev.2.00) 9 s DMA5-9 Interrupt Mask Register (DM59ITMK) DMAC 9.2 DMAC Related Registers D 8 - 10 11 12 13 14 15 Bit Name No functions assigned DMITMK9 (DMA9 interrupt request mask) DMITMK8 (DMA8 interrupt request mask) DMITMK7 (DMA7 interrupt request mask) DMITMK6 (DMA6 interrupt request mask) DMITMK5 (DMA5 interrupt request mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — The DMA5-9 Interrupt Mask Register is used to mask interrupt requests in DMA channels 5-9. DMITMKn (DMAn interrupt request mask) bit (n = 5 to 9) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-25 32171 Group User's Manual (Rev.2.00) 9 DM04ITST DMA4UDF Data bus b3 b11 DMITST4 F/F DMITMK4 F/F DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 0 (Level) DMA3UDF b4 b12 DMITST3 F/F DMITMK3 F/F DMA2UDF b5 b13 DMITST2 F/F DMITMK2 F/F DMA1UDF b6 b14 DMITST1 F/F DMITMK1 F/F DMA0UDF b7 b15 DMITST0 F/F DMITMK0 F/F Figure 9.2.3 Block Diagram of DMA Transfer Interrupt 0 9-26 32171 Group User's Manual (Rev.2.00) 9 DM59ITST DMA9UDF Data bus b3 b11 DMITST9 F/F DMITMK9 F/F DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 1 (Level) DMA8UDF b4 b12 DMITST8 F/F DMITMK8 F/F DMA7UDF b5 b13 DMITST7 F/F DMITMK7 F/F DMA6UDF b6 b14 DMITST6 F/F DMITMK6 F/F DMA5UDF b7 b15 DMITST5 F/F DMITMK5 F/F Figure 9.2.4 Block Diagram of DMA Transfer Interrupt 1 9-27 32171 Group User's Manual (Rev.2.00) 9 9.3 Functional Description of the DMAC 9.3.1 Cause of DMA Request DMAC 9.3 Functional Description of the DMAC For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources. There are various causes of DMA transfer, so that DMA transfer can be started by a request from internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers in a DMA channel (cascade mode). The cause of DMA request is selected using the cause of request select bit provided for each channel, REQSLn (DMAn Channel Control Register bits D2, D3). The table below lists the causes of DMA requests in each channel. Table 9.3.1 Causes of DMA Requests in DMA0 and Generation Timings REQSL0 0 0 Cause of DMA Request Software start or one DMA2 transfer completed DMA Request Generation Timing When any data is written to DMA0 Software Request Generation Register (software start) or one DMA2 transfer is completed (cascade mode) 0 1 1 1 0 1 A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) When A-D0 conversion is completed When MJT TIO8 underflow occurs When MJT's input event bus 2 signal is generated Table 9.3.2 Causes of DMA Requests in DMA1 and Generation Timings REQSL1 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA1 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 0) None (Use inhibited) One DMA0 transfer completed When MJT's output event bus 0 signal is generated – When one DMA0 transfer is completed (cascade mode) 9-28 32171 Group User's Manual (Rev.2.00) 9 REQSL2 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings DMA Request Generation Timing When any data is written to DMA2 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed When MJT's output event bus 1 signal is generated When MJT's TIN18 input signal is generated When one DMA1 transfer is completed (cascade mode) Table 9.3.4 Causes of DMA Requests in DMA3 and Generation Timings REQSL3 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA3 Software Request Generation Register 0 1 1 1 0 1 Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) When serial I/O0 transmit buffer is emptied When serial I/O1 reception is completed When MJT's TIN0 input signal is generated Table 9.3.5 Causes of DMA Requests in DMA4 and Generation Timings REQSL4 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA4 Software Request Generation Register 0 1 1 1 0 1 One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) When one DMA3 transfer is completed (cascade mode) When serial I/O0 reception is completed When MJT's TIN19 input signal is generated 9-29 32171 Group User's Manual (Rev.2.00) 9 REQSL5 0 0 Cause of DMA Request Software start or one DMA7 transfer completed DMAC 9.3 Functional Description of the DMAC Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings DMA Request Generation Timing When any data is written to DMA5 Software Request Generation Register or one DMA7 transfer is completed (cascade mode) 0 1 1 1 0 1 All DMA0 transfers completed Serial I/O2 (reception completed) MJT (TIN20 input signal) When all DMA0 transfers are completed (cascade mode) When serial I/O2 reception is completed When MJT's TIN20 input signal is generated Table 9.3.7 Causes of DMA Requests in DMA6 and Generation Timings REQSL6 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA6 Software Request Generation Register 0 1 1 1 0 1 Serial I/O1 (transmit buffer empty) None (Use inhibited) One DMA5 transfer completed When serial I/O1 transmit buffer is emptied – When one DMA5 transfer is completed (cascade mode) Table 9.3.8 Causes of DMA Requests in DMA7 and Generation Timings REQSL7 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA7 Software Request Generation Register 0 1 1 1 0 1 Serial I/O2 (transmit buffer empty) None (Use inhibited) One DMA6 transfer completed When serial I/O2 transmit buffer is emptied – When one DMA6 transfer is completed (cascade mode) 9-30 32171 Group User's Manual (Rev.2.00) 9 REQSL8 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.9 Causes of DMA Requests in DMA8 and Generation Timings DMA Request Generation Timing When any data is written to DMA8 Software Request Generation Register 0 1 1 1 0 1 MJT (input event bus 0) None (Use inhibited) None (Use inhibited) When MJT's input event bus 0 signal is generated – – Table 9.3.10 Causes of DMA Requests in DMA9 and Generation Timings REQSL9 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA9 Software Request Generation Register 0 1 1 1 0 1 None (Use inhibited) None (Use inhibited) One DMA8 transfer completed – – When one DMA8 transfer is completed (cascade mode) 9-31 32171 Group User's Manual (Rev.2.00) 9 9.3.2 DMA Transfer Processing Procedure DMAC 9.3 Functional Description of the DMAC Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0. DMA transfer processing starts Setting interrupt controller related registers Set the interrupt controller's DMA0-4 Interrupt Control Register • Interrupt priority level Set DMA0 Channel Control Register • Transfers disabled Set DMA0-4 Interrupt Request Status Register • Clears interrupt request status bit • Enables interrupt request Set DMA0-4 Interrupt Mask Register Setting DMAC related registers Set DMA0 Source Address Register • Source address of transfer Set DMA0 Destination Address Register • Destination address of transfer Set DMA0 Count Register • Number of times DMA transfer performed • Transfer mode, cause of request, transfer size, address direction, and transfer enable Set DMA0 Channel Control Register Starting DMA transfer DMA transfer starts as requested by internal peripheral I/O Transfer count register underflows DMA transfer completed Interrupt request generated DMA operation completed Figure 9.3.1 Example of a DMA Transfer Processing Procedure 9-32 32171 Group User's Manual (Rev.2.00) 9 9.3.3 Starting DMA DMAC 9.3 Functional Description of the DMAC Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1. 9.3.4 Channel Priority Channel 0 has the highest priority. The priority of this and other channels is shown below. Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are requested, the channel that has the highest priority is selected. Channel selection is made every transfer cycle (one DMA bus cycle consisting of three machine cycles). 9.3.5 Gaining and Releasing Control of the Internal Bus For any channel, control of the internal bus is gained and released in "single transfer DMA" mode. In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA operation in single transfer DMA. Requested Internal bus arbitration (control requested by DMAC) Gained Requested Gained Requested Gained CPU Internal bus DMAC R W Released Released Released R W R W One DMA transfer One DMA transfer R: Read W: Write One DMA transfer Figure 9.3.2 Gaining and Releasing Control of the Internal Bus 9-33 32171 Group User's Manual (Rev.2.00) 9 9.3.6 Transfer Units DMAC 9.3 Functional Description of the DMAC Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one each time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. 9.3.8 Address Space The address space in which data can be transferred by DMA is the internal peripheral I/O or 64 Kbytes of RAM space (H'0080 0000 through H'0080 FFFF) for either source or destination. To set the source and destination addresses in each channel, use the DMA Source Address Register and DMA Destination Address Register. 9.3.9 Transfer Operation (1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is temporarily taken into the DMA's internal temporary register.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, the same applies to both bus protocol and bus timing as in peripheral module access from the CPU. (3) Transfer rate The maximum transfer rate is calculated using the equation below: 1 1 / f (BCLK) × 3 cycles Maximum transfer rate [bytes/second] = 2 bytes × 9-34 32171 Group User's Manual (Rev.2.00) 9 (4) Address count direction and address changes DMAC 9.3 Functional Description of the DMAC The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Address fixed Transfer Unit 8 bits 16 bits Address incremental 8 bits 16 bits Address Change for One DMA 0 0 +1 +2 (5) Transfer count value The transfer count value is decremented by one at a time irrespective of the size of transfer unit (8 or 16 bits). 9-35 32171 Group User's Manual (Rev.2.00) 9 (6) Transfer byte positions DMAC 9.3 Functional Description of the DMAC When the transfer unit = 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) When the transfer unit = 16 bits, the LSB of the address register (D15 of the address register) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid transfer byte positions. +0 D0 D7 D8 8 bits 8 bits +1 D15 +0 D0 D7 D8 16 bits +1 D15 Source Destination 8 bits 8 bits 16 bits Figure 9.3.3 Transfer Byte Positions 9-36 32171 Group User's Manual (Rev.2.00) 9 (7) Ring buffer mode DMAC 9.3 Functional Description of the DMAC When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B'00000. The address increment operation in ring buffer mode is described below. ➀ When the transfer unit = 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B'11111, they are recycled to B'00000 by the next increment operation, thus returning to the start address again. ➁ When the transfer unit = 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B'111110, they are recycled to B'000000 by the next increment operation, thus returning to the start address again. When the source address has been set to be incremented, it is the source address that recycles to the start address; when the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially being B'00000. During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to (to disable transfer). Transfer count 1 2 3 | 31 32 ↓ 1 2 | Transfer address H'0080 1000 H'0080 1001 H'0080 1002 | H'0080 101E H'0080 101F ↓ H'0080 1000 H'0080 1001 | Transfer count 1 2 3 | 31 32 ↓ 1 2 | Transfer address H'0080 1000 H'0080 1002 H'0080 1004 | H'0080 103C H'0080 103E ↓ H'0080 1000 H'0080 1002 | Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode 9-37 32171 Group User's Manual (Rev.2.00) 9 9.3.10 End of DMA and Interrupt DMAC 9.3 Functional Description of the DMAC In normal mode, DMA transfer is terminated when the transfer count register underflows. When transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, this interrupt is not generated for channels where interrupt requests have been masked by the DMA Interrupt Mask Register. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to 0 (to disable transfer). In this case, therefore, the DMA transfer-completed interrupt request is not generated. Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 Status of Each Register after Completion of DMA Transfer When DMA transfer is completed, the status of the source address and destination address registers becomes as follows: (1) Address fixed • The value set in the address register before DMA transfer started remains intact (fixed). (2) Address incremental • For 8-bit transfer, the value of the address register is the last transfer address + 1. • For 16-bit transfer, the value of the address register is the last transfer address + 2. The transfer count register when DMA transfer completed is in an underflow state (H'FF). Therefore, to perform another DMA transfer, set the transfer count register newly again, except when you are performing transfers 256 times (H'FF). 9-38 32171 Group User's Manual (Rev.2.00) 9 9.4 Precautions about the DMAC • About writing to DMAC related registers DMAC 9.4 Precautions about the DMAC Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). When transfer is enabled, do not write to the DMAC related registers because write operation to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer Count Register which is protected in hardware, is instable. The table below shows the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status When transfer is enabled When transfer is disabled : Can be accessed ; ✕ : Cannot be accessed Transfer enable bit Transfer request flag Other DMAC related registers ✕ For even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. ➀ DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. Note that you only can write a 0 to the transfer request flag as valid data. ➁ DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. ➂ Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case, you are writing to the DMAC related registers while DMA is enabled, but this practically does not present any problem. However, you cannot DMA-transfer to the DMAC related registers on the local channel itself in which you are currently operating. 9-39 32171 Group User's Manual (Rev.2.00) 9 DMAC 9.4 Precautions about the DMAC • Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) Only if residing on other channels, you can write to the DMAC related registers by means of DMA transfer. (For example, you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0.) • About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write 1s to all bits but the one you want to clear. The bits to which you wrote 1s retain the previous data they had before the write. • About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the DMA Channel Control Register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another. 9-40 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.2 Common Units of Multijunction Timer 10.3 TOP (Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) 10.5 TMS (Input-related 16-bit Timer) 10.6 TML (Input-related 32-bit Timer) 10 10.1 Outline of Multijunction Timers MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event bus at multiple points that they are called the "multijunction" timers. The 32171 has four types of multijunction timers as listed in the table below, providing a total of 37 channels of timers. Table 10.1.1 Outline of Multijunction Timers Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) Number of Channels Description 11 One of three output modes can be selected by software. • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TIO (Timer Input Output) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) Input-related 16-bit timer (up-counter) Input-related 32-bit timer (up-counter) 8 32-bit input measure timer 8 16-bit input measure timer 10-2 32171 Group User's Manual (Rev.2.00) 10 Table 10.1.2 Interrupt Generation Functions of MJT Signal Name IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 MJT Interrupt Request Source TIN3 input TIN20 - TIN23 input TIN16 - TIN19 input TIN0 input TMS0, TMS1 output TOP8, TOP9 output TOP10 output TIO4 - 7 output TIO8, TIO9 output TOP0 - 5 output TOP6, TOP7 output TIO0 - 3 output MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Source of Interrupt Request MJT input interrupt 4 MJT input interrupt 3 MJT input interrupt 2 MJT input interrupt 1 MJT output interrupt 7 MJT output interrupt 6 MJT output interrupt 5 MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 MJT output interrupt 0 No. of ICU Input Source 1 4 4 1 2 2 1 4 2 6 2 4 Table 10.1.3 DMA Transfer Request Generation by MJT Signal Name DRQ0 DRQ1 DRQ2 DRQ4 DRQ5 DRQ6 DRQ7 DRQ12 DRQ13 DMA Transfer Request Source TIO8 underflow Input event bus 2 Output event bus 0 Output event bus 1 TIN18 input TIN19 input TIN0 input TIN20 input Input event bus 0 DMAC Input Channel Channel 0 Channel 0 Channel 1 Channel 2 Channel 2 Channel 4 Channel 3 Channel 5 Channel 8 Table 10.1.4 A-D Conversion Start Request by MJT Signal Name AD0TRG A-D Conversion Start Request Source Output event bus 3 A-D Converter Can be input to A-D0 conversion start trigger 10-3 32171 Group User's Manual (Rev.2.00) 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Input event bus 3210 Output event bus IRQ2 0123 clk S TCLK0 (P124) TCLK0S IRQ9 en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 udf IRQ2 F/F0 F/F1 IRQ2 TO 0 (P110) TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) clk clk S DRQ7 udf udf IRQ2 F/F2 F/F3 IRQ2 TIN0 (P150) TIN0S clk clk clk clk udf udf IRQ2 F/F4 F/F5 IRQ1 udf udf IRQ1 S S S S S S F/F6 clk en TOP 7 udf IRQ6 S S IRQ6 F/F7 TO 7 (P117) clk clk clk en en en TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf IRQ0 F/F8 F/F8 F/F10 F/F11 F/F12 F/F13 F/F14 TO 8 (P100) TO 9 (P101) TO 10 (P102) TO 11 (P103) TO 12 (P104) TO 13 (P105) TO 14 (P106) S IRQ5 S S IRQ0 IRQ12 S S clk clk S clk S clk TIN3 (P153) TIN3S en/cap en/cap en/cap en/cap en/cap udf udf IRQ0 S S IRQ0 udf udf IRQ4 S S 1/2 internal peripheral clock PRS0 PRS1 PRS2 clk S udf S F/F15 TO 15 (P107) S TCLK1 (P125) TCLK2 (P126) TCLK1S IRQ4 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 (P93) TCLK2S S S S S S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 (P94) clk en/cap TIO 7 udf DRQ0 IRQ3 S F/F18 TO 18 (P95) clk en/cap TIO 8 udf IRQ3 S F/F19 TO 19 (P96) S S 3210 3210 PRS0-2 clk en/cap TIO 9 udf F/F20 TO 20 (P97) 0123 : Prescaler F/F : Output flip-flop S : Selector Note 1: IRQ0-7 and IRQ9-12 are interrupt signals, with the same number representing interrupts of the same group (see Table 10.1.2). DRQ 0-2, DRQ4-7, DRQ12, and DRQ13 are DMA request signals to the DMAC (see Table 10.1.3). AD0TRG is a trigger signal to the A-D converter (see Table 10.1.4). Note 2: Indicates timer input pin edge selection output. Note 3: Indicates input signals from peripheral circuits (AD and SIO). Figure 10.1.1 Block Diagram of MJT (1/3) 10-4 32171 Group User's Manual (Rev.2.00) 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Input event bus 3210 Output event bus 0123 IRQ7 TCLK3 (P127) TCLK3S S S S S clk cap3 TMS 0 cap2 cap1 cap0 ovf S (Note1) IRQ10 S S clk cap3 TMS 1 cap2 cap1 IRQ7 cap0 ovf TIN16 (P130) TIN17 (P131) TIN18 (P132) TIN16S IRQ10 TIN17S IRQ10 S S DRQ5 IRQ10 TIN18S TIN19 (P133) 1/2 internal peripheral clock TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) TIN19S DRQ6 S S DRQ12 IRQ11 clk cap3 S TML 0 cap2 cap1 cap0 TIN20S IRQ11 TIN21S IRQ11 S S IRQ11 TIN22S TIN23S S AD0TRG (To A-D0 converter) 1/2 internal peripheral clock S S clk cap3 S S S TML 1 cap2 cap1 cap0 3210 3210 0123 Figure 10.1.2 Block Diagram of MJT (2/3) 10-5 32171 Group User's Manual (Rev.2.00) 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Input event bus 3210 Output event bus 0123 (Note 3) AD0 completed TIO8-udf (Note 3) S DMA0 udf end udf end udf end udf end DMAIRQ0 S DMA1 DMAIRQ0 TIN18 (Note 2) (Note 3) SIO0-TXD SIO1-RXD (Note 3) (Note 3) SIO0-RXD S DMA2 DMAIRQ0 TIN0 (Note 2) TIN19 (Note 2) S DMA3 DMAIRQ0 S DMA4 udf DMAIRQ0 (Note 3) SIO2-RXD TIN20 (Note 2) (Note 3) SIO1-TXD S DMA5 udf end udf end udf end DMAIRQ1 S DMA6 DMAIRQ1 (Note 3) SIO2-TXD S DMA7 DMAIRQ1 S DMA8 udf end udf DMAIRQ1 S DMA9 DMAIRQ1 3210 3210 0123 Figure 10.1.3 Block Diagram of MJT (3/3) 10-6 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2 Common Units of Multijunction Timer The common units of the multijunction timer include the following: • Prescaler unit • Clock bus/input-output event bus control unit • Input processing control unit • Output flip-flop control unit • Interrupt control unit 10.2.1 Timer Common Register Map The diagrams in the next pages show a map of registers in the common units of the multijunction timer. 10-7 32171 Group User's Manual (Rev.2.00) 10 Address H'0080 0200 H'0080 0202 H'0080 0204 D0 +0 Address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D7 D8 +1 Address D15 Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) H'0080 0210 H'0080 0212 H'0080 0214 H'0080 0216 H'0080 0218 H'0080 021A TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A F/F Source Select Register 0 (FFS0) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 5 (TINIR5) H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E Blank addresses are reserved. Note: • The registers included in thick frames must always be accessed in halfwords. Figure 10.2.1 Timer Common Register Map 10-8 32171 Group User's Manual (Rev.2.00) 10 10.2.2 Prescaler Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The prescalers PRS0-2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, and TML) from the divide-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripheral clock = 20 MHz). The values of prescaler registers are initialized to H'00 immediately after reset. Also, when you rewrite the set value of any prescaler register, the device starts operating with the new value simultaneously when the prescaler underflows. Values H'00 to H'FF can be set in the counter registers of prescalers. The prescalers' divide-by ratios are given by the equation below: 1 Prescaler divide-by ratio = ————— Prescaler set value + 1 s Prescaler Register 0 (PRS0) s Prescaler Register 1 (PRS1) s Prescaler Register 2 (PRS2) D 0-7 8 - 15 Bit Name PRS0, 2 PRS1 Function Sets the prescaler's divide-by value R W Prescaler Registers 0-2 start counting after exiting reset. 10-9 32171 Group User's Manual (Rev.2.00) 10 (1) Clock bus MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.3 Clock Bus/Input-Output Event Bus Control Unit The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0-3. Each timer can use this clock bus signal as clock input signal. The table below lists the signals that can be fed to the clock bus. Table 10.2.1 Signals That Can Be Fed to Each Clock Bus Line Clock Bus 3 2 1 0 Acceptable Signal TCLK0 input Internal prescaler (PRS2) or TCLK3 input Internal prescaler (PRS1) Internal prescaler (PRS0) (2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0-3. Each timer can use this input event bus signal as enable (or capture) signal input. The table below lists the signals that can be fed to the input event bus. Table 10.2.2 Signals That Can Be Fed to Each Input Event Bus Line Input Event Bus 3 2 1 0 Acceptable Signal TIN3 input, output event bus 2 or TIO7 underflow signal TIN0 input TIO6 underflow signal TIO5 underflow signal 10-10 32171 Group User's Manual (Rev.2.00) 10 (3) Output event bus MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0-3. Output event bus signals are connected to output flip-flops, and can also be connected to other peripheral circuits-output event bus 3 to A-D0 converter, output event bus 0 to DMA channel 1, and output event bus 1 to DMA channel 2. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Signals That Can Be Connected (Fed) to Each Output Event Bus Line Output Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TOP8, TIO3, TIO4, or TIO8 underflow signal TOP9 or TIO2 underflow signal TOP7 or TIO1 underflow signal TOP6 or TIO0 underflow signal Note 1: For details about the output destinations of output event bus signals, refer to Figure 10.1.1, "Block Diagram of MJT." Timings at which signals are generated to the output event bus by each timer (and those generated to the input event bus by TIO5, 6) are shown below. (Note that they are generated at different timings than those forwarded to output flip-flops by timers.) Table 10.2.4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO (Note 1) Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML (16-bit measure input) (32-bit measure input) Timings at which signals are generated to the output event bus When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows No signal generation function No signal generation function Note 1: TIO5, 6 output underflow signals to the input event bus. 10-11 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Output event bus 0123 clk TCLK0 (P124) TIN0 (P150) TCLK0S clk clk TIN0S clk TIN3S en en en en TOP 6 TOP 7 TOP 8 TOP 9 udf udf udf udf TIN3 (P153) TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf udf udf 1/2 internal peripheral clock PRS0 PRS1 PRS2 S TIO 5 udf udf udf udf 0123 TCLK3 (P127) TCLK3S TIO 6 3210 3210 TIO 7 TIO 8 PRS0-2 : Prescaler S : Selector Figure 10.2.2 Conceptual Diagram of the Clock Bus and Input/Output Event Bus 10-12 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The clock bus/input-output bus control unit has the following registers: • Clock Bus & Input Event Bus Control Register (CKIEBCR) • Output Event Bus Control Register (OEBCR) s Clock Bus & Input Event Bus Control Register (CKIEBCR) D 8, 9 Bit Name IEB3S Function 0X : Selects external input 3 (TIN3) R W (input event bus 3 input selection) 10 : Selects output event bus 2 11 : Selects TIO7 output 10, 11 IEB2S 00 : Selects external input 0 (TIN0) (input event bus 2 input selection) 01 : No selection 1X : No selection 12 IEB1S 0 : No selection (input event bus 1 input selection) 1 : Selects TIO6 output 13 IEB0S 0 : No selection (input event bus 0 input selection) 1 : Selects TIO5 output 14 15 No functions assigned CKB2S (Clock Bus 2 input selection) 0 : Selects prescaler 2 1 : Selects external clock 3 (TCLK3) 0 — The register CKIEBCR is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus. 10-13 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s Output Event Bus Control Register (OEBCR) D8 OEB3S 9 10 11 OEB2S 12 13 OEB1S D 8, 9 Bit Name OEB3S Function 00 : Selects TOP8 output R W (output event bus 3 input selection) 01 : Selects TIO3 output 10 : Selects TIO4 output 11 : Selects TIO8 output 10 11 No functions assigned OEB2S 0 : Selects TOP9 output 0 — (output event bus 2 input selection) 1 : Selects TIO2 output 12 13 No functions assigned OEB1S 0 : Selects TOP7 output 0 — (output event bus 1 input selection) 1 : Selects TIO1 output 14 15 No functions assigned OEB0S 0 : Selects TOP6 output 0 — (output event bus 0 input selection) 1 : Selects TIO0 output The register OEBCR is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus. 10-14 32171 Group User's Manual (Rev.2.00) 10 10.2.4 Input Processing Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The input processing control unit processes the TCLK and TIN signals fed into the MJT. In the TCLK input processing unit, selection is made of the source of TCLK signal, or for external input, the active edge (rising or falling or both) or level (high or low) of the signal, with or at which to generate the clock signal fed to the clock bus. In the TIN input processing unit, selection is made of the active edge (rising or falling or both) or level (high or low) of the signal at which to generate the enable, measure or count source signal for each timer or the signal fed to each event bus. Following input processing control registers are included: • TCLK Input Processing Control Register (TCLKCR) • TIN Input Processing Control Register 0 (TINCR0) • TIN Input Processing Control Register 3 (TINCR3) • TIN Input Processing Control Register 4 (TINCR4) 10-15 32171 Group User's Manual (Rev.2.00) 10 Item 1/2 internal peripheral clock MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (1) Functions of TCLK input processing control registers Function 1/2 internal peripheral clock Count clock Rising clock edge TCLK Count clock Falling clock edge TCLK Count clock Both edges TCLK Count clock Low level TCLK 1/2 internal peripheral clock Count clock High level TCLK 1/2 internal peripheral clock Count clock 10-16 32171 Group User's Manual (Rev.2.00) 10 Item Rising edge TIN MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (2) Functions of TIN input processing control registers Function Internal edge signal Falling edge TIN Internal edge signal Both edges TIN Internal edge signal Low level TCLK PRS clock output period or TCLK input period Internal edge signal High level TIN PRS clock output period or TCLK input period Internal edge signal 10-17 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TLCK Input Processing Control Register (TCLKCR) D0 1 2 3 4 5 6 TCLK2S D 0, 1 2, 3 Bit Name No functions assigned TCLK3S (TCLK3 input processing selection) 00 : 1/2 internal peripheral clock 01 : Rising edge 10 : Falling edge 11 : Both edges 4 5-7 No functions assigned TCLK2S (TCLK2 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8 9 - 11 No functions assigned TCLK1S (TCLK1 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 12, 13 14, 15 No functions assigned TCLK0S (TCLK0 input processing selection) 00 : 1/2 internal peripheral clock 01 : Rising edge 10 : Falling edge 11 : Both edges Note: • This register must always be accessed in halfwords. 0 — 0 — 0 — Function R 0 W — 10-18 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 0 (TINCR0) D0 1 2 TIN4S D 0 1-3 4 5-7 Bit Name No functions assigned TIN4S (reserved) No functions assigned TIN3S (TIN3 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8, 9 10, 11 12, 13 14, 15 No functions assigned TIN2S (reserved) TIN1S (reserved) TIN0S (TIN0 input processing selection) Set these bits to '00' (Note 2) Set these bits to '00' (Note 2) 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges Note 1: Always set the TIN4S bits to '000.' Note 2: Always set the TIN2S bits and TIN1S bits to '00.' N Function R 0 W — Set these bits to '000' (Note 1) 0 — 0 — Note: • This register must always be accessed in halfwords. 10-19 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 3 (TINCR3) D0 1 2 3 4 5 6 7 8 9 10 11 D 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN19S (TIN19 input processing selection) TIN18S (TIN18 input processing selection) TIN17S (TIN17 input processing selection) TIN16S (TIN16 input processing selection) TIN15S (reserved) TIN14S (reserved) TIN13S (reserved) TIN12S (reserved) Function 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges Set these bits to '00' (Note) R W Notes: • Always set the TIN15S bits, TIN14S bits, TIN13S bits, and TIN12S bits to '00' . • This register must always be accessed in halfwords. s TIN Input Processing Control Register 4 (TINCR4) D0 1 2 3 4 5 6 7 8 9 10 11 D 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN33S (reserved) TIN32S (reserved) TIN31S (reserved) TIN30S (reserved) TIN23S (TIN23 input processing selection) TIN22S (TIN22 input processing selection) TIN21S (TIN21 input processing selection) TIN20S (TIN20 input processing selection) 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges Function Set these bits to '00' (Note) R W Notes: • Always set the TIN33S bits, TIN32S bits, TIN31S bits, and TIN30S bits to '00' . • This register must always be accessed in halfwords. 10-20 32171 Group User's Manual (Rev.2.00) 10 10.2.5 Output Flip-Flop Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. Following flip-flop control registers are included: • F/F Source Select Register 0 (FFS0) • F/F Source Select Register 1 (FFS1) • F/F Protect Register 0 (FFP0) • F/F Protect Register 1 (FFP1) • F/F Data Register 0 (FFD0) • F/F Data Register 1 (FFD1) Timings at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5 below. (Note that signals are generated at different timings than those fed to the output event bus.) 10-21 32171 Group User's Manual (Rev.2.00) 10 Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML (16-bit measure input) (32-bit measure input) MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Table 10.2.5 Timings at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timings at which signals are generated to the output flip-flop When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows When counter underflows When counter underflows When counter underflows When counter is enabled and when underflows When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows No signal generation function No signal generation function TOP TIO F/F source selection (FFn) udf Port operation mode register(PnMOD) F/F Output event bus 0 Output event bus 1 Output event bus 2 Output event bus 3 Internal edge signal F/Fn output data (FDn) Dn F/F Output control (ON/OFF) WR F/F protect (FPn) Dn F/F TOn Note: • Dn denotes the data bus Figure 10.2.3 Configuration of the F/F Output Circuit 10-22 32171 Group User's Manual (Rev.2.00) 10 s F/F Source Select Register 0 (FFS0) D0 1 2 3 4 5 6 7 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0-2 3 Bit Name No functions assigned FF15 (F/F15 source selection) 0 : TIO4 output 1 : Output event bus 0 4 FF14 (F/F14 source selection) 0 : TIO3 output 1 : Output event bus 0 5 FF13 (F/F13 source selection) 0 : TIO2 output 1 : Output event bus 3 6 FF12 (F/F12 source selection) 0 : TIO1 output 1 : Output event bus 2 7 FF11 (F/F11 source selection) 0 : TIO0 output 1 : Output event bus 1 8, 9 FF10 (F/F10 source selection) 0X : TOP10 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF9 (F/F9 source selection) 0X : TOP9 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF8 (F/F8 source selection) 00 : TOP8 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 2 14 FF7 (F/F7 source selection) 0 : TOP7 output 1 : Output event bus 0 15 FF6 (F/F6 source selection) 0 : TOP6 output 1 : Output event bus 1 Note: • This register must always be accessed in halfwords. Function R 0 W — 10-23 32171 Group User's Manual (Rev.2.00) 10 s F/F Source Select Register 1 (FFS1) D8 FF19 9 10 FF18 11 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8, 9 Bit Name FF19 (F/F19 source selection) Function 0X : TIO8 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF18 (F/F18 source selection) 0X : TIO7 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF17 (F/F17 source selection) 0X : TIO6 output 10 : Output event bus 0 11 : Output event bus 1 14, 15 FF16 (F/F16 source selection) 00 : TIO5 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 3 R W The registers FFS0 and FFS1 are used to select the signal sources fed to each output F/F (flipflop). For these signal sources, you can choose signals from the internal output bus or underflow output from each timer. 10-24 32171 Group User's Manual (Rev.2.00) 10 s F/F Protect Register 0 (FFP0) D0 1 2 3 4 5 6 FP9 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FP15 (F/F15 protect) FP14 (F/F14 protect) FP13 (F/F13 protect) FP12 (F/F12 protect) FP11 (F/F11 protect) FP10 (F/F10 protect) FP9 (F/F9 protect) FP8 (F/F8 protect) FP7 (F/F7 protect) FP6 (F/F6 protect) FP5 (F/F5 protect) FP4 (F/F4 protect) FP3 (F/F3 protect) FP2 (F/F2 protect) FP1 (F/F1 protect) FP0 (F/F0 protect) Function 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit R W Note: • This register must always be accessed in halfwords. This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. 10-25 32171 Group User's Manual (Rev.2.00) 10 s F/F Protect Register 1 (FFP1) D8 9 10 11 FP20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 - 10 11 12 13 14 15 Bit Name No functions assigned FP20 (F/F20 protect) FP19 (F/F19 protect) FP18 (F/F18 protect) FP17 (F/F17 protect) FP16 (F/F16 protect) 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit Function R 0 W — This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. 10-26 32171 Group User's Manual (Rev.2.00) 10 s F/F Data Register 0 (FFD0) D0 1 2 3 4 5 6 FD9 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FD15 (F/F15 output data) FD14 (F/F14 output data) FD13 (F/F13 output data) FD12 (F/F12 output data) FD11 (F/F11 output data) FD10 (F/F10 output data) FD9 (F/F9 output data) FD8 (F/F8 output data) FD7 (F/F7 output data) FD6 (F/F6 output data) FD5 (F/F5 output data) FD4 (F/F4 output data) FD3 (F/F3 output data) FD2 (F/F2 output data) FD1 (F/F1 output data) FD0 (F/F0 output data) Function 0 : F/F output data = 0 1 : F/F output data = 1 R W Note: • This register must always be accessed in halfwords. This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. 10-27 32171 Group User's Manual (Rev.2.00) 10 s F/F Data Register 1 (FFD1) D8 9 10 11 FD20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 - 10 11 12 13 14 15 Bit Name No functions assigned FD20 (F/F20 output data) FD19 (F/F19 output data) FD18 (F/F18 output data) FD17 (F/F17 output data) FD16 (F/F16 output data) 0 : F/F output data = 0 1 : F/F output data = 1 Function R 0 W — This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. 10-28 32171 Group User's Manual (Rev.2.00) 10 10.2.6 Interrupt Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer. Following timer interrupt control registers are provided for each timer. • TOP Interrupt Control Register 0 (TOPIR0) • TOP Interrupt Control Register 1 (TOPIR1) • TOP Interrupt Control Register 2 (TOPIR2) • TOP Interrupt Control Register 3 (TOPIR3) • TIO Interrupt Control Register 0 (TIOIR0) • TIO Interrupt Control Register 1 (TIOIR1) • TIO Interrupt Control Register 2 (TIOIR2) • TMS Interrupt Control Register (TMSIR) • TIN Interrupt Control Register 0 (TINIR0) • TIN Interrupt Control Register 1 (TINIR1) • TIN Interrupt Control Register 4 (TINIR4) • TIN Interrupt Control Register 5 (TINIR5) • TIN Interrupt Control Register 6 (TINIR6) For interrupts which have only one source of interrupt in one interrupt table, no interrupt control registers are provided in the timer, and the interrupt status flags are automatically managed within the interrupt controller. For details, refer to Chapter 5, "Interrupt Controller." • TOP10 MJT Output Interrupt 5 (IRQ5) For interrupts which have two or more sources of interrupt in one interrupt table, interrupt control registers are provided, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the interrupt controller function only as a bit to show whether an interrupt-enabled interrupt request occurred and cannot be written to. (1) Interrupt request status bit This status bit shows whether an interrupt request occurred. When an interrupt request is generated, this bit is set in hardware (but cannot be set in software). The status bit is cleared by writing a 0, but not affected by writing a 1, in which case the bit holds the status intact. Because the status bit is unaffected by interrupt mask bits, it can also be used to check the operation of peripheral function. In interrupt processing, make sure that among grouped interrupt flags, only the flag for the serviced interrupt is cleared. Clearing flags for unserviced interrupts results in the pending interrupt requests also being cleared. 10-29 32171 Group User's Manual (Rev.2.00) 10 (2) Interrupt mask bit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer This bit is used to disable unnecessary interrupts among grouped interrupt requests. Set this bit to 0 to enable interrupts or 1 to disable interrupts. Group interrupt Each timer or TIN input interrupt request Set Data = 0 clear Interrupt status F/F F/F Interrupt enable Interrupt controller Data bus Figure 10.2.4 Interrupt Status Register and Mask Register 10-30 32171 Group User's Manual (Rev.2.00) 10 Example for clearing the interrupt status MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Interrupt status flag b4 5 0 6 0 b7 0 Initial state 0 Interrupt request b6 event occurred 0 0 1 0 b4 event occurred Write to the interrupt status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only b6 cleared b4 data retained Example program When clearing the TOP Interrupt Control Register 0 (TOPIR0)'s TOP1 interrupt status (TOPIS1) *TOPIR0 = 0xfd; /* Clears only TOPIS1 (0x02 bit) */ To clear an interrupt status flag, be sure to write "1"s for all other status flags. At this time, if a logical operation like the one shown below is used,because this operation involves three steps (TOPIR0 read, logical operation, and write), an unintended status may be inadvertently cleared should another interrupt request occur during a read-to-write interval time. *TOPIR0 &= 0xfd; /* Clears only TOPIS1 (0x02 bit) */ Interrupt status flag b4 5 0 6 1 b7 0 b6 event occurred 0 Read 0 0 1 0 b4 event occurred 1 0 1 0 0 0 b6 cleared (AND with 1101) 0 0 Write 0 0 0 0 Only b6 cleared b4 also cleared Figure 10.2.5 Example for Clearing the Interrupt Status 10-31 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller. Table 10.2.6 Interrupt Signals Generated by MJT Signal Name Source of Interrupt Generated IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 TIO0, TIO1, TIO2, TIO3 TOP6, TOP7 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TIO8, TIO9 TIO4, TIO5, TIO6, TIO7 TOP8, TOP9 TMS0, TMS1 TIN0 TIN16, TIN17, TIN18, TIN19 TIN20, TIN21, TIN22, TIN23 TIN3 Interrupt Sources Input to ICU (Note 1) Number of Input Sources MJT output interrupt 0 MJT output interrupt 1 MJT output interrupt 2 MJT output interrupt 3 MJT output interrupt 4 MJT output interrupt 6 MJT output interrupt 7 MJT input interrupt 1 MJT input interrupt 2 MJT input interrupt 3 MJT input interrupt 4 4 2 6 2 4 2 2 1 4 4 1 Note 1: Refer to Chapter 5, "Interrupt Controller (ICU)." Note: • For TOP10, there are no interrupt status and mask bits in MJT interrupt control register because it only has one source of interrupt in the group. (It is controlled directly by the interrupt controller.) 10-32 32171 Group User's Manual (Rev.2.00) 10 D0 1 2 TOPIS5 3 TOPIS4 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TOP Interrupt Control Register 0 (TOPIR0) 4 TOPIS3 5 TOPIS2 D 0, 1 2 3 4 5 6 7 W= Bit Name No functions assigned TOPIS5 (TOP5 interrupt status) TOPIS4 (TOP4 interrupt status) TOPIS3 (TOP3 interrupt status) TOPIS2 (TOP2 interrupt status) TOPIS1 (TOP1 interrupt status) TOPIS0 (TOP0 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt request generated Function R 0 W — s TOP Interrupt Control Register 1 (TOPIR1) D8 9 10 TOPIM5 11 TOPIM4 12 TOPIM3 13 TOPIM2 D 8, 9 10 11 12 13 14 15 Bit Name No functions assigned. TOPIM5 (TOP5 interrupt mask) TOPIM4 (TOP4 interrupt mask) TOPIM3 (TOP3 interrupt mask) TOPIM2 (TOP2 interrupt mask) TOPIM1 (TOP1 interrupt mask) TOPIM0 (TOP0 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — 10-33 32171 Group User's Manual (Rev.2.00) 10 TOPIR0 TOP5udf Data bus b2 b10 TOPIS5 F/F TOPIM5 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 6-source inputs MJT output interrupt 2 IRQ2 (Level) TOP4udf b3 b11 TOP3udf b4 b12 TOPIS3 F/F TOPIM3 F/F TOPIS4 F/F TOPIM4 F/F TOP2udf b5 b13 TOP1udf b6 b14 TOPIS1 F/F TOPIM1 F/F TOPIS2 F/F TOPIM2 F/F TOP0udf b7 b15 TOPIS0 F/F TOPIM0 F/F Figure 10.2.6 Block Diagram of MJT Output Interrupt 2 10-34 32171 Group User's Manual (Rev.2.00) 10 D0 1 2 TOPIS7 3 TOPIS6 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TOP Interrupt Control Register 2 (TOPIR2) 4 5 D 0, 1 2 3 4, 5 6 7 W= Bit Name No functions assigned TOPIS7 (TOP7 interrupt status) TOPIS6 (TOP6 interrupt status) No functions assigned TOPIM7 (TOP7 interrupt mask) TOPIM6 (TOP6 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TOPIR2 D 8, 9 10 11 12, 13 14 15 W= Bit Name No functions assigned TOPIS9 (TOP9 interrupt status) TOPIS8 (TOP8 interrupt status) No functions assigned TOPIM9 (TOP9 interrupt mask) TOPIM8 (TOP8 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. Note: • For TOP10, there are no interrupt status and mask bits in MJT interrupt control registers because it only has one source of interrupt in the group. (It is controlled directly by the interrupt controller.) TOPIR3 D 0 1 2 3 4 5 6 7 W= Bit Name TIOIS3 (TIO3 interrupt status) TIOIS2 (TIO2 interrupt status) TIOIS1 (TIO1 interrupt status) TIOIS0 (TIO0 interrupt status) TIOIM3 (TIO3 interrupt mask) TIOIM2 (TIO2 interrupt mask) TIOIM1 (TIO1 interrupt mask) TIOIM0 (TIO0 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W TIOIR0 D 8 9 10 11 12 13 14 15 W= Bit Name TIOIS7 (TIO7 interrupt status) TIOIS6 (TIO6 interrupt status) TIOIS5 (TIO5 interrupt status) TIOIS4 (TIO4 interrupt status) TIOIM7 (TIO7 interrupt mask) TIOIM6 (TIO6 interrupt mask) TIOIM5 (TIO5 interrupt mask) TIOIM4 (TIO4 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W TIOIR1 D 0, 1 2 3 4, 5 6 7 W= Bit Name No functions assigned TIOIS9 (TIO9 interrupt status) TIOIS8 (TIO8 interrupt status) No functions assigned TIOIM9 (TIO9 interrupt mask) TIOIM8 (TIO8 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TIOIR2 D 8, 9 10 11 12, 13 14 15 W= Bit Name No functions assigned TMSIS1 (TMS1 interrupt status) TMSIS0 (TMS0 interrupt status) No functions assigned TMSIM1 (TMS1 interrupt mask) TMSIM0 (TMS0 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TMSIR D 0-2 3 Bit Name No functions assigned TINIS0 (TIN0 interrupt status) 0 : No interrupt request 1 : Interrupt request generated 4 5 6 7 No functions assigned TINIM2 (reserved) TINIM1 (reserved) TINIM0 (TIN0 interrupt mask) Setting this bit has no effect Setting this bit has no effect 0 : Enables interrupt request 1 : Masks (disables) interrupt request W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 — Function R 0 W — TINIR0 < H'0080 0238 > Data bus TIN0 edge b3 b7 TINIS0 F/F TINIM0 F/F (Level) MJT input interrupt 1 IRQ9 Figure 10.2.13 Block Diagram of MJT Input Interrupt 1 10-41 32171 Group User's Manual (Rev.2.00) 10 s TIN Interrupt Control Register 1 (TINIR1) D8 TINIS6 9 TINIS5 10 TINIS4 11 TINIS3 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 - 10 11 Bit Name No functions assigned TINIS3 (TIN3 interrupt status) 0 : No interrupt request 1 : Interrupt request generated 12 13 14 15 TINIM6 (reserved) TINIM5 (reserved) TINIM4 (reserved) TINIM3 (TIN3 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. Setting this bit has no effect Function R 0 W — TINIR1 < H'0080 0239 > Data bus TIN3edge b11 b15 TINIS3 F/F TINIM3 F/F (Level) MJT input interrupt 4 IRQ12 Figure 10.2.14 Block Diagram of MJT Input Interrupt 4 10-42 32171 Group User's Manual (Rev.2.00) 10 s TIN Interrupt Control Register 4 (TINIR4) D0 TINIS19 1 TINIS18 2 TINIS17 3 TINIS16 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4-7 W= Bit Name TINIS19 (TIN19 interrupt status) TINIS18 (TIN18 interrupt status) TINIS17 (TIN17 interrupt status) TINIS16 (TIN16 interrupt status) No functions assigned : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 — Function 0 : No interrupt request 1 : Interrupt request generated R W s TIN Interrupt Control Register 5 (TINIR5) D8 TINIM19 9 TINIM18 10 TINIM17 11 TINIM16 12 TINIM15 13 TINIM14 D 8 9 10 11 12 13 14 15 Bit Name TINIM19 (TIN19 interrupt mask) TINIM18 (TIN18 interrupt mask) TINIM17 (TIN17 interrupt mask) TINIM16 (TIN16 interrupt mask) TINIM15 (reserved) TINIM14 (reserved) TINIM13 (reserved) TINIM12 (reserved) Setting this bit has no effect Function 0 : Enables interrupt request 1 : Masks (disables) interrupt request R W 10-43 32171 Group User's Manual (Rev.2.00) 10 TINIR4 < H'0080 023C > TINIR5 < H'0080 023D > TIN19 edge Data bus b0 b8 TIN18 edge TINIS18 b1 b9 TIN17 edge b2 b10 TIN16 edge b3 b11 TINIS16 F/F TINIM16 F/F TINIS17 F/F TINIM17 F/F F/F TINIM18 F/F TINIS19 F/F TINIM19 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 4-source inputs (Level) MJT input interrupt 2 IRQ10 Figure 10.2.15 Block Diagram of MJT Input Interrupt 2 10-44 32171 Group User's Manual (Rev.2.00) 10 s TIN Interrupt Control Register 6 (TINIR6) D0 TINIS23 1 TINIS22 2 TINIS21 3 TINIS20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 W= Bit Name TINIS23 (TIN23 interrupt status) TINIS22 (TIN22 interrupt status) TINIS21 (TIN21 interrupt status) TINIS20 (TIN20 interrupt status) TINIM23 (TIN23 interrupt mask) TINIM22 (TIN22 interrupt mask) TINIM21 (TIN21 interrupt mask) TINIM20 (TIN20 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W TINIR6 D 0,1 2,3 4,5 6,7 8 9-10 Bit Name TOP3M (TOP3 operation mode selection) TOP2M (TOP2 operation mode selection) TOP1M (TOP1 operation mode selection) TOP0M (TOP0 operation mode selection) No functions assigned TOP05ENS (TOP0-5 enable source selection) 0XX: External TIN0 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 14,15 No functions assigned TOP05CKS (TOP0-5 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 0 – 0 – Function 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode R W Notes: • This register must always be accessed in halfwords. • Always make sure the counter has stopped and is idle before setting or changing operation modes. 10-54 32171 Group User's Manual (Rev.2.00) 10 s TOP0-5 Control Register 1 (TOP05CR1) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 8-11 12,13 14,15 Bit Name No functions assigned TOP5M (TOP5 operation mode selection) TOP4M (TOP4 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – Clock bus Input event bus 3210 3210 S clk en TOP 0 TOP 1 clk en en clk TOP 2 clk en TOP 3 clk en TOP 4 clk TIN0 (P150) TIN0S S en TOP 5 S : Selector Note: • This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.6 Outline Diagram of TOP0-5 Clock/Enable Inputs 10-55 32171 Group User's Manual (Rev.2.00) 10 s TOP6,7 Control Register (TOP67CR) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0 1 Bit Name No functions assigned TOP7ENS (TOP7 enable source selection) 2,3 TOP7M (TOP7 operation mode selection) 0: Result selected by TOP67ENS bit 1: TOP6 output 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 4,5 6,7 No functions assigned TOP6M (TOP6 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 8 9-11 No functions assigned TOP67ENS (TOP6, TOP7 enable source selection) 0XX: No selection 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 14,15 No functions assigned TOP67CKS (TOP6, TOP7 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Always make sure the counter has stopped and is idle before setting or changing operation modes. 0 – 0 – 0 – Function R 0 W – 10-56 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) S clk en TOP 6 udf clk S S en TOP 7 udf S : Selector Note: • This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.7 Outline Diagram of TOP6, TOP7 Clock/Enable Inputs 10-57 32171 Group User's Manual (Rev.2.00) 10 s TOP8-10 Control Register (TOP810CR) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0,1 2,3 4,5 6,7 8-10 11 Bit Name No functions assigned TOP10M (TOP10 operation mode selection) 00: Single-shot output mode TOP9M (TOP9 operation mode selection) TOP8M (TOP8 operation mode selection) No functions assigned TOP810ENS (TOP8-10 enable source selection) 12,13 14,15 No functions assigned TOP810CKS (TOP8-10 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 01: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Always make sure the counter has stopped and is idle before setting or changing operation modes. 0: No selection 1: Input event bus 3 0 – 01: Delayed single-shot output mode 1X: Continuous output mode 0 – Function R 0 W – 10-58 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) S clk en en TOP 8 clk TOP 9 clk S en TOP 10 S : Selector Note: • This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.8 Outline Diagram of TOP8-10 Clock/Enable Inputs 10-59 32171 Group User's Manual (Rev.2.00) 10 10.3.5 TOP Counters (TOP0CT-TOP10CT) s TOP0 Counter (TOP0CT) s TOP1 Counter (TOP1CT) s TOP2 Counter (TOP2CT) s TOP3 Counter (TOP3CT) s TOP4 Counter (TOP4CT) s TOP5 Counter (TOP5CT) s TOP6 Counter (TOP6CT) s TOP7 Counter (TOP7CT) s TOP8 Counter (TOP8CT) s TOP9 Counter (TOP9CT) s TOP10 Counter (TOP10CT) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN D 0-4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TOP10PRO (TOP10 enable protect) TOP9PRO (TOP9 enable protect) TOP8PRO (TOP8 enable protect) TOP7PRO (TOP7 enable protect) TOP6PRO (TOP6 enable protect) TOP5PRO (TOP5 enable protect) TOP4PRO (TOP4 enable protect) TOP3PRO (TOP3 enable protect) TOP2PRO (TOP2 enable protect) TOP1PRO (TOP1 enable protect) TOP0PRO (TOP0 enable protect) 0: Enables rewrite 1: Disables rewrite Function R 0 W – Note: • This register must always be accessed in halfwords. The TOP0-10 Enable Protect Register controls rewriting of the TOP0-10 count enable bits shown in the next page by enabling or disabling rewrite. 10-64 32171 Group User's Manual (Rev.2.00) 10 s TOP0-10 Count Enable Register (TOPCEN) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0-4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TOP10CEN (TOP10 count enable) TOP9CEN (TOP9 count enable) TOP8CEN (TOP8 count enable) TOP7CEN (TOP7 count enable) TOP6CEN (TOP6 count enable) TOP5CEN (TOP5 count enable) TOP4CEN (TOP4 count enable) TOP3CEN (TOP3 count enable) TOP2CEN (TOP2 count enable) TOP1CEN (TOP1 count enable) TOP0CEN (TOP0 count enable) 0: Stops count 1: Enables count Function R 0 W – Note: • This register must always be accessed in halfwords. The TOP0-10 Count Enable Register controls the operation of TOP counter. To enable the counter in software, enable the relevant TOP0-10 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOP0-10 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOP0-10 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-65 32171 Group User's Manual (Rev.2.00) 10 TOPm external enable (TOPmEEN) F/F Edge selection TINn TINnS Event bus Dn TOPm enable protect (TOPmPRO) F/F WR MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) EN-ON TOPm enable (TOPmCEN) F/F WR TOP enable control Figure 10.3.9 Configuration of the TOP Enable Circuit 10-66 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TOP single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload register value + 1) only once and stops. When after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of the reload register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload register set value + 1). In the case shown below, for example, if the reload register value = 7, then the count value = 8. Because all internal circuits operate synchronously with the count clock, a finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Count value = 8 1 Count clock Enable Counter 2 3 4 5 6 7 8 (Note 1) (7) 6 5 4 3 2 1 0 H'FFFF Reload register 7 F/F output Interrupt * A finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7. Note: • This diagram does not show detail timing information. Figure 10.3.10 Example of Counting in TOP Single-shot Output Mode 10-67 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the reload register has the initial value H'A000 set in it. (The initial value of the counter can be indeterminate, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter causing it to start counting. Thereafter, it continues counting down clock pulses until it underflows after reaching the minimum count. Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit H'FFFF Starts counting down from the reload register set value H'A000 Counter H'FFFF H'0000 Reload register H'A000 Correction register (Not used) F/F output Data inverted by enable Data inverted by underflow TOP interrupt due to underflow Note: • This diagram does not show detail timing information. Figure 10.3.11 Typical Operation in TOP Single-shot Output Mode 10-68 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts. Count value =(7+1)+(3+1)=12 1 2 3 4 5 6 7 8 9 10 11 12 Count clock Prescaler delay Enable (Note 1) (7) 6 6 4 3 +3 Counter 5 5 4 3 2 1 0 H'FFFF Reload register 7 Correction register Interrupt 3 Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7. Note: • This diagram does not show detail timing information. Figure 10.3.12 Example of Counting in TOP Single-shot Output Mode When Count is Corrected 10-69 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. In the example next page, the reload register has the initial value H'8000 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'4000 is written to the correction register when the counter has counted down to H'5000. As a result of this correction, the count has been increased to H'9000, so that the counter stops after counting a total of (H'8000 + 1 + H'4000 + 1) counts. 10-70 32171 Group User's Manual (Rev.2.00) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Disabled (by underflow) Count clock Enable bit Write to correction register H'FFFF H'FFFF H'5000+H'4000 Counter H'8000 H'5000 H'0000 Reload register H'8000 Correction register Indeterminate H'4000 F/F output Data inverted by enable Data inverted by underflow TOP interrupt due to underflow Note: • This diagram does not show detail timing information. Figure 10.3.13 Example of Counting in TOP Single-shot Output Mode When Count is Corrected 10-71 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. • When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. 10-72 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the reload register has the initial value H'FFF8 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'0014 is written to the correction register when the counter has counted down to H'FFF0. As a result of this correction, the count overflows to H'0004 and fails to count correctly. Also, an interrupt is generated for an erroneous overcount. Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit Write to correction register Overflow occurs H'(FFF0+0014) H'FFFF H'FFF8 H'FFFF Indeterminate H'FFF0 Counter H'0004 H'0000 Actual count after overflow Reload register H'FFF8 Correction register Indeterminate H'0014 F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Note: • This diagram does not show detail timing information. Figure 10.3.14 Example of Operation in TOP Single-shot Output Mode Where Count Overflows due to Correction 10-73 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TOP delayed single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function) In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops. When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Count value =(4+1)+(5+1)=11 1 2 3 4 5 6 7 8 9 10 11 Count clock Prescaler delay Enable Counter (Note 2) (5) 4 2 1 0 H'FFFF (Note 1) (4) 3 3 2 1 0 H'FFFF Reload register F/F output Interrupt 5 Underflow Underflow Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note: • This diagram does not show detail timing information. Figure 10.3.15 Example of Counting in TOP Delayed Single-shot Output Mode 10-74 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'F000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register. Then when the counter underflows next time while continuing downcount, it stops. Enabled (by writing to enable bit or by external input) Underflow (first time) Underflow (second time) Count clock Enable bit H'FFFF H'F000 Down-count starting from counter's set value H'(F000-1) Down-count starting from reload register's set value H'FFFF H'A000 Counter H'0000 Reload register H'F000 Correction register (Not used) F/F output Data inverted by underflow TOP interrupt due to underflow Data inverted by underflow Note: • This diagram does not show detail timing information. Figure 10.3.16 Typical Operation in TOP Delayed Single-shot Output 10-75 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP delayed single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts after reload. Count value after reload =(7+1)+(3+1)=12 1 2 3 4 5 6 7 8 9 10 11 12 Count clock Enable = "H" (Note 1) (7) Counter 6 5 6 4 3 +3 5 4 3 2 0 1 0 H'FFFF Reload register 7 Correction register Interrupt 3 Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7. Note: • This diagram does not show detail timing information. Figure 10.3.17 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. 10-76 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter and the reload register are initially set to H'A000 and H'F000, respectively. When the timer is enabled, the counter starts counting down and when it underflows first time after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down. In the diagram below, the value H'0008 is written to the correction register when the counter has counted down to H'9000. As a result of this correction, the counter has its count value increased to H'9008 and counts (H'F000 + 1 + H'0008 +1) after the first underflow before it stops. Underflow (first time) Count clock Enable bit Write to correction register H'FFFF H'(F000+0008+1) H'F000 Underflow (second time) Counter corrected Counter H'A000 H'0000 Reload register Correction register Indeterminate H'F000 H'0008 F/F output Data inverted by underflow TOP interrupt due to underflow Data inverted by underflow Note: • This diagram does not show detail timing information. Figure 10.3.18 Typical Operation in TOP Delayed Single-shot Output Mode when Correction Applied 10-77 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. Reload due to underflow Count clock Enable bit "H" Reload cycle Counter value H'0001 H'0000 H'FFFF Down-count starting from reloaded register value H'AAA9 H'(AAAA-1) H'AAA8 H'(AAAA-2) Reload register H'AAAA During reload cycle, you always see H'FFFF, and not the reload register value (in this case, H'AAAA). Figure 10.3.19 Counter Value Immediately after Underflow 10-78 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TOP continuous output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. 10-79 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Count value =5 Count value =6 Count value =6 1 2 3 4 5 1 2 3 4 5 6 1 2 3 4 5 6 Count clock Prescaler delay Enable Counter (Note 1) (4) 3 (Note 2) (5) 4 2 1 0 3 (Note 2) (5) 4 2 1 0 (Note 2) (5) 3 2 1 0 H'FFFF Reload register 5 F/F output Interrupt Underflow Underflow Underflow Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note: • This diagram does not show detail timing information. Figure 10.3.20 Example of Counting in TOP Continuous Output Mode 10-80 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'E000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register and continues counting down. Enabled (by writing to enable bit or by external input) Count clock Enable bit Underflow (first time) Underflow (second time) H'FFFF H'FFFF H'E000 H'A000 Down-count starting from counter's set value H'(E000-1) Down-count starting from reload register set value H'FFFF H'(E000-1) Down-count starting from reload register set value Counter H'0000 Reload register H'E000 Correction register (Not used) F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Data inverted by underflow Note: • This diagram does not show detail timing information. Figure 10.3.21 Typical Operation in TOP Continuous Output Mode 10-81 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-82 32171 Group User's Manual (Rev.2.00) 10 10.4.1 Outline of TIO MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode The following shows TIO specifications. Figure 10.4.1 shows a TIO block diagram. Table 10.4.1 Specifications of TIO (Input/Output-related 16-bit Timer) Item Number of channels Counter Reload register Measure register Timer startup Specification 10 channels 16-bit down-counter 16-bit reload register 16-bit capture register Started by writing to enable bit in software or by enabling with external input (rising/falling edge or both or high/low level) Mode selection • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode Interrupt generation DMA transfer request generation Can be generated by a counter underflow Can be generated by a counter underflow (for only the TIO8) 10-83 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Output event bus 0123 TIO 0 Reload 0/measure register IRQ0 S clk Down-counter Reload 1 register (note 1) udf S F/F11 TO 11 (P103) IRQ12 (16 bits) en/cap S clk S clk S clk S S clk en/cap en/cap TIO 3 TIO 4 udf IRQ4 IRQ0 TIN3 (P153) TIN3S en/cap en/cap TIO 1 TIO 2 udf IRQ0 S S IRQ0 F/F12 F/F13 F/F14 TO 12 (P104) TO 13 (P105) TO 14 (P106) udf S udf S F/F15 TO 15 (P107) 1/2 internal clock TCLK1 (P125) TCLK2 (P126) PRS0 PRS1 PRS2 S IRQ4 TCLK1S S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 (P93) TO 17 (P94) TO 18 (P95) TO 19 (P96) TO 20 (P97) TCLK2S S S clk en/cap TIO 6 udf IRQ4 S F/F17 S S S S clk en/cap TIO 7 udf IRQ3 S DRQ0 F/F18 clk en/cap TIO 8 udf IRQ3 S F/F19 S S 3210 3210 clk en/cap TIO 9 udf F/F20 0123 PRS0-2 : Prescaler F/F : Output flip-flop S : Selector Note 1: Reload 1 Register is used in only PWM output mode. Figure 10.4.1 Block Diagram of TIO (Input/Output-related 16-bit Timer) 10-84 32171 Group User's Manual (Rev.2.00) 10 10.4.2 Outline of Each Mode of TIO MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to a register called the "measure register." Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. In measure free-run mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. An interrupt can be generated by a counter underflow or execution of measure operation. Also, a DMA transfer request (for only the TIO8) can be generated when the counter underflows. (2) Noise processing input mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt as well as a DMA transfer request (for only the TIO8) can be generated by a counter underflow. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. 10-85 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every even time (second time, fourth time, and so on) after being enabled. Also, a DMA ttransfer request (for only the TIO8) can be generated every time the counter underflows. (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt as well as a DMA transfer request (for only the TIO8) can be generated when the counter underflows. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt and a DMA transfer request (for only the TIO8) can be generated when the counter underflows first time and next. 10-86 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt as well as a DMA transfer request (for only the TIO8) can be generated each time the counter underflows. • Because the timer operates synchronously with the count clock, there is a count clockdependent delay from when the timer is enabled till it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, the F/F output is inverted synchronously with the count clock. Write to the enable bit BCLK Count clock period Count clock Enable F/F operation (Note 1) Count clock-dependent delay Inverted Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Figure 10.4.2 Count Clock Dependent Delay 10-87 32171 Group User's Manual (Rev.2.00) 10 10.4.3 TIO Related Register Map MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) The diagram below shows a TIO related register map. Address D0 +0 Address D7 D8 +1 Address D15 H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306 TIO0 Counter (TIO0CT) TIO0 Reload 1 Register (TIO0RL1) TIO0 Reload 0/ Measure Register (TIO0RL0) H'0080 0310 H'0080 0312 H'0080 0314 H'0080 0316 H'0080 0318 H'0080 031A H'0080 031C TIO1 Counter (TIO1CT) TIO1 Reload 1 Register (TIO1RL1) TIO1 Reload 0/ Measure Register (TIO1RL0) TIO0-3 Control Register 0 (TIO03CR0) TIO0-3 Control Register 1 (TIO03CR1) H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 TIO2 Counter (TIO2CT) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 TIO3 Counter (TIO3CT) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) Blank addresses are reserved. Note: • The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.4.3 TIO Related Register Map (1/3) 10-88 32171 Group User's Manual (Rev.2.00) 10 Address D0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H'0080 0340 H'0080 0342 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A TIO4 Counter (TIO4CT) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) TIO4 Control Register (TIO4CR) TIO5 Control Register (TIO5CR) H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356 TIO5 Counter (TIO5CT) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO6 Counter (TIO6CT) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR) H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376 TIO7 Counter (TIO7CT) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) Blank addresses are reserved. Figure 10.4.4 TIO Related Register Map (2/3) 10-89 32171 Group User's Manual (Rev.2.00) 10 Address D0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H'0080 0380 H'0080 0382 H'0080 0384 H'0080 0386 H'0080 0388 H'0080 038A TIO8 Counter (TIO8CT) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/ Measure Register (TIO8RL0) TIO8 Control Register (TIO8CR) TIO9 Control Register (TIO9CR) H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396 TIO9 Counter (TIO9CT) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) H'0080 03BC H'0080 03BE TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) Blank addresses are reserved. Note: • The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.4.5 TIO Related Register Map (3/3) 10-90 32171 Group User's Manual (Rev.2.00) 10 10.4.4 TIO Control Registers MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) The TIO control registers are used to select TIO0-9 operation modes (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output, or continuous output mode), as well as select the counter enable and counter clock sources. Following eight TIO control registers are provided for each timer group. • TIO0-3 Control Register 0 (TIO03CR0) • TIO0-3 Control Register 1 (TIO03CR1) • TIO4 Control Register (TIO4CR) • TIO5 Control Register (TIO5CR) • TIO6 Control Register (TIO6CR) • TIO7 Control Register (TIO7CR) • TIO8 Control Register (TIO8CR) • TIO9 Control Register (TIO9CR) 10-91 32171 Group User's Manual (Rev.2.00) 10 s TIO0-3 Control Register 0 (TIO3CR0) D0 TIO3 EEN MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0 Bit Name TIO3EEN (TIO3 external input enable) (Note 1) 1-3 TIO3M (TIO3 operation mode selection) Function 0: Disables external input 1: Enables external input 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode 4 5-7 TIO2ENS (reserved) TIO2M (TIO2 operation mode selection) (Note 2) Setting this bit has no effect 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Use inhibited 8 TIO1ENS (reserved) Setting this bit has no effect (Continues to the next page) Note 1: To select TIO3 enable/measurement input source, use the TIO4 Control Register TIO34ENS (TIO3,4 enable/measurement input source select) bits. Note 2: Even when this bit is 0 (external input disabled) during measurement (free-run/clear) input mode, if a capture signal is entered from an external device, the counter value at that point in time is written to the measurement register. However, because if this bit is 0 (external input disabled) during measurement clear input mode, the counter value may not be initialized (H’FFFF) upon capturing, make sure this bit = 1 (external input enabled) before using the measurement clear function. Notes: • During measurement (free-run/clear) input mode, the TIO1 and TIO2 timers do not have the capture function. • This register must always be accessed in half word. • Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-92 32171 Group User's Manual (Rev.2.00) 10 (Continued from the preceding page) D 9-11 Bit Name TIO1M (TIO1 operation mode selection) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Function 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Use inhibited R W 12 TIO0ENS (TIO0 enable/ measure input source selection) 0: No selection 1: External input TIN3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode 13-15 TIO0M (TIO0 operation mode selection) Notes: • This register must always be accessed in halfwords. • Always make sure the counter has stopped and is idle before setting or changing operation modes. Clock bus Input event bus 3210 3210 S clk TIN3 (P153) TIN3S S clk S clk S clk en/cap TIO 3 en/cap TIO 2 en/cap TIO 1 en/cap TIO 0 S clk en/cap TIO 4 S 3210 3210 S : Selector Note: • This diagram is shown for the explanation of TIO control registers, and is partly omitted. Figure 10.4.6 Outline Diagram of TIO0-4 Clock/Enable Inputs 10-93 32171 Group User's Manual (Rev.2.00) 10 s TIO0-3 Control Register 1 (TIO03CR1) D8 9 10 11 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8-13 14,15 Bit Name No functions assigned TIO03CKS (TIO0-3 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Function R 0 W – 10-94 32171 Group User's Manual (Rev.2.00) 10 s TIO4 Control Register (TIO4CR) D0 TIO4CKS 1 2 TIO4EEN 3 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0, 1 Bit Name TIO4CKS (TIO4 clock source selection) Function 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2 TIO4EEN (Note 1) (TIO4 external input enable) 3,4 TIO34ENS (TIO3,4 enable/measure input source selection) 5-7 TIO4M (TIO4 operation mode selection) 0: Disables external input 1: Enables external input 0X: No selection 10: Input event bus 2 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to 0 (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. However, because in measure clear input mode, if this bit = 0 (external input disabled), the counter value is not initialized (H'FFFF) upon capture, we recommend that this bit be set to 1 (external input enabled) when using measure clear input mode. Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-95 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TCLK1 (P125) TCLK1S S S clk en/cap TIO 5 TCLK2 (P126) TCLK2S S S clk en/cap TIO 6 S S clk en/cap TIO 7 S S clk en/cap TIO 8 S S 3210 3210 clk en/cap TIO 9 S : Selector Note: • This is an outline diagram shown for the explanation of TIO Control Register. Figure 10.4.7 Outline Diagram of TIO5-9 Clock/Enable Inputs 10-96 32171 Group User's Manual (Rev.2.00) 10 s TIO5 Control Register (TIO5CR) D8 9 TIO5CKS 10 11 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8-10 Bit Name TIO5CKS (TIO5 clock source selection) Function 0XX: External input TCLK1 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11,12 TIO5ENS (TIO5 enable/measure input source selection) 13-15 TIO5M (TIO5 operation mode selection) 0X: No selection 10: No selection 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-97 32171 Group User's Manual (Rev.2.00) 10 s TIO6 Control Register (TIO6CR) D0 1 TIO6CKS 2 3 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0-2 Bit Name TIO6CKS (TIO6 clock source selection) Function 0XX: External input TCLK2 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3,4 TIO6ENS (TIO6 enable/measure input source selection) 5-7 TIO6M (TIO6 operation mode selection) 0X: No selection 10: Input event bus 2 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-98 32171 Group User's Manual (Rev.2.00) 10 s TIO7 Control Register (TIO7CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8 9,10 Bit Name No functions assigned TIO7CKS (TIO7 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO7ENS (TIO7 enable/measure input source selection) 13-15 TIO7M (TIO7 operation mode selection) 0X: No selection 10: Input event bus 0 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – 10-99 32171 Group User's Manual (Rev.2.00) 10 s TIO8 Control Register (TIO8CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0,1 Bit Name TIO8CKS (TIO8 clock source selection) Function 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2-4 TIO8ENS (TIO8 enable/measure input source selection) 0XX: No selection 100: No selection 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5-7 TIO8M (TIO8 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-100 32171 Group User's Manual (Rev.2.00) 10 s TIO9 Control Register (TIO9CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8 9,10 Bit Name No functions assigned TIO9CKS (TIO9 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO9ENS (TIO9 enable/measure input source selection) 13-15 TIO9M (TIO9 operation mode selection) 0X: No selection 10: Input event bus 1 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: • Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – 10-101 32171 Group User's Manual (Rev.2.00) 10 10.4.5 TIO Counter (TIO0CT-TIO9CT) s TIO0 Counter (TIO0CT) s TIO1 Counter (TIO1CT) s TIO2 Counter (TIO2CT) s TIO3 Counter (TIO3CT) s TIO4 Counter (TIO4CT) s TIO5 Counter (TIO5CT) s TIO6 Counter (TIO6CT) s TIO7 Counter (TIO7CT) s TIO8 Counter (TIO8CT) s TIO9 Counter (TIO9CT) D0 1 2 3 4 5 6 7 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 8 9 10 11 12 13 14 D15 TIO0CT-TIO9CT D 0-15 W= Bit Name TIO0CT-TIO9CT Function 16-bit counter value R W : Write to this register is not accepted in PWM output mode. Note: • This register must always be accessed in halfwords. The TIO Counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. The counter cannot be written to during PWM output mode. 10-102 32171 Group User's Manual (Rev.2.00) 10 10.4.6 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0) 9 10 11 12 13 14 D15 s TIO0 Reload 0/ Measure Register (TIO0RL0) s TIO1 Reload 0/ Measure Register (TIO1RL0) s TIO2 Reload 0/ Measure Register (TIO2RL0) s TIO3 Reload 0/ Measure Register (TIO3RL0) s TIO4 Reload 0/ Measure Register (TIO4RL0) s TIO5 Reload 0/ Measure Register (TIO5RL0) s TIO6 Reload 0/ Measure Register (TIO6RL0) s TIO7 Reload 0/ Measure Register (TIO7RL0) s TIO8 Reload 0/ Measure Register (TIO8RL0) s TIO9 Reload 0/ Measure Register (TIO9RL0) D0 1 2 3 4 5 6 7 8 TIO0RL0-TIO9RL0 D 0-15 W= Bit Name TIO0RL0-TIO9RL0 Function 16-bit reload register value R W : Write to this register is not accepted in measure input mode. Note: • This register must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading TIO Count Registers (TIO0CT-TIO9CT) with data, and as a measure register during measure input mode. These registers are disabled against write during measure input mode. It is in the following cases that the content of reload 0 register is loaded into the counter: • When after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows • When the counter is enabled in single-shot mode • When the counter underflowed in delayed single-shot or continuous mode • When the counter is enabled in PWM mode and when the counter value set by reload 1 register underflowed Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. When used as a measure register, the counter value is latched into the measure register by an event input. 10-103 32171 Group User's Manual (Rev.2.00) 10 s TIO0 Reload 1 Register (TIO0RL1) s TIO1 Reload 1 Register (TIO1RL1) s TIO2 Reload 1 Register (TIO2RL1) s TIO3 Reload 1 Register (TIO3RL1) s TIO4 Reload 1 Register (TIO4RL1) s TIO5 Reload 1 Register (TIO5RL1) s TIO6 Reload 1 Register (TIO6RL1) s TIO7 Reload 1 Register (TIO7RL1) s TIO8 Reload 1 Register (TIO8RL1) s TIO9 Reload 1 Register (TIO9RL1) D0 1 2 3 4 5 6 7 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) 8 9 10 11 12 13 14 D15 TIO0RL1-TIO9RL1 D 0-15 Bit Name TIO0RL1-TIO9RL1 Function 16-bit reload register value R W Note: • This register must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload data into the TIO Counter Registers (TIO0CTTIO9CT). The content of reload 1 register is loaded into the counter in the following cases: • When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. 10-104 32171 Group User's Manual (Rev.2.00) 10 10.4.8 TIO Enable Control Registers MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) s TIO0-9 Enable Protect Register (TIOPRO) D 0-5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TIO9PRO (TIO9 Enable Protect) TIO8PRO (TIO8 Enable Protect) TIO7PRO (TIO7 Enable Protect) TIO6PRO (TIO6 Enable Protect) TIO5PRO (TIO5 Enable Protect) TIO4PRO (TIO4 Enable Protect) TIO3PRO (TIO3 Enable Protect) TIO2PRO (TIO2 Enable Protect) TIO1PRO (TIO1 Enable Protect) TIO0PRO (TIO0 Enable Protect) 0: Enables rewrite 1: Disables rewrite Function R 0 W – Note: • This register must always be accessed in halfwords. The TIO0-9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling rewrite. 10-105 32171 Group User's Manual (Rev.2.00) 10 s TIO0-9 Count Enable Register (TIOCEN) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0-5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TIO9CEN (TIO9 count enable) TIO8CEN (TIO8 count enable) TIO7CEN (TIO7 count enable) TIO6CEN (TIO6 count enable) TIO5CEN (TIO5 count enable) TIO4CEN (TIO4 count enable) TIO3CEN (TIO3 count enable) TIO2CEN (TIO2 count enable) TIO1CEN (TIO1 count enable) TIO0CEN (TIO0 count enable) 0: Stops count 1: Enables count Function R 0 W – Note: • This register must always be accessed in halfwords. The TIO0-9 Count Enable Register controls operation of TIO counters. To enable the counter in software, enable the relevant TIO0-9 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TIO0-9 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TIO0-9 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-106 32171 Group User's Manual (Rev.2.00) 10 TIOm external enable (TIOmEEN or TIOmENS) F/F Edge selection TINnS Event bus Dn TIOm enable protect (TIOmPRO) F/F MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) EN-ON TIOm enable (TIOmCEN) F/F WR TIO enable control WR Figure 10.4.8 Configuration of the TIO Enable Circuit 10-107 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.9 Operation in TIO Measure Free-run/Clear Input Modes (1) Outline of TIO measure free-run/clear input modes In TIO measure free-run/clear input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. An interrupt can be generated by a counter underflow or execution of measure operation. Also, a DMA transfer request (for only the TIO8) can be generated when the counter underflows. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. When the counter underflows after reaching the minimum count, it starts counting down from H'FFFF again. In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. 10-108 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit) Measure event (capture) occurs Measure event (capture) occurs Count clock Enable bit H'FFFF Indeterminate value H'9000 Counter H'7000 H'0000 Measure register Indeterminate H'7000 H'9000 TIN interrupt TIN interrupt by external event input TIO interrupt TIO interrupt by underflow TIO8 DMA transfer request TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. TIN interrupt by external event input Figure 10.4.9 Typical Operation in Measure Free-run Input Mode 10-109 32171 Group User's Manual (Rev.2.00) 10 Enabled (by writing to enable bit) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Measure event (capture) occurs Count clock Enable bit H'FFFF Indeterminate value Counter H'7000 H'0000 Measure register Indeterminate H'7000 TIN interrupt TIN interrupt by external event input TIO interrupt TIO interrupt by underflow TIO8 DMA transfer request TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. Figure 10.4.10 Typical Operation in Measure Clear Input Mode 10-110 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Precautions to be observed when using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched into the measure register. 10-111 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.10 Operation in TIO Noise Processing Input Mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The valid count value is (reload 0 register set value + 1). The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Also, an interrupt as well as a DMA transfer request (for only the TIO8) can be generated by a counter underflow. Enabled (by writing to enable bit or by external input) Count clock Disabled by underflow Enable bit External input (noise processing) Invalid H'FFFF Invalid Valid signal width H'A000 Counter H'0000 Reload 0 register TIO interrupt H'A000 TIO interrupt by underflow TIO8 DMA transfer request TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. Figure 10.4.11 Typical Operation in Noise Processing Input Mode 10-112 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TIO PWM output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.11 Operation in TIO PWM Output Mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every even time (second time, fourth time, and so on) after being enabled. Also, a DMA transfer request (for only the TIO8) can be generated every time the counter underflows. Note that TIO's PWM output mode does not have the correction function. 10-113 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit Underflow or by external input) (first time) Underflow (second time) Count clock Enable bit Down-count starting from reload 0 register set value H'FFFF H'C000 H'(C000-1) H'(A000-1) H'A000 H'A000 Down-count starting from reload 1 register set value Down-count starting from reload 0 register set value Counter H'0000 Reload 0 register H'A000 Reload 1 register H'C000 F/F output Data inverted by enable TIO interrupt by underflow PWM output period TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. Data inverted by underflow Data inverted by underflow Figure 10.4.12 Typical Operation in PWM Output Mode 10-114 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Internal bus Reload 1 TIOnRL1 Reload1WR Reload0WR Reload 0 Buffer TIOnRL0 PWM mode control Prescaler output 16-bit counter F/F TO Figure 10.4.13 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. (3) Precautions on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge. • Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled. 10-115 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 1 Reload 0 register Reload 1 register H'1000 Write to reload 0 (reload 1 data latched) H'8000 H'9000 H'2000 Old PWM output period F/F output New PWM output period Operation by new reload value written Enlarged view New PWM output period Count clock Counter H'0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output Timing at which reload 1 and reload 0 registers are updated PWM period latched H'1000 H'2000 H'2000 H'8000 H'9000 H'9000 H'0000 H'FFFF H'7FFF H'7FFE Note: • This diagram does not show detail timing information. (b) When reload register updates take effect in the next period (reflected one period later) Write to reload 1 Reload 0 register Reload 1 register H'1000 H'2000 H'9000 Write to reload 0 (reload 1 data latched) H'8000 Old PWM output period F/F output Old PWM output period Operation by old reload value Enlarged view Old PWM output period Count clock Counter H'0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output PWM period latched Timing at which reload 1 and reload 0 registers are updated H'2000 H'2000 H'1000 H'9000 H'9000 H'8000 H'0000 H'FFFF H'0FFF H'0FFE Note: • This diagram does not show detail timing information. Figure 10.4.14 Reload 0 and Reload 1 Register Updates in PWM Output Mode 10-116 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TIO single-shot output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt as well as a DMA transfer request (for only the TIO8) can be generated when the counter underflows. The count value is (reload 0 register set value + 1). For details about count operation, also refer to Section 10.3.9, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-117 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit or by external input) Count clock Enable bit Disabled (by underflow) H'FFFF H'A000 Counter Counts down starting from reload 0 register set value H'0000 Reload 0 register H'A000 Reload 1 register (Not used) F/F output Data inverted by enable TIO interrupt by underflow Data inverted by underflow TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. Figure 10.4.15 Typical Operation in TIO Single-shot Output Mode (without Correction Function) 10-118 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt and a DMA transfer request (for only the TIO8) can be generated when the counter underflows first time and next . The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.10, "Operation in TOP Delayed Single-shot Output Mode." (2) Precautions to be observed when using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-119 32171 Group User's Manual (Rev.2.00) 10 Enabled (by writing to enable bit or by external input) Count clock Enable bit MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Underflow (first time) Underflow (second time) H'FFFF H'F000 Down-count starting from counter set value H'EFFF Down-count starting from reload 0 register set value H'A000 Counter H'0000 Reload 0 register H'F000 Reload 1 register (Not used) F/F output Data inverted by underflow TIO interrupt by underflow Data inverted by underflow TIO8 DMA transfer request by underflow Note: • This diagram does not show detail timing information. Figure 10.4.16 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function) 10-120 32171 Group User's Manual (Rev.2.00) 10 (1) Outline of TIO continuous output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt as well as a DMA transfer request (for only the TIO8) can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output Mode (Without Correction Function) ." (2) Precautions to be observed when using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-121 32171 Group User's Manual (Rev.2.00) 10 Enabled (by writing to enable bit or by external input) Count clock Enable bit H'FFFF MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Underflow (first time) Underflow (second time) H'DFFF H'E000 Down-count starting from counter set value Down-count starting from reload 0 register set value H'DFFF Down-count starting from reload 0 register set value H'A000 Counter H'0000 Reload 0 register H'E000 Reload 1 register (Not used) F/F output Data inverted by enable TIO interrupt by underflow TIO8 DMA transfer request by underflow Data inverted by underflow Data inverted by underflow Note: • This diagram does not show detail timing information. Figure 10.4.17 Typical Operation in TIO Continuous Output Mode (without Correction Function) 10-122 32171 Group User's Manual (Rev.2.00) 10 10.5 TMS (Input-related 16-bit Timer) 10.5.1 Outline of TMS MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total eight channels. The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS. Table 10.5.1 Specifications of TMS (Input-related 16-bit Timer) Item Number of channels Counter Measure register Timer startup Interrupt generation Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) 16-bit up-counter x 2 16-bit measure register x 8 Started by writing to enable bit in software Can be generated by a counter overflow 10.5.2 Outline of TMS Operation In TMS, when the timer is started by writing to the enable bit in software, the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. TIN interrupts can be generated by entering an external measurement signal (no TIN interrupts available for TMS0), and TMS interrupts can be generated by an overflow signal from the counter. 10-123 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) Output event bus 0123 TMS 0 ovf TCLK3 (P127) TCLK3S S clk Counter (16 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ7 cap3 S cap2 cap1 cap0 S S S S IRQ10 clk cap3 S TMS 1 cap2 cap1 ovf cap0 IRQ7 TIN16 (P130) TIN17 (P131) TIN18 (P132) TIN19 (P133) TIN16S IRQ10 TIN17S IRQ10 S TIN18S DRQ5 IRQ10 S TIN19S DRQ6 3210 3210 S 0123 S : Selector Figure 10.5.1 Block Diagram of TMS (Input-related 16-bit Timer) • Because the timer operates synchronously with the count clock, there is a count clockdependent delay from when the timer is enabled tilll it actuually starts operating. Write to the enable bit BCLK Count clock period Count clock Enable Count clock-dependent delay Figure 10.5.2 Count Clock-Dependent Delay 10-124 32171 Group User's Manual (Rev.2.00) 10 10.5.3 TMS Related Register Map The diagram below shows a TMS related register map. MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) Address D0 +0 Address D7 D8 +1 Address D15 H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) TMS1 Control Register (TMS1CR) ~ ~ H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) ~ ~ Blank addresses are reserved. Note: • The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.5.3 TMS Related Register Map 10-125 32171 Group User's Manual (Rev.2.00) 10 10.5.4 TMS Control Registers MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) The TMS control registers are used to select TMS0/1 input events and the counter clock source, as well as control counter startup. Following two TMS control registers are included: • TMS0 Control Register (TMS0CR) • TMS1 Control Register (TMS1CR) s TMS0 Control Register (TMS0CR) D 0 Bit Name TMS0SS0 (TMS0 measure 0 source selection) 1 TMS0SS1 (TMS0 measure 1 source selection) 2 TMS0SS2 (TMS0 measure 2 source selection) 3 TMS0SS3 (TMS0 measure 3 source selection) 4,5 TMS0CKS (TMS0 clock source selection) Function 0: No selection 1: Input event bus 0 0: No selection 1: Input event bus 1 0: No selection 1: Input event bus 2 0: No selection 1: Input event bus 3 00: External input TCLK3 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 7 No functions assigned TMS0CEN (TMS0 count enable) 0: Count stops 1: Count starts 0 – R W 10-126 32171 Group User's Manual (Rev.2.00) 10 s TMS1 Control Register (TMS1CR) MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) D 8 Bit Name TMS1SS0 (TMS1 measure 0 source selection) 9 TMS1SS1 (TMS1 measure 1 source selection) 10 TMS1SS2 (TMS1 measure 2 source selection) 11 TMS1SS3 (TMS1 measure 3 source selection) 12 13 No functions assigned TMS1CKS (TMS1 clock source selection) 14 15 No functions assigned TMS1CEN (TMS1 count enable) 0: Count stops 1: Count starts 0: Clock bus 0 1: Clock bus 3 0 – Function 0: External input TIN19 1: Input event bus 0 0: External input TIN18 1: Input event bus 1 0: External input TIN17 1: Input event bus 2 0: External input TIN16 1: Input event bus 3 0 – R W 10-127 32171 Group User's Manual (Rev.2.00) 10 10.5.5 TMS Counter (TMS0CT, TMS1CT) s TMS0 Counter (TMS0CT) s TMS1 Counter (TMS1CT) D0 1 2 3 4 5 6 7 8 9 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10 11 12 13 14 D15 TMS0CT, TMS1CT D 0-15 Bit Name TMS0CT, TMS1CT Function 16-bit counter value R W Note: • This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counter can be read during operation. 10-128 32171 Group User's Manual (Rev.2.00) 10 s TMS0 Measure 3 Register (TMS0MR3) s TMS0 Measure 2 Register (TMS0MR2) s TMS0 Measure 1 Register (TMS0MR1) s TMS0 Measure 0 Register (TMS0MR0) s TMS1 Measure 3 Register (TMS1MR3) s TMS1 Measure 2 Register (TMS1MR2) s TMS1 Measure 1 Register (TMS1MR1) s TMS1 Measure 0 Register (TMS1MR0) MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TMS0MR3-0, TMS1MR3-0 D 0-15 Bit Name TMS0MR3-TMS0MR0 TMS1MR3-TMS1MR0 Notes: • This register is a read-only register. • This register can be accessed in either byte or halfword. Function 16-bit counter value R W – The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. 10-129 32171 Group User's Manual (Rev.2.00) 10 10.5.7 Operation of TMS Measure Input (1) Outline of TMS measure input MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) In TMS measure input, the counter starts counting up clock pulses when the timer is actuated by writing to the enable bit in software. When event input is entered to TMS while the timer is operating, the counter value is latched into measure registers 0-3. The timer stops at the same time count is disabled by writing to the enable bit. A TIN interrupt can be generated by entering a measure signal from an external device (for TMS1 only; no TIN interrupts available for TMS0). Also, when the counter overflows, a TMS interrupt can be generated. Enabled Measure Measure (by writing to event 0 event 1 Overflow enable bit) occurs occurs occurs Count clock Measure event 0 occurs Measure event 1 occurs Enable bit H'FFFF H'D000 H'C000 Counter Indeterminate value H'0000 H'8000 H'6000 Measure 0 register TIN19 interrupt (Note1) Measure 1 register TIN18 interrupt (Note1) TMS interrupt by overflow Indeterminate H'8000 H'6000 Indeterminate H'C000 H'D000 Note1: TIN interrupts can be generated by entering an external measurement signal for TMS1 only (No TIN interrupts available for TMS0). Note: • This diagram does not show detail timing information. Figure 10.5.4 Typical Operation in TMS Measure Input 10-130 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) (2) Precautions to be observed when using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched to the measure register. 10-131 32171 Group User's Manual (Rev.2.00) 10 10.6 TML (Input-related 32-bit Timer) 10.6.1 Outline of TML MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML. The diagram in the next page shows a block diagram of TML. Table 10.6.1 Specifications of TML (Input-related 32-bit Timer) Item Number of channels Input clock Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Divided-by-2 frequency of the internal peripheral operating clock (e.g., 10.0 MHz when using 20 MHz internal peripheral operating clock) or clock bus 1 input Counter Measure register Timer startup 32-bit up-counter × 2 32-bit measure register × 8 Starts counting after exiting reset 10-132 32171 Group User's Manual (Rev.2.00) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) Output event bus 0123 TML0 1/2 internal peripheral clock S clk Counter (32 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ11 cap3 S cap2 cap1 cap0 TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) TIN20S IRQ11 TIN21S IRQ11 S S IRQ11 TIN22S TIN23S S TML1 S clk Counter (32 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 cap3 S S S cap2 cap1 cap0 S 3210 3210 0123 S : Selector Figure 10.6.1 Block Diagram of TML (Input-related 32-bit Timer) 10.6.2 Outline of TML Operation In TML, the counter starts counting upon deassertion of the reset input signal. The counter is a 32bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When the reset input signal is deasserted, the counter starts operating with a divided-by-2 frequency of the internal peripheral clock, and cannot be stopped once it has started. The counter is idle only when the device remains reset. TIN interrupts can be generated by entering an external measurement signal (for TML0 only; no TIN interrupts available for TML1). However, the TML does not have counter overflow interrupts. 10-133 32171 Group User's Manual (Rev.2.00) 10 10.6.3 TML Related Register Map The diagram below shows a TML related register map. MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) Address D0 +0 Address D7 D8 +1 Address D15 H'0080 03E0 H'0080 03E2 TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) H'0080 03EA TML0 Control Register (TML0CR) H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA H'0080 03FC H'0080 03FE TML0 Measure 3 Register, High (TML0MR3H) TML0 Measure 3 Register, Low (TML0MR3L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 0 Register, High (TML0MR0H) TML0 Measure 0 Register, Low (TML0MR0L) H'0080 0FE0 H'0080 0FE2 TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) H'0080 0FEA TML1 Control Register (TML1CR) H'0080 0FF0 H'0080 0FF2 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA H'0080 0FFC H'0080 0FFE TML1 Measure 3 Register, High (TML1MR3H) TML1 Measure 3 Register, Low (TML1MR3L) TML1 Measure 2 Register, High (TML1MR2H) TML1 Measure 2 Register, Low (TML1MR2L) TML1 Measure 1 Register, High (TML1MR1H) TML1 Measure 1 Register, Low (TML1MR1L) TML1 Measure 0 Register, High (TML1MR0H) TML1 Measure 0 Register, Low (TML1MR0L) Blank addresses are reserved. Note: • The registers enclosed in thick frames must always be accessed in words. Figure 10.6.2 TML Related Register Map 10-134 32171 Group User's Manual (Rev.2.00) 10 10.6.4 TML Control Registers s TML0 Control Register (TML0CR) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D 8 Bit Name TML0SS0 (TML0 measure 0 source selection) 9 TML0SS1 (TML0 measure 1 source selection) 10 TML0SS2 (TML0 measure 2 source selection) 11 TML0SS3 (TML0 measure 3 source selection) 12-14 15 No functions assigned TML0CKS (TML0 clock source selection) 0: 1/2 internal peripheral clock 1: Clock bus 1 Function 0: External input TIN23 1: Input event bus 0 0: External input TIN22 1: Input event bus 1 0: External input TIN21 1: Input event bus 2 0: External input TIN20 1: Input event bus 3 0 – R W The TML0 Control Register is used to select TML0 input event and the counter clock source. Note: • The counter can be written normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. 10-135 32171 Group User's Manual (Rev.2.00) 10 s TML1 Control Register (TML1CR) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D 8 Bit Name TML1SS0 (TML1 measure 0 source selection) 9 TML1SS1 (TML1 measure 1 source selection) 10 TML1SS2 (TML1 measure 2 source selection) 11 TML1SS3 (TML1 measure 3 source selection) 12-14 15 No functions assigned TML1CKS (TML1 clock source selection) 0: 1/2 internal peripheral clock 1: Clock bus 1 Function 0: No selection 1: Input event bus 0 0: No selection 1: Input event bus 1 0: No selection 1: Input event bus 2 0: No selection 1: Input event bus 3 0 – R W The TML1 Control Register is used to select TML1 input event and the counter clock source. Note: • The counter can be written normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. 10-136 32171 Group User's Manual (Rev.2.00) 10 10.6.5 TML Counters s TML0 Counter, High (TML0CTH) s TML0 Counter, Low (TML0CTL) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTH (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTL (16 low-order bits) D 0-15 Bit Name TML0CTH TML0CTL Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W Note: • This register must always be accessed in words (32 bits) beginning with the address of TML0CTH. The TML0 Counter is a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The TML0CTH register accommodates the 16 high-order bits, and the TML0CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read duaring operation. 10-137 32171 Group User's Manual (Rev.2.00) 10 s TML1 Counter, High (TML1CTH) s TML1 Counter, Low (TML1CTL) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTH (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTL (16 low-order bits) D 0-15 Bit Name TML1CTH TML1CTL Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W Note: • This register must always be accessed in words (32 bits) beginning with the address of TML1CTH. The TML1 Counter is a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The TML1CTH register accommodates the 16 high-order bits, and the TML1CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read during operation. 10-138 32171 Group User's Manual (Rev.2.00) 10 10.6.6 TML Measure Registers s TML0 Measure 3 Register (TML0MR3H) s TML0 Measure 3 Register (TML0MR3L) s TML0 Measure 2 Register (TML0MR2H) s TML0 Measure 2 Register (TML0MR2L) s TML0 Measure 1 Register (TML0MR1H) s TML0 Measure 1 Register (TML0MR1L) s TML0 Measure 0 Register (TML0MR0H) s TML0 Measure 0 Register (TML0MR0L) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0MR3H-TML0MR0H (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0MR3L-TML0MR0L (16 low-order bits) D 0-15 Bit Name TML0MR3H-0H TML0MR3L-0L Notes: • These registers are a read-only register. • These registers must always be accessed in words (32 bits) beginning with a word boundary. Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W – The TML0 Measure Registers are used to latch counter contents upon event input. The TML0 Measure Registers are configured with 32 bits, the TML0MR3H-0H accommodating the 16 highorder bits, and the TML0MR3L-0L accommodating the 16 low-order bits. The TML0 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. 10-139 32171 Group User's Manual (Rev.2.00) 10 s TML1 Measure 3 Register (TML1MR3H) s TML1 Measure 3 Register (TML1MR3L) s TML1 Measure 2 Register (TML1MR2H) s TML1 Measure 2 Register (TML1MR2L) s TML1 Measure 1 Register (TML1MR1H) s TML1 Measure 1 Register (TML1MR1L) s TML1 Measure 0 Register (TML1MR0H) s TML1 Measure 0 Register (TML1MR0L) D0 1 2 3 4 5 6 7 8 9 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10 11 12 13 14 D15 TML1MR3H-TML1MR0H (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1MR3L-TML1MR0L (16 low-order bits) D 0-15 Bit Name TML1MR3H-0H TML1MR3L-0L Notes: • These registers are a read-only register. • These registers must always be accessed in words (32 bits) beginning with a word boundary. Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W – The TML1 Measure Registers are used to latch counter contents upon event input. The TML1 Measure Registers are configured with 32 bits, the TML1MR3H-0H accommodating the 16 highorder bits, and the TML1MR3L-0L accommodating the 16 low-order bits. The TML1 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. 10-140 32171 Group User's Manual (Rev.2.00) 10 10.6.7 Operation of TML Measure Input (1) Outline of TML measure input MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) In TML measure input, the counter starts counting up clock pulses upon deassertion of the reset input signal. When event input is entered to measure registers 0-3, the counter value is latched into the measure registers. A TIN interrupt can be generated by entering an external measure signal. (For TML0 only; No TIN interrupts are available for TML1.) However, no counter overflow interrupts are available. Enabled Measure (by deassertion event 0 of reset signal) occurs Measure event 1 occurs Overflow occurs Measure event 0 occurs Measure event 1 occurs Count clock Reset H'FFFF FFFF H'C000 0000 H'D000 0000 Counter (32 bits) H'8000 0000 H'6000 0000 Indeterminate value H'0000 0000 Measure 0 register TIN23 interrupt (Note1) Measure 1 register TIN22 interrupt (Note1) Indeterminate H'8000 0000 H'6000 0000 Indeterminate H'C000 0000 H'D000 0000 Note1: TIN interrupts can be generated by entering an external measurement signal for TML0 only (No TIN interrupts available for TML1). Note: • This diagram does not show detail timing information. Figure 10.6.3 Typical Operation in TML Measure Input 10-141 32171 Group User's Manual (Rev.2.00) 10 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) (2) Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched to the measure register. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the counter cannot be written normally. Therefore, when operating with any clock other than the 1/2 internal peripheral clock, do not write to the counter. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the captured value is one that leads the actual counter value by one clock period. However, during the 1/2 internal peripheral clock interval from the count clock, this problem does not occur and the counter value is captured at exact timing. The diagram below shows the relationship between counter operation and the valid data that can be captured. • When 1/2 internal peripheral clock is selected 1/2 internal peripheral clock Counter A B C D E F Capture A B C D E F • When clock bus 1 is selected 1/2 internal peripheral clock Count clock Counter A B C Capture B C D Figure 10.6.4 Mistimed Counter Value and Captured Value 10-142 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 11 A-D CONVERTER 11.1 Outline of A-D Converter 11.2 A-D Converter Related Registers 11.3 Functional Description of A-D Converter 11.4 Precautions on Using A-D Converter 11 11.1 Outline of A-D Converter A-D CONVERTER 11.1 Outline of A-D Converter The 32171 contains a 10-bit resolution A-D converter based on successive approximation method. A total of 16 analog input pins (channels) from AD0IN0 to AD0IN15 are available. The A-D conversion results can be read out in either 8 bits or 10 bits. For A-D conversion, there are following conversion modes and operation modes: (1) Conversion mode • A-D conversion mode: Ordinary mode in which analog input voltages are converted into digital quantities. • Comparator mode (Note 1): A mode in which analog input voltage is compared with a preset comparison voltage to only find the relative magnitude of two quantities. (Single mode only) (2) Operation mode • Single mode: Analog input voltage in one channel is A-D converted once or comparated (Note 1) with a given quantity. • Scan mode: Analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. (3) Types of scan modes • Single-shot scan mode: Scan operation is performed for one machine cycle. • Continuous scan mode: Scan operation is performed repeatedly until stopped. (4) Special operation mode • Forcible single mode execution during scan mode: Conversion is forcibly executed in single mode during scan operation. • Scan mode start after single mode execution: Scan operation is started subsequently after executing conversion in single mode. • Conversion restart: A-D conversion being executed in single or scan mode is restarted. The A-D conversion and comparate rates can be selected between normal and double rate. An AD conversion interrupt request or a DMA transfer request can be generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation. Note 1: To discriminate between the comparison operation performed internally by the successive approximation-type A-D converter and the operation in comparator mode performed using the A-D converter as a comparator, the comparison operation in comparator mode in this manual is referred to as "comparate." 11-2 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.1 Outline of A-D Converter Table 11.1.1 outlines the A-D converter. Figure 11.1.1 shows a block diagram of the A-D converter. Table 11.1.1 Outline of A-D Converter Item Analog input A-D conversion method Resolution Absolute accuracy (Note1) (Conditions : Ta = -40 to 125°C, AVCC0=VREF0=5.12V) Conversion mode Operation mode Scan mode Conversion start trigger A-D conversion mode, comparator mode Single mode, scan mode Single-shot scan mode, continuous scan mode Software start Hardware start Started by setting A-D converter start bit to 1 Starts A-D0 converter by MJT output event bus 3. (Note 2) Conversion rate f(BCLK): Internal peripheral clock operating frequency (Note 3) Interrupt request generation function During single mode (shortest time) Normal rate Double rate 299 × 1/f(BCLK) (Note 3) 173 × 1/f(BCLK) 47 × 1/f(BCLK) 29 × 1/f(BCLK) Content 16 channels Successive approximation method 10 bits (Conversion results can be read out in either 8 bits or 10 bits) Normal mode Double speed mode ±2LSB ±2LSB During comparator mode Normal rate (shortest time) Double rate Generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation DMA transfer request generation function Generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation Note 1: The rated value (accuracy) is that of the microcomputer alone, premised on an assumption that power supply wiring on the board where the microcomputer is mounted is stable and unaffected by noise. Note 2: Refer to Chapter 10, "Multijunction Timers." Note 3: Note 3: f(BCLK) = 20 MHz when the input clock (XIN) = 10 MHz. 11-3 32171 Group User's Manual (Rev.2.00) 11 Internal data bus 8-bit readout 10-bit readout Shifter A-D CONVERTER 11.1 Outline of A-D Converter AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 AD0CMP 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 A-D0 Comparate Data Register A-D Control Circuit Output event bus 3 (multijunction timer) AD0SIM0,1 AD0SCM0,1 Single Mode Register Scan Mode Register AVCC0 AVSS0 10-bit A-D Successive Approximation Register (AD0SAR) VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 10-bit D-A Converter Comparator • Mode selection • Channel selection interrupt request • Conversion time selection • Flag control • Interrupt control DMA transfer request Selector Successive Approximation -type A-D Converter Unit Figure 11.1.1 Block Diagram of A-D0 Converter 11-4 32171 Group User's Manual (Rev.2.00) 11 11.1.1 Conversion Modes A-D CONVERTER 11.1 Outline of A-D Converter The A-D converter has two conversion modes: "A-D conversion mode" and "Comparator mode." (1) A-D conversion mode In A-D conversion mode, the analog input voltage in a specified channel is converted into digital quantity. In single mode, A-D conversion is performed on a channel selected by the Single Mode Register 1 analog input pin select bit. In scan mode, A-D conversion is performed on channels selected by Scan Mode Register 1 according to settings of Scan Mode Register 0. The conversion result is stored in each channel's corresponding 10-bit A-D Data Register. Also, 8-bit A-D conversion results can be read from each 8-bit A-D Data Register. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of A-D conversion when in single mode, or when operating in scan mode, at completion of one cycle of scan loop. (2) Comparator mode In comparator mode, the analog input voltage in a specified channel is "comparated" (compared) with the Successive Approximation Register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged (1 or 0) by setting the A-D Comparate Data Register bit that corresponds to the selected channel. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of comparate operation. 11-5 32171 Group User's Manual (Rev.2.00) 11 11.1.2 Operation Modes A-D CONVERTER 11.1 Outline of A-D Converter The A-D converter operates in two modes: "Single mode" and "Scan mode." When comparator mode is selected as A-D conversion mode, only single mode can be used. (1) Single mode In single mode, the analog input voltage in one selected channel is A-D converted once or comparated with a given quantity. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of A-D conversion. A-D conversion interrupt request or DMA transfer request Conversion starts (Note 1) AN0INn Completed n=0-15 AD0DTn 10-bit A-D0 data register Note 1: A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1 Hardware trigger → Started by output event bus 3 Figure 11.1.2 Operation in Single Mode (A-D Conversion) A-D successive approximation register AD0SAR A-D conversion interrupt request or DMA transfer request n=0-15 Conversion starts (Note 1) AD0INn Completed AD0CMP A-D0 comparate data register Comparate result AD0CMP=0 (ANn>AD0SAR) Note 1: Comparate start: Started by writing a comparison value to the successive approximation register (AD0SAR) Figure 11.1.3 Operation in Single Mode (Comparate) 11-6 32171 Group User's Manual (Rev.2.00) 11 (2) Scan mode A-D CONVERTER 11.1 Outline of A-D Converter In scan mode, analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. There are two types of scan modes: "Single-shot scan mode" in which A-D conversion is completed by performing one cycle of scan operation, and "Continuous scan mode" in which scan operation is continued until halted by setting the Scan Mode Register A-D conversion stop bit to 1. These types of scan modes are selected using Scan Mode Register 0. The channels to be scanned are selected using Scan Mode Register 1. The number of channels and the sequence to be scanned can be selected from three combinations available: 4, 8, or 16 channels. Channels AD0IN0 to AD0IN3 are used for 4-channel scan. Similarly, channels AD0IN0 to AD0IN7 and channels AD0IN0 to AD0IN15 are used for 8-channel scan and 16-channel scan, respectively. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of one cycle of scan operation. During continuous scan mode Completed here when operating in single-shot scan mode AD0DT3 Conversion starts (Note 1) AD0IN0 AD0IN1 AD0IN2 AD0IN3 10-bit A-D0 data register AD0DT0 AD0DT1 AD0DT2 A-D conversion interrupt request or DMA transfer request Note 1: A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1 Hardware trigger → Started by output event bus 3 Figure 11.1.4 Operation of A-D Conversion in Scan Mode (for 4-channel Scan) 11-7 32171 Group User's Manual (Rev.2.00) 11 During continuous scan mode A-D CONVERTER 11.1 Outline of A-D Converter Conversion starts (Note 1) AD0IN0 AD0IN1 AD0IN2 AD0IN3 10-bit A-D0 data register AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Completed here when operating in single-shot scan mode AD0DT7 AD0DT4 AD0DT5 AD0DT6 During continuous scan mode Conversion starts (Note 1) AD0IN0 AD0IN1 AD0IN2 AD0IN3 10-bit A-D0 data register AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Completed here when operating in single-shot scan mode AD0DT15 AD0DT12 AD0DT13 AD0DT14 A-D conversion interrupt request or DMA transfer request Note 1 : A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1 Hardware trigger → Started by output event bus 3 Figure 11.1.5 Operation of A-D Conversion in Scan Mode (for 8-channel/16-channel Scan) 11-8 32171 Group User's Manual (Rev.2.00) 11 Scan loop selection 4-channel scan Selected channels for single-shot scan AD0IN0 AD0IN1 AD0IN2 AD0IN3 Completed Selected channels for continue scan A-D CONVERTER 11.1 Outline of A-D Converter Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored A-D Conversion result storage Register AD0IN0 10-bit A-D0 Data Register 0 AD0IN1 10-bit A-D0 Data Register 1 AD0IN2 10-bit A-D0 Data Register 2 AD0IN3 10-bit A-D0 Data Register 3 AD0IN0 10-bit A-D0 Data Register 0 · (Repeated until forcibly halted) · · · · · AD0IN0 10-bit A-D0 Data Register 0 8-channel scan AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Completed AD0IN1 10-bit A-D0 Data Register 1 AD0IN2 10-bit A-D0 Data Register 2 AD0IN3 10-bit A-D0 Data Register 3 AD0IN4 10-bit A-D0 Data Register 4 AD0IN5 10-bit A-D0 Data Register 5 AD0IN6 10-bit A-D0 Data Register 6 AD0IN7 10-bit A-D0 Data Register 7 AD0IN0 10-bit A-D0 Data Register 0 · · (Repeated until forcibly halted) · · · · AD0IN0 10-bit A-D0 Data Register 0 AD0IN1 10-bit A-D0 Data Register 1 AD0IN2 10-bit A-D0 Data Register 2 AD0IN3 10-bit A-D0 Data Register 3 AD0IN4 10-bit A-D0 Data Register 4 AD0IN5 10-bit A-D0 Data Register 5 AD0IN6 10-bit A-D0 Data Register 6 AD0IN7 10-bit A-D0 Data Register 7 AD0IN8 10-bit A-D0 Data Register 8 AD0IN9 10-bit A-D0 Data Register 9 AD0IN10 10-bit A-D0 Data Register 10 AD0IN11 10-bit A-D0 Data Register 11 AD0IN12 10-bit A-D0 Data Register 12 AD0IN13 10-bit A-D0 Data Register 13 AD0IN14 10-bit A-D0 Data Register 14 AD0IN15 10-bit A-D0 Data Register 15 AD0IN0 10-bit A-D Data Register 0 · (Repeated until forcibly halted) · · · · · 16-channel scan AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Completed 11-9 32171 Group User's Manual (Rev.2.00) 11 11.1.3 Special Operation Modes (1) Forcible single mode execution during scan mode A-D CONVERTER 11.1 Outline of A-D Converter This special operation mode forcibly executes single mode conversion (A-D conversion or comparate) in a specified channel during scan mode operation. For A-D conversion mode, the conversion result is stored in the 10-bit A-D Data Register corresponding to the specified channel. For comparate mode, the conversion result is stored in the 10-bit A-D Comparate Data Register. When the A-D conversion or comparate operation in the specified channel is completed, scan mode A-D conversion is restarted from where it was canceled during scan operation. To start single mode conversion during scan mode operation in software, select software trigger using the Single Mode Register 0’s A-D conversion start trigger select bit and for A-D conversion, set the said register’s A-D conversion start bit to 1. For comparate mode, write the value to be compared into the A-D Successive Approximation Register (AD0SAR) during scan mode operation. To start single mode conversion during scan mode operation in hardware, select hardware trigger using Single Mode Register 0’s A-D conversion start trigger select bit and enter the hardware trigger (output event bus 3) specified by the said register. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of conversion in the specified channel, or at completion of one cycle of scan operation. Forcible single mode execution starts AD0IN2 Scan mode conversion starts AD0IN0 AD0IN1 AD0IN5 (Note 1) AD0IN2 AD0IN3 Completed 10-bit A-D0 data register AD0DT0 AD0DT1 AD0DT5 AD0DT2 AD0DT3 A-D conversion interrupt request or DMA transfer request Note 1: The canceled convert operation in channel 2 is reexecuted from the beginning. Figure 11.1.6 Forcible Single Mode Execution during Scan Mode 11-10 32171 Group User's Manual (Rev.2.00) 11 (2) Scan mode start after single mode execution A-D CONVERTER 11.1 Outline of A-D Converter This special operation mode starts scan operation subsequently after executing conversion in single mode (A-D conversion or comparate). To start this mode in software, choose a software trigger using the Scan Mode Register 0 A-D conversion start trigger select bit. Then set the said register's A-D conversion start bit to 1 during single mode conversion operation. To start in hardware, select hardware trigger using the Scan Mode Register 0’s A-D conversion start trigger select bit and enter the hardware trigger (output event bus 3) specified by the said register while single mode conversion is in operation. When a hardware trigger (output event bus 3) is entered after selecting hardware trigger with the A-D conversion start trigger select bits of both Single Mode Register 0 and Scan Mode Register 0, conversion is first performed in single mode and then after execution of it, conversion is performed in scan mode. An A-D conversion interrupt request or a DMA transfer request can be generated at completion of single mode conversion in the specified channel, or at completion of one cycle of scan operation. Instructed to start scan mode conversion Single mode conversion starts AD0IN5 AD0IN0 AD0IN1 AD0IN2 AD0IN3 Completed 10-bit A-D0 data register AD0DT5 AD0DT0 AD0DT1 AD0DT2 AD0DT3 A-D conversion interrupt request or DMA transfer request Figure 11.1.7 Scan Mode Start after Single Mode Execution 11-11 32171 Group User's Manual (Rev.2.00) 11 (3) Conversion restart A-D CONVERTER 11.1 Outline of A-D Converter This special operation mode stops operation being executed in single mode or scan mode and reexecutes the operation from the beginning. In the case of single mode, the operation being executed is redone by setting Single Mode Register 0’s A-D conversion start bit to 1 again during A-D conversion or comparate operation or by entering a hardware trigger (output event bus 3). For scan mode, the channel being converted is canceled and A-D conversion is restarted from channel 0 by setting Scan Mode Register 0’s A-D conversion start bit to 1 again during scan operation or by entering a hardware trigger (output event bus 3). Single mode AD0IN5 conversion restarts AD0IN5 Single mode AD0IN5 AD0IN5 conversion starts A-D conversion interrupt request or DMA transfer request Completed 10-bit A-D0 data register AD0DT5 Figure 11.1.8 Restarting Conversion during Single Mode Operation Scan mode restarts AD0IN2 Scan mode conversion starts AD0IN0 AD0IN1 AD0IN0 AD0IN1 AD0IN2 AD0IN3 Completed 10-bit A-D0 data register AD0DT0 AD0DT1 AD0DT0 AD0DT1 AD0DT2 AD0DT3 A-D conversion interrupt request or DMA transfer request Figure 11.1.9 Restarting Conversion during Scan Operation 11-12 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.1 Outline of A-D Converter 11.1.4 A-D Converter Interrupt and DMA Transfer Requests The A-D converter can generate an A-D conversion interrupt request or DMA transfer request at completion of A-D conversion, comparate operation, or one-shot scan or when each cycle of continuous scan mode is completed. To select between A-D conversion interrupt or DMA transfer requests to generate, use Single Mode Register 0 and Scan Mode Register 0. A-D0 Scan Mode Register 0 interrupt request /DMA transfer request select bit Scan mode (when one cycle of scan completed) A-D0 conversion interrupt request (To the interrupt controller) DMA transfer request (To the DMAC) Single mode (when A-D conversion or comparate operation completed) A-D0 Single Mode Register 0 interrupt request /DMA transfer request select bit Figure 11.1.10 Selecting between Interrupt Request and DMA Transfer Request 11-13 32171 Group User's Manual (Rev.2.00) 11 11.2 A-D Converter Related Registers A-D CONVERTER 11.2 A-D Converter Related Registers The diagrams below show an A-D converter related register map. Address D0 +0 Address D7 D8 A-D0 Single Mode Register 0 (AD0SIM0) +1 Address D15 A-D0 Single Mode Register 1 (AD0SIM1) H'0080 0080 H'0080 0082 H'0080 0084 H'0080 0086 H'0080 0088 H'0080 008A H'0080 008C A-D0 Scan Mode Register 0 (AD0SCM0) A-D0 Scan Mode Register 1 (AD0SCM1) A-D0 Successive Approximation Register (AD0SAR) A-D0 Comparate Data Register (AD0CMP) H'0080 0090 H'0080 0092 H'0080 0094 H'0080 0096 H'0080 0098 H'0080 009A H'0080 009C H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 H'0080 00A8 H'0080 00AA H'0080 00AC H'0080 00AE 10-bit A-D0 Data Register 0 (AD0DT0) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) 10-bit A-D0 Data Register 4 (AD0DT4) 10-bit A-D0 Data Register 5 (AD0DT5) 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15) Blank addresses are reserved. Note: • The registers enclosed in thick frames must always be accessed in halfwords. Figure 11.2.1 A-D Converter Related Register Map (1/2) 11-14 32171 Group User's Manual (Rev.2.00) 11 Address D0 +0 Address A-D CONVERTER 11.2 A-D Converter Related Registers +1 Address D7 D8 8-bit A-D0 Data Register 0 (AD08DT0) 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 15 (AD08DT15) D15 H'0080 00D0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE Blank addresses are reserved. Figure 11.2.2 A-D Converter Related Register Map (2/2) 11-15 32171 Group User's Manual (Rev.2.00) 11 11.2.1 A-D Single Mode Register 0 s A-D0 Single Mode Register 0 (AD0SIM0) D0 1 2 3 4 A-D CONVERTER 11.2 A-D Converter Related Registers D 0,1 2 Bit Name No functions assigned AD0STRG (A-D0 hardware trigger selection) 3 AD0SSEL (A-D0 conversion start trigger selection) 4 AD0SREQ (Interrupt request/DMA transfer request selection) 5 AD0SCMP (A-D0 conversion/comparate completed) 6 AD0SSTP (A-D0 conversion stop) 7 AD0SSTT (A-D0 conversion start) 0: Use inhibited 1: Output event bus 3 0: Software trigger 1: Hardware trigger (Note 1) 0: A-D0 interrupt request 1: DMA transfer request 0: A-D0 conversion/comparate in progress 1: A-D0 conversion/comparate completed 0: Performs no operation 1: Stops A-D0 conversion 0: Performs no operation 1: Starts A-D0 conversion 0 0 – Function R 0 W – Note 1: During comparator mode, hardware triggers, if any selected, are ignored and operation is started by a software trigger. A-D0 Single Mode Register 0 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-16 32171 Group User's Manual (Rev.2.00) 11 (1) AD0STRG (A-D0 hardware trigger select) bit (D2) A-D CONVERTER 11.2 A-D Converter Related Registers When starting A-D conversion of the A-D0 converter in hardware, this bit specifies the conversion to be started by MJT output (output event bus 3). If software trigger is selected with the AD0SSEL (A-D0 conversion start trigger select) bit, the content of this bit is ignored. (2) AD0SSEL (A-D0 conversion start trigger select) bit (D3) This bit selects whether to apply the A-D0 conversion start trigger in software or in hardware during single mode. When software trigger is selected, A-D conversion is started by setting the AD0SSTT (A-D0 conversion start) bit to 1. When hardware trigger is selected, set the AD0STRG (hardware trigger select) bit to 1 and specify conversion to be started by MJT output. (3) AD0SREQ (A-D0 interrupt request/DMA transfer request select) bit (D4) This bit selects whether to generate an A-D0 conversion interrupt request or a DMA transfer request at completion of single mode (A-D conversion or comparate). (4) AD0SCMP (A-D0 conversion/comparate complete) bit (D5) This is a read-only bit, and is 1 when reset. This bit is 0 when the A-D0 converter in single mode (A-D conversion or comparate) is operating and set to 1 when the operation is completed. It also is set to 1 when A-D conversion or comparate operation is forcibly terminated by setting the AD0SSTT (A-D0 conversion stop) bit to 1 during A-D conversion or comparate operation. (5) AD0SSTP (A-D0 conversion stop) bit (D6) The A-D0 converter in single mode (A-D conversion or comparate) can be stopped by setting this bit to 1 while the converter is operating. Manipulation of this bit is ignored while the converter in single mode remains idle or is operating in scan mode. Operation is stopped immediately after writing to this bit and the content of the A-D0 Successive Approximation Register when read after being stopped shows an intermediate value that was in the middle of conversion. (No transfers to the A-D0 Data Register are performed.) If the A-D0 conversion start and A-D0 conversion stop bits are set to 1 simultaneously, the A-D0 conversion stop bit is effective. If this bit is set to 1 while single mode operation of special mode is under way (forcible execution of single mode during scan mode operation), only single mode conversion stops and scan mode operation restarts. 11-17 32171 Group User's Manual (Rev.2.00) 11 (6) AD0SSTT (A-D0 conversion start) bit (D7) A-D CONVERTER 11.2 A-D Converter Related Registers A-D conversion of the A-D0 converter is started by setting this bit to 1 while software trigger has been selected with the AD0SSEL (A-D0 conversion start trigger select) bit. If the A-D0 conversion start and A-D0 conversion stop bits are set to 1 simultaneously, the A-D0 conversion stop bit is effective. When this bit is set to 1 during single mode conversion, special operation mode “Conversion restart” is assumed, so that conversion in single mode restarts. When this bit is set to 1 during A-D conversion in scan mode, special operation mode “Forcible execution of single mode during scan mode operation” is assumed, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When single mode conversion finishes, A-D conversion in scan mode restarts from the canceled channel. 11-18 32171 Group User's Manual (Rev.2.00) 11 11.2.2 A-D Single Mode Register 1 s A-D0 Single Mode Register 1 (AD0SIM1) D8 9 10 11 12 A-D CONVERTER 11.2 A-D Converter Related Registers D 8 Bit Name AD0SMSL (A-D0 conversion mode selection) 9 AD0SSPD (A-D0 conversion rate selection) 10,11 12-15 No functions assigned AN0SEL (Analog input pin selection) 0000: Selects AD0IN0 0001: Selects AD0IN1 0010: Selects AD0IN2 0011: Selects AD0IN3 0100: Selects AD0IN4 0101: Selects AD0IN5 0110: Selects AD0IN6 0111: Selects AD0IN7 1000: Selects AD0IN8 1001: Selects AD0IN9 1010: Selects AD0IN10 1011: Selects AD0IN11 1100: Selects AD0IN12 1101: Selects AD0IN13 1110: Selects AD0IN14 1111: Selects AD0IN15 W= : Only writing a 0 is effective; when you write a 1, device operation cannot be guaranteed. Function 0: A-D0 conversion mode 1: Comparator mode 0: Normal rate 1: Double rate 0 R W A-D0 Single Mode Register 1 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-19 32171 Group User's Manual (Rev.2.00) 11 (1) AD0SMSL (A-D0 conversion mode selection) bit A-D CONVERTER 11.2 A-D Converter Related Registers (D8) This bit selects A-D conversion mode for the A-D0 converter during single mode. Setting this bit to 0 selects A-D conversion mode, and setting this bit to 1 selects comparator mode. (2) AD0SSPD (A-D0 conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-D0 converter during single mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed. (3) AN0SEL (analog input pin selection) bits (D12-D15) These bits select analog input pins for the A-D0 converter during single mode. It is the channels selected by these bits that are operated on for A-D conversion or comparate operation. When you read these bits, they show the values written to them. 11-20 32171 Group User's Manual (Rev.2.00) 11 11.2.3 A-D Scan Mode Register 0 s A-D0 Scan Mode Register 0 (AD0SCM0) D0 1 2 3 4 A-D CONVERTER 11.2 A-D Converter Related Registers D 0 1 Bit Name No functions assigned AD0CMSL (A-D0 scan mode selection) 2 AD0CTRG (A-D0 hardware trigger selection) 3 AD0CSEL (A-D0 conversion start trigger selection) 4 AD0CREQ (Interrupt request/DMA request selection) 5 AD0CCMP (A-D0 conversion completed) 6 AD0CSTP (A-D0 conversion stop) 7 AD0CSTT (A-D0 conversion start) 0: Single-shot mode 1: Continuous mode 0: Use inhibited 1: Output event bus 3 0: Software trigger 1: Hardware trigger 0: Requests A-D0 interrupt 1: Requests DMA transfer 0: A-D0 conversion in progress 1: A-D0 conversion completed 0: Performs no operation 1: Stops A-D0 conversion 0: Performs no operation 1: Starts A-D0 conversion 0 0 – Function R 0 W – A-D0 Scan Mode Register 0 is used to control operation of the A-D0 converter during scan mode. 11-21 32171 Group User's Manual (Rev.2.00) 11 (1) AD0CMSL (A-D0 scan mode select) bit (D1) A-D CONVERTER 11.2 A-D Converter Related Registers This bit selects the A-D0 converter scan mode between one-shot scan and continuous scan modes. Setting this bit to 0 selects one-shot scan mode, so that A-D conversion of channels selected with the AN0SCAN (scan loop select) bit are performed sequentially. When A-D conversion on all selected channels is completed, the convert operation stops. Setting this bit to 1 selects continuous scan mode, so that when operation in one-shot mode finishes, A-D conversion is performed from the first channel again. This is repeated until stopped by setting the AD0CSTP (A-D0 conversion stop) bit to 1. (2) AD0CTRG (A-D0 hardware trigger select) bit (D2) When starting A-D conversion of the A-D0 converter in hardware, this bit specifies the conversion to be started by MJT output (output event bus 3). If software trigger is selected with the AD0CSEL (A-D conversion start trigger select) bit, the content of this bit is ignored. (3) AD0CSEL (A-D0 conversion start trigger select) bit (D3) This bit selects whether to apply the A-D conversion start trigger in software or in hardware during scan mode of the A-D0 converter. When software trigger is selected, A-D conversion is started by setting the AD0CSTT (A-D0 conversion start) bit to 1. When hardware trigger is selected, set the AD0CTRG (hardware trigger select) bit to 1 and specify conversion to be started by MJT output. (4) AD0CREQ (A-D0 interrupt/DMA transfer request select) bit (D4) This bit selects whether to generate an A-D0 conversion interrupt request or a DMA transfer request at completion of one cycle of scan mode operation. (5) AD0CCMP (A-D0 conversion complete) bit (D5) This is a read-only bit, and is 1 when reset. This bit is 0 when scan mode conversion of the A-D0 converter is in progress and set to 1 when one-shot scan mode operation is completed or when continuous scan mode is stopped by setting the AD0CSTT (A-D0 conversion stop) bit to 1. 11-22 32171 Group User's Manual (Rev.2.00) 11 (6) AD0CSTP (A-D0 conversion stop) bit (D6) A-D CONVERTER 11.2 A-D Converter Related Registers Scan mode operation of the A-D0 converter can be stopped by setting this bit to 1 while scan mode A-D conversion is under way. This bit is effective for only scan mode operation, and does not affect single mode operation when both single and scan modes of special operation mode are active. Operation is stopped immediately after writing to this bit and A-D conversion on the channel which is in the middle of conversion is aborted, with no data transferred to the A-D Data Register. If the A-D0 conversion start and A-D0 conversion stop bits are set to 1 simultaneously, the A-D0 conversion stop bit is effective. (7) AD0CSTT (A-D0 conversion start) bit (D7) This bit is used to start scan mode operation of the A-D0 converter in software. Only when software trigger has been selected with the AD0CSEL (A-D0 conversion start trigger select) bit, A-D conversion can be started by setting this bit to 1. If the A-D0 conversion start and A-D0 conversion stop bits are set to 1 simultaneously, the A-D0 conversion stop bit is effective. When this bit is set to 1 during scan mode conversion again, special operation mode “Conversion restart” is assumed, so that scan operation restarts according to the contents set by Scan Mode Register 0 and Scan Mode Register 1. When this bit is set to 1 during A-D conversion in single mode, special operation mode “Start scan mode after executing single mode” is assumed, so that scan mode operation starts on successive channels after single mode finishes. 11-23 32171 Group User's Manual (Rev.2.00) 11 11.2.4 A-D Scan Mode Register 1 s A-D0 Scan Mode Register 1 (AD0SCM1) D8 9 AD0CSPD 10 11 12 A-D CONVERTER 11.2 A-D Converter Related Registers D 8 9 Bit Name No functions assigned AD0CSPD (A-D0 conversion rate selection) 10,11 12-15 No functions assigned AN0SCAN (A-D0 scan loop selection) 01XX: 4-channel scan 10XX: 8-channel scan 11XX: 16-channel scan 00XX: 16-channel scan 0: Normal rate 1: Double rate 0 – Function R 0 W – 0000: Converting AD0IN0 0001: Converting AD0IN1 0010: Converting AD0IN2 0011: Converting AD0IN3 0100: Converting AD0IN4 0101: Converting AD0IN5 0110: Converting AD0IN6 0111: Converting AD0IN7 1000: Converting AD0IN8 1001: Converting AD0IN9 1010: Converting AD0IN10 1011: Converting AD0IN11 1100: Converting AD0IN12 1101: Converting AD0IN13 1110: Converting AD0IN14 1111: Converting AD0IN15 A-D0 Scan Mode Register 1 is used to control operation of the A-D0 converter during scan mode. 11-24 32171 Group User's Manual (Rev.2.00) 11 (1) AD0CSPD (A-D0 conversion rate selection) bit A-D CONVERTER 11.2 A-D Converter Related Registers (D9) This bit selects an A-D conversion rate for the A-D0 converter during scan mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed. (2) AN0SCAN (A-D0 scan loop selection) bits (D12-D15) The AN0SCAN (A-D0 scan loop selection) bits set the channels to be scanned during scan mode of the A-D0 converter. In this case, writes to D14 and D15 have no effect. The AN0SCAN (A-D0 scan loop selection) bits when read during scan operation show the status of the A-D0 converter, indicating the channel it is converting. The value read from these bits during single mode are always "B'0000." If A-D conversion is halted by setting Scan Mode Register 0 AD0CSTP (A-D0 conversion stop) bit to 1 during scan mode execution, the bits when read at this time show the value of the channel in which the A-D conversion has been canceled. Also, if halted during single mode conversion in special operation mode "Forcible single mode execution during scan mode," the bits when read at this time show the value of the channel in which the A-D conversion has been canceled in the middle of scan. 11-25 32171 Group User's Manual (Rev.2.00) 11 11.2.5 A-D Successive Approximation Register A-D CONVERTER 11.2 A-D Converter Related Registers s A-D0 Successive Approximation Register (AD0SAR) D0 1 2 3 4 5 6 7 8 9 10 11 8 9 10 11 12 13 14 D15 1 2 3 AD0 CMP3 4 5 6 7 AD0 AD0 CMP1 CMP2 AD0 AD0 CMP4 CMP5 AD0 AD0 CMP6 CMP7 AD0 CMP8 AD0 AD0 AD0 AD0 AD0 AD0 AD0 CMP9 CMP10 CMP11 CMP12 CMP13 CMP14 CMP15 D 0-15 Bit Name AD0CMP0-AD0CMP15 (Note 2) (A-D0 comparate result flag) Function 0: Analog input voltage > comparison voltage 1: Analog input voltage < comparison voltage R W – Notes : • This register must always be accessed in halfwords. • During comparator mode, each bit corresponds to channels 0 through 15. When comparator mode is selected by setting the A-D0 Single Mode Register 1 AD0SMSL (A-D0 conversion mode selection) bit, the selected analog input value is compared with the value written to the A-D0 Successive Approximation Register, with the result stored in the corresponding bit of this comparate data register. The bit is 0 when the analog input voltage > comparison voltage, and is 1 when the analog input voltage < comparison voltage. 11-27 32171 Group User's Manual (Rev.2.00) 11 11.2.7 10-bit A-D Data Registers s 10-bit A-D0 Data Register 0 (AD0DT0) s 10-bit A-D0 Data Register 1 (AD0DT1) s 10-bit A-D0 Data Register 2 (AD0DT2) s 10-bit A-D0 Data Register 3 (AD0DT3) s 10-bit A-D0 Data Register 4 (AD0DT4) s 10-bit A-D0 Data Register 5 (AD0DT5) s 10-bit A-D0 Data Register 6 (AD0DT6) s 10-bit A-D0 Data Register 7 (AD0DT7) s 10-bit A-D0 Data Register 8 (AD0DT8) s 10-bit A-D0 Data Register 9 (AD0DT9) s 10-bit A-D0 Data Register 10 (AD0DT10) s 10-bit A-D0 Data Register 11 (AD0DT11) s 10-bit A-D0 Data Register 12 (AD0DT12) s 10-bit A-D0 Data Register 13 (AD0DT13) s 10-bit A-D0 Data Register 14 (AD0DT14) s 10-bit A-D0 Data Register 15 (AD0DT15) D0 1 2 3 4 5 6 7 8 A-D CONVERTER 11.2 A-D Converter Related Registers 9 10 11 12 13 14 D15 AD0DT0-AD0DT15 D 0-5 6-15 Bit Name No functions assigned AD0DT0-AD0DT15 (10-bit A-D0 data) A-D conversion result Function R 0 W – – Note: • This register must always be accessed in halfwords. In single mode of the A-D0 converter, the result of A-D conversion is stored in the 10-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 10-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-28 32171 Group User's Manual (Rev.2.00) 11 11.2.8 8-bit A-D Data Registers s 8-bit A-D0 Data Register 0 (AD08DT0) s 8-bit A-D0 Data Register 1 (AD08DT1) s 8-bit A-D0 Data Register 2 (AD08DT2) s 8-bit A-D0 Data Register 3 (AD08DT3) s 8-bit A-D0 Data Register 4 (AD08DT4) s 8-bit A-D0 Data Register 5 (AD08DT5) s 8-bit A-D0 Data Register 6 (AD08DT6) s 8-bit A-D0 Data Register 7 (AD08DT7) s 8-bit A-D0 Data Register 8 (AD08DT8) s 8-bit A-D0 Data Register 9 (AD08DT9) s 8-bit A-D0 Data Register 10 (AD08DT10) s 8-bit A-D0 Data Register 11 (AD08DT11) s 8-bit A-D0 Data Register 12 (AD08DT12) s 8-bit A-D0 Data Register 13 (AD08DT13) s 8-bit A-D0 Data Register 14 (AD08DT14) s 8-bit A-D0 Data Register 15 (AD08DT15) D8 9 10 11 12 A-D CONVERTER 11.2 A-D Converter Related Registers 13 14 D15 AD08DT0-AD08DT15 D 8-15 Bit Name AD08DT0-AD08DT15 (8-bit A-D0 data) Function 8-bit A-D conversion result R W – This A-D data register stores the 8-bit conversion data from the A-D0 converter. In single mode of the A-D0 converter, the result of A-D conversion is stored in the 8-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 8-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-29 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter 11.3 Functional Description of A-D Converter 11.3.1 How to Find Along Input Voltages The A-D converter uses a 10-bit successive approximation method, and finds the actual analog input voltage from the value (digital quantity) obtained through execution of A-D conversion by performing the following calculation. A-D conversion result x VREF0 input voltage [V] 1024 Analog input voltage [V] = The A-D converter is a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A-D converter is the voltage applied to the VREF0 pin, make sure an exact and stable constant-voltage power supply is connected to VREF0. Also, make sure the analog circuit power supply and ground (AVCC0, AVSS0) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated. For details about the conversion accuracy, refer to Section 11.3.5, "Accuracy of A-D Conversion." 10-bit A-D0 data register A-D0 comparate data register AD0DT0-15 AD0CMP AVCC0 AVSS0 10-bit A-D0 successive approximation register (AD0SAR) Vref A-D control circuit Comparator VREF0 10-bit D-A converter VIN AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Selector Successive approximation-type A-D converter unit Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A-D Converter Unit 11-30 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter 11.3.2 A-D Conversion by Successive Approximation Method The A-D converter has A-D convert operation started by an A-D conversion start trigger (in software or hardware). Once A-D conversion begins, the following operation is automatically executed. 1. During single mode, Single Mode Register 0's A-D conversion/comparate completion bit is cleared to 0. During scan mode, Scan Mode Register 0's A-D conversion completion bit is cleared to 0. 2. The content of the A-D Successive Approximation Register is cleared to "H'0000." 3. The A-D Successive Approximation Register's most significant bit (D6) is set to 1. 4. The comparison voltage, Vref (Note 1), is fed from the D-A converter into the comparator. 5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in D6. If Vref < VIN, then D6 = 1 If Vref > VIN, then D6 = 0 Operations in steps 3 through 5 above are executed for all other bits from D7 to D15. 6. 7. The value stored in the A-D Successive Approximation Register at completion of the comparison of D15 is the final A-D conversion result. A-D Successive Approximation Register (AD0SAR) D6 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 D15 0 1st comparison 1 2nd comparison n9 1 0 0 0 0 0 0 0 0 If Vref > VIN, then nX=0 If Vref < VIN, then nX=1 Result of 1st comparison 3rd comparison n9 n8 1 0 0 0 0 0 0 0 Result of 2nd comparison 10th comparison n9 n8 n7 n6 n5 n4 n3 n2 n1 1 Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation Note 1: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref. • When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0 • When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) x (content of the A-D Successive Approximation Register - 0.5) 11-31 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter The comparison result is stored in the 10-bit A-D Data Register (AD0DTn) corresponding to each converted channel. Also, the 8 high-order bits of the 10-bit A-D conversion result can be read out from the 8-bit A-D Data Register (AD08DTn). The following shows the procedure for A-D conversion by successive approximation in each operation mode. (1) Single mode The convert operation stops when comparison of the A-D Successive Approximation Register's D15 bit is completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred to the 10-bit A-D Data Registers 0-15 for the converted channel. (2) Single-shot scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A-D conversion for one specified scan loop is completed. (3) Continuous scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. During continuous scan mode, the convert operation is executed continuously until scan operation is forcibly halted by setting the A-D conversion stop bit (Scan Mode Register 0's D6 bit) to 1. 11-32 32171 Group User's Manual (Rev.2.00) 11 11.3.3 Comparator Operation A-D CONVERTER 11.3 Functional Description of A-D Converter When comparator mode (single mode only) is selected, the A-D converter functions as a comparator which compares analog input voltages with the comparison voltage that is set by software. When a comparison value is written to the successive approximation register, the A-D converter starts 'comparating' the analog input voltage selected by the Single Mode Register 1 analog input selection bit with the value written to the successive approximation register. Once comparate begins, the following operation is automatically executed. 1. The Single Mode Register 0 or Scan Mode Register 0's A-D conversion/comparate completion flag is cleared to 0. 2. The comparison voltage, Vref (Note 1), is fed from the D-A converter into the comparator. 3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in the comparate result flag (A-D Comparate Data Register's D15). If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 4. The comparate operation stops after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP)'s corresponding bit. Note 1: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref. • When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0 • When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) x (content of the A-D Successive Approximation Register - 0.5) 11-33 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter 11.3.4 Calculation of the A-D Conversion Time The A-D conversion time is expressed by the sum of dummy cycle time and the actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1. Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D converter starts A-D conversion 2. A-D conversion execution cycle time 3. Comparate execution cycle time 4. End dummy time A time from when the A-D converter finished A-D conversion to when the CPU can stably read out this conversion result from the A-D data register 5. Scan to scan dummy time A time during single-shot or continuous scan mode from when the A-D converter finished A-D conversion in a channel to when it starts A-D conversion in the next channel The equation to calculate the A-D conversion time is as follows: A-D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: • Shown in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. 11-34 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter (1) Calculating the conversion time during A-D conversion mode The following shows how to calculate the conversion time during A-D conversion mode. A-D conversion start trigger Convert operation begins Transferred to A-D data register Completed Start dummy Execution cycle End dummy (Channel 0) Start dummy Execution cycle Scan to scan dummy (Channel 1) Execution cycle (Last channel) ..... Scan to scan dummy Execution cycle End dummy Figure 11.3.3 Conceptual Diagram of Conversion Time in A-D Conversion mode Table 11.3.1 Conversion Clock Cycles in A-D Conversion Mode Conversion rate Normal rate Double rate Start dummy 4 4 A-D conversion execution cycle 294 168 End dummy 1 1 Unit: BCLK Scan to scan dummy (Note 1) 4 4 Note 1: This applies to only scan mode, and is added to the execution time for each channel. (2) Calculating the conversion time during comparate mode The following shows how to calculate the conversion time during comparate mode. Transferred to comparate data register Comparate start trigger Convert operation begins Completed Start dummy Execution cycle End dummy Figure 11.3.4 Conceptual Diagram of Conversion Time in Comparate mode Table 11.3.2 Conversion Clock Cycles in Comparate Mode Conversion rate Normal rate Double rate Start dummy 4 4 Comparate execution cycle 42 24 End dummy 1 1 Unit: BCLK 11-35 32171 Group User's Manual (Rev.2.00) 11 (2) A-D conversion time A-D CONVERTER 11.3 Functional Description of A-D Converter The table below lists A-D conversion times. Table 11.3.3 Total A-D Conversion Time Conversion started by Software trigger (Note 2) Conversion rate Normal rate Conversion mode (Note 1) Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode Double rate Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode Hardware trigger (Note 3) Normal Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode Double speed Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode Conversion time [BCLK] 299 1193 2385 4769 47 173 689 1377 2753 29 299 1193 2385 4769 47 173 689 1377 2753 29 Note 1: For single and comparator modes, this shows the time for A-D conversion in one channel or for comparate operation. For single-shot and continuous scan modes, this shows the time for A-D conversion in one scan loop. Note 2: This shows the time from when a write-to-register cycle is completed to when an A-D conversion interrupt request is generated. Note 3: This shows the time from when output event bus 3 is actuated to when an A-D conversion interrupt request is generated. 11-36 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.3 Functional Description of A-D Converter 11.3.5 Definition of the A-D Conversion Accuracy The accuracy of the A-D Converter is expressed by absolute accuracy. Absolute accuracy refers to the difference, expressed in terms of LSB, between the output code actually obtained by converting analog input voltages into digital quantities and the output code that can be expected from an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are chosen to be the midpoint values of voltage width at which an A-D converter with ideal characteristics will produce the same output code. For example, when VREF0 = 5.12 V, the width of 1 LSB of a 10-bit A-D converter is 5 mV, so that the middle points of analog input voltages are chosen to be 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, and so on. If the absolute accuracy of an A-D converter is said to be ±2 LSB, it means that if the input voltage is 25 mV, for example, then the actual A-D conversion result is in the range of H’003 to H’007, whereas the output code that can be expected from an ideal A-D converter is H’005. Note that absolute accuracy includes a zero error and full-scale error. Although when actually using the A-D Converter, the analog input voltages are in the range of AVSS0 to VREF0, excessively lowering the VREF0 voltage requires caution because resolution may be degraded. Note also that output codes for analog input voltages from VREF0 to AVCC0 are always H’3FF. A-D conversion result (hexadecimal) H'3FF H'3FE Ideal A-D conversion characteristic H'003 H'002 A-D conversion characteristic with infinite resolution H'001 H'000 0 VREF X1 1024 VREF X2 1024 VREF X3 1024 VREF X1023 1024 VREF X1024 1024 VREF X1022 1024 Analog input voltage [V] Figure 11.3.5 Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter's Analog Input Voltages 11-37 32171 Group User's Manual (Rev.2.00) 11 → Output code (hexadecimal) A-D CONVERTER 11.3 Functional Description of A-D Converter H'00B Ideal A-D conversion characteristic H'00A H'009 H'008 H'007 H'006 H'005 H'004 H'003 H'002 H'001 H'000 0 5 10 15 20 25 30 35 40 45 50 55 A-D conversion characteristic with infinite resolution +2 LSB -2 LSB → Analog input voltage [mV] Figure 11.3.6 Absolute Accuracy of an A-D Converter 11-38 32171 Group User's Manual (Rev.2.00) 11 A-D CONVERTER 11.4 Precautions on Using A-D Converter 11.4 Precautions on Using A-D Converter • Forcible termination during scan operation If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP) to 1 during scan mode operation and you read the content of the A-D data register for the channel in which conversion was in progress, it shows the last conversion result that had been transferred to the A-D data register before the conversion was forcibly terminated. • Modification of A-D converter related registers If you want to change the contents of the A-D Conversion Interrupt Control Register, each Single and Scan Mode Register, or A-D Successive Approximation Register, except for the A-D conversion stop bit, do your change while A-D conversion is inactive, or be sure to restart A-D conversion after you changed the register contents. If the contents of these registers are changed in the middle of A-D conversion, the conversion results cannot be guaranteed. • Handling of analog input signals The A-D converter included in the 32171 does not have a sample-and-hold circuit. Therefore, make sure the analog input levels are fixed during A-D conversion. • A-D conversion completion bit readout timing If you want to read the A-D conversion completion bit (Single Mode Register 0's D5 bit or Scan Mode Register 0's D5 bit) immediately after A-D conversion has started, be sure to adjust the timing one clock cycle by, for example, inserting a NOP instruction before you read. • Rated value of absolute accuracy The rated value of absolute accuracy is that of the microcomputer alone, premised on an assumption that power supply wiring on the board where the microcomputer is mounted is stable and unaffected by noise. When designing the board, pay careful attention to its layout by, for example, separating AVCC0, AVSS0, and VREF0 from other digital power supplies or protecting the analog input pins against noise from other digital signals. 11-39 32171 Group User's Manual (Rev.2.00) 11 • Regarding the analog input pins A-D CONVERTER 11.4 Precautions on Using A-D Converter Figure 11.4.1 shows an internal equivalent circuit of the analog input unit. To obtain exact A-D conversion results, it is necessary that the A-D conversion circuit finishes charging its internal capacitor C2 within a designated time (sampling time). To meet this sampling time requirement, we recommend connecting a stabilizing capacitor, C1, external to the chip. The following shows the analog output device’s output impedance and how to determine the value of the external stabilizing capacitor to meet this timing requirement. Also shown below is the case where the analog output device’s output impedance is low and the external stabilizing capacitor C1 is unnecessary. Inside the microcomputer 10-bit AD Successive Approximation Register (ADiSAR) VREF Analog Output Device 10-bit DA Converter V2 C2 ADIN n R1 E i C1 i1 i2 Cin R2 Selector Comparator C1 : Board’s parasitic capacitance + stabilizing C VREF : Analog reference voltage C2 : Comparator capacitance (approx. 2.9 pF) Cin : Input pin capacitance (approx. 10 pF) R2 : Selector ’s parasitic resistance (1- 2 kΩ) R1 : Analog output device’s resistance V2 : Voltage across C2 E : Analog output device’s voltage Figure 11.4.1 Internal Equivalent Circuit of the Analog Input Unit (a) Example for calculating the value of an external stabilizing capacitor C1 (recommended) In Figure 11.4.1, as we calculate the capacitance of C1, we assume R1 is infinitely large, that the current needed to charge the internal capacitor C2 is sourced from C1, and that the voltage fluctuation due to C1 and C2 capacitance divisions, Vp, is 0.1 LSB or less. For the10-bit A-D converter where VREF is 5.12 V, the 1 LSB determination voltage = 5.12 V / 1024 = 5 mV. With up to 0.1 LSB voltage fluctuations considered, this equals 0.5 mV fluctuation. 11-40 32171 Group User's Manual (Rev.2.00) 11 Vp = C2 C1 + C2 × (E - V2) A-D CONVERTER 11.4 Precautions on Using A-D Converter The relationship between C1 and C2 capacitance divisions and Vp is obtained by the equation: Eq. (A-1) Also, Vp is obtained by the equation: Vp = Vp1 × x-1 ∑ i=0 1 2i < VREF 10 × 2x Eq. (A-2) Notes: • Where Vp1 = voltage fluctuation in first A-D conversion. • The exponent x is 10 because of a 10-bit resolution A-D converter. When Eqs. (A-1) and (A-2) are solved, C1 = C2 { E - V2 Vp1 -1} Eq. (A-3) ∑ ∴ C1 > C2 {10 × 2x × x-1 i=0 1 2i -1} Eq. (A-4) Thus, for 10-bit resolution A-D converter where C2 = 2.9 pF, C1 is 0.06 µF or greater. Use this for reference when determining the value of C1. (b) Maximum value of the output impedance R1 when not adding C1 In Figure 11.4.1, if the external capacitor C1 is not used, examination must be made of whether C2 can be fully charged. First, the following shows the equation to find i2 when C1 is nonexistent in Figure 11.4.1. i2 = C2(E - V2) Cin × R1 + C2(R1 + R2) × exp { -t Cin × R1 + C2(R1 + R2) } Eq. (B-1) 1 bit conversion time ADIN i Sampling time Comparison time Repeated for 10 bits (10 times) Figure 11.4.2 A-D Conversion Timing Diagram 11-41 32171 Group User's Manual (Rev.2.00) 11 Conversion Timing Diagram) divided by 2. Assuming t = T (time needed for charging C2) T= Sampling time = 2 A-D CONVERTER 11.4 Precautions on Using A-D Converter The time needed for charging C2 must be within the sampling time (in Figure 11.4.2, A-D A-D conversion time 10 × 4 Therefore, from Eq. (B-1), the time needed for charging C2 is T= (time needed for charging C2) > Cin × R1 + C2(R1 + R2) Eq. (B-2) Thus, the maximum value of R1 as an approximate guide can be obtained by the equation: R1 < A-D conversion time 10 × 4 Cin + C2 - C2 × R2 Eq. (B-3) The table below shows an example of how to calculate the maximum value of R1 during A-D conversion mode when Xin = 10 and 8 MHz. Xin BCLK period Conversion mode A-D conversion mode/Single 8MHz 62.5ns A-D conversion mode/Single Speed mode Normal Double speed Normal Double speed Conversion cycles 294 168 294 168 T (C2 charging time) in ns 367 210 459 262 Maximum value of R1 (Ω) 28,225 16,054 35,357 20,085 10MHz 50ns Note: • The above conversion cycles do not include dummy cycles at the start and end of conversion. In comparate mode, because sampling and comparison each are performed only once, the maximum value of R1 can be derived from the equation R1 < A-D conversion time 4 Cin + C2 - C2 × R2 Eq. (B-4) The table below shows an example of how to calculate the maximum value of R1 during comparate mode when Xin = 10 and 8 MHz. Xin BCLK period Conversion mode Speed mode Conversion cycles 42 24 42 24 T (C2 charging time) in ns 525 300 656 375 Maximum value of R1 (Ω) 40,473 23,031 50,628 28,845 10MHz 50ns comparate mode Normal /Single Double speed 8MHz 62.5ns comparate mode Normal /Single Double speed Note: • The above conversion cycles do not include dummy cycles at the start and end of conversion. 11-42 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 12 SERIAL I/O 12.1 12.2 12.3 12.4 12.5 12.6 Outline of Serial I/O Serial I/O Related Registers Transmit Operation in CSIO Mode Receive Operation in CSIO Mode Precautions on Using CSIO Mode Transmit Operation in UART Mode 12.7 Receive Operation in UART Mode 12.8 Fixed Period Clock Output Function 12.9 Precautions on Using UART Mode 12 12.1 Outline of Serial I/O SERIAL I/O 12.1 Outline of Serial I/O The 32171 contains a total of three serial I/O channels: SIO0, SIO1, and SIO2. Serial channels SIO0 and SIO1 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O). SIO2 is UART mode only. • CSIO mode (clock-synchronous serial I/O) Communication is performed synchronously with transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed). • UART mode (asynchronous serial I/O) Communication is performed asynchronously. The transfer data length can be selected from 7 bits, 8 bits, and 9 bits. Serial I/Os 0-2 each have transmit DMA and receive DMA transfer requests. Through a combined use with the internal DMAC, they allow for fast serial communication, and help to reduce the data communication load on the CPU. Serial I/O is outlined in the pages to follow. 12-2 32171 Group User's Manual (Rev.2.00) 12 Table 12.1.1 Outline of Serial I/O Item Number of channels Content CSIO/UART : 2 channels (SIO0, SIO1) UART only : 1 channels (SIO2) Clock SERIAL I/O 12.1 Outline of Serial I/O During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transfer mode BRG count source Transmit half-duplex, receive half-duplex, transmit/receive full-duplex f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (when internal peripheral clock selected) (Note 2) f(BCLK) : Internal peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (when added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate CSIO mode : UART mode : 152 bits/sec to 2M bits/sec (at f(BCLK) = 20 MHz) 19 bits/sec to 1.25M bits/sec (at f(BCLK) = 20 MHz) Overrun error only Overrun error, parity error, framing error (Occurrence of any of these errors is indicated by an error sum bit) Error detection CSIO mode : UART mode : Fixed period clock function When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin. Note 1 : The maximum input frequency of external clock during CSIO mode is 1/16 of f(BCLK). Note 2 : When f(BCLK) is selected as the BRG count source, the BRG set value is subject to limitations. 12-3 32171 Group User's Manual (Rev.2.00) 12 Table 12.1.2 Serial I/O Interrupt Request Generation Function Serial I/O Interrupt Request SIO0 transmit buffer empty interrupt SIO0 receive-finished or receive error interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 receive-finished or receive error interrupt (selectable) SIO2 transmit buffer empty interrupt SIO2 receive-finished or receive error interrupt (selectable) SIO1 transmit interrupt SIO1 receive interrupt ICU Interrupt Cause SIO0 transmit interrupt SIO0 receive interrupt SERIAL I/O 12.1 Outline of Serial I/O SIO2 transmit/receive interrupt (group interrupt) SIO2 transmit/receive interrupt (group interrupt) Table 12.1.3 Serial I/O DMA Transfer Request Generation Function Serial I/O DMA Transfer Request SIO0 transmit buffer empty SIO0 receive-finished SIO1 transmit buffer empty SIO1 receive-finished SIO2 transmit buffer empty SIO2 receive-finished DMAC Input Channel Channel 3 Channel 4 Channel 6 Channel 3 Channel 7 Channel 5 12-4 32171 Group User's Manual (Rev.2.00) 12 SIO0 SIO0 Transmit Buffer Register Transmit interrupt SERIAL I/O 12.1 Outline of Serial I/O TXD0 SIO0 Transmit Shift Register Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller To DMA3 To DMA4 RXD0 SIO0 Receive Shift Register SIO0 Receive Buffer Register UART mode CSIO mode When external clock selected When internal clock selected BCLK Clock divider Baud rate generator (BRG) CSIO mode When internal clock selected When UART mode selected SIO1 Transmit interrupt Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request TXD1 SIO1 Transmit Shift Register Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 1/16 1 (Set value + 1) 1/2 SCLKI0/ SCLKO0 To interrupt controller To DMA6 To DMA3 SCLKI1/ SCLKO1 RXD1 SIO1 Receive Shift Register SIO2 TXD2 Transmit interrupt Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request SIO2 Transmit Shift Register To interrupt controller RXD2 To DMA7 To DMA5 SIO2 Receive Shift Register Notes: • When BCLK is selected, the BRG set value is subject to limitations. • SIO2 does not have the SCLKI/SCLKO function. Figure 12.1.1 Block Diagram of SIO0-SIO2 12-5 32171 Group User's Manual (Rev.2.00) 12 12.2 Serial I/O Related Registers The diagram below shows a serial I/O related register map. SERIAL I/O 12.2 Serial I/O Related Registers Address H'0080 0100 H'0080 0102 D0 +0 Address D7 D8 +1 Address D15 SIO23 Interrupt Status Register (SI23STAT) SIO03 Cause of Receive Interrupt Select Register (SI03SEL) SIO0 Transmit Control Register (S0TCNT) SIO03 Interrupt Mask Register (SI03MASK) H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register (S0RCNT) SIO0 Baud Rate Register (S0BAUR) H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 SIO1 Transmit Control Register (S1TCNT) SIO1 Transmit/Receive Mode Register (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register (S1RCNT) SIO2 Transmit Control Register (S2TCNT) SIO1 Baud Rate Register (S1BAUR) SIO2 Transmit/Receive Mode Register (S2MOD) H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136 SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register (S2RCNT) SIO2 Baud Rate Register (S2BAUR) Blank addresses are reserved. Figure 12.2.1 Serial I/O Related Register Map 12-6 32171 Group User's Manual (Rev.2.00) 12 12.2.1 SIO Interrupt Related Registers (1) Selecting the cause of interrupt SERIAL I/O 12.2 Serial I/O Related Registers Interrupt signals sent from each SIO to the ICU (Interrupt Controller) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty. Receive interrupts are either receive-finished interrupts or receive error interrupts as selected by the Cause of Receive Interrupt Select Register (SI03SEL). Note: • No interrupt signals are generated unless interrupts are enabled by the SIO Interrupt Mask Register after enabling the TEN (transmit enable) bit or REN (receive enable) bit for the corresponding SIO. (2) Precautions on using transmit interrupts Transmit interrupts are generated when the corresponding TEN (transmit enable) bit is enabled while the SIO Interrupt Mask Register is set to enable interrupts. (3) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a receive-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO's corresponding TEN (transmit enable) bit or REN (receive enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMAC before enabling the TEN or REN bits. When a receive error occurs, no receive-finished DMA transfer requests are generated. • Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (transmit enable bit) TBE (transmit buffer empty bit) Transmit DMA transfer request Figure 12.2.2 Transmit DMA Transfer Request 12-7 32171 Group User's Manual (Rev.2.00) 12 • Receive-finished DMA transfer request SERIAL I/O 12.2 Serial I/O Related Registers DMA transfer request is generated when the receive buffer is filled. RFIN (receive-completed bit) Receive DMA transfer request Note: • When a receive error occurs, no receive-finished DMA transfer requests are generated. Figure 12.2.3 Receive-finished DMA Transfer Request 12-8 32171 Group User's Manual (Rev.2.00) 12 12.2.2 SIO Interrupt Control Registers s SIO23 Interrupt Status Register (SI23STAT) D0 1 2 3 4 IRQT2 SERIAL I/O 12.2 Serial I/O Related Registers D 0-3 4 Bit Name No functions assigned IRQT2 (SIO2 transmit-finished 0 : Interrupt not requested Function R 0 W — interrupt request status bit) 1 : Interrupt requested 5 IRQR2 (SIO2 receive interrupt request status bit) 6-7 W= 0 : Interrupt not requested 1 : Interrupt requested 0 — These bits have no functions assigned. : Only writing a 0 is effective; when you write a 1, the previous value is retained. Transmit/receive interrupt requests from SIO2 are described below. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing a 0 in software. Note: • If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write. 12-9 32171 Group User's Manual (Rev.2.00) 12 s SIO03 Interrupt Mask Register (SI03MASK) D8 9 10 11 12 SERIAL I/O 12.2 Serial I/O Related Registers D 8 Bit Name T0MASK (SIO0 transmit interrupt mask bit) 9 R0MASK (SIO0 receive interrupt mask bit) 10 T1MASK (SIO1 transmit interrupt mask bit) 11 R1MASK (SIO1 receive interrupt mask bit) 12 T2MASK (SIO2 transmit interrupt mask bit) 13 R2MASK (SIO2 receive interrupt mask bit) 14 - 15 No functions assigned. Function 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 — R W This register enables or disables interrupt requests generated by each SIO. Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1. 12-10 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.2 Serial I/O Related Registers s SIO03 Cause of Receive Interrupt Select Register (SI03SEL) D 0-3 4 Bit Name No functions assigned ISR0 (SIO0 receive interrupt cause select bit) 5 ISR1 (SIO1 receive interrupt cause select bit) 6 ISR2 (SIO2 receive interrupt cause select bit) 7 No functions assigned. 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt 0 — Function R 0 W — This register selects the cause of an interrupt generated at completion of receive operation. [When set to 0] Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts occur for receive errors (except an overrun error), as well as for completion of receive operation. [When set to 1] Receive error interrupt is selected. The following lists the types of errors detected for reception errors. • CSIO mode : Overrun error • UART mode : Overrun error, parity error, and framing error 12-11 32171 Group User's Manual (Rev.2.00) 12 TXD2 Data bus b4 b12 IRQT2 F/F T2MASK F/F SERIAL I/O 12.2 Serial I/O Related Registers 2-source inputs SIO23 transmit/receive interrupts (Level) RXD2 receive-finished RXD2 receive error ISR2 b6 F/F b5 b13 IRQR2 F/F R2MASK F/F Figure 12.2.4 Block Diagram of SIO23 Transmit Interrupts 12-12 32171 Group User's Manual (Rev.2.00) 12 12.2.3 SIO Transmit Control Registers s SIO0 Transmit Control Register (S0TCNT) s SIO1 Transmit Control Register (S1TCNT) s SIO2 Transmit Control Register (S2TCNT) SERIAL I/O 12.2 Serial I/O Related Registers D 0,1 2,3 Bit Name No functions assigned CDIV (BRG count source select bit) 00 : Selects f(BCLK) 01 : Selects divided-by-8 f(BCLK) 10 : Selects divided-by-32 f(BCLK) 11 : Selects divided-by-256 f(BCLK) 4 5 No functions assigned TSTAT (Transmit status bit) 0 : Transmit halted & no data in transmit buffer register 1 : Transmit in progress or data exists in transmit buffer register 6 TBE (Transmit buffer empty bit) 7 TEN (Transmit enable bit) 0 : Data exists in transmit buffer register 1 : No data in transmit buffer register 0 : Disables transmit 1 : Enables transmit — 0 — — Function R 0 W — 12-13 32171 Group User's Manual (Rev.2.00) 12 (1) CDIV (baud rate generator count source select) bits SERIAL I/O 12.2 Serial I/O Related Registers (D2, D3) These bits select the count source for the baud rate generator (BRG). Note : • If f(BCLK) is selected as the count source for the BRG, make sure when you set BRG that the baud rate will not exceed the maximum transfer rate. For details, refer to the section of this manual where the SIO baud rate register is described. (2) TSTAT (transmit status) bit [Set condition] This bit is set to 1 by a write to the Transmit Buffer Register when transmit is enabled. [Clear condition] This bit is cleared to 0 when transmit is idle (no data in the Transmit Shift Register) and no data exists in the Transmit Buffer Register. This bit also is cleared by clearing the transmit enable bit. (3) TBE (transmit buffer empty) bit [Set condition] This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register and the Transmit Buffer Register becomes empty. This bit also is set by clearing the transmit enable bit. [Clear condition] This bit is cleared to 0 by writing data to the lower byte of the Transmit Buffer Register when transmit is enabled (TEN = 1). (4) TEN (transmit enable) bit (D7) (D6) (D5) Transmit is enabled by setting this bit to 1 and disabled by clearing this bit to 0. If this bit is cleared to 0 while transmitting data, the transmit operation stops. 12-14 32171 Group User's Manual (Rev.2.00) 12 12.2.4 SIO Transmit/Receive Mode Registers s SIO0 Mode Register (S0MOD) s SIO1 Mode Register (S1MOD) s SIO2 Mode Register (S2MOD) SERIAL I/O 12.2 Serial I/O Related Registers D0 1 2 3 4 5 6 7 8 9 10 11 TDATA 12 13 14 D15 D 0-6 7 - 15 Bit Name No functions assigned TDATA (Transmit data) R = ? : Indeterminate when read Sets transmit data. Function R ? ? W The SIOn Transmit Buffer Register is used to set transmit data. This register is a write-only register, so you cannot read out the content of this register. Set data LSB-aligned, and write transmit data to bits D9-D15 for 7-bit data (UART mode only), D8-D15 for 8-bit data, or D7-D15 for 9-bit data (UART mode only). Before you set data in this register, enable the Transmit Control Register TEN (transmit enable) bit by setting it to 1. Writing data to this register while the TEN bit is disabled (cleared to 0) has no effect. When data is written to the Transmit Buffer Register while transmit is enabled, the data is transferred from the SIO Transmit Buffer Register to the SIO Transmit Shift Register, upon which the serial I/O starts transmitting the data. Note: • For 7-bit and 8-bit data, the register can be accessed bytewise. 12-18 32171 Group User's Manual (Rev.2.00) 12 12.2.6 SIO Receive Buffer Registers s SIO0 Receive Buffer Register (S0RXB) s SIO1 Receive Buffer Register (S1RXB) s SIO2 Receive Buffer Register (S2RXB) SERIAL I/O 12.2 Serial I/O Related Registers D0 1 RSTAT 2 RFIN 3 REN 4 OVR 5 PTY 6 FLM D7 ERS D8 9 10 11 BRG 12 13 14 D15 D 8 - 15 Bit Name BRG (Baud rate divide value) Function Divides the baud rate count source selected by SIO Mode Register by (n + 1) according to the BRG set value 'n.' R W BRG (baud rate divide value) (D8-D15) The SIO Baud Rate Register divides the baud rate count source selected by SIO Mode Register by (BRG set value + 1) according to the BRG set value. In the initial state, the BRG value is indeterminate, so be sure to set the divide value before serial I/O starts operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after the BRG counter finished counting. When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the resulting clock by (BRG set value + 1) according to the BRG set value and then by 2, which results in generating a transmit/receive shift clock. When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/ receive operations are synchronized to the externally supplied clock.) 12-23 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.2 Serial I/O Related Registers In UART mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the resulting clock by (BRG set value + 1) according to the BRG set value and then by 16, which results in generating a transmit/receive shift clock. When using SIO0 or SIO1 in UART mode, you can choose the relevant port (P84 or P87) to function as the SCLKO pin, so that a divided-by-2 BRG output clock can be output from the SCLKO pin. When using the internal clock (internally clocked CSIO), with f(BCLK) selected as the BRG count source, make sure that during CSIO mode, the transfer rate does not exceed 2 Mbits per second. 12-24 32171 Group User's Manual (Rev.2.00) 12 12.3 Transmit Operation in CSIO Mode 12.3.1 Setting the CSIO Baud Rate SERIAL I/O 12.3 Transmit Operation in CSIO Mode The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which to generate the transmit/receive shift clock is selected from the internal clock f(BCLK) or external clock. The CKS (internal/external clock select) bit (SIO Transmit/Receive Mode Register D11 bit) is used to select the clock source. The equation by which to calculate the transmit/receive baud rate values differs with the selected clock source, whether internal or external. (1) When internal clock is selected in CSIO mode When the internal clock is selected, f(BCLK) is divided by the clock divider before being fed into the baud rate generator (BRG). The clock divider's divide-by value is selected from 1, 8, 32, or 256 by using the CDIV (baud rate generator count source select) bits (Transmit Control Register D2, D3 bits). The baud rate generator divides the clock divider output by (baud rate register set value + 1) and then by 2, which results in generating a transmit/receive shift clock. When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below. f (BCLK) Baud rate = [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 2 f(BCLK):Internal peripheral clock operating frequency Baud rate register set value = H'00 to H'FF (Note 1) Clock divider's divide-by value = 1, 8, 32, or 256 Note 1: If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK) itself), make sure the baud rate register value you set does not exceed 2 Mbps. (2) When external clock is selected in CSIO mode In this case, the baud rate generator is not used; instead, the input clock from the SCLKI pin serves directly as CSIO transmit/receive shift clock. The maximum frequency of the SCLKI pin input clock is 1/16 of f(BCLK). Baud rate = SCLKI pin input clock [bps] 12-25 32171 Group User's Manual (Rev.2.00) 12 12.3.2 Initial Settings for CSIO Transmission SERIAL I/O 12.3 Transmit Operation in CSIO Mode To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to CSIO mode • Select the internal or an external clock (2) Setting SIO Transmit Control Register • Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register • Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register) (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit buffer empty interrupt during transmission, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") 12-26 32171 Group User's Manual (Rev.2.00) 12 Initial settings for CSIO transmission SERIAL I/O 12.3 Transmit Operation in CSIO Mode Set SIO Transmit/Receive Mode Register • Set register to CSIO mode • Select internal or external clock Set SIO Transmit Control Register Serial I/O related registers • Select clock divider's divide-by ratio (Note 1) Set SIO Baud Rate Register • Divide-by ratio H'00 to H'FF (Note 2) Set SIO Interrupt Mask Register • Enable/disable transmit buffer empty interrupt Set the Interrupt Controller (When using interrupt) Set DMAC (When using DMAC) Set input/output port Operation Mode Register Initial settings for CSIO transmission finished Note 1 : This is necessary when you use the internal clock. Note 2 : When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. Figure 12.3.1 Procedure for CSIO Transmit Initialization 12-27 32171 Group User's Manual (Rev.2.00) 12 12.3.3 Starting CSIO Transmission SERIAL I/O 12.3 Transmit Operation in CSIO Mode When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. (1) Transmit conditions when CSIO mode internal clock is selected • The SIO Transmit Control Register's transmit enable bit is set to 1. • Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0). (2) Transmit conditions when CSIO mode external clock is selected • The SIO Transmit Control Register's transmit enable bit is set to 1. • Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0). • A falling edge of transmit clock on the SCLKI pin is detected. Notes: • While the transmit enable bit is cleared to 0, writes to the transmit buffer register are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. • When the internal clock is selected, a write to the lower byte of the transmit buffer register in the note above triggers a start of transmission. • The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register. When transmission starts, the serial I/O transmits data following the procedure below. • Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register. • Set the transmit buffer empty bit to 1. (Note 1) • Start sending data synchronously with the shift clock beginning with the LSB. Note 1: A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied. 12.3.4 Successive CSIO Transmission Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Status Register's transmit buffer empty flag. 12-28 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.5 Processing at End of CSIO Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively • When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0. 12.3.6 Transmit Interrupt If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts. 12.3.7 Transmit DMA Transfer Request When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers. 12-29 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.3 Transmit Operation in CSIO Mode The following processing is automatically executed in hardware CSIO transmit operation starts Transmit conditions met? Y N (Note 1) ¥ Transfer content of transmit buffer to transmit shift register ¥ Set transmit buffer empty bit to 1 Transmit interrupt request Transmit DMA transfer request Transmit data Y (Successive transmission) Transmit conditions met? N Clear transmit status bit to 0 CSIO transmit operation completed Note 1: This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing) 12-30 32171 Group User's Manual (Rev.2.00) 12 12.3.8 Typical CSIO Transmit Operation SERIAL I/O 12.3 Transmit Operation in CSIO Mode The following shows a typical transmit operation in CSIO mode. SCLKO TXD SCLKI RXD Internal clock selected Transmit clock (SCLKO) Set External clock selected Transmit enable bit Write to transmit buffer register Cleared Transmit buffer empty bit Set by a write to transmit buffer Transmit status bit TXD Transmit interrupt (Note 4) SIO transmit interrupt (Note 1) Interrupt request accepted : Processing by software (Note 2) (Note 3) : Interrupt generation D7 D6 D5 D4 D3 D2 D1 D0 Content of transmit buffer register transferred to transmit shift register Cleared by completion of transmission Transmit interrupt (Note 5) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once, with Transmit Interrupt Used) 12-31 32171 Group User's Manual (Rev.2.00) 12 SCLKO TXD SERIAL I/O 12.3 Transmit Operation in CSIO Mode SCLKI RXD Internal clock selected External clock selected Transmit clock (SCLKO) Set Transmit enable bit Write to transmit buffer register (First data) Transmit buffer empty bit Write to transmit buffer register (Next data) Cleared Transmit status bit First data TXD (Note 3) (Note 2) SIO transmit interrupt (Note 1) : Processing by software : Interrupt generation D7 D6 D5 D0 D7 Next data D6 D5 D0 Upon transmit buffer empty interrupt, next data is written (Note 2) (Note 4) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : Transmit interrupt request is generated when transmission is enabled. Note 4 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Figure 12.3.4 Example of CSIO Transmission (Successive Transmission, with Transmit Buffer Empty and Transmit Finished Interrupts Used) 12-32 32171 Group User's Manual (Rev.2.00) 12 12.4 Receive Operation in CSIO Mode 12.4.1 Initial Settings for CSIO Reception SERIAL I/O 12.4 Receive Operation in CSIO Mode To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation even when you only want to receive data. (1) Setting SIO Transmit/Receive Mode Register • Set the register to CSIO mode • Select the internal or an external clock (2) Setting SIO Transmit Control Register • Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register • Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register) • Select the cause of receive interrupt (receive finished/error) (Cause of Receive Interrupt Select Register) (5) Setting SIO Receive Control Register Set the receive enable bit (6) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt or receive interrupt during transmission/reception, set its priority level. (7) Setting DMAC When you generate a DMA transfer request to the internal DMAC when the transmit buffer is empty or transmission is completed, set the DMAC. (Refer to Chapter 9, "DMAC.") 12-33 32171 Group User's Manual (Rev.2.00) 12 (8) Selecting pin functions SERIAL I/O 12.4 Receive Operation in CSIO Mode Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") Initial settings for CSIO reception Set SIO Transmit/Receive Mode Register ¥ Set to CSIO mode ¥ Select internal or external clock Set SIO Transmit Control Register ¥ Select clock divider’s divide-by ratio (Note 1) Serial I/O related registers Set SIO Baud Rate Register ¥ Divide-by ratio H’00 to H’FF (Note 2) Set SIO Interrupt Mask Register ¥ Enable/disable transmit buffer empty interrupt Set SIO Receive Control Register ¥ Set receive enable bit Set the Interrupt Controller (When using interrupt) Set DMAC (When using DMAC) Set input/output port Operation Mode Register Initial settings for CSIO reception finished Note 1 : This is necessary when you use the internal clock. Note 2 : When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. Figure 12.4.1 Procedure for CSIO Receive Initialization 12-34 32171 Group User's Manual (Rev.2.00) 12 12.4.2 Starting CSIO Reception SERIAL I/O 12.4 Receive Operation in CSIO Mode When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. (1) Receive conditions when CSIO mode internal clock is selected • The SIO Receive Control Register's receive enable bit is set to 1. • Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") (2) Receive conditions when CSIO mode external clock is selected • The SIO Receive Control Register's receive enable bit is set to 1. • Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") Note: • The receive status bit is set to 1 at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register. When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with the receive shift clock. 12.4.3 Processing at End of CSIO Reception When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Notes: • If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. • A DMA transfer request is generated. (2) When error occurs during reception When an error (only overrun error in CSIO mode) occurs during reception, the overrun error bit and receive sum bit are set to 1. Notes: • If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), neither a receive-finished interrupt request nor a DMA transfer request is generated. • If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated. 12-35 32171 Group User's Manual (Rev.2.00) 12 12.4.4 About Successive Reception SERIAL I/O 12.4 Receive Operation in CSIO Mode When the following conditions are met at completion of data reception, data may be received successively. • The receive enable bit is set to 1. • Transmit conditions are met. • No overrun error has occurred. CSIO receive operation starts Receive conditions met? Y N Receive data Overrun error? Y N Set SIO Receive Control Register's receive-finished bit to 1 Set SIO Receive Control Register's overrun error and receive sum error bits to 1 Store received data in Receive Buffer Register CSIO receive operation completed Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing) 12-36 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.5 Flags Indicating the Status of CSIO Receive Operation Following flags are available that indicate the status of receive operation in CSIO mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit • SIO Receive Control Register receive error sum bit • SIO Receive Control Register overrun error bit After reception is completed, you may read out the content of the SIO Receive Buffer Register, but if the serial I/O finishes receiving the next data before you read, an overrun error occurs. In this case, the data received thereafter is not transferred to the SIO Receive Buffer Register. To restart reception, temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart. The said receive enable bit can be cleared, when there are no receive errors (Note 1) encountered, by reading the lower byte from the SIO Receive Buffer Register or clearing the REN (receive enable) bit. If any receive error has occurred, it can only be cleared by clearing the REN (receive enable) bit, and cannot be cleared by reading the lower byte from the SIO Receive Buffer Register. Note 1: Overrun error is the only error that can be detected during reception in CSIO mode. 12-37 32171 Group User's Manual (Rev.2.00) 12 12.4.6 Typical CSIO Receive Operation SERIAL I/O 12.4 Receive Operation in CSIO Mode The following shows a typical receive operation in CSIO mode. SCLKI TXD RXD SCLKO Internal clock selected Receive clock (SCLKI) Set External clock selected Clock stopped Receive enable bit Cleared RXD D7 Set by a write to transmit buffer D6 D5 D4 D3 D2 D1 D0 Receive status bit Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer Receive-finished interrupt (Note 2) SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) : Processing by software Interrupt request accepted (Note 3) No interrupt request : Interrupt generation Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared Figure 12.4.3 Example of CSIO Reception (When Received Normally) 12-38 32171 Group User's Manual (Rev.2.00) 12 SCLKO RXD SERIAL I/O 12.4 Receive Operation in CSIO Mode SCLKI TXD Internal clock selected Receive clock (SCLKI) Set External clock selected Cleared Receive enable bit First data reception completed Next data reception completed RXD D7 D6 D0 D7 D6 D0 Receive buffer not read during this interval Set Receive-finished bit Overrun error bit Overrun error bit cleared (Note 4) Receive-finished interrupt (Note 2) SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Interrupt request accepted (Note 5) Receive error interrupt (Note 3) (When receive error interrupt is selected) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled Note 3 : When receive error interrupt is enabled Note 4 : Receive enable bit cleared Note 5 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred) 12-39 32171 Group User's Manual (Rev.2.00) 12 12.5 Precautions on Using CSIO Mode SERIAL I/O 12.5 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers. • Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set does not exceed 2 Mbps. • About successive transmission To transmit multiple data successively, set the next transmit data in the SIO Transmit Buffer Register before transmission of the preceding data is completed. • About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation (by sending dummy data) even when you only want to receive data. In this case, note that if the port function is set for TXD pin (by setting the operation mode register to 1), dummy data is actually output from the pin. • About successive reception To receive multiple data successively, set data (dummy data) in the SIO Transmit Buffer Register before the transmitter starts sending data. • Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication. • About the receive-finished bit If a receive error (overrun error) occurs, the receive-finished bit cannot be cleared by reading out the receive buffer register. In this case, it can only be cleared by clearing the receive enable bit. 12-40 32171 Group User's Manual (Rev.2.00) 12 • About overrun error SERIAL I/O 12.5 Precautions on Using CSIO Mode If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Thereafter, although receive operation is continued, no receive data is stored in the Receive Buffer Register (the receive status bit = 1). To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag. • About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty (the transmit buffer empty flag = 1) while the transmit enable bit is set to 1 (transmit enabled), an SIO transmit buffer empty DMA transfer request is generated. • About DMA transfer request generation during SIO reception When the receive-finished bit is set to 1 (the receive buffer register full), a receive-finished DMA transfer request is generated. However, if an overrun error has occurred, this DMA transfer request is not generated. 12-41 32171 Group User's Manual (Rev.2.00) 12 12.6 Transmit Operation in UART Mode 12.6.1 Setting the UART Baud Rate SERIAL I/O 12.6 Transmit Operation in UART Mode The baud rate (data transfer rate) during UART mode is determined by a transmit/receive shift clock. In UART mode, the source for this transmit/receive shift clock is always the internal clock regardless of how the internal/external clock select bit (SIO Transmit/Receive Mode Register bit D11) is set. (1) Calculating the UART mode baud rate After being divided by the clock divider, f(BCLK) is fed into the Baud Rate Generator (BRG), after which it is further divided by 16 to produce a transmit/receive shift clock. The clock divider's divide-by value is selected from 1, 8, 32, or 256 using the SIO Transmit Control Register's CDIV (baud rate generator count source select) bits (D2, D3). The Baud Rate Generator divides the clock it received from the clock divider by (baud rate register set value + 1) and further divides the resulting clock by 16 to produce a transmit/receive shift clock. During UART mode (in which the internal clock is always used), the baud rate is calculated using the equation below. f (BCLK) Baud rate = [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 16 Baud rate register set value = H'00 to H'FF Clock divider's divide-by value = 1, 8, 32, or 256 12-42 32171 Group User's Manual (Rev.2.00) 12 12.6.2 UART Transmit/Receive Data Formats SERIAL I/O 12.6 Transmit Operation in UART Mode The transmit/receive data format during UART mode is determined by setting the SIO Transmit/ Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode. Transmit data Data bits (8 bits) LSB ST Start bit D7 D6 D5 D4 D3 D2 D1 MSB D0 PAR Parity bit SP SP ST Next data Stop bit Figure 12.6.1 Example of Transmit/Receive Data Format in UART Mode Table 12.6.1 Transfer Data in UART Mode Bit Name ST (start bit) Content Indicates the beginning of data transmission. This is a low signal of a one bit duration, which is added immediately before the transmit data. D0-D8 (character bits) Transmit/receive data transferred via serial I/O. In UART mode, data in 7, 8, or 9 bits can be transmitted/received. PAR (parity bit) Added to the transmit/receive characters. When parity is enabled, parity is automatically set in such a way that the number of 1's in characters including the parity bit itself is always even or odd as selected by the even/odd parity select bit. SP (stop bit) Indicates the end of data transmission, and is added immediately after characters (or if parity enabled, immediately after the parity bit). The stop bit can be chosen to be one bit or two bits long. 12-43 32171 Group User's Manual (Rev.2.00) 12 LSB ST ST ST ST D7 D7 D7 D7 D6 D6 D6 D6 D5 D5 D5 D5 D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 SERIAL I/O 12.6 Transmit Operation in UART Mode MSB D1 D1 D1 D1 SP SP PAR PAR SP SP SP SP 7-bit characters LSB ST ST ST ST D7 D7 D7 D7 D6 D6 D6 D6 D5 D5 D5 D5 D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 D1 D1 D1 D1 MSB D0 D0 D0 D0 SP SP PAR PAR SP SP SP SP 8-bit characters LSB ST ST ST ST D8 D8 D8 D8 D7 D7 D7 D7 D6 D6 D6 D6 D5 D5 D5 D5 D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 D1 D1 D1 D1 MSB D0 D0 D0 D0 SP SP PAR PAR SP SP SP SP 9-bit characters SIO Transmit Buffer Register SIO Receive Buffer Register D0 D7 D8 ST : D0 - D7 : PAR : SP : D15 Start bit Character (data) bits Parity bit Stop bit 7-bit characters 8-bit characters 9-bit characters Notes : • The high-order bits of the SIO Receive Buffer Register's selected character bits are fixed to 0. • The data bit numbers (Dn) above indicate bit numbers in a data list, and not the register bit numbers (Dn). Figure 12.6.2 Selectable Data Formats during UART Mode 12-44 32171 Group User's Manual (Rev.2.00) 12 12.6.3 Initial Settings for UART Transmission SERIAL I/O 12.6 Transmit Operation in UART Mode To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to UART mode • Set parity (when enabled, select odd/even) • Set stop bit length • Set character length Note : • During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO Interrupt Mask Register • Enable or disable SIO transmit interrupt (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") 12-45 32171 Group User's Manual (Rev.2.00) 12 Initial settings for UART transmission SERIAL I/O 12.6 Transmit Operation in UART Mode Set SIO Transmit/Receive Mode Register • Set register to UART mode • Set parity (when enabled, select odd/even) • Set stop bit length • Set character length • Select clock divider's divide-by ratio Set SIO Transmit Control Register Serial I/O related registers Set SIO Baud Rate Register • Divide-by ratio H'00 to H'FF Set SIO Interrupt Related Registers Set the Interrupt Controller • Enable/disable transmit interrupt (When using interrupt) Set DMAC related registers (When using DMAC) Set input/output port Operation Mode Register Initial settings for UART transmission finished Figure 12.6.3 Procedure for UART Transmit Initialization 12-46 32171 Group User's Manual (Rev.2.00) 12 12.6.4 Starting UART Transmission SERIAL I/O 12.6 Transmit Operation in UART Mode When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. • The SIO Transmit Control Register's TEN (transmit enable) bit is set to 1. (Note 1) • Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = 0). Note 1: While the transmit enable bit is cleared to 0, writes to the transmit buffer are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. When transmission starts, the serial I/O transmits data following the procedure below. • Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register. • Set the transmit buffer empty bit to 1. (Note 2) • Start sending data synchronously with the shift clock beginning with the LSB. Note 2: A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied. 12.6.5 Successive UART Transmission Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Transmit Control Register's transmit buffer empty flag. 12-47 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.6 Processing at End of UART Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively • When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0. 12.6.7 Transmit Interrupt If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts. 12.6.8 Transmit DMA Transfer Request When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the DMAC before you can transmit data using DMA transfers. 12-48 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.6 Transmit Operation in UART Mode The following processing is automatically executed in hardware UART transmit operation starts Transmit conditions met? Y N (Note 1) • Transfer content of transmit buffer to transmit shift register • Set transmit buffer empty bit to 1 Transmit interrupt request Transmit DMA transfer request Transmit data Y (Successive transmission) Transmit conditions met? N Clear transmit status bit to 0 UART transmit operation completed Note 1: This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing) 12-49 32171 Group User's Manual (Rev.2.00) 12 12.6.9 Typical UART Transmit Operation SERIAL I/O 12.6 Transmit Operation in UART Mode The following shows a typical transmit operation in CSIO mode. TXD RXD Set Transmit enable bit Write to transmit buffer register Set Cleared Transmit buffer empty bit Transferred from transmit buffer to transmit shift register (transmission starts) Cleared Transmit status bit TXD Transmit interrupt (Note 4) SIO transmit interrupt (Note 1) Interrupt request accepted : Processing by software (Note 2) (Note 3) : Interrupt generation ST D7 D6 D0 PAR SP SP Transmit interrupt (Note 5) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Figure 12.6.5 Example of UART Transmission (Transmitted Only Once, with Transmit Interrupt Used) 12-50 32171 Group User's Manual (Rev.2.00) 12 TXD SERIAL I/O 12.6 Transmit Operation in UART Mode RXD Set Transmit enable bit Write to transmit buffer register (First data) Transmit buffer empty bit Transferred from transmit buffer to transmit shift register (transmission starts) Transmit status bit First data TXD (Note 4) (Note 2) SIO transmit interrupt (Note 1) Interrupt request accepted (Note 3) ST D7 D0 SP ST Next data D7 D0 SP Cleared when transmission of last data is completed Write to transmit buffer register (Next data) Cleared Upon transmit interrupt, next data is written (Note 2) (Note 5) : Processing by software : Interrupt generation Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Figure 12.6.6 Example of UART Transmission (Successive Transmission, with Transmit Interrupt Used) 12-51 32171 Group User's Manual (Rev.2.00) 12 12.7 Receive Operation in UART Mode 12.7.1 Initial Settings for UART Reception SERIAL I/O 12.7 Receive Operation in UART Mode To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to UART mode • Set parity (when enabled, select odd/even) • Set stop bit length • Set character length Note : • During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO interrupt related registers • Cause of Receive Interrupt Select Register Select the cause of receive interrupt (receive finished/receive error) • Interrupt Mask Register Enable/disable receive interrupts (5) Setting the Interrupt Controller When you use interrupts during reception, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when reception is completed, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") 12-52 32171 Group User's Manual (Rev.2.00) 12 Initial settings for UART reception SERIAL I/O 12.7 Receive Operation in UART Mode Set SIO Transmit/Receive Mode Register • Set register to UART mode • Set parity (when enabled, select odd/even) • Set stop bit length • Set character length • Select clock divider's divide-by ratio Set SIO Transmit Control Register Serial I/O related registers Set SIO Baud Rate Register • Divide-by ratio H'00 to H'FF Set SIO Interrupt Related Registers • Cause of Receive Interrupt Select Register (receive finished/receive error) • Interrupt Mask Register (enable/disable receive interrupts) Set the interrupt controller SIO Receive Interrupt Control Register (When using interrupt) Set DMAC related registers (When using DMAC) Set input/output port Operation Mode Register Initial settings for UART reception finished Figure 12.7.1 Procedure for UART Receive Initialization 12-53 32171 Group User's Manual (Rev.2.00) 12 12.7.2 Starting UART Reception SERIAL I/O 12.7 Receive Operation in UART Mode When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. • The SIO Receive Control Register's receive enable bit is set to 1 • Start bit (falling edge signal) is applied to the RXD pin When the above conditions are met, the serial I/O enters UART receive operation. However, if the start bit when checked again at the first rise of the internal receive shift clock is detected high for reason of noise, etc., the serial I/O stops receive operation and waits for the start bit again. 12.7.3 Processing at End of UART Reception When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Notes: • If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. • A DMA transfer request is generated. (2) When error occurs during reception When an error occurs during reception, the corresponding error bit (OE, FE, or PE) and the receive sum bit are set to 1. Notes: • If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive-finished interrupt request is generated when interrupt requests are enabled. However, if an overrun error has occurred, this interrupt is not generated. • If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. • No DMA transfer requests are generated. 12-54 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.7 Receive Operation in UART Mode The following processing is automatically executed in hardware UART receive operation starts Receive conditions met ? Y Start bit detected normally? Y Set receive status bit to 1 N N Receive data Y Overrun error? N Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register's overrun error bit and error sum bit to 1 Parity error or framing error? N Y Set SIO Receive Control Register's corresponding error bit and receive error sum bit to 1 Set SIO Receive Control Register's receive-finished bit to 1 UART reception completed Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing) 12-55 32171 Group User's Manual (Rev.2.00) 12 12.7.4 Typical UART Receive Operation SERIAL I/O 12.7 Receive Operation in UART Mode The following shows a typical receive operation in UART mode. TXD RXD Internal clock selected Set Receive enable bit (SIO Receive Control Register) RXD ST D7 D6 D0 PAR SP SP Cleared Receive status bit Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer Receive-finished interrupt (Note 2) SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) Interrupt request accepted (Note 3) No interrupt request : Processing by software : Interrupt generation Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared Figure 12.7.3 Example of UART Reception (When Received Normally) 12-56 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.7 Receive Operation in UART Mode TXD RXD Set Receive enable bit (SIO Receive Control Register) RXD ST First data reception completed Next data reception completed D7 SP ST D7 SP Receive buffer not read during this interval Set (Note 5) Overrun error bit Overrun error bit cleared (Note 4) Receive-finished interrupt (Note 2) Receive-finished bit SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Interrupt request accepted (Note 5) Receive error interrupt (Note 3) (When receive error interrupt is selected) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled Note 3 : When receive error interrupt is enabled Note 4 : This is done by clearing the receive enable bit to 0. Note 5 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred) 12-57 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.5 Detecting the Start Bit during UART Reception The start bit is sampled synchronously with the internal BRG output timing. The start bit is detected as valid when RXD is sampled low eight internal BRG output cycles after detecting a falling edge of the start bit, and another eight cycles later the CPU starts latching RXD as the LSB data (first bit data). If RXD is sampled high at the 8th cycle, the CPU again starts detecting a low-going transition of the start bit. Because RXD is sampled synchronously with the internal BRG, there is a delay equal to a BRG output at maximum. Thereafter, RXD is received with the delayed timing. 16 cycles Internal BRG output 8 cycles RXD Note: • This diagram does not include detailed timing information. 8 cycles LSB data Figure 12.7.5 Detecting the Start Bit Internal BRG output 8 cycles RXD Note: • This diagram does not include detailed timing information. Figure 12.7.6 Example of an Invalid Start Bit (Not Received) Internal BRG output Delay equal to BRG output at maximum RXD Internal RXD Figure 12.7.7 Delay when Receiving 12-58 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.8 Fixed Period Clock Output Function 12.8 Fixed Period Clock Output Function When using SIO0 or SIO1 in UART mode, you can choose the relevant port (P84 or P87) to function as the SCLKO0 or SCLKO1 pin. In this way, a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin. Note : • This clock is output not just during data transfer. 1. Configuration when using BRG/2 clock TXD RXD ST Data Data SP SP UART transmit/receive ST SCLKO Clock output to peripheral circuits 2. Operation timing Internal BRG output BRG period SCLKO output 50% 50% Figure 12.8.1 Example of Fixed Period Clock Output 12-59 32171 Group User's Manual (Rev.2.00) 12 12.9 Precautions on Using UART Mode SERIAL I/O 12.9 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers. • Settings of Baud Rate (BRG) Register The value written to the SIO Baud Rate Register becomes effective beginning with the next period after the BRG counter finished counting. However, when transmit and receive operations are disabled, the register value can be changed at the same time you write to the register. • Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication. • About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Once an overrun error occurs, no receive data is stored in the Receive Buffer Register although receive operation is continued. To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag. 12-60 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.9 Precautions on Using UART Mode • Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit • SIO Receive Control Register receive error sum bit • SIO Receive Control Register overrun error bit • SIO Receive Control Register parity error bit • SIO Receive Control Register framing error bit The manner in which the receive-finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not, as described below. [When no overrun error has occurred] Said bits can be cleared by reading the lower byte from the receive buffer register or clearing the receive enable bit to 0. [When an overrun error has occurred] Said bits can only be cleared by clearing the receive enable bit to 0. 12-61 32171 Group User's Manual (Rev.2.00) 12 SERIAL I/O 12.9 Precautions on Using UART Mode * This is a blank page. * 12-62 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 13 CAN MODULE 13.1 Outline of the CAN Module 13.2 CAN Module Related Registers 13.3 CAN Protocol 13.4 Initializing the CAN Module 13.5 Transmitting Data Frames 13.6 Receiving Data Frames 13.7 Transmitting Remote Frames 13.8 Receiving Remote Frames 13 13.1 Outline of the CAN Module CAN MODULE 13.1 Outline of the CAN Module The 32171 contains CAN (Controller Area Network) Specification 2.0B active-compliant Full CAN module. This module has 16 message slots and three mask registers, effective use of which helps to reduce the CPU load for data processing. The following outlines the Full CAN module. Table 13.1.1 Outline of the CAN Module Item Protocol Number of message slots Polarity Content CAN Specification 2.0B acvtive Total 16 slots (14 global slots, two local slots) 0: Dominant 1: Recessive Acceptance filter One global mask (Function to receive ID in only a specified range by using receive ID filter) Two local masks Baud rate 1 Time quantum (Tq) = (BRP + 1)/CPU clock (BRP: Baud rate prescaler set value) Baud rate = 1 Tq period x number of Tq's for one bit BRP :1-255 (0: Inhibited) ··· Max 1 Mbps (Note 1) Number of Tq's for one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 + Progagation Segment Phase Segment 1 Phase Segment 2 : 1-8Tq : 1-8Tq : 2-8Tq (IPT = 2) Remote frame automatic A slot which received a remote frame automatically sends a data frame. response function Time stamp function Time stamp function implemented by a 16-bit counter. Using CAN bus bit period as the fundamental period, a count period can be set to 1/1 through 1/4 of it. BasicCAN function is materialized using two local slots. Transmit request can be canceled. The data transmitted by CAN module itself is received. Forcibly placed into error active mode after clearing error counter. BasicCAN mode Transmit abort function Loopback function Return bus off function Note 1: The maximum baud rate depends on the system configuration (e.g., bus length, clock error, CAN bus transceiver, sampling position, and bit configuration). 13-2 32171 Group User's Manual (Rev.2.00) 13 Table 13.1.2 CAN Module Interrupt Generation Function CAN module interrupt source CAN0 transmit complete interrupt CAN0 receive complete interrupt CAN0 bus error interrupt CAN0 error passive interrupt CAN0 bus off interrupt ICU interrupt source CAN MODULE 13.1 Outline of the CAN Module CAN0 Transmit/Receive & Error interrupt CAN0 Transmit/Receive & Error interrupt CAN0 Transmit/Receive & Error interrupt CAN0 Transmit/Receive & Error interrupt CAN0 Transmit/Receive & Error interrupt Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CTX CAN0 Protocol Controller Ver 2.0B active CRX Acceptance Filtering 16-bit Timer CAN0 Time Stamp Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 Transmit/ Receive & Error Interrupt Figure 13.1.1 Block Diagram of the CAN Module 13-3 32171 Group User's Manual (Rev.2.00) 13 13.2 CAN Module Related Registers CAN MODULE 13.2 CAN Module Related Registers The diagram below shows a CAN module related register map. Address D0 H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1006 H'0080 1008 H'0080 100A H'0080 100C H'0080 100E H'0080 1010 H'0080 1012 H'0080 1014 H'0080 1016 CAN0 Error Interrupt Status Register (CAN0ERIST) CAN0 Baud Rate Prescaler (CAN0BRP) CAN0 Error Interrupt Mask Register (CAN0ERIMK) CAN0 Slot Interrupt Mask Register (CAN0SLIMK) +0 Address D7 D8 CAN0 Control Register (CAN0CNT) CAN0 Status Register (CAN0STAT) CAN0 Extended ID Register (CAN0EXTID) CAN0 Configuration Register (CAN0CONF) CAN0 Time Stamp Count Register (CAN0TSTMP) CAN0 Receive Error Count Register (CAN0REC) CAN0 Transmit Error Count Register (CAN0TEC) +1 Address D15 CAN0 Slot Interrupt Status Register (CAN0SLIST) ~ ~ H'0080 1028 CAN0 Global Mask Register Standard ID0 (C0GMSKS0) H'0080 102A CAN0 Global Mask Register Extended ID0 (C0GMSKE0) H'0080 102C CAN0 Global Mask Register Extended ID2 (C0GMSKE2) H'0080 102E H'0080 1030 CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) CAN0 Global Mask Register Standard ID1 (C0GMSKS1) CAN0 Global Mask Register Extended ID1 (C0GMSKE1) ~ ~ H'0080 1032 CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) H'0080 1036 H'0080 1038 CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) ~ ~ H'0080 1050 H'0080 1052 H'0080 1054 H'0080 1056 H'0080 1058 CAN0 Message Slot 0 Control Register (C0MSL0CNT) CAN0 Message Slot 2 Control Register (C0MSL2CNT) CAN0 Message Slot 4 Control Register (C0MSL4CNT) CAN0 Message Slot 6 Control Register (C0MSL6CNT) CAN0 Message Slot 8 Control Register (C0MSL8CNT) CAN0 Message Slot 1 Control Register (C0MSL1CNT) CAN0 Message Slot 3 Control Register (C0MSL3CNT) CAN0 Message Slot 5 Control Register (C0MSL5CNT) CAN0 Message Slot 7 Control Register (C0MSL7CNT) CAN0 Message Slot 9 Control Register (C0MSL9CNT) CAN0 Message Slot 11 Control Register (C0MSL11CNT) CAN0 Message Slot 13 Control Register (C0MSL13CNT) CAN0 Message Slot 15 Control Register (C0MSL15CNT) ~ ~ H'0080 105A CAN0 Message Slot 10 Control Register (C0MSL10CNT) H'0080 105C CAN0 Message Slot 12 Control Register (C0MSL12CNT) H'0080 105E CAN0 Message Slot 14 Control Register (C0MSL14CNT) Blank addresses are reserved. ~ ~ Figure 13.2.1 CAN Module Related Register Map (1/4) 13-4 32171 Group User's Manual (Rev.2.00) 13 Address H'0080 1100 H'0080 1102 H'0080 1104 H'0080 1106 H'0080 1108 H'0080 110A H'0080 110C H'0080 110E H'0080 1110 H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1118 H'0080 111A H'0080 111C H'0080 111E H'0080 1120 H'0080 1122 H'0080 1124 H'0080 1126 H'0080 1128 H'0080 112A H'0080 112C H'0080 112E H'0080 1130 H'0080 1132 H'0080 1134 H'0080 1136 H'0080 1138 H'0080 113A H'0080 113C H'0080 113E H'0080 1140 H'0080 1142 H'0080 1144 H'0080 1146 H'0080 1148 H'0080 114A H'0080 114C H'0080 114E H'0080 1150 H'0080 1152 D0 +0 Address D7 D8 CAN MODULE 13.2 CAN Module Related Registers +1 Address D15 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 0 Data 2 (C0MSL0DT2) CAN0 Message Slot 0 Data 4 (C0MSL0DT4) CAN0 Message Slot 0 Data 6 (C0MSL0DT6) CAN0 Message Slot 0 Data 1 (C0MSL0DT1) CAN0 Message Slot 0 Data 3 (C0MSL0DT3) CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 0 Data 7 (C0MSL0DT7) CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) CAN0 Message Slot 1 Data 0 (C0MSL1DT0) CAN0 Message Slot 1 Data 2 (C0MSL1DT2) CAN0 Message Slot 1 Data 4 (C0MSL1DT4) CAN0 Message Slot 1 Data 6 (C0MSL1DT6) CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) CAN0 Message Slot 1 Data 1 (C0MSL1DT1) CAN0 Message Slot 1 Data 3 (C0MSL1DT3) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 1 Data 7 (C0MSL1DT7) CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) CAN0 Message Slot 2 Data 0 (C0MSL2DT0) CAN0 Message Slot 2 Data 2 (C0MSL2DT2) CAN0 Message Slot 2 Data 4 (C0MSL2DT4) CAN0 Message Slot 2 Data 6 (C0MSL2DT6) CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) CAN0 Message Slot 2 Data 1 (C0MSL2DT1) CAN0 Message Slot 2 Data 3 (C0MSL2DT3) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 2 Data 7 (C0MSL2DT7) CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) CAN0 Message Slot 3 Data 0 (C0MSL3DT0) CAN0 Message Slot 3 Data 2 (C0MSL3DT2) CAN0 Message Slot 3 Data 4 (C0MSL3DT4) CAN0 Message Slot 3 Data 6 (C0MSL3DT6) CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) CAN0 Message Slot 3 Data 1 (C0MSL3DT1) CAN0 Message Slot 3 Data 3 (C0MSL3DT3) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) CAN0 Message Slot 3 Data 7 (C0MSL3DT7) CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) CAN0 Message Slot 4 Data 0 (C0MSL4DT0) CAN0 Message Slot 4 Data 2 (C0MSL4DT2) CAN0 Message Slot 4 Data 4 (C0MSL4DT4) CAN0 Message Slot 4 Data 6 (C0MSL4DT6) CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) CAN0 Message Slot 4 Data 1 (C0MSL4DT1) CAN0 Message Slot 4 Data 3 (C0MSL4DT3) CAN0 Message Slot 4 Data 5 (C0MSL4DT5) CAN0 Message Slot 4 Data 7 (C0MSL4DT7) CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) Blank addresses are reserved. Figure 13.2.2 CAN Module Related Register Map (2/4) 13-5 32171 Group User's Manual (Rev.2.00) 13 Address D0 H'0080 1154 H'0080 1156 H'0080 1158 H'0080 115A H'0080 115C H'0080 115E H'0080 1160 H'0080 1162 H'0080 1164 H'0080 1166 H'0080 1168 H'0080 116A H'0080 116C H'0080 116E H'0080 1170 H'0080 1172 H'0080 1174 H'0080 1176 H'0080 1178 H'0080 117A H'0080 117C H'0080 117E H'0080 1180 H'0080 1182 H'0080 1184 H'0080 1186 H'0080 1188 H'0080 118A H'0080 118C H'0080 118E H'0080 1190 H'0080 1192 H'0080 1194 H'0080 1196 H'0080 1198 H'0080 119A H'0080 119C H'0080 119E H'0080 11A0 H'0080 11A2 H'0080 11A4 H'0080 11A6 +0 Address D7 D8 CAN MODULE 13.2 CAN Module Related Registers +1 Address D15 CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Data 2 (C0MSL5DT2) CAN0 Message Slot 5 Data 4 (C0MSL5DT4) CAN0 Message Slot 5 Data 6 (C0MSL5DT6) CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 5 (C0MSL5DT5) CAN0 Message Slot 5 Data 7 (C0MSL5DT7) CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) CAN0 Message Slot 6 Data 0 (C0MSL6DT0) CAN0 Message Slot 6 Data 2 (C0MSL6DT2) CAN0 Message Slot 6 Data 4 (C0MSL6DT4) CAN0 Message Slot 6 Data 6 (C0MSL6DT6) CAN0 Message Slot 6 Data 1 (C0MSL6DT1) CAN0 Message Slot 6 Data 3 (C0MSL6DT3) CAN0 Message Slot 6 Data 5 (C0MSL6DT5) CAN0 Message Slot 6 Data 7 (C0MSL6DT7) CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) CAN0 Message Slot 7 Data 0 (C0MSL7DT0) CAN0 Message Slot 7 Data 2 (C0MSL7DT2) CAN0 Message Slot 7 Data 4 (C0MSL7DT4) CAN0 Message Slot 7 Data 6 (C0MSL7DT6) CAN0 Message Slot 7 Data 1 (C0MSL7DT1) CAN0 Message Slot 7 Data 3 (C0MSL7DT3) CAN0 Message Slot 7 Data 5 (C0MSL7DT5) CAN0 Message Slot 7 Data 7 (C0MSL7DT7) CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) CAN0 Message Slot 8 Data 0 (C0MSL8DT0) CAN0 Message Slot 8 Data 2 (C0MSL8DT2) CAN0 Message Slot 8 Data 4 (C0MSL8DT4) CAN0 Message Slot 8 Data 6 (C0MSL8DT6) CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) CAN0 Message Slot 8 Data 1 (C0MSL8DT1) CAN0 Message Slot 8 Data 3 (C0MSL8DT3) CAN0 Message Slot 8 Data 5 (C0MSL8DT5) CAN0 Message Slot 8 Data 7 (C0MSL8DT7) CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) CAN0 Message Slot 9 Data 0 (C0MSL9DT0) CAN0 Message Slot 9 Data 2 (C0MSL9DT2) CAN0 Message Slot 9 Data 4 (C0MSL9DT4) CAN0 Message Slot 9 Data 6 (C0MSL9DT6) CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) CAN0 Message Slot 9 Data 1 (C0MSL9DT1) CAN0 Message Slot 9 Data 3 (C0MSL9DT3) CAN0 Message Slot 9 Data 5 (C0MSL9DT5) CAN0 Message Slot 9 Data 7 (C0MSL9DT7) CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) CAN0 Message Slot 10 Data 0 (C0MSL10DT0) CAN0 Message Slot 10 Data 1 (C0MSL10DT1) Blank addresses are reserved. Figure 13.2.3 CAN Module Related Register Map (3/4) 13-6 32171 Group User's Manual (Rev.2.00) 13 Address D0 H'0080 11A8 H'0080 11AA H'0080 11AC H'0080 11AE H'0080 11B0 H'0080 11B2 H'0080 11B4 H'0080 11B6 H'0080 11B8 H'0080 11BA H'0080 11BC H'0080 11BE H'0080 11C0 H'0080 11C2 H'0080 11C4 H'0080 11C6 H'0080 11C8 H'0080 11CA H'0080 11CC H'0080 11CE H'0080 11D0 H'0080 11D2 H'0080 11D4 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DC H'0080 11DE H'0080 11E0 H'0080 11E2 H'0080 11E4 H'0080 11E6 H'0080 11E8 H'0080 11EA H'0080 11EC H'0080 11EE H'0080 11F0 H'0080 11F2 H'0080 11F4 H'0080 11F6 H'0080 11F8 H'0080 11FA H'0080 11FC H'0080 11FE ~ ~ H'0080 3FFE Blank addresses are reserved. CAN0 Message Slot 10 Data 2 (C0MSL10DT2) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) CAN0 Message Slot 10 Data 6 (C0MSL10DT6) +0 Address D7 D8 CAN MODULE 13.2 CAN Module Related Registers +1 Address D15 CAN0 Message Slot 10 Data 3 (C0MSL10DT3) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 7 (C0MSL10DT7) CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) CAN0 Message Slot 11 Data 0 (C0MSL11DT0) CAN0 Message Slot 11 Data 2 (C0MSL11DT2) CAN0 Message Slot 11 Data 4 (C0MSL11DT4) CAN0 Message Slot 11 Data 6 (C0MSL11DT6) CAN0 Message Slot 11 Data 1 (C0MSL11DT1) CAN0 Message Slot 11 Data 3 (C0MSL11DT3) CAN0 Message Slot 11 Data 5 (C0MSL11DT5) CAN0 Message Slot 11 Data 7 (C0MSL11DT7) CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) CAN0 Message Slot 12 Data 0 (C0MSL12DT0) CAN0 Message Slot 12 Data 2 (C0MSL12DT2) CAN0 Message Slot 12 Data 4 (C0MSL12DT4) CAN0 Message Slot 12 Data 6 (C0MSL12DT6) CAN0 Message Slot 12 Data 1 (C0MSL12DT1) CAN0 Message Slot 12 Data 3 (C0MSL12DT3) CAN0 Message Slot 12 Data 5 (C0MSL12DT5) CAN0 Message Slot 12 Data 7 (C0MSL12DT7) CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) CAN0 Message Slot 13 Data 0 (C0MSL13DT0) CAN0 Message Slot 13 Data 2 (C0MSL13DT2) CAN0 Message Slot 13 Data 4 (C0MSL13DT4) CAN0 Message Slot 13 Data 6 (C0MSL13DT6) CAN0 Message Slot 13 Data 1 (C0MSL13DT1) CAN0 Message Slot 13 Data 3 (C0MSL13DT3) CAN0 Message Slot 13 Data 5 (C0MSL13DT5) CAN0 Message Slot 13 Data 7 (C0MSL13DT7) CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) CAN0 Message Slot 14 Data 0 (C0MSL14DT0) CAN0 Message Slot 14 Data 2 (C0MSL14DT2) CAN0 Message Slot 14 Data 4 (C0MSL14DT4) CAN0 Message Slot 14 Data 6 (C0MSL14DT6) CAN0 Message Slot 14 Data 1 (C0MSL14DT1) CAN0 Message Slot 14 Data 3 (C0MSL14DT3) CAN0 Message Slot 14 Data 5 (C0MSL14DT5) CAN0 Message Slot 14 Data 7 (C0MSL14DT7) CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) CAN0 Message Slot 15 Data 0 (C0MSL15DT0) CAN0 Message Slot 15 Data 2 (C0MSL15DT2) CAN0 Message Slot 15 Data 4 (C0MSL15DT4) CAN0 Message Slot 15 Data 6 (C0MSL15DT6) CAN0 Message Slot 15 Data 1 (C0MSL15DT1) CAN0 Message Slot 15 Data 3 (C0MSL15DT3) CAN0 Message Slot 15 Data 5 (C0MSL15DT5) CAN0 Message Slot 15 Data 7 (C0MSL15DT7) CAN0 Message Slot 15 Time Stamp (C0MSL15TSP) ~ ~ Figure 13.2.4 CAN Module Related Register Map (4/4) 13-7 32171 Group User's Manual (Rev.2.00) 13 13.2.1 CAN Control Register s CAN0 Control Register (CAN0CNT) D0 1 2 3 4 5 6 TSP 7 8 9 CAN MODULE 13.2 CAN Module Related Registers D 0-3 4 Bit Name No functions assigned RBO (Return bus off) 5 TSR (Time stamp counter reset) 6-7 TSP (Time stamp prescaler) 0: Enables normal operation 1: Requests clearing of error counter 0: Enables count operation 1: Initializes count (by setting H'0000) D6 D7 0 0 : Selects CAN bus bit clock 0 1 : Selects CAN bus bit clock divided by 2 1 0 : Selects CAN bus bit clock divided by 3 1 1 : Selects CAN bus bit clock divided by 4 8-9 10 11 No functions assigned No functions assigned (Always set this bit to 0) FRST (Forcible reset) 12 BCM (BasicCAN mode) 13 14 No functions assigned LBM (Loopback mode) 15 RST (CAN reset) W= 0: Disables loopback function 1: Enables loopback function 0: Negates reset 1: Requests reset 0: Negates rest 1: Forcibly resets 0: Disables BasicCAN function 1: BasicCAN mode 0 – 0 0 – – Function R 0 W – : Only writing a 1 is effective. Automatically cleared to 0 in hardware. 13-8 32171 Group User's Manual (Rev.2.00) 13 (1) RBO (Return Bus Off) bit (D4) CAN MODULE 13.2 CAN Module Related Registers Setting this bit to 1 clears the Receive Error Counter (CAN0REC) and Transmit Error Counter (CAN0TEC) and forcibly places the CAN module into an error active state. This bit is cleared when an error active state is entered. Note: • After clearing the error counter, transmission becomes possible when 11 consecutive recessive bits are detected on the CAN bus. (2) TSR (Time Stamp Counter Reset) bit (D5) Setting this bit to 1 clears the value of the CAN Time Stamp Counter Register (CAN0TSTMP) to H'0000. This bit is cleared when the value of the CAN Time Stamp Counter Register (CAN0TSTMP) is cleared to H'0000. (3) TSP (Time Stamp Prescaler) bits (D6, D7) These bits select the count clock source for the time stamp counter. Note: • Do not change settings of TSP bits while CAN is operating (CAN Status Register CRS bit = 0). (4) FRST (Forcible Reset) bit (D11) When the FRST bit is set to 1, the CAN module is separated from the CAN bus regardless of whether or not the CAN module is communicating and the protocol control unit is reset. Up to 5 BCLK periods are required before the protocol control unit is reset after setting the FRST bit. Notes: • If the FRST bit is set to 1 during communication, the CTX pin output goes high immediately after that. Therefore, setting the FRST bit to 1 while transmitting CAN frame may cause a CAN bus error. • When the protocol control unit is reset by setting the RST bit to 1, the CAN Time Stamp Count Register and CAN Transmit/Receive Error Count Registers are initialized to 0. • To restart CAN communication, the FRST and RST bits must be cleared to 0. • The CAN Message Slot Control Register's transmit/receive request are not cleared for reasons that the FRST or RST bits are set. (5) BCM (BasicCAN Mode) bit (D12) By setting this bit to 1, the CAN module can be operated in BasicCAN mode. • Operation during BasicCAN mode In BasicCAN mode, two local slots-slots 14 and 15-are used as double buffers, and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15. Used for this acceptance filtering when slot 14 is active (next receive frame to be stored in slot 14) are the ID set for slot 14 and local mask A, and those used when slot 15 is active are the ID set for slot 15 and local mask B. Two types of frames-data frame and remote frame-can be received in this mode. 13-9 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers By using the same ID and setting the same value in mask registers for the two slots, the possibility of a message-lost trouble when, for example, receiving frames which have many IDs can be reduced. • Procedure for entering BasicCAN mode Follow the procedure below during initialization: 1 Set the IDs for slots 14 and 15 and local mask registers A and B. (We recommend 2 3 4 setting the same value.) Set the frame types handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type.) Set the Message Slot Control Register for slots 14 and 15 to for data frame reception. Set the BCM bit to 1. Notes: • Do not change settings of BCM bit when CAN is operating (CAN Status Register CRS bit = 0). • The first slot that is active after clearing the RST bit is slot 14. • Even during BasicCAN mode, slots 0 to 13 can be used as in normal operation. (6) LBM (Loopback Mode) bit (D14) When the LBM bit is set to 1, if a receive slot exists whose ID matches that of the frame sent by the CAN module itself, then the frame can be received. Notes: • No ACK is returned for the transmit frame. • Do not change settings of LBM bit when CAN is operating (CAN Status Register CRS bit = 0). (7) RST (CAN Reset) bit (D15) When the RST bit is cleared to 0, the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits. Also, the CAN Time Stamp Count Register thereby starts counting. When the RST bit is set to 1, the CAN module is reset so that after sending a frame from the slot which has had a transmit request set, the protocol control unit is reset and the CAN module is disconnected from the CAN bus. Frames received during this time are processed normally. Notes: • It is inhibited to set a new transmit request for a while from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset. • When the protocol control unit is reset by setting the RST bit to 1, the CAN Time Stamp Count Register and CAN Transmit/Receive Error Count Registers are initialized to 0. • To restart CAN communication, the FRST and RST bits must be cleared to 0. 13-10 32171 Group User's Manual (Rev.2.00) 13 13.2.2 CAN Status Register s CAN0 Status Register (CAN0STAT) D0 1 2 3 4 5 0 6 7 8 9 CAN MODULE 13.2 CAN Module Related Registers D 0 1 Bit Name No functions assigned BOS (Bus off status) 2 EPS (Error passive status) 3 CBS (CAN bus error) 4 BCS (BasicCAN status) 5 6 No functions assigned LBS (Loopback status) 7 CRS (CAN reset status) 8 RSB (Receive status) 9 TSB (Transmit status) 10 RSC (Receive complete status) 11 TSC (Transmit complete status) 0: Normal mode 1: Loopback mode 0: Operating 1: Reset 0: Not receiving 1: Receiving 0: Not transmitting 1: Transmitting 0: Reception not completed yet 1: Reception completed 0: Transmission not completed yet 1: Transmission completed – – – – – 0: Not Bus off 1: Bus off state 0: Not error passive 1: Error passive state 0: No error occurred 1: Error occurred 0: Normal mode 1: BasicCAN mode 0 – – – – – Function R 0 W – – 13-11 32171 Group User's Manual (Rev.2.00) 13 D 12-15 Bit Name MSN (Message slot number) Function CAN MODULE 13.2 CAN Module Related Registers R W Number of message slot which has finished sending or receiving 0000 : Slot0 0001 : Slot1 0010 : Slot2 0011 : Slot3 0100 : Slot4 0101 : Slot5 0110 : Slot6 0111 : Slot7 1000 : Slot8 1001 : Slot9 1010 : Slot10 1011 : Slot11 1100 : Slot12 1101 : Slot13 1110 : Slot14 1111 : Slot15 – (1) BOS (Bus Off Status) bit (D1) When BOS bit = 1, it means that the CAN module is in a bus-off state. [Set condition] This bit is set to 1 when the transmit error counter value exceeded 255 and a bus-off state is entered. [Clear condition] This bit is cleared when returned from the bus-off state. (2) EPS (Error Passive Status) bit (D2) When EPS bit = 1, it means that the CAN module is in an error passive state. [Set condition] This bit is set to 1 when the transmit or receive error counter value exceeded 127 and an error passive state is entered. [Clear condition] This bit is cleared when switched from the error passive state. 13-12 32171 Group User's Manual (Rev.2.00) 13 (3) CBS (CAN Bus Error) bit (D3) [Set condition] CAN MODULE 13.2 CAN Module Related Registers This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when normally transmitted or received. (4) BCS (BasicCAN Status) bit (D4) When BCS bit = 1, it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to 1 when operating in BasicCAN mode. BasicCAN mode operates under the following conditions: • The CAN Control Register BCM bit must be set to 1. • Slots 14 and 15 both must be set for data frame reception. [Clear condition] This bit is cleared by clearing the BCM bit to 0. (5) LBS (Loopback Status) bit (D6) When LBS bit = 1, it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to 1 by setting the CAN Control Register LBM (loopback mode) bit to 1. [Clear condition] This bit is cleared by clearing the LBM bit to 0. (6) CRS (CAN Reset Status) bit (D7) When CRS bit = 1, it means that the protocol control unit is in a reset state. [Set condition] This bit is set to 1 when the CAN module's protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) bit to 0. 13-13 32171 Group User's Manual (Rev.2.00) 13 (7) RSB (Receive Status) bit (D8) CAN MODULE 13.2 CAN Module Related Registers [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module started operating as a transmit node or entered a bus idle state. (8) TSB (Transmit Status) bit (D9) [Set condition] This bit is set to 1 when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module started operating as a receive node or entered a bus idle state. (9) RSC (Receive Complete Status) bit (D10) [Set condition] This bit is set to 1 when the CAN module finished receiving normally (regardless of whether any slot exists that meets receive conditions). [Clear condition] This bit is cleared when the CAN module finished transmitting normally. (10) TSC (Transmit Complete Status) bit (D11) [Set condition] This bit is set to 1 when the CAN module finished transmitting normally. [Clear condition] This bit is cleared when the CAN module finished receiving normally. (11) MSN (Message Slot Number) bits (D12-D15) These bits show the relevant slot number when the CAN module finished transmitting or finished storing received data. This bit cannot be cleared to 0 in software. 13-14 32171 Group User's Manual (Rev.2.00) 13 13.2.3 CAN Extended ID Register s CAN0 Extended ID Register (CAN0EXTID) D0 IDE0 CAN MODULE 13.2 CAN Module Related Registers D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name IDE0 (Extended ID0) IDE1 (Extended ID1) IDE2 (Extended ID2) IDE3 (Extended ID3) IDE4 (Extended ID4) IDE5 (Extended ID5) IDE6 (Extended ID6) IDE7 (Extended ID7) IDE8 (Extended ID8) IDE9 (Extended ID9) IDE10 (Extended ID10) IDE11 (Extended ID11) IDE12 (Extended ID12) IDE13 (Extended ID13) IDE14 (Extended ID14) IDE15 (Extended ID15) Function 0: Standard ID format 1: Extended ID format R W This register selects the format of frames handled in message slots corresponding to each bit. The standard ID format is selected when a message slot's corresponding bit is set to 0, or the extended ID format is selected when the bit is set to 1. Note: • Settings of each bit of this register can only be changed when the corresponding slot does not have transmit or receive requests set. 13-15 32171 Group User's Manual (Rev.2.00) 13 13.2.4 CAN Configuration Register s CAN0 Configuration Register (CAN0CONF) D0 SJW 1 2 3 PH2 4 5 6 PH1 7 8 9 CAN MODULE 13.2 CAN Module Related Registers D 0-1 Bit Name SJW (reSynchronization Jump Width) Function Sets reSynchronization Jump Width 00: SJW = 1Tq 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq 2-4 PH2 (Phase Segment2) Sets Phase Segment2 000: Settings inhibited 001: Phase Segment2 = 2Tq 010: Phase Segment2 = 3Tq 011: Phase Segment2 = 4Tq 100: Phase Segment2 = 5Tq 101: Phase Segment2 = 6Tq 110: Phase Segment2 = 7Tq 111: Phase Segment2 = 8Tq 5-7 PH1 (Phase Segment1) Sets Phase Segment1 000: Phase Segment1 = 1Tq 001: Phase Segment1 = 2Tq 010: Phase Segment1 = 3Tq 011: Phase Segment1 = 4Tq 100: Phase Segment1 = 5Tq 101: Phase Segment1 = 6Tq 110: Phase Segment1 = 7Tq 111: Phase Segment1 = 8Tq R W 13-16 32171 Group User's Manual (Rev.2.00) 13 D 8-10 Bit Name PRB (Propagation Segment) CAN MODULE 13.2 CAN Module Related Registers 12 13 14 D15 CANTSTMP 5 6 D7 D 8-15 Bit Name TEC (Transmit error counter) Function Transmit error count value R W – In an error-active/error-passive state, a transmit error count is stored in this register. When transmitted normally, the counter counts down; when an error occurs, the counter counts up. In a bus-off state, an indeterminate value is stored in this register. The count is reset to H'00 upon returning to an error-active state. 13-21 32171 Group User's Manual (Rev.2.00) 13 13.2.7 CAN Baud Rate Prescaler s CAN0 Baud Rate Prescaler (CAN0BRP) D0 1 2 3 BRP 4 CAN MODULE 13.2 CAN Module Related Registers D 0-7 Bit Name BRP Function Selects baud rate prescaler value R W This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period x number of Tq's for 1 bit). Tq period = (CANBRP + 1)/ CPU clock CAN transfer baud rate = 1 Tq period × number of Tq's for 1 bit Progagation Segment + Phase Segment 1 + Phase Segment 2 Note: • Setting H'00 (divided by 1) is inhibited. Number of Tq's for 1 bit = Synchronization Segment + 13-22 32171 Group User's Manual (Rev.2.00) 13 13.2.8 CAN Interrupt Related Registers CAN MODULE 13.2 CAN Module Related Registers s CAN0 Slot Interrupt Status Register (CAN0SLIST) D0 1 2 3 4 5 6 7 8 9 10 11 D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 W= Bit Name SSB0 (Slot 0 interrupt request status) SSB1 (Slot 1 interrupt request status) SSB2 (Slot 2 interrupt request status) SSB3 (Slot 3 interrupt request status) SSB4 (Slot 4 interrupt request status) SSB5 (Slot 5 interrupt request status) SSB6 (Slot 6 interrupt request status) SSB7 (Slot 7 interrupt request status) SSB8 (Slot 8 interrupt request status) SSB9 (Slot 9 interrupt request status) SSB10 (Slot 10 interrupt request status) SSB11 (Slot 11 interrupt request status) SSB12 (Slot 12 interrupt request status) SSB13 (Slot 13 interrupt request status) SSB14 (Slot 14 interrupt request status) SSB15 (Slot 15 interrupt request status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. Function 0: No interrupt request 1: Interrupt requested R W 13-23 32171 Group User's Manual (Rev.2.00) 13 • Slots set for transmission CAN MODULE 13.2 CAN Module Related Registers When using CAN interrupts, this register lets you know which slot requested an interrupt. The bit is set to 1 when the CAN module finished transmitting. The bit is cleared by writing a 0 in software. • Slots set for reception The bit is set to 1 when the CAN module finished receiving and finished storing the received message in the message slot. The bit is cleared by writing a 0 in software. When writing to the CAN slot interrupt status, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write. Notes: • If the automatic response function is enabled for remote frame receive slots, the status is set after the CAN module received a remote frame and when it transmitted a data frame. • For remote frame transmit slots, the status is set after the CAN module transmitted a remote frame and when it received a data frame. • If the status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the status is set. 13-24 32171 Group User's Manual (Rev.2.00) 13 D0 IRB0 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Slot Interrupt Mask Register (CAN0SLIMK) 1 IRB1 D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name IRB0 (Slot 0 interrupt request mask) IRB1 (Slot 1 interrupt request mask) IRB2 (Slot 2 interrupt request mask) IRB3 (Slot 3 interrupt request mask) IRB4 (Slot 4 interrupt request mask) IRB5 (Slot 5 interrupt request mask) IRB6 (Slot 6 interrupt request mask) IRB7 (Slot 7 interrupt request mask) IRB8 (Slot 8 interrupt request mask) IRB9 (Slot 9 interrupt request mask) IRB10 (Slot 10 interrupt request mask) IRB11 (Slot 11 interrupt request mask) IRB12 (Slot 12 interrupt request mask) IRB13 (Slot 13 interrupt request mask) IRB14 (Slot 14 interrupt request mask) IRB15 (Slot 15 interrupt request mask) Function 0: Masks (disables) interrupt request 1: Enables interrupt request R W This register controls interrupt requests generated at completion of data transmission or reception in each corresponding slot by enabling or disabling them. When IRBn (n = 0-15) is set to 1, interrupt requests to be generated at completion of transmission or reception in the corresponding slot are enabled. The CAN Slot Interrupt Status Register (CAN0SLIST) shows you which slot has requested the interrupt. 13-25 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Error Interrupt Status Register (CAN0ERIST) D0 1 2 3 4 5 EIS Slot 0 transmit/receive completed Data bus b0 b0 SSB0 F/F IRB0 F/F CAN MODULE 13.2 CAN Module Related Registers 19-source inputs CAN0 transmit/receive & error interrupts (Level) Slot 1 transmit/receive completed b1 b1 SSB1 F/F IRB1 F/F Slot 2 transmit/receive completed b2 b2 SSB2 F/F IRB2 F/F Slot 3 transmit/receive completed b3 b3 SSB3 F/F IRB3 F/F Slot 4 transmit/receive completed b4 b4 SSB4 F/F IRB4 F/F Slot 5 transmit/receive completed b5 b5 SSB5 F/F IRB5 F/F Slot 6 transmit/receive completed b6 b6 SSB6 F/F IRB6 F/F Slot 7 transmit/receive completed b7 b7 SSB7 F/F IRB7 F/F To remaining 11-source inputs in the next page ~ Figure 13.2.5 Block Diagram of CAN0 Group Interrupts (1/3) 13-28 32171 Group User's Manual (Rev.2.00) 13 CAN0SLIST Slot 8 transmit/receive completed Data bus b8 b8 SSB8 F/F IRB8 F/F CAN MODULE 13.2 CAN Module Related Registers From 8-source inputs in the previous page ~ 19-source inputs To preceding page (Level) Slot 9 transmit/receive completed b9 b9 SSB9 F/F IRB9 F/F Slot 10 transmit/receive completed b10 b10 SSB10 F/F IRB10 F/F Slot 11 transmit/receive completed b11 b11 SSB11 F/F IRB11 F/F Slot 12 transmit/receive completed b12 b12 SSB12 F/F IRB12 F/F Slot 13 transmit/receive completed b13 b13 SSB13 F/F IRB13 F/F Slot 14 transmit/receive completed b14 b14 SSB14 F/F IRB14 F/F Slot 15 transmit/receive completed b15 b15 SSB15 F/F IRB15 F/F To remaining 3-source inputs in the next page ~ Figure 13.2.6 Block Diagram of CAN0 Group Interrupts (2/3) 13-29 32171 Group User's Manual (Rev.2.00) 13 CAN0ERIST CAN bus error occurs Data bus b5 b13 EIS F/F EIM F/F CAN MODULE 13.2 CAN Module Related Registers From 16-source inputs in the previous pages ~ 19-source inputs To preceding page (Level) Go to error passive state b6 b14 PIS F/F PIM F/F Go to bus-off state b7 b15 OIS F/F OIM F/F Figure 13.2.7 Block Diagram of CAN0 Group Interrupts (3/3) 13-30 32171 Group User's Manual (Rev.2.00) 13 13.2.9 CAN Mask Registers CAN MODULE 13.2 CAN Module Related Registers s CAN0 Global Mask Register Standard ID0 (C0GMSKS0) s CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) D 0-2 3-7 Bit Name No functions assigned SID0M-SID4M (Standard ID0 to standard ID4) 0: ID not checked 1: ID checked Function R 0 W – s CAN0 Global Mask Register Standard ID1 (C0GMSKS1) s CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) D 8-9 10-15 Bit Name No functions assigned SID5M-SID10M (Standard ID5 to standard ID10) 0: ID not checked 1: ID checked Function R 0 W – 13-31 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively. • When a bit in this register is set to 0, its corresponding ID bit is masked (assumed to have matched) during acceptance filtering. • When a bit in this register is set to 1, its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot, the received data is stored in it. Notes: • SID0M corresponds to the MSB of standard ID. • The Global Mask Register can only be changed when none of slots 0-13 have receive requests set. • The Local Mask Register A can only be changed when slot 14 does not have a receive request set. • The Local Mask Register B can only be changed when slot 15 does not have a receive request set. 13-32 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Global Mask Register Extended ID0 (C0GMSKE0) s CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) D 0-3 4-7 Bit Name No functions assigned EID0M-EID3M (Extended ID0 to extended ID3) 0: ID not checked 1: ID checked Function R 0 W – s CAN0 Global Mask Register Extended ID1 (C0GMSKE1) s CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) D 8-15 Bit Name EID4M-EID11M (Extended ID4 to extended ID11) Function 0: ID not checked 1: ID checked R W 13-33 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Global Mask Register Extended ID2 (C0GMSKE2) s CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) D 0,1 2-7 Bit Name No functions assigned EID12M-EID17M (Extended ID12 to extended ID17) 0: ID not checked 1: ID checked Function R 0 W – Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively. • When a bit in this register is set to 0, its corresponding ID bit is masked (assumed to have matched) during acceptance filtering. • When a bit in this register is set to 1, its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot, the received data is stored in it. Notes: • EID0M corresponds to the MSB of extended ID. •The Global Mask Register can only be changed when none of slots 0-13 have receive requests set. • The Local Mask Register A can only be changed when slot 14 does not have a receive request set. • The Local Mask Register B can only be changed when slot 15 does not have a receive request set. 13-34 32171 Group User's Manual (Rev.2.00) 13 Slot 0 CAN MODULE 13.2 CAN Module Related Registers Slot 1 Slot 2 Slots controlled by the Global Mask Register Slot 13 Slots controlled by Local Mask Register A Slot 14 Slot 15 Slots controlled by Local Mask Register B Figure 13.2.8 Relationship between Mask Registers and the Controlled Slots Receive frame ID ID set in slot Mask register set value Mask bit value 0: Don’t care matching of the corresponding ID of the received message 1: Check matching of the corresponding ID of the received message Acceptance determination signal Acceptance determination signal 0: The received message is ignored (not stored in any slot) 1: The received message is stored in a slot whose ID matches that of the message Figure 13.2.9 Operation of the Acceptance Filter 13-35 32171 Group User's Manual (Rev.2.00) 13 13.2.10 CAN Message Slot Control Registers CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot0 Control Registers (COMSL0CNT) s CAN0 Message Slot1 Control Registers (COMSL1CNT) s CAN0 Message Slot2 Control Registers (COMSL2CNT) s CAN0 Message Slot3 Control Registers (COMSL3CNT) s CAN0 Message Slot4 Control Registers (COMSL4CNT) s CAN0 Message Slot5 Control Registers (COMSL5CNT) s CAN0 Message Slot6 Control Registers (COMSL6CNT) s CAN0 Message Slot7 Control Registers (COMSL7CNT) s CAN0 Message Slot8 Control Registers (COMSL8CNT) s CAN0 Message Slot9 Control Registers (COMSL9CNT) s CAN0 Message Slot10 Control Registers (COMSL10CNT) s CAN0 Message Slot11 Control Registers (COMSL11CNT) s CAN0 Message Slot12 Control Registers (COMSL12CNT) s CAN0 Message Slot13 Control Registers (COMSL13CNT) s CAN0 Message Slot14 Control Registers (COMSL14CNT) s CAN0 Message Slot15 Control Registers (COMSL15CNT) D0(D8) TR 1 RR 2 RM 3 RL 4 RA 5 ML 6 TRSTAT D7(D15) TRFIN 6 SID3 D7 SID4 D 0-2 3-7 Bit Name No functions assigned (Always set these bits to 0) SID0-SID4 (Standard ID0 to standard ID4) Standard ID0 to standard ID4 Function R 0 W – These registers are the transmit frame/receive frame memory space. 13-40 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) s CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) s CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) s CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) s CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) s CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) s CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) s CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) s CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) s CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) s CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) s CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) s CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) s CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) s CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) s CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) D8 9 10 SID5 11 SID6 12 SID7 13 SID8 14 SID9 D15 SID10 D 8,9 10-15 Bit Name No functions assigned (Always set these bits to 0) SID5-SID10 (Standard ID5 to standard ID10) Standard ID5 to standard ID10 Function R 0 W – These registers are the transmit frame/receive frame memory space. 13-41 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) s CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) s CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) s CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) s CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) s CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) s CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) s CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) s CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) s CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) s CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) s CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) s CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) s CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) s CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) s CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) D0 1 2 3 4 EID0 5 EID1 6 EID2 D7 EID3 D 0-3 4-7 Bit Name No functions assigned (Always set these bits to 0) EID0-EID3 (Extended ID0 to extended ID3) Extended ID0 to extended ID3 Function R 0 W – These registers are the transmit frame/receive frame memory space. Note: • When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-42 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) s CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) s CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) s CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) s CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) s CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) s CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) s CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) s CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) s CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) s CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) s CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) s CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) s CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) s CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) s CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) D8 EID4 9 EID5 10 EID6 11 EID7 12 EID8 13 EID9 14 EID10 D15 EID11 D 8-15 Bit Name EID4-EID11 (Extended ID4 to extended ID11) Function Extended ID4 to extended ID11 R W These registers are the transmit frame/receive frame memory space. Note: • When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-43 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) s CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) s CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) s CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) s CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) s CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) s CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) s CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) s CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) s CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) s CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) s CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) s CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) s CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) s CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) s CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) D0 1 2 EID12 3 EID13 4 EID14 5 EID15 6 EID16 D7 EID17 D 0,1 2-7 Bit Name No functions assigned (Always set these bits to 0) EID12-EID17 (Extended ID12 to extended ID17) Extended ID12 to extended ID17 Function R 0 W – These registers are the transmit frame/receive frame memory space. Note: • When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-44 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) s CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) s CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) s CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) s CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) s CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) 14 DLC2 D15 DLC3 D 8-11 12-15 Bit Name No functions assigned (Always set these bits to 0) DLC0-DLC3 (Sets data length) 0 0 0 0 : 0 byte 0 0 0 1 : 1 byte 0 0 1 0 : 2 byte 0 0 1 1 : 3 byte 0 1 0 0 : 4 byte 0 1 0 1 : 5 byte 0 1 1 0 : 6 byte 0 1 1 1 : 7 byte 1 X X X : 8 byte Function R 0 W – These registers are the transmit frame/receive frame memory space. When transmitting, the register sets the length of transmit data. When receiving, the register stores the received DLC. 13-45 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 0 (C0MSL0DT0) s CAN0 Message Slot 1 Data 0 (C0MSL1DT0) s CAN0 Message Slot 2 Data 0 (C0MSL2DT0) s CAN0 Message Slot 3 Data 0 (C0MSL3DT0) s CAN0 Message Slot 4 Data 0 (C0MSL4DT0) s CAN0 Message Slot 5 Data 0 (C0MSL5DT0) s CAN0 Message Slot 6 Data 0 (C0MSL6DT0) s CAN0 Message Slot 7 Data 0 (C0MSL7DT0) s CAN0 Message Slot 8 Data 0 (C0MSL8DT0) s CAN0 Message Slot 9 Data 0 (C0MSL9DT0) s CAN0 Message Slot 10 Data 0 (C0MSL10DT0) s CAN0 Message Slot 11 Data 0 (C0MSL11DT0) s CAN0 Message Slot 12 Data 0 (C0MSL12DT0) s CAN0 Message Slot 13 Data 0 (C0MSL13DT0) s CAN0 Message Slot 14 Data 0 (C0MSL14DT0) s CAN0 Message Slot 15 Data 0 (C0MSL15DT0) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT0 D 0-7 Bit Name COMSLnDT0 Function Message slot n data 0 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 0, an indeterminate value is written to this register. 13-46 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 1 (C0MSL0DT1) s CAN0 Message Slot 1 Data 1 (C0MSL1DT1) s CAN0 Message Slot 2 Data 1 (C0MSL2DT1) s CAN0 Message Slot 3 Data 1 (C0MSL3DT1) s CAN0 Message Slot 4 Data 1 (C0MSL4DT1) s CAN0 Message Slot 5 Data 1 (C0MSL5DT1) s CAN0 Message Slot 6 Data 1 (C0MSL6DT1) s CAN0 Message Slot 7 Data 1 (C0MSL7DT1) s CAN0 Message Slot 8 Data 1 (C0MSL8DT1) s CAN0 Message Slot 9 Data 1 (C0MSL9DT1) s CAN0 Message Slot 10 Data 1 (C0MSL10DT1) s CAN0 Message Slot 11 Data 1 (C0MSL11DT1) s CAN0 Message Slot 12 Data 1 (C0MSL12DT1) s CAN0 Message Slot 13 Data 1 (C0MSL13DT1) s CAN0 Message Slot 14 Data 1 (C0MSL14DT1) s CAN0 Message Slot 15 Data 1 (C0MSL15DT1) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT1 D 8-15 Bit Name COMSLnDT1 Function Message slot n data 1 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 1 or less , an indeterminate value is written to this register. 13-47 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 2 (C0MSL0DT2) s CAN0 Message Slot 1 Data 2 (C0MSL1DT2) s CAN0 Message Slot 2 Data 2 (C0MSL2DT2) s CAN0 Message Slot 3 Data 2 (C0MSL3DT2) s CAN0 Message Slot 4 Data 2 (C0MSL4DT2) s CAN0 Message Slot 5 Data 2 (C0MSL5DT2) s CAN0 Message Slot 6 Data 2 (C0MSL6DT2) s CAN0 Message Slot 7 Data 2 (C0MSL7DT2) s CAN0 Message Slot 8 Data 2 (C0MSL8DT2) s CAN0 Message Slot 9 Data 2 (C0MSL9DT2) s CAN0 Message Slot 10 Data 2 (C0MSL10DT2) s CAN0 Message Slot 11 Data 2 (C0MSL11DT2) s CAN0 Message Slot 12 Data 2 (C0MSL12DT2) s CAN0 Message Slot 13 Data 2 (C0MSL13DT2) s CAN0 Message Slot 14 Data 2 (C0MSL14DT2) s CAN0 Message Slot 15 Data 2 (C0MSL15DT2) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT2 D 0-7 Bit Name COMSLnDT2 Function Message slot n data 2 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 2 or less, an indeterminate value is written to this register. 13-48 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 3 (C0MSL0DT3) s CAN0 Message Slot 1 Data 3 (C0MSL1DT3) s CAN0 Message Slot 2 Data 3 (C0MSL2DT3) s CAN0 Message Slot 3 Data 3 (C0MSL3DT3) s CAN0 Message Slot 4 Data 3 (C0MSL4DT3) s CAN0 Message Slot 5 Data 3 (C0MSL5DT3) s CAN0 Message Slot 6 Data 3 (C0MSL6DT3) s CAN0 Message Slot 7 Data 3 (C0MSL7DT3) s CAN0 Message Slot 8 Data 3 (C0MSL8DT3) s CAN0 Message Slot 9 Data 3 (C0MSL9DT3) s CAN0 Message Slot 10 Data 3 (C0MSL10DT3) s CAN0 Message Slot 11 Data 3 (C0MSL11DT3) s CAN0 Message Slot 12 Data 3 (C0MSL12DT3) s CAN0 Message Slot 13 Data 3 (C0MSL13DT3) s CAN0 Message Slot 14 Data 3 (C0MSL14DT3) s CAN0 Message Slot 15 Data 3 (C0MSL15DT3) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT3 D 8-15 Bit Name COMSLnDT3 Function Message slot n data 3 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 3 or less, an indeterminate value is written to this register. 13-49 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 4 (C0MSL0DT4) s CAN0 Message Slot 1 Data 4 (C0MSL1DT4) s CAN0 Message Slot 2 Data 4 (C0MSL2DT4) s CAN0 Message Slot 3 Data 4 (C0MSL3DT4) s CAN0 Message Slot 4 Data 4 (C0MSL4DT4) s CAN0 Message Slot 5 Data 4 (C0MSL5DT4) s CAN0 Message Slot 6 Data 4 (C0MSL6DT4) s CAN0 Message Slot 7 Data 4 (C0MSL7DT4) s CAN0 Message Slot 8 Data 4 (C0MSL8DT4) s CAN0 Message Slot 9 Data 4 (C0MSL9DT4) s CAN0 Message Slot 10 Data 4 (C0MSL10DT4) s CAN0 Message Slot 11 Data 4 (C0MSL11DT4) s CAN0 Message Slot 12 Data 4 (C0MSL12DT4) s CAN0 Message Slot 13 Data 4 (C0MSL13DT4) s CAN0 Message Slot 14 Data 4 (C0MSL14DT4) s CAN0 Message Slot 15 Data 4 (C0MSL15DT4) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT4 D 0-7 Bit Name COMSLnDT4 Function Message slot n data 4 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 4 or less, an indeterminate value is written to this register. 13-50 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 5 (C0MSL0DT5) s CAN0 Message Slot 1 Data 5 (C0MSL1DT5) s CAN0 Message Slot 2 Data 5 (C0MSL2DT5) s CAN0 Message Slot 3 Data 5 (C0MSL3DT5) s CAN0 Message Slot 4 Data 5 (C0MSL4DT5) s CAN0 Message Slot 5 Data 5 (C0MSL5DT5) s CAN0 Message Slot 6 Data 5 (C0MSL6DT5) s CAN0 Message Slot 7 Data 5 (C0MSL7DT5) s CAN0 Message Slot 8 Data 5 (C0MSL8DT5) s CAN0 Message Slot 9 Data 5 (C0MSL9DT5) s CAN0 Message Slot 10 Data 5 (C0MSL10DT5) s CAN0 Message Slot 11 Data 5 (C0MSL11DT5) s CAN0 Message Slot 12 Data 5 (C0MSL12DT5) s CAN0 Message Slot 13 Data 5 (C0MSL13DT5) s CAN0 Message Slot 14 Data 5 (C0MSL14DT5) s CAN0 Message Slot 15 Data 5 (C0MSL15DT5) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT5 D 8-15 Bit Name COMSLnDT5 Function Message slot n data 5 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 5 or less, an indeterminate value is written to this register. 13-51 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 6 (C0MSL0DT6) s CAN0 Message Slot 1 Data 6 (C0MSL1DT6) s CAN0 Message Slot 2 Data 6 (C0MSL2DT6) s CAN0 Message Slot 3 Data 6 (C0MSL3DT6) s CAN0 Message Slot 4 Data 6 (C0MSL4DT6) s CAN0 Message Slot 5 Data 6 (C0MSL5DT6) s CAN0 Message Slot 6 Data 6 (C0MSL6DT6) s CAN0 Message Slot 7 Data 6 (C0MSL7DT6) s CAN0 Message Slot 8 Data 6 (C0MSL8DT6) s CAN0 Message Slot 9 Data 6 (C0MSL9DT6) s CAN0 Message Slot 10 Data 6 (C0MSL10DT6) s CAN0 Message Slot 11 Data 6 (C0MSL11DT6) s CAN0 Message Slot 12 Data 6 (C0MSL12DT6) s CAN0 Message Slot 13 Data 6 (C0MSL13DT6) s CAN0 Message Slot 14 Data 6 (C0MSL14DT6) s CAN0 Message Slot 15 Data 6 (C0MSL15DT6) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT6 D 0-7 Bit Name COMSLnDT6 Function Message slot n data 6 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 6 or less, an indeterminate value is written to this register. 13-52 32171 Group User's Manual (Rev.2.00) 13 s CAN0 Message Slot 0 Data 7 (C0MSL0DT7) s CAN0 Message Slot 1 Data 7 (C0MSL1DT7) s CAN0 Message Slot 2 Data 7 (C0MSL2DT7) s CAN0 Message Slot 3 Data 7 (C0MSL3DT7) s CAN0 Message Slot 4 Data 7 (C0MSL4DT7) s CAN0 Message Slot 5 Data 7 (C0MSL5DT7) s CAN0 Message Slot 6 Data 7 (C0MSL6DT7) s CAN0 Message Slot 7 Data 7 (C0MSL7DT7) s CAN0 Message Slot 8 Data 7 (C0MSL8DT7) s CAN0 Message Slot 9 Data 7 (C0MSL9DT7) s CAN0 Message Slot 10 Data 7 (C0MSL10DT7) s CAN0 Message Slot 11 Data 7 (C0MSL11DT7) s CAN0 Message Slot 12 Data 7 (C0MSL12DT7) s CAN0 Message Slot 13 Data 7 (C0MSL13DT7) s CAN0 Message Slot 14 Data 7 (C0MSL14DT7) s CAN0 Message Slot 15 Data 7 (C0MSL15DT7) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT7 D 0-7 Bit Name COMSLnDT7 Function Message slot n data 7 R W These registers are the transmit frame/receive frame memory space. Note: • For receive slots, if when storing a data frame the data length (DLC value) = 7 or less, an indeterminate value is written to this register. 13-53 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) s CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) s CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) s CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) s CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) s CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) s CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) s CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) s CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) s CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) s CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) s CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) s CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) s CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) s CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) s CAN0 Message Slot 15 Time Stamp (C0MSL15TSP) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 C0MSLnTSP D 0-15 Bit Name COMSLnTSP Function Message slot n time stamp R W These registers are the transmit frame/receive frame memory space. When the CAN module finishes transmitting or receiving, the CAN0 Time Stamp Count Register value is set in this register. 13-54 32171 Group User's Manual (Rev.2.00) 13 13.3 CAN Protocol 13.3.1 CAN Protocol Frame There are four types of frames which are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each other by an interframe space. CAN MODULE 13.3 CAN Protocol Data frame Standard format 1 11 1 6 0-64 16 2 7 Extended format 1 SOF 11 1 1 18 1 6 0-64 16 2 7 EOF Arbitration field CRC field Data field Control field ACK field Remote frame Standard format 1 11 1 6 16 2 7 Extended format 1 SOF 11 1 1 18 1 6 16 2 7 EOF Arbitration field ACK field CRC field Control field Numbers in each field denote the number of bits. Figure 13.3.1 CAN Protocol Frames (1) 13-55 32171 Group User's Manual (Rev.2.00) 13 Error frame 6-12 Error flag 8 Error delimiter CAN MODULE 13.3 CAN Protocol Interframe space or overload flag Overload frame 6-12 Overload flag Overload delimiter 8 Interframe space or overload flag Interframe space In an error-active state ~ ~ 3 0- 1 SOF of next frame Bus idle Intermission In an error-passive state ~ ~ 3 8 0- 1 SOF of next frame Bus idle Suspend transmission Intermission Numbers in each field denote the number of bits. Figure 13.3.2 CAN Protocol Frames (2) 13-56 32171 Group User's Manual (Rev.2.00) 13 Initial settings CAN MODULE 13.3 CAN Protocol Error-active state Transmit error counter ≥ 128 or Receive error counter ≥ 128 Transmit error counter < 128 and Receive error counter < 128 11 consecutive recessive bits detected on CAN bus 128 times or reset by software Error-passive state Transmit error counter > 255 Bus-off state Figure 13.3.3 CAN Control Error States The CAN controller assumes one of the following three error states depending on the transmit error and receive error counter values. (1) Error-active state • This is a state where almost no errors have occurred. • When an error is detected, an active error flag is transmitted. • Immediately after being initialized, the CAN controller is in this state. (2) Error-passive state • This is a state where many errors have occurred. • When an error is detected, a passive error flag is transmitted. (3) Bus-off state • This is a state where a large number of errors have occurred. • CAN communication with other nodes cannot be performed until the CAN module returns to an error-active state. Error status of the unit Error-active state Error-passive state Bus-off state Transmit error counter 0 -127 128 - 255 256 Receive error counter 0 - 127 128 – and or 13-57 32171 Group User's Manual (Rev.2.00) 13 13.4 Initializing the CAN Module 13.4.1 Initialization of the CAN Module CAN MODULE 13.4 Initializing the CAN Module Before you perform communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output ports, so be sure to select the functions of these pins. (Refer to Chapter 8, "Input/ Output Ports and Pin Functions." (2) Setting the interrupt controller (ICU) When you use CAN module interrupts, set the interrupt priority. (3) Setting CAN Error Interrupt Mask and CAN Slot Interrupt Mask Registers When you use CAN bus error interrupts, CAN error passive interrupts, CAN error bus-off interrupts, or CAN slot interrupts, set each corresponding bit to 1 to enable interrupt requests. (4) Setting bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of times the CAN bus is sampled. 1) Setting the bit timing Determine the period Tq that is the base of bit timing, the configuration of Propagation Segment, Phase Segment1, and Phase Segment2, and reSynchronization Jump Width. The equation to calculate Tq is shown below. Tq = (BRP+1) /CPU clock The baud rate is determined by the number of Tq's that comprise one bit. The equation to calculate the baud rate is shown below. Baud rate (bps) = 1 Tq period × number of Tq's for 1 bit Number of Tq's for 1 bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Note: • The maximum communicatable baud rate depends on the system configuration (e.g., bus length, clock error, CAN bus transceiver, sampling position, and bit configuration). Please consider the system configuration when setting the baud rate and the number of Tq’s. 13-58 32171 Group User's Manual (Rev.2.00) 13 1 Bit Time Synchronization Segment CAN MODULE 13.4 Initializing the CAN Module Propagation Segment Phase Segment1 Phase Segment2 1Tq (3) (2) (1) Sampling Point • • • Shown in this diagram is the bit timing for cases where one bit consists of 8 Tq's. When one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit. When three-time sampling is selected, the value of the bit is determined by majority from CAN bus values sampled at Sampling Points (1), (2), and (3). Figure 13.4.1 Example of Bit Timing 2) Setting the number of times sampled Select the number of times the CAN bus is sampled from "one time" and "three times." • When you select one-time sampling, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. • When you select three-time sampling, the value of the bit is determined by majority from values sampled at three points, i.e., the value sampled at the first point and those sampled one Tq before and two Tq's before that. (5) Setting ID Mask Registers Set the values of ID Mask Registers (Global Mask Register, Local Mask Register A, and Local Mask Register B) which are used in acceptance filtering of received messages. (6) Settings when running in BasicCAN mode • • • Set the CAN Extended ID Register IDE14 and IDE15 bits. (We recommend setting the same value in these bits.) Set IDs for message slots 14 and 15. Set the Message Control Registers 14 and 15 for data frame reception (H'40). (7) Setting CAN module operation mode Using the CAN Control Register (CAN0CNT), select the CAN module's operation mode (BasicCAN or loopback mode) and the clock source for the time stamp counter. (8) Releasing the CAN module from reset After you finished settings (1) through (7) above, clear the CAN Control Register (CAN0CNT)'s forcible reset bit (FRST) and reset bit (RST) to 0. Then, after detecting 11 consecutive "recessive" bits on the CAN bus, the CAN module becomes ready to communicate. 13-59 32171 Group User's Manual (Rev.2.00) 13 Initialize CAN module CAN MODULE 13.4 Initializing the CAN Module Set Input/output Port Operation Mode Register Set Interrupt Controller Set interrupt priority Set CAN Error Interrupt Mask Register • Enable/disable CAN bus error interrupt Set CAN Slot Interrupt Mask Register • Enable/disable interrupt to be generated at completion of transmission or reception in the slot Set CAN Related Interrupt Mask Register • Enable/disable CAN error passive interrupt • Enable/disable CAN bus off interrupt Set CAN Configuration Register • Set bit timing (baud rate) • Set the number of times sampled Set ID Mask Register Set ID mask bit Set loopback mode Set CAN operation mode Set BasicCAN mode • Set CAN Extended IDRegister • Set IDs for message slots 14 and 15 • Set Message Slot Control Register Negate CAN reset Release CAN module from reset • Clear the CAN Control Register (CAN0CNT)'s FRST and RST bits CAN module initialization completed Figure 13.4.2 Initializing the CAN Module 13-60 32171 Group User's Manual (Rev.2.00) 13 13.5 Transmitting Data Frames 13.5.1 Data Frame Transmit Procedure CAN MODULE 13.5 Transmitting Data Frames The following describes the procedure for transmitting data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the initialized CAN Message Slot Control Register and check the TRSTAT (transmit/ receive status) bit to see that CAN has stopped sending or receiving. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit data Set the transmit ID and transmit data in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the data as a standard frame or 1 when you want to transmit the data as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'80 (Note 1) to the CAN Message Slot Control Register to set the TR (Transmit Request) bit to 1. Note 1: When you are transmitting a data frame, always write H'80 to this register. 13-61 32171 Group User's Manual (Rev.2.00) 13 Data frame transmit procedure CAN MODULE 13.5 Transmitting Data Frames Initialize CAN Message Slot Control Register Write H'00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that transmission is idle YES Set ID and data in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H'80 (transmit request) Settings completed Figure 13.5.1 Data Frame Transmit Procedure 13-62 32171 Group User's Manual (Rev.2.00) 13 13.5.2 Data Frame Transmit Operation CAN MODULE 13.5 Transmitting Data Frames The following describes data frame transmit operation. The operations described below are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (2) Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (3) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (4) Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 13-63 32171 Group User's Manual (Rev.2.00) 13 CAN Message Slot Control Registers TR RR RM RL RA ML TRSTAT TRFIN CAN MODULE 13.5 Transmitting Data Frames B'0000 0000 (Note 1) Write H'80 d Transmit aborted n re io cur d at c tr pte bi r o ce Waiting for ar rro ac se B'1000 0000 st transmission bu us ue d t eq te os N b it r bor LA sm it a C an Tr ansm Transmit request Lost bus arbitration Tr accepted CAN bus error occurred B'0000 0010 Transmit aborted B'1000 0010 d rte ed bo let t a omp mi ns it c Tra ansm Tr B'0000 0001 (Note 1) Transmit completed B'1000 0001 Note 1: When in this state, data can be written to the message slot. Figure 13.5.2 Operation of the CAN Message Slot Control Register when Transmitting Data Frames 13.5.3 Transmit Abort Function The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by writing H'0F to the CAN Message Slot Control Register for the slot concerned. When transmit abort is accepted, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0, allowing for data to be written to the message slot. The following shows conditions under which transmit abort is accepted: [Conditions] • When the target message is waiting for transmission • When a CAN bus error occurs during transmission • When the CAN module lost bus arbitration 13-64 32171 Group User's Manual (Rev.2.00) 13 13.6 Receiving Data Frames 13.6.1 Data Frame Receive Procedure The following describes the procedure for receiving data frames. (1) Initializing the CAN Message Slot Control Register CAN MODULE 13.6 Receiving Data Frames Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register Write H'40 to the CAN Message Slot Control Register to set the RR (Receive Request) bit to 1. 13-65 32171 Group User's Manual (Rev.2.00) 13 Data frame receive procedure CAN MODULE 13.6 Receiving Data Frames Initialize CAN Message Slot Control Register Write H'00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that reception is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H'40 (receive request) Settings completed Figure 13.6.1 Data Frame Receive Procedure 13-66 32171 Group User's Manual (Rev.2.00) 13 13.6.2 Data Frame Receive Operation CAN MODULE 13.6 Receiving Data Frames The following describes data frame receive operation. The operations described below are automatically performed in hardware. (1) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions] • The receive frame is a data frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bits." • The standard and extended frame types are the same. Note: • In BasicCAN mode, slots 14 and 15 while being set for data frame reception can also receive remote frames. (2) When receive conditions are met When receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. (3) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. 13-67 32171 Group User's Manual (Rev.2.00) 13 CAN Message Slot Control Registers TR RR RM RL RA ML TRSTAT TRFIN CAN MODULE 13.6 Receiving Data Frames B'0000 0000 Receive request set Clear receive request Wait for receive data ta da est ed qu eiv e re rec eiv ore ec St ear r Cl B'0100 0000 Store received data CPU read Clear receive request B'0000 0011 eiv rec st ing ue tor req s ed ive ish ece Fin ear r l C Clear receive d ed ata B'0100 0011 Finished storing received data Finished storing received data B'0000 0001 request B'0100 0001 B'0000 0111 B'0100 0111 Finished storing received data ta da ed eiv rec st g Finished rin que sto re received ed ive ish rece Fin ear Cl storing data Store received data Wait for receive data B'0000 0101 Clear receive request B'0100 0101 Figure 13.6.2 Operation of the CAN Message Slot Control Register when Receiving Data Frames 13-68 32171 Group User's Manual (Rev.2.00) CPU read ata st d d ue ive e req e rec iv re rece Stolear C Clear receive request Store received data 13 13.6.3 Reading Out Received Data Frames CAN MODULE 13.6 Receiving Data Frames The following describes the procedure for reading out received data frames from the slot. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'4E, H'40 or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to C0MSLnCNT H'4E H'40 H'00 Slot operation after write Operates as a data frame receive slot. Overwrite can be verified by ML bit. Operates as a data frame receive slot. Overwrite cannot be verified by ML bit. The slot stops transmit/receive operation. Notes: • If message-lost check by the ML bit is needed, write H'4E to the C0MSLnCNT register as you clear the TRFIN bit. • If you clear the TRFIN bit by writing H'4E, H'40 or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. 1) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). 2) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. 13-69 32171 Group User's Manual (Rev.2.00) 13 Reading out received data CAN MODULE 13.6 Receiving Data Frames Clear TRFIN bit to 0 Write H'4E, H'40 or H'00 Read out from message slot Read CAN Message Slot Control Register NO TRFIN bit = 0 YES Finished reading out received data Figure 13.6.3 Procedure for Reading Out Received Data 13-70 32171 Group User's Manual (Rev.2.00) 13 13.7 Transmitting Remote Frames 13.7.1 Remote Frame Transmit Procedure CAN MODULE 13.7 Transmitting Remote Frames The following describes the procedure for transmitting remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit ID Set the ID to be transmitted in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the frame as a standard frame or 1 when you want to transmit the frame as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'A0 to the CAN Message Slot Control Register to set the TR (Transmit Request) and RM (Remote) bits to 1. 13-71 32171 Group User's Manual (Rev.2.00) 13 Remote frame transmit procedure CAN MODULE 13.7 Transmitting Remote Frames Initialize CAN Message Slot Control Register Write H'00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that transmission is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H'A0 (transmit request, remote) Settings completed Figure 13.7.1 Remote Frame Transmit Procedure 13-72 32171 Group User's Manual (Rev.2.00) 13 13.7.2 Remote Frame Transmit Operation CAN MODULE 13.7 Transmitting Remote Frames The following describes remote frame transmit operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit At the same time H'A0 (Transmit Request, Remote) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Selecting a transmit frame The CAN module checks slots which have transmit requests (including data frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (3) Transmitting a remote frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (4) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (5) Completion of remote frame transmission When remote frame transmission is completed, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP) and the CAN Message Slot Control Register's RA (Remote Active) bit is cleared to 0. Also, the CAN Slot Interrupt Status bit is set to 1 by completion of transmission, but the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit is not set to 1. If the CAN slot interrupt has been enabled, an interrupt request is generated upon completion of transmission. (6) Receiving a data frame When remote frame transmission is completed, the slot automatically starts functioning as a data frame receive slot. (7) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). 13-73 32171 Group User's Manual (Rev.2.00) 13 [Conditions] CAN MODULE 13.7 Transmitting Remote Frames The following shows receive conditions for slots that have been set for data frame reception. • The receive frame is a data frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit." • The standard and extended frame types are the same. Note: • In BasicCAN mode, slots 14 and 15 cannot be used as transmit slots. (8) When receive conditions are met When receive conditions in (7) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. Note: • If the CAN module received a data frame before transmitting a remote frame, it stores the data frame in the slot and does not transmit the data frame. (9) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. 13-74 32171 Group User's Manual (Rev.2.00) 13 CAN Message Slot Control Registers TR RR RM RL RA ML TRSTAT TRFIN CAN MODULE 13.7 Transmitting Remote Frames B'0000 0000 B'0000 1000 CAN bus error occurs B'0000 1010 Finished transmitting remote frame B'0000 0000 B'1010 1000 Store received data B'1010 1011 Finished storing received data Clear transmit request B'0000 1011 Finished storing received data B'0000 0001 Clear transmit request B'1010 1010 sa bu st us s Lo N b ccur mit CA or o rans err ear t t Cl ues req tra rbi tio n Finished transmitting remote frame Wait for receive data B'1010 0000 Store received data Store received data Clear receive request B'0000 0011 g rin st sto ue ed ata req ish ed d ive Fin eiv ece rec ear r Cl B'1010 0011 Finished storing received data B'1010 0001 Store received data B'0000 0001 Store received data Clear receive request B'0000 0111 Finished storing received data B'0000 0101 g rin sto ed ata ish ed d ive Fin eiv ece rec ear r t Cl ues req B'1010 0111 Finished storing received data Store received data Wait for receive data CPU read B'1010 0101 Figure 13.7.2 Operation of the CAN Message Slot Control Register when Transmitting Remote Frames 13-75 32171 Group User's Manual (Rev.2.00) 13 CAN MODULE 13.7 Transmitting Remote Frames 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission The following describes the procedure for reading out received data frames from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'AE or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to C0MSLnCNT H'AE H'00 Slot operation after write Operates as a data frame receive slot. Overwrite can be verified by ML bit. The slot stops transmit/receive operation. Notes: • If message-lost check by the ML bit is needed, write H'AE to the C0MSLnCNT register as you clear the TRFIN bit. • If you clear the TRFIN bit by writing H'AE or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. • The received data frame cannot be read out by writing H'A0 to the register. If you clear the TRFIN bit by writing H'A0, the slot performs remote frame transmit operation. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. 1) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). 2) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. 13-76 32171 Group User's Manual (Rev.2.00) 13 Reading out received data CAN MODULE 13.7 Transmitting Remote Frames Clear TRFIN bit to 0 Write H'AE or H'00 Read out from message slot Read CAN Message Slot Control Register NO TRFIN bit = 0 YES Finished reading out received data Figure 13.7.3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission 13-77 32171 Group User's Manual (Rev.2.00) 13 13.8 Receiving Remote Frames 13.8.1 Remote Frame Receive Procedure CAN MODULE 13.8 Receiving Remote Frames The following describes the procedure for receiving remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register 1) When automatic response (data frame transmission) for remote frame reception is desired Write H'60 to the CAN Message Slot Control Register to set the RR (Receive Request) and RM (Remote) bits to 1. 2) When automatic response (data frame transmission) for remote frame reception is not needed Write H'70 to the CAN Message Slot Control Register to set the RR (Receive Request), RM (Remote), and RL (Automatic Response Inhibit) bits to 1. Note: • In BasicCAN mode, slots 14 and 15, although capable of receiving remote frames, cannot automatically respond to remote frame reception. 13-78 32171 Group User's Manual (Rev.2.00) 13 Remote frame reception procedure CAN MODULE 13.8 Receiving Remote Frames Initialize CAN Message Slot Control Register Write H'00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that reception is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H'60 (receive request, remote, automatic response enable) Write H'70 (receive request, remote, automatic response disable) Settings completed Figure 13.8.1 Remote Frame Receive Procedure 13-79 32171 Group User's Manual (Rev.2.00) 13 13.8.2 Remote Frame Receive Operation CAN MODULE 13.8 Receiving Remote Frames The following describes remote frame receive operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit When H'60 (Receive Request, Remote) or H'70 (Receive Request, Remote, Automatic Response Disable) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions] • The receive frame is a remote frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit." • The standard and extended frame types are the same. (3) When receive conditions are met When receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated. Notes: • The ID field and DLC value are written to the message slot. • When receiving standard format frames, an indeterminate value is written to the extended ID area. • The data field is not accessed for write. • The RA and TRFIN bits are cleared to 0 after writing the remote frame received data. (4) When receive conditions are not met The received frame is discarded, and the CAN module waits for the next receive frame. No data is written to the message slot. 13-80 32171 Group User's Manual (Rev.2.00) 13 (5) Operation after receiving a remote frame CAN MODULE 13.8 Receiving Remote Frames The operation performed after receiving a remote frame differs depending on how automatic response is set. 1) When automatic response is disabled The slot which finished receiving goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 2) When automatic response is enabled After receiving a remote frame, the slot automatically changes to a data frame transmit slot and performs the transmit operation described below. In this case, the transmitted data conforms to the ID and DLC of the received remote frame. • Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. • Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. • If the CAN module lost bus arbitation or a CAN bus error occurs If the CAN module lost bus arbitation or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. • Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 13-81 32171 Group User's Manual (Rev.2.00) 13 CAN Message Slot Control Registers TR RR RM RL RA ML TRSTAT TRFIN B'0000 0000 Write H'60 (automatic response enable) Wait for receive data B'0110 1000 Clear receive request CAN MODULE 13.8 Receiving Remote Frames Write H'70 (automatic response enable) B'0111 1000 Store received data Clear receive request Store Store received data received data B'0111 1011 Store received data Clear receive request B'0000 1010 Finished storing received data B'0000 0000 Finished storing received data Clear receive request B'0000 0010 Finished transmitting data frame B'0000 0001 B'0110 1011 Finished Finished storing received storing data received data B'0110 0000 Transmit data frame B'0111 0000 B'0000 Fi da nish Cle ta ed st ori ar ng rec rec eiv eiv er ed eq ue st 1010 B'0000 0000 Transmit data frame Clear receive request B'0110 0010 Finished transmitting data frame B'0110 0001 Figure 13.8.2 Operation of the CAN Message Slot Control Register when Receiving Remote Frames 13-82 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.2 Pin Function of the RTD 14.3 Functional Description of the RTD 14.4 Typical Connection with the Host 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.1 Outline of the Real-Time Debugger (RTD) The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU. Table 14.1.1 Outline of the Real-Time Debugger (RTD) Item Transfer method Generation of transfer clock RAM access area Transmit/receive data length Bit transfer sequence Maximum transfer rate Input/output pins Number of commands Content Clock-synchronized serial I/O Generated by external host Entire area of internal RAM (controlled by A16-A29) 32 bits (fixed) LSB first 2 Mbits/second 4 lines (RTDTXD, RTDRXD, RTDACK, RTDCLK) Following five functions • Monitors continuously • Outputs real-time RAM contents • Forcibly rewrites RAM contents (with verify) • Recovers from runaway • Requests RTD interrupt RTD control circuit Entire RAM area CPU Control circuit RTDCLK Address Data Address Data Address Data Command RTDACK RTDTXD Data RTDRXD Bus switching circuit Figure 14.1.1 Block Diagram of the Real-Time Debugger (RTD) 14-2 32171 Group User's Manual (Rev.2.00) 14 14.2 Pin Function of the RTD Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name RTDTXD RTDRXD RTDACK Type Output Input Output Function RTD serial data output RTD serial data input REAL-TIME DEBUGGER (RTD) 14.2 Pin Function of the RTD Outputs a low-level pulse synchronously with the beginning clock edge of the output data word. The width of the low-level pulse thus output indicates the type of instruction/data that the RTD received. 1 clock period 1 clock period 2 clock periods 3 clock periods : VER (continuous monitor) command : VEI (RTD interrupt request) command : RDR (real-time RAM content output) command : WRR (RAM content forcible rewrite) command or the data to rewrite 4 clock periods or more : RCV (recover from runaway) command RTDCLK Input RTD transfer clock input 14-3 32171 Group User's Manual (Rev.2.00) 14 14.3 Functional Description of the RTD 14.3.1 Outline of RTD Operation REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19 (Note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data b19 b18 b17 b16 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 VEI (VErify Interrupt request) RDR (ReaD RAM) WRR (WRite RAM) RCV (ReCoVer) System reserved (use inhibited) RTD interrupt request Real-time RAM content output RAM content forcibly rewrite (with verify) Recover from runaway (Note 2, Note 3) VER (VERify) Continuous monitor Command Mnemonic RTD Function ↑ (Note 1) Note 1 : Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command, is handled as "Don't Care" bit. (Bits 16-18 are effective for the command specified.) Note 2 : The RCV command must always be transmitted twice in succession. Note 3 : For the RCV command, all bits, not just bits 16-19, (i.e., bits 0-15 and bits 20-31) must be set to 1. 14-4 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.2 Operation of RDR (Real-time RAM Content Output) When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop. Because the RTD reads data from the internal RAM while no transfers are being performed between the CPU and internal RAM, the CPUinno extra load. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device. (LSB side) 31 RTDRXD X •••••• •••••• 20 19 18 17 16 15 14 13 12 X 0 0 1 0 X X A29 A28 •••••• •••••• (MSB side) 1 0 A17 A16 Command (RDR) Specified address Note: • X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.1 RDR Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) RDR (A2) RDR (A3) •••••• RTDTXD •••••• D (A1) D (A2) RTDACK 2 clock periods Note: • (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.2 Operation of the RDR Command 14-5 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD (LSB side) 31 30 D31 D30 (MSB side) •••••••••••••••••• •••••••••••••••••• Read data 1 0 RTDTXD D1 D0 Note: • The read data is transferred LSB-first. Figure 14.3.3 Read Data Transfer Format 14-6 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, the CPU incurs no extra load. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are written to the internal RAM in units of 32 bits. The external host should transmit the command and address in the first frame and then the write data in the second frame. The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data. a) First frame (LSB side) 31 RTDRXD X •••••• •••••• 20 19 18 17 16 15 14 13 12 X 0 0 1 1 X X A29 A28 •••••• •••••• (MSB side) 1 0 A17 A16 Command (WRR) Specified address b) Second frame (LSB side) 31 30 RTDRXD D31 D30 (MSB side) •••••••••••••••••• •••••••••••••••••• Write data 1 0 D1 D0 Notes: • X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) • The specified address and write data are transferred LSB-first. Figure 14.3.4 WRR Command Data Format 14-7 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD WRR (A1) (A1) Write data WRR (A2) (A2) Write data RTDTXD •••••• RTDACK 3 clock periods D (A1) Read value before write D (A1) Verify value after write Note: • (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.5 Operation of the WRR Command 14-8 32171 Group User's Manual (Rev.2.00) 14 14.3.4 Operation of VER (Continuous Monitor) REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command. (LSB side) 31 RTDRXD X •••••• •••••• 20 19 18 17 16 15 X 0 0 0 0 X •••••••••• •••••••••• (MSB side) 0 X Command (VER) Note: • X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.6 VER (Continuous Monitor) Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) (Note 1) VER VER •••••• RTDTXD •••••• RTDACK 2 clock periods D (A1) Read value (Note 2) D (A1) Latest read value Note 1 : WRR command can also be used. Note 2 : (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.7 Operation of the VER (Continuous Monitor) Command 14-9 32171 Group User's Manual (Rev.2.00) 14 14.3.5 Operation of VEI (Interrupt Request) REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command. (LSB side) 31 RTDRXD X •••••• •••••• (Note 1) (MSB side) 20 19 18 17 16 15 X 0 1 1 0• X •••••••••• ••••••••• (Note 1) 0 X VEI (interrupt request generation) command Note 1: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.8 VEI (Interrupt Request) Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) (Note 1) VEI •••••• RTDTXD •••••• RTDACK 2 clock periods D (A1) Read value (Note 2) RTD interrupt request D (A1) Read value (Note 2) RTD interrupt Note 1 : WRR command can also be used. Note 2 : (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.9 Operation of the VEI (Interrupt Request) Command 14-10 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.6 Operation of RCV (Recover from Runaway) When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession. Also, any command issued subsequently after the RCV command must have its bits 20-31 all set to 1. (LSB side) 31 RTDRXD 1 •••••• •••••• (Note 1) (MSB side) 20 19 18 17 16 15 1 1 1 1 1• 1 •••••••••• ••••••••• (Note 1) 0 1 Command (RCV) Note 1: All of 32 data bits are 1's. The RCV command must always be issued twice in succession. Figure 14.3.10 RCV Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods Bits 20-31 RTDRXD RCV RCV 1• • • 1 RDR (A1) •••••• Next command following the RCV command RTDTXD Indeterminate data during runway condition D (A1) RTDACK Indeterminate value during runway condition 2 clock periods 2 clock periods RCV command stored here Note: • The next command following the RCV command must have its bits 20-31 all set to 1. Figure 14.3.11 Operation of the RCV Command 14-11 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.7 Method to Set a Specified Address when Using the RTD When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses (H'4000 to H'FFFF) of that area. However, access to any locations other than the area where the RAM resides is inhibited. Note also that two least significant address bits, A31 and A30, are always 0's because data are read and written to the internal RAM in a fixed length of 32 bits. Memory map X X A29 - A16 ••• H'0080 0000 SFR 16KB H'0080 4000 H'0080 4000~H'0080 FFFF only can be specified RAM area H'0080 FFFF Figure 14.3.12 Method for Setting Addresses in Real-Time Debugger 14-12 32171 Group User's Manual (Rev.2.00) 14 14.3.8 Resetting the RTD REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after Releasing System from Reset Pin Name RTDACK RTDTXD State High-level output High-level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK. 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RESET System reset RTDRXD Don't Care RDR (A1) RDR (A2) •••••• RTDTXD "H" 0000 0000 0000 0000 D (A1) D (A2) RTDACK "H" Note : • (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.13 Command Transfer to the RTD after System Reset 14-13 32171 Group User's Manual (Rev.2.00) 14 14.4 Typical Connection with the Host REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. M32R/ECU Host microprocessor RTDCLK RTDRXD RTDTXD RTDACK (Note) SCLK RXD TXD PORT Note: • In this example, the RTDACK level is checked between transfer frames. Figure 14.4.1 Connecting the RTD and Host 14-14 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally. After transmitting a command, the RTDACK signal is pulled low, making it possible to verify the communication status. When issuing the VER command, the RTDACK signal goes low for only one clock period. Therefore, after sending 32 bits in one frame, turn off RTDCLK output and check whether RTDACK is low. If RTDACK is low, you know that the RTD is communicating normally. If you want to identify the type of transmitted command by the width of RTDACK, use the 32171's internal measurement timer (to count RTDCLK pulses while RTDACK is low) or create a dedicated circuit. Transfer of next frame Transfer of 1 frame (32 bits) 1 RTDCLK 2 RTDRXD (8 bits) (8 bits) (8 bits) RTDTXD •••••• RTDACK Check the RTDACK signal L level. Figure 14.4.2 Typical Operation for Communication with the Host (when Issuing VER Command) 14-15 32171 Group User's Manual (Rev.2.00) 14 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host * This is a blank page.* 14-16 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.2 Read/Write Operations 15.3 Bus Arbitration 15.4 Typical Connection of External Extension Memory 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.1 External Bus Interface Related Signals The 32171 comes with external bus interface related signals shown below. These signals can be used in external extension mode or processor mode. (1) Address The 32171 outputs a 19-bit address (A12-A30) for addressing any location in 1 Mbytes of space. ___ The least significant A31 is not output, and in external write cycles, the 32171 outputs BHW and ___ BLW signals to indicate the valid byte position at which to write on the 16-bit data bus. In read cycles, the 32171 reads data always in 16 bits, transferring only the data read from the valid byte position of the bus. ___ ___ (2) Chip select (CS0, CS1) ___ ___ These signals are output in external extension mode or processor mode, with CS0 and CS1 ___ specifying an external extension area of 2 Mbytes each. The CS0 signal points to a 2-Mbyte area in processor mode or a 1-Mbyte area in external extension mode. (For details, refer to Chapter 3, "Address Space.") __ (3) Read strobe (RD) Output during external read cycle, this signal indicates the timing at which to read data from the bus. This signal is driven high when writing to the bus or accessing the internal function. ___ ___ (4) Byte High Write/Byte High Enable (BHW / BHE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte High Write (BHW), during external write access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. During external read and when accessing the internal function it outputs a high. ___ When BUSMOD = 1 and this signal is Byte High Enable (BHE), during external access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high. ___ ___ (5) Byte Low Write/Byte Low Enable (BLW / BLE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte Low Write (BLW), during external write access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. During external read cycle, it outputs a high. ___ When BUSMOD = 1 and this signal is Byte Low Enable (BLE), during external access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high. 15-2 32171 Group User's Manual (Rev.2.00) 15 (6) Data bus (DB0 - DB15) EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals This is the 16-bit data bus used to access external devices. __ (7) System clock/write (BCLK / WR) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = 0 and this signal is System Clock (BCLK), it outputs the system clock necessary to synchronize operations in an external system. When the CPU clock = 40 MHz, a 20 MHz clock is output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by setting the P7 Operation Mode Register P70MOD bit to 0. __ When BUSMOD = 1 and this signal is Write (WR), during external write access it indicates the valid data on the data bus to transfer. During external read cycle and when accessing the internal function, it outputs a high. ____ (8) Wait (WAIT) ____ When the 32171 started an external bus cycle, it automatically inserts wait cycles while the WAIT signal is asserted. For details, refer to Chapter 16, "Wait Controller." When not using the WAIT function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. Note that the 32171 always inserts one or more wait cycles for external access. Therefore, the shortest time in which an external device can be accessed is one wait cycle (2 BCLK periods). ____ ____ (9) Hold control (HREQ, HACK) The hold state refers to a state in which the 32171 has stopped bus access and bus interface related pins are tristated (high impedance). While the 32171 is in a hold state, any bus master external to the chip can use the system bus to transfer data. ____ The 32171 is placed in a hold state by pulling the HREQ pin input low. While the 32171 remains in ____ a hold state after accepting the hold request and during a transition to the hold state, the HACK pin outputs a low-level signal. To exit from the hold state and return to normal operating state, release ____ the HREQ signal back high. When not using the HREQ and HACK functions, these pins can be used as P72 and P73 by setting the P7 Operation Mode Register P72MOD and P73MOD bits to 0. The status of each 32171 pin during hold are shown below. Table 15.1.1 Pin State during Hold Period Pin Name ___ ___ __ ___ ___ ___ ___ __ Pin State or Operation High impedance Outputs a low Normal operation A12-A30, DB0-DB15, CS0, CS1, RD, BHW, BLW, BHE, BLE, WR ____ HACK Other pins (e.g., ports and timer output) 15-3 32171 Group User's Manual (Rev.2.00) 15 ______ ____ ____ ____ EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (10) Port P7 Operation Mode Register (P7MOD) The BCLK/WR, WAIT, HREQ, and HACK pins respectively are shared with P70, P71, P72, and P73. The Port P7 Operation Mode Register is used to select the function of port P7. Configuration of this register is shown below. s P7 Operation Mode Register D8 9 10 11 12 13 D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 __ R W 1 : BCLK / WR 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK 15-4 32171 Group User's Manual (Rev.2.00) 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (11) Bus Mode Control Register (BUSMODC) The 32171 contains a function to switch between two external bus modes. s Bus Mode Control Register (BUSMODC) D8 9 10 11 12 13 D 8 - 15 15 Bit Name No functions assigned BUSMOD (Bus mode control) 0: WR signal separate mode 1: Byte enable separate mode Function R 0 W — This register is used to facilitate memory connection in processor mode and external extension mode. When Bus Mode Control Register (BUSMOD) = 0, the WR signal is output separately for each byte __ ___ ___ ____ ____ area. Signals RD, BHW, BLW, BCLK, and WAIT can be used. For memory connection in boot mode, the Bus Mode Control Register has no effect and the interface operates under conditions where Bus Mode Control Register (BUSMOD) = 0. When Bus Mode Control Register (BUSMOD) = 1, the byte enable signal is output separately for __ ___ ___ __ ____ each byte area. Signals RD, BHW, BLE, WR, and WAIT can be used. For WAIT control circuit configuration, because BCLK is not output, external timing control is required. BUSMOD = 0 A12 - A30 CS0, CS1 BCLK RD BHW BLW DB0 - DB15 WAIT BUSMOD = 1 A12 - A30 CS0, CS1 RD WR BHE BLE DB0 - DB15 WAIT Figure 15.1.1 Pin Function when Bus Modes are Changed 15-5 32171 Group User's Manual (Rev.2.00) 15 15.2 Read/Write Operations (1) When Bus Mode Control Register = 0 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ __ ___ CS1, RD, BHW, BLW, WAIT, and BCLK. In external read cycle, the RD signal is low while BHW and ___ BLW both are high, reading data from only the valid byte position of the bus. In external write cycle, ___ ___ BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low. ____ Unless the WAIT signal is needed, leave it held high. During external bus cycles, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) Bus-free state internal bus access BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" "H" Hi-z DB0 - DB15 WAIT "H" Note: • THi-Z denotes a high-impedance state. Figure 15.2.1 Internal Bus Access during Bus Free State 15-6 32171 Group User's Manual (Rev.2.00) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT "H" Note: • Circles above indicate points at which signals are sampled. Figure 15.2.2 Read/Write Timing (for Shortest-case External Access) 15-7 32171 Group User's Manual (Rev.2.00) 15 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (4 cylces) Read BCLK A12 - A30 CS0, CS1 RD 2 internal wait cycles 1 external wait cycle BHW, BLW "H" DB0 - DB15 WAIT "H" (Don’t Care) "L" Write Write (4 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW 1 external wait cycle "H" DB0 - DB15 WAIT (Don’t Care) "H" "L" Note: • Circles above indicate points at which signals are sampled. Figure 15.2.3 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) 15-8 32171 Group User's Manual (Rev.2.00) 15 (2) When Bus Mode Control Register = 1 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ ___ __ ___ ___ ____ __ __ ___ CS1, RD, BHE, BLE, WAIT, and WR. In external read cycle, the RD signal goes low and BHE or BLE output for the byte position from which to read is pulled low, reading data from only the byte __ ___ ___ position of the bus. In external write cycle, the WR signal goes low and BHE or BLE output for the byte position to which to write is pulled low, writing data to the necessary byte position. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low. ____ Unless the WAIT signal is needed, leave it held high. During external bus cycle, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) When not using the WAIT function, the pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. Bus-free state internal bus access BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE "H" "H" "H" Hi-z DB0 - DB15 WAIT "H" Notes: • Hi-Z denotes a high-impedance state. • BCLK is not output. Figure 15.2.4 Internal Bus Access during Bus Free State 15-9 32171 Group User's Manual (Rev.2.00) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 15.2.5 Read/Write Timing (for Shortest-case External Access) 15-10 32171 Group User's Manual (Rev.2.00) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (4 cycles) 1 external 2 internal wait cycles wait cycle BCLK A12 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "L" "H" Write (4 cycles) Write 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE DB0 - DB15 WAIT 1 external wait cycle "H" "H" (Don’t Care) "L" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 15.2.6 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) 15-11 32171 Group User's Manual (Rev.2.00) 15 15.3 Bus Arbitration (1) When Bus Mode Control Register = 0 ____ EXTERNAL BUS INTERFACE 15.3 Bus Arbitration When HREQ pin input is pulled low and the hold request is accepted, the 32171 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the highimpedance state, allowing data to be transferred on the system bus. To exit the hold state and ____ return to normal operating state, release the HREQ signal back high. Bus cycle Idle Go to hold Hold state Return Next bus cycle BCLK HREQ HACK A12 - A30 Hi-Z CS0, CS1 Hi-Z RD Hi-Z BHW, BLW Hi-Z DB0 - DB15 Hi-Z WAIT Notes: • Circles above indicate points at which signals are sampled. • Hi-z indicate the high-impedance state. • Idle cycles are inserted only when the hold state is assumed after external read access. Figure 15.3.1 Bus Arbitration Timing 15-12 32171 Group User's Manual (Rev.2.00) 15 (2) When Bus Mode Control Register = 1 ____ EXTERNAL BUS INTERFACE 15.3 Bus Arbitration When HREQ pin input is pulled low and the hold request is accepted, the 32171 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the highimpedance state, allowing data to be transferred on the system bus. To exit the hold state and ____ return to normal operating state, release the HREQ signal back high. Bus cycle Idle Go to hold Hold state Return Next bus cycle BCLK HREQ HACK A12 - A30 Hi-Z CS0, CS1 Hi-Z RD Hi-Z WR Hi-Z BHW, BLW Hi-Z DB0 - DB15 Hi-Z WAIT Notes: • Circles above indicate points at which signals are sampled. • Hi-z indicate the high-impedance state. • Idle cycles are inserted only when the hold state is assumed after external read access. Figure 15.3.2 Bus Arbitration Timing 15-13 32171 Group User's Manual (Rev.2.00) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory 15.4 Typical Connection of External Extension Memory (1) When Bus Mode Control Register = 0 A typical connection when using external extension memory is shown in Figure 15.4.1. (External extension memory can only be used in external extension mode and processor mode.) M32171F3 A12 Flash memory H’0000 0000 A18 A0 D15 D0 RD CS max1MB H’0006 0000 Memory mapping Internal flash memory (384KB) Unused A30 D0 D15 RD CS0 H’000F FFFF H’0010 0000 External memory area (1MB) SRAM H’001F FFFF H’0020 0000 1M-CS0 area A17 A0 D15 max512KB 2 * External memory area (1MB) (total 1MB) H’0030 0000 D0 BHW BLW CS1 WAIT Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. WR (D0-D7) WR (D8-D15) RD (D0-D15) CS 2M-CS1 area Ghost area H’0040 0000 Figure 15.4.1 Typical Connection of External Extension Memory (When BUSMOD = 0) Note: • The 32171 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-14 32171 Group User's Manual (Rev.2.00) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (2) When Bus Mode Control Register = 1 A typical connection when using external extension memory is shown in Figure 15.4.2. (External extension memory can only be used in external extension mode and processor mode.) M32171F3 A12 Flash memory H'0000 0000 A18 A0 D15 D0 RD CS max1MB H'0006 0000 Memory mapping Internal flash memory (384KB) Unused A30 D0 D15 RD CS0 H'000F FFFF H'0010 0000 External memory area (1MB) SRAM H'001F FFFF H'0020 0000 1M-CS0 area A18 A0 D15 D0 BHE BLE CS1 WR WAIT Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. BHE (D0-D7) BLE (D8-D15) RD (D0-D15) CS WR (D0-D15) max1MB H'0030 0000 External memory area (1MB) 2M-CS1 area Ghost area H'0040 0000 Figure 15.4.2 Typical Connection of External Extension Memory (When BUSMOD = 1) Note: • The 32171 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-15 32171 Group User's Manual (Rev.2.00) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (3) Using 8/16-bit data bus memories in combination when Bus Mode Control Register = 1 The diagram below shows a typical connection of external extension memory, with 8-bit data bus memory located in the CS0 area, and 16-bit data bus memory located in the CS1 area. (External extension memory can only be used in external extension mode and processor mode.) When CL = 50 pF, memory can be connected with only 2 ns data delay M32171F3 A12 8-bit memory H’0000 0000 A18 A1 QS32X2245 D7 AB AB OE D0 max1MB H’000F FFFF H’0010 0000 WR RD CS A0 H’0006 0000 Memory mapping Internal flash memory (384KB) Unused External memory area (1MB) 8-bit bus area A30 D0 D7 D8 D15 RD CS0 1M-CS0 area SRAM H’0020 0000 A18 A0 D15 max1MB D0 WR BHE BLE CS1 WAIT WR (D0-D15) RD (D0-D15) BHE BLE CS H’0030 0000 External memory area (1MB) 16-bit bus area 2M-CS1 area Ghost area H’0040 0000 Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. Note: • The QS32X2245 is a product made by IDT Company. Figure 15.4.3 Typical Connection of External Extension Memory (Using 8/16-bit Mixed Memories when BUSMOD = 1) Note: • The 32171 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-16 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.2 Wait Controller Related Registers 16.3 Typical Operation of the Wait Controller 16 16.1 Outline of the Wait Controller WAIT CONTROLLER 16.1 Outline of the Wait Controller The wait controller controls the number of wait cycles inserted in bus cycles during access to an external extension area. The following outlines the wait controller. Table 16.1.1 Outline of the Wait Controller Item Target space Specification Wait cycles in following memory spaces are controlled depending on operation mode Single-chip mode : No target space (Wait controller settings have no effect) External extension mode : CS0 area (1 Mbytes), CS1 area (1 Mbytes) Processor mode Number of wait cycles that can be inserted : CS0 area (1 Mbytes), CS1 area (1 Mbytes) 1 to 4 wait cycles inserted by software + any number of wait cycles inserted from ____ WAIT pin (Bus cycles with 1 wait cycle are the shortest bus cycle for external access.) ___ ___ In external extension mode and processor mode, two chip select signals (CS0, CS1) are output to ___ ___ an external extension area. Two areas in it corresponding to CS0 and CS1 signals are called the CS0 and the CS1 areas, respectively. Non-CS0 area (Internal ROM access area) H’0000 0000 Internal ROM area CS0 area (1 Mbytes) External extension area H’000F FFFF H’0010 0000 External extension area Reserved area CS0 area (1 Mbytes) Ghost of CS0 area (1 Mbytes) H’001F FFFF H’0020 0000 CS1 area (1 Mbytes) CS1 area (1 Mbytes) H’002F FFFF H’0030 0000 Ghost of CS1 area (1 Mbytes) Ghost of CS1 area (1 Mbytes) H’003F FFFF Figure 16.1.1 CS0 and CS1 Area Address Map 16-2 32171 Group User's Manual (Rev.2.00) 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller When accessing an external extension area, the wait controller controls the number of wait cycles to be inserted in bus cycles based on the number of wait cycles set by software and those entered ____ from the WAIT pin. The number of wait cycles that can controlled in software is 1 to 4. (For external access, bus cycles with 1 wait cycle are the shortest bus cycle.) ____ When the WAIT pin input is sampled low in the last cycle of internal wait cycles set by software, the ____ ____ wait cycle is extended as long as the WAIT signal is held low. Then when the WAIT signal is released back high, the wait cycle is terminated and the next new bus cycle is entered into. Table 16.1.2 Number of Wait Cycles that Can be Set by the Wait Controller External Extension Area CS0 area Address H'0010 0000 - H'001F FFFF (External extension mode) H'0000 0000 - H'000F FFFF (Processor mode) (Note 1) CS1 area H'0020 0000 - H'002F FFFF (External extension mode and processor mode) (Note 2) One to 4 wait cycles set by software + any number of ____ Number of Wait Cycles Inserted One to 4 wait cycles set by software + any number of ____ wait cycles entered from WAIT pin (However, wait cycles set by software have priority.) wait cycles entered from WAIT pin (However, wait cycles set by software have priority.) Note 1: During processor mode, a ghost (1 Mbyte) of the CS0 area appears in an area of H’0010 0000 through H’001F FFFF. Note 2: A ghost (1 Mbyte) of the CS1 area appears in an area of H’0030 0000 through H’003F FFFF. 16-3 32171 Group User's Manual (Rev.2.00) 16 16.2 Wait Controller Related Registers WAIT CONTROLLER 16.2 Wait Controller Related Registers The following shows a wait controller related register map. Address D0 +0 Address D7 D8 +1 Address D15 H'0080 0180 Wait Cycles Control Register (WTCCR) Blank addresses are reserved area. Figure 16.2.1 Wait Controller Related Register Map 16-4 32171 Group User's Manual (Rev.2.00) 16 16.2.1 Wait Cycles Control Register s Wait Cycles Control Register (WTCCR) D0 1 2 CS0WTC 3 4 WAIT CONTROLLER 16.2 Wait Controller Related Registers D 0,1 2,3 Bit Name No functions assigned CS0WTC (CS0 wait cycles control) 00 : 4 wait cycles (when reset) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle 4,5 6,7 No functions assigned CS1WTC (CS1 wait cycles control) 00 : 4 wait cycles (when reset) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle 0 — Function R 0 W — 16-5 32171 Group User's Manual (Rev.2.00) 16 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller 16.3 Typical Operation of the Wait Controller The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller. (1) When Bus Mode Control Register = 0 ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. Bus-free state internal bus access BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" "H" Hi-z DB0 - DB15 WAIT "H" Note: • Hi-Z denotes a high-impedance state. Figure 16.3.1 Internal Bus Access during Bus Free State 16-6 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD BHW, BLW DB0 - DB15 "H" WAIT "H" Write Write (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1 RD BHW, BLW DB0 - DB15 WAIT "H" "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.2 Read/Write Timing (for Access with 1 Internal Wait Cycle) 16-7 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "H" Write Write (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.3 Read/Write Timing (for Access with 2 Internal Wait Cycles) 16-8 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "H" Write Write (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.4 Read/Write Timing (for Access with 3 Internal Wait Cycles) 16-9 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT "H" (Don't Care) Write Write (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.5 Read/Write Timing (for Access with 4 Internal Wait Cycles) 16-10 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (6 cycles) 4 internal wait cycles BCLK 1 external wait cycle A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (6 cycles) 1 external wait cycle 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "L" "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.6 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) 16-11 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3+n cycles) 2 internal wait cycles BCLK n external wait cycles A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT "H" (Don't Care) "L" "L" "L" Write Write (3+n cycles) 2 internal wait cycles BCLK n external wait cycles A12 - A30 CS0, CS1 RD BHW, BLW "H" DB0 - DB15 WAIT (Don't Care) "L" "L" "L" "H" Note: • Circles above indicate points at which signals are sampled. Figure 16.3.7 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) 16-12 32171 Group User's Manual (Rev.2.00) 16 (2) When Bus Mode Control Register = 1 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ __ CS1, RD, BHE, BLE, WAIT, and WR. Bus-free state internal bus access BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE DB0 - DB15 WAIT "H" "H" "H" Hi-z "H" Notes: • Hi-Z denotes a high-impedance state. • BCLK is not output. Figure 16.3.8 Internal Bus Access during Bus Free State 16-13 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (2 cycles) 1 internal wait cycle BCLK A12 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) 1 internal wait cycle BCLK A12 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.9 Read/Write Timing (for Access with 1 Internal Wait Cycle) 16-14 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE DB0 - DB15 "H" WAIT "H" (Don't Care) Write Write (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.10 Read/Write Timing (for Access with 2 Internal Wait Cycles) 16-15 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE DB0 - DB15 "H" WAIT (Don't Care) "H" Write Write (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.11 Read/Write Timing (for Access with 3 Internal Wait Cycles) 16-16 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE "H" DB0 - DB15 WAIT "H" (Don't Care) Write Write (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE "H" DB0 - DB15 WAIT (Don't Care) "H" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.12 Read/Write Timing (for Access with 4 Internal Wait Cycles) 16-17 32171 Group User's Manual (Rev.2.00) 16 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (6 cycles) 1 external wait cycle 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR BHE, BLE "H" DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (6 cycles) 1 external wait cycle 4 internal wait cycles BCLK A12 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.13 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) 16-18 32171 Group User's Manual (Rev.2.00) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3+n cycles) 2 internal wait cycles BCLK n external wait cycles A12 - A30 CS0, CS1 RD WR BHE, BLE "H" DB0 - DB15 WAIT "H" (Don't Care) "L" "L" "L" Write Write (3+n cycles) 2 internal wait cycles BCLK n external wait cycles A12 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" "L" "L" Notes: • Circles above indicate points at which signals are sampled. • BCLK is not output. Figure 16.3.14 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) 16-19 32171 Group User's Manual (Rev.2.00) 16 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller * This is a blank page.* 16-20 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode 17.2 Example of RAM Backup when Power is Down 17.3 Example of RAM Backup for Saving Power Consumption 17.4 Exiting RAM Backup Mode (Wakeup) 17 17.1 Outline of RAM Backup Mode RAM BACKUP MODE 17.1 Outline In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes: • Back up the internal RAM data when the power is down • Turn off the power to the CPU whenever necessary to save on the system's power consumption The 32R/E CPU is placed in RAM backup mode by applying a voltage of 2.0-3.3 V to the VDD pin (provided for RAM backup) and 0 V to all other pins. During RAM backup mode, the contents of the internal RAM are retained, while the CPU and internal peripheral I/O remain idle. Also, because all pins except VDD are held low during RAM backup mode, power consumption in the system can effectively reduced. 17.2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 17.2.1. The following explains how the RAM can be backed up by using this circuit as an example. DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C Power supply monitor IC VCC VDD Backup power supply for power outage (Note 1) Reference voltage for power outage detection VREF VBB Backup battery VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 3) Power outage detection signal SBI (Note 2) OUT ADnINi M32R/ECU Note 1 : Power outage is detected by the DC IN (regulator input) voltage. Note 2 : These pins are used to detect a RAM backup signal. Note 3 : This pin outputs a high when the power is on and outputs a low when the power is down. Figure 17.2.1 Typical Circuit for RAM Backup at Power Outage 17-2 32171 Group User's Manual (Rev.2.00) 17 17.2.1 Normal Operating State RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down Figure 17.2.2 shows the normal operating state of the M32R/ECU. During normal operation, input _______ on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C Power supply monitor IC VCC VDD Backup power supply for power outage (Note 4) 3.3V 3.3V 3.3V (Note 1) Reference voltage for power outage detection 5V 5V 5V VREF VBB Backup battery (Note 3) Power outage detection signal SBI OUT ADnINi "H" VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 2) M32R/ECU Note 1 : Power outage is detected by the DC IN (regulator input) voltage. Note 2 : These pins are used to detect a RAM backup signal. Note 3 : This pin outputs a high when the power is on and outputs a low when the power is down. Note 4 : Backup power supply = 2.0 to 3.3 V Figure 17.2.2 Normal Operating State 17-3 32171 Group User's Manual (Rev.2.00) 17 17.2.2 RAM Backup State RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down Shown in Figure 17.2.3 is the power outage RAM backup state of the M32R/ECU. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/ECU. Also, the power supply monitor IC's power outage detection pin outputs a low, ___ causing the SBI pin or ADnINi pin input to go low, which generates a RAM backup signal ((a) in Figure 17.2.3). Whether the power is down or not must be determined with respect to the DC IN (regulator input) voltage in order to allow for a software processing time at power outage. To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.2.3). When the power supply to VCC goes down after settings in (1), the voltage applied to the VDD pin becomes 2.0-3.3 V and voltages applied to all other pins drop to 0 V, and the M32R/ECU thereby enters RAM backup mode ((c) in Figure 17.2.3). DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C (Note 5) (Note 1) Reference voltage for power outage detection Power supply monitor IC VCC VDD Backup power supply for power outage 2.0V - 3.3V 3.3V 0V 0V 0V 0V 0V VREF (Note 4) Backup battery VBB (Note 3) Power outage detection signal SBI OUT ADnINi "L" VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 2) M32R/ECU Example of RAM backup processing (a) Power goes down (Note 4) Create check data for backup RAM (b) (c) RAM backup mode Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. ___ Note 4: Determined by the input voltage level on SBI pin or ADnINi pin. Note 5: Adjust this capacitance to provide the necessary processing time in (b). Figure 17.2.3 RAM Backup State at Power Outage 17-4 32171 Group User's Manual (Rev.2.00) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3 Example of RAM Backup for Saving Power Consumption Figure 17.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example. DC IN Input Regulator Output (3.3V system) Regulator Output (5V system) Regulator Output (3.3V system) RAM backup power supply IB External circuit RAM backup signal (Note 1) Port X (Note 2) SBI ADnINi (Note 3) VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Note 1 : This signal outputs a low for RAM backup. Note 2 : This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3 : These pins are used to detect a RAM backup signal. Figure 17.3.1 Typical Circuit for RAM Backup to Save on Power Consumption 17-5 32171 Group User's Manual (Rev.2.00) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.1 Normal Operating State Figure 17.3.2 shows the normal operating state of the M32R/ECU. During normal operation, the ___ RAM backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 015) pin used for RAM backup signal detection remains high. Port X, which is the transistor's base connecting pin, should output a high. This causes the transistor's base voltage, IB, to go high, so that current is fed from the power supply to the VCC pin via the transistor. DC IN Input Regulator Output (3.3V system) Regulator Output (5V system) Regulator Output (3.3V system) "H" RAM backup power supply IB External circuit RAM backup signal (Note 1) "H" Port X (Note 2) "H" SBI ADnINi (Note 3) 3.3V 3.3V 5V 5V 5V 3.3V VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Note 1 : This signal outputs a low for RAM backup. Note 2 : This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode (One of the port pins selected). Note 3 : These pins are used to detect a RAM backup signal. Figure 17.3.2 Normal Operating State 17-6 32171 Group User's Manual (Rev.2.00) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.2 RAM Backup State Figure 17.3.3 shows the RAM backup state of the M32R/ECU. Figure 17.3.4 shows a RAM backup ___ sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and (a) in Figure 17.3.3). To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.3.3). (2) To materialize low-power operation, set all programmable input/output pins except port X for input mode (or for output mode, with pins outputting a low) ((c) in Figure 17.3.3). (3) Set port X for input mode (B and (d) in Figure 17.3.3). This causes the transistor's base voltage, IB, to go low, so that no current flows from the power supply to the VCC pin via the transistor (C in Figure 17.3.3). Consequently, the power to the VCC pin is shut off (D in Figure 17.3.3). Due to settings in (1) to (3), the voltage applied to the VDD pin becomes 3.3 V ± 10% and voltages applied to all other pins drop to 0 V, thus placing the M32R/ECU in RAM backup mode ((d) in Figure 17.3.3). DC IN Input C IB "L" Regulator Output (5V system) Regulator Output (3.3V system) "L" B "L" Port X (Note 2) A "L" SBI ADnINi (Note 3) 0V 0V 0V 0V 0V 3.3V Regulator Output (3.3V system) D Power supply for RAM External circuit RAM backup signal (Note 1) "L" VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Example of RAM backup processing (a) Generate RAM backup signal (Note 4) Create check data for backup RAM Set transistor's base connecting pin (port X) for input mode (Note 5) (b) (c) (d) RAM backup mode Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. ___ Note 4: Determined by the input voltage level on SBI pin or ADnINi pin. Note 5: Base voltage IB = 0 causes the current fed to the VCC pin to stop. Explained in A to D above. Figure 17.3.3 RAM Backup State for Low-Power Operation 17-7 32171 Group User's Manual (Rev.2.00) 17 Power on VCCE, VREFn, AVCCn VCCI, OSC-VCC RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 5.0V RAM backup period 0V 3.3V 0V VDD Port output setting (High level) Port input mode Port output setting (High level) Port X External input signal goes low External input signal goes high SBI ADnINi f (XIN) Oscillation stabilization time Oscillation stabilization time RESET Figure 17.3.4 Example of RAM Backup Sequence for Low-Power Operation 17.3.3 Precautions to Be Observed at Power-on When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port's initial output level is indeterminate. Therefore, be sure to set the output high level in the Port X Data Register before you set port X for output mode. Unless this method is followed, port output may go low at the same time port output is set after the clock oscillation has stabilized, causing the device to enter RAM backup mode. 17-8 32171 Group User's Manual (Rev.2.00) 17 RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) 17.4 Exiting RAM Backup Mode (Wakeup) Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input. The following shows how to execute wakeup processing. (1) Reset the device ((a) in Figure 17.4.1). For details about reset, refer to Chapter 7, "Reset." (2) Set port X for output mode and output a high from the port ((b) in Figure 17.4.1). (Note 1) (3) Check the RAM contents against the check data created before entering RAM backup mode ((c) in Figure 17.4.1). (4) If the RAM contents and check data did not match when checked in (3), initialize the RAM ((d) in Figure 17.4.1). If the RAM contents and check data matched, use the retained data in the program. (5) After initializing each internal circuit ((e) in Figure 17.4.1), return the main routine ((f) in Figure 17.4.1). Note 1: For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Example of wakeup processing (a) Reset (b) Set transistor's base connecting pin (port X) for high-level output mode (Note 1) (c) Check RAM contents against backup RAM check data Error OK (d) Initialize RAM (e) Initial each internal circuit (f) To main routine Note 1: For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Figure 17.4.1 Wakeup Processing 17-9 32171 Group User's Manual (Rev.2.00) 17 RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) * This is a blank page.* 17-10 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.2 Clock Generator Circuit 18 18.1 Oscillator Circuit OSCILLATION CIRCUIT 18.1 Oscillator Circuit The M32R/ECU contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory. The frequency of this clock is divided by 2 in the subsequent circuit to produce the internal peripheral clock, which is the operating clock for the internal peripheral I/O. 18.1.1 Example of an Oscillator Circuit A clock generating circuit can be configured by connecting a ceramic (or crystal) resonator between the XIN and XOUT pins external to the chip. Figure 18.1.1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin (VCNT). For constants Rf, CIN, COUT, and Rd, consult your resonator manufacturer to determine the appropriate values. When you use an externally sourced clock signal without using the internal oscillator circuit, connect the external clock signal to the XIN pin and leave the XOUT pin open. M32R/ECU Oscillator module Oscillator circuit PLL circuit 1/2 To CPU clock To internal peripheral clock OSC-VSS OSC-VCC XIN Rf XOUT Rd VCNT 220pF BCLK / P70 C CIN COUT (Note 1) 0.1µF (Note 1) 1K OSCVCC : 3.3 V power supply Note 1: allowable error ±10% Figure 18.1.1 Example of a System Clock Generating Circuit 18-2 32171 Group User's Manual (Rev.2.00) 18 18.1.2 System Clock Output Function OSCILLATION CIRCUIT 18.1 Oscillator Circuit A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1. Configuration of the P7 Operation Mode Register is shown below. s P7 Operation Mode Register (P7MOD) D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 1 : BCLK 0 : P71 ____ R W 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK 18-3 32171 Group User's Manual(Rev.2.00) 18 18.1.3 Oscillation Stabilization Time at Power-on OSCILLATION CIRCUIT 18.1 Oscillator Circuit The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used. Figure 18.1.2 shows an oscillation stabilization time at poweron. Oscillation stabilization time OSC-VCC RESET XIN Figure 18.1.2 Oscillation Stabilization Time at Power-on 18-4 32171 Group User's Manual (Rev.2.00) 18 18.2 Clock Generator Circuit OSCILLATION CIRCUIT 18.2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits. XIN (8MHz - 10MHz) X4 CPUCLK (CPU clock) (32MHz - 40MHz) 1/2 BCLK (peripheral clock) (16MHz - 20MHz) 1/2 peripheral clock (8MHz - 10MHz) 1/4 Figure 18.2.1 Configuration of the Clock Generator Circuit 18-5 32171 Group User's Manual(Rev.2.00) 18 OSCILLATION CIRCUIT 18.2 Clock Generator Circuit * This is a blank page.* 18-6 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 19 JTAG 19.1 Outline of JTAG 19.2 Configuration of the JTAG Circuit 19.3 JTAG Registers 19.4 Basic Operation of JTAG 19.5 Boundary Scan Description Language 19.6 Precautions on Board Design when Using JTAG 19.7 Processing Pins when Not Using JTAG 19 19.1 Outline of JTAG JTAG 19.1 Outline of JTAG The 32171 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std. 1149.1a-1993 documentation. The functions of JTAG interface related pins mounted on the 32171 are shown below. Table 19.1.1 JTAG Pin Functions Type Symbol Pin Name Test clock Test data input I/O Input input Function Clock input to the test circuit. Synchronous serial data input pin used to enter test instruction code and test data. This input is sampled on rising edges of JTCK. JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data. This signal changes state on falling edges of JTCK, and is output only in Shift-IR or ShiftDR state. JTMS Test mode select Input Test mode select input to control the test circuit's state transitions. This input is sampled on rising edges of JTCK. JTRST Test reset Input Active-low test reset input to initialize the test circuit asynchronously. To ensure that the test circuit is reset without fail, JTMS signal input must be held high while this signal changes state from low to high. Note 1: TAP = Test Access Port, a JTAG interface stipulated in IEEE 1149.1. TAP JTCK (Note1) JTDI 19-2 32171 Group User's Manual (Rev.2.00) 19 19.2 Configuration of the JTAG Circuit JTAG 19.2 Configuration of the JTAG Circuit The 32171's JTAG circuit consists of the following blocks: • Instruction register to hold instruction codes which are fetched through the boundary-scan path • A set of data registers which are accessed through the boundary-scan path • Test access port (abbreviated TAP) controller to control the JTAG unit's state transitions • Control logic to select input, output, etc. A configuration of the JTAG circuit is shown below. M32R/ECU Data register set JTDI Boundary-scan register (JTAGBSR) Bypass register (JTAGBPR) ID code register (JTAGIDR) Output selection Decoder Output selection Instruction register (6 bits) (JTAGIR) JTMS JTCK JTRST TAP controller Figure 19.2.1 Configuration of the JTAG Circuit 19-3 32171 Group User's Manual (Rev.2.00) Buffer JTDO 19 19.3 JTAG Registers 19.3.1 Instruction Register (JTAGIR) JTAG 19.3 JTAG Registers The Instruction Register (JTAGIR) is a 6-bit register to hold instruction code. This register is set in IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. When test is reset (to initialize the test circuit), the initial value of this register is b'000010 (IDCODE instruction). After a test reset, the IDCODE Register is selected as the data register until an instruction code is set by an external device. In "Capture-IR" state, this register always has b'110001 (fixed value) loaded into it. Therefore, when in "Shift-IR" state, no matter what value was set in this register, b'110001 is always output from the JTDO pin (sequentially beginning with LSB). However, this value normally is not handled as instruction code. Shown below is outside the scope of guaranteed operations. Note that if this operation is performed, the device may inadvertently handle b'110001 as instruction code, which makes it unable to operate normally. [Capture-IR] → [Exit1-IR] → [Update-IR] The 32171's JTAG interface supports the following instructions: • Three instructions stipulated as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS) • Device ID register access instruction (IDCODE) Table 19.3.1 JTAG Instruction List Instruction Code Abbreviation b'000000 b'000001 EXTEST SAMPLE/PRELOAD Operation Tests circuit/board-level connections outside the chip. Samples operating circuit status and outputs the sampled status from JTDO pin, while at the same time entering the data used for boundary-scan test from the JTDI pin and presets it in Boundary Scan Register. b'000010 IDCODE Selects ID Code Register and outputs device and manufacturer identification data from JTDO pin. b'111111 BYPASS Selects Bypass Register and inspects or sets data. Notes: • Do not set any other instruction code. • For details about "IR path sequence," "DR path sequence," "Test reset," "Capture-IR" state, "Shift-IR" state, "Exit1-IR" state, and "Update-IR" state, refer to Section 19.4. 19-4 32171 Group User's Manual (Rev.2.00) 19 19.3.2 Data Registers (1) Boundary Scan Register (JTAGBSR) JTAG 19.3 JTAG Registers The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this register are assigned to each pin on the 32171. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/PRELOAD instruction. In "Capture-DR" state, this register captures the status of input pins or internal logic output values. In "Shift-DR" state, while outputting the sampled value, it is used to set pin functions (input/output pin and tristate output pin direction) and output values by entering data for boundary-scan test. (2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32171 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction. This register when in "Capture-DR" state has b'0 (fixed value) loaded into it. (3) ID Code Register (JTAGIDR) The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds the following information: • Version information (4 bits) • Part number (16 bits) • Manufacturer ID (11 bits) : b'0000 : b'0011 0010 0010 0000 : b'000 0001 1100 This register is connected between the JTDI and JTDO pins, and is selected when issuing IDCODE instruction. When in "Capture-DR" state, this register has the said IDCODE data loaded into it, which is output from the JTDO pin in "Shift_DR" state. This register is a read-only register, so that the data written from the JTDI pin during DR pass sequence is ignored. Therefore, make sure JTDI input = low during "Shift-DR" state. 0 34 Version 4 bits Part number 16 bits 19 20 Manufacturer ID 11 bits 30 31 1 Note: • For details about "Capture-DR" and "Shift-DR" states, refer to Section 19.4. 19-5 32171 Group User's Manual (Rev.2.00) 19 19.4 Basic Operation of JTAG 19.4.1 Outline of JTAG Operation JTAG 19.4 Basic Operation of JTAG The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state. • Capture operation The result of boundary-scan test or the fixed data defined for each register is sampled. As register operation, the input data is loaded into the shift register stage. • Shift operation The register is accessed from outside through the boundary-scan path. The sampled value is output to an external device at the same time data is set from outside. As register operation, bits are shifted right between each shift register stage. • Update operation The data set from outside during shift is driven. As register operation, the value set in the shift register stage is transferred to the parallel output stage. The JTAG interface undergoes transitions of internal state depending on JTMS input as it performs the following two operations. In either case, the operation basically is performed in order of Capture → Shift → Update. • IR path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subsequent DR path sequence. • DR path sequence The selected data register is operated on to inspect or set data. 19-6 32171 Group User's Manual (Rev.2.00) 19 registers are shown below. JTAG 19.4 Basic Operation of JTAG The state transitions of the TAP controller and the basic configuration of the 32171's JTAG related 1 Test-Logic-Reset 0 1 1 1 0 Run-Test/Idle Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 Select-IR-Scan 0 1 0 Capture-IR 0 Shift-IR 1 0 1 0 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 1 0 Note: • Values (0 and 1) in this diagram denote the state of JTMS input signal. Figure 19.4.1 TAP Controller State Transition Input multiplexer Shift register stage To next cell Data input From preceding cell "Shift-DR" or "Shift-IR" "Clock-DR" or "Clock-IR" "Update-DR" or "Update-IR" Test reset 0 1 G DQ T DQ T R Data output Parallel output stage Note: • Shown here is the basic configuration, and the configuration of DR and IR does not all have to be like this. Figure 19.4.2 Basic Configuration of JTAG Related Registers 19-7 32171 Group User's Manual (Rev.2.00) 19 19.4.2 IR Path Sequence JTAG 19.4 Basic Operation of JTAG Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of two JTCK cycles from "Run-Test/Idle" state to go to "Select-IR-Scan" state. (2) Set JTMS = low to go to "Capture-IR" state. At this time, b'110001 (fixed value) is set in the instruction register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-IR" state. In "Shift-IR" state, the value of the shift register stage is shifted right one bit every cycle, and the data b'110001 (fixed value) that was set in (2) is serially output from the JTDO pin. At the same time, the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit. Because instruction code is set in the instruction register which is comprised of 6 bits, the "Shift-IR" state continues for a period of 6 JTCK cycles. To stop the shift operation in the middle, go to "Pause-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). Also, to return from "Pause-IR" state, go to "Shift-IR" state via temporarily "Exit2-IR" state (by setting JTMS input from high to low). (4) By setting JTMS = high, go from "Shift-IR" state to "Exit1-IR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-IR" state. In "Update-IR" state, the instruction code that was set in the instruction register's shift register stage is transferred to the instruction register's parallel output stage and, thus, JTAG instruction decoding begins. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state. 19-8 32171 Group User's Manual (Rev.2.00) 19 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise of JTCK in "Shift-IR" state. Instruction code is set in the parallel output stage at fall of JTCK in "Update-IR" state. JTCK JTMS Select-DR-Scan Select-IR-Scan Run-Test/Idle TAP state JTDI Don't Care Instruction code (6 bits) LSB value MSB value Don't Care High impedance JTDO High impedance 1 0 0 0 1 1 JTDO is output at fall of JTCK in "Shift-IR" state. Shift output from the instruction register is fixed to b'110001. Finished storing instruction code in the instruction register's shift register stage. Figure 19.4.3 IR Path Sequence 19-9 32171 Group User's Manual (Rev.2.00) Run-Test/Idle Capture-IR Update-IR Exit1-IR Shift-IR 19 19.4.3 DR Path Sequence JTAG 19.4 Basic Operation of JTAG The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of one JTCK cycle from "Run-Test/Idle" state to go to "SelectDR-Scan" state. Which data register will be selected at this time depends on the instruction that was set during the IR path sequence performed prior to the DR path sequence. (2) Set JTMS = low to go to "Capture-DR" state. At this time, the result of boundary-scan test or the fixed data defined for each register is set in the data register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-DR" state. In "Shift-DR" state, the DR value is shifted right one bit every cycle, and the data that was set in (2) is serially output from the JTDO pin. At the same time, the setup data serially entered from the JTDI pin is set in the data register's shift register stage bit by bit. By continuing the "Shift-DR" state as long as the number of bits of the selected data register (by entering JTMS = low), all bits of data can be set in and read out from the shift register stage. To stop the shift operation in the middle, go to "Pause-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). Also, to return from "Pause-DR" state, go to "Shift-DR" state via temporarily "Exit2-DR" state (by setting JTMS input from high to low). (4) Set JTMS = high to go from "Shift-DR" state to "Exit1-DR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-DR" state. In "Update-DR" state, the data that was set in the data register's shift register stage is transferred to the parallel output stage and, thus, the setup data becomes ready for use. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state. 19-10 32171 Group User's Manual (Rev.2.00) 19 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise of JTCK in "Shift-DR" state. Setup data is set in the parallel output stage at fall of JTCK in "Update-DR" state. JTCK JTMS Select-DR-Scan Run-Test/Idle TAP state JTDI Don't Care Don't Care LSB value JTDO High impedance MSB value High impedance JTDO is output at fall of JTCK in "Shift-DR" state. Finished storing setup data in the shift register stage of the selected data register. Note: • The shift operation of the data register for the shift register stage is right-shifted, therefore, the output from JTDO is from the LSB side. Input to JTDI starts from the value to be set in LSB side. Figure 19.4.4 DR Path Sequence 19-11 32171 Group User's Manual (Rev.2.00) Run-Test/Idle Capture-DR Update-DR Shift-DR Exit1-DR 19 19.4.4 Examining and Setting Data Registers JTAG 19.4 Basic Operation of JTAG To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit). Test reset can be entered by one of the following two methods: • Pull JTRST pin input low • Drive JTMS pin input high and enter JTCK for 5 cycles or more (2) Set JTMS = low to go to "Run-Test/Idle" state. To continue the idle state, hold JTMS input low. (3) Set JTMS = high to exit "Run-Test/Idle" state and perform IR path sequence. In IR path sequence, specify the data register you want to inspect or set. (4) Subsequently, perform DR path sequence. For the data register specified in IR path sequence, enter setup data from the JTDI pin and read out reference data from the JTDO pin. (5) If you want to proceed and perform IR path sequence or DR path sequence after DR path sequence is completed, enter JTMS = high to return to "Select-DR-Scan" state. If you want to wait for the next processing after a series of IR and DR path sequence processing is completed, enter JTMS = low to go to "Run-Test/Idle" state and retain the state. 19-12 32171 Group User's Manual (Rev.2.00) 19 TAPstates Test-Logic- Run-Test Reset state /Idle state IR path sequence DR path sequence JTAG 19.4 Basic Operation of JTAG Run-Test /Idle state IR path sequence DR path sequence JTDI (Note 1) Instruction Setup data code #0 #0 Fixed value b'110001 Specify the data register you want to inspect or set. Instruction Setup data code #1 #1 Fixed value b'110001 JTDO (Note 2) (Note 3) (Note 3) Setup data is entered serially from JTDI. Reference data is serially output from JTDO. (1) Basic access TAP states Test-Logic- Run-Test Reset state /Idle state IR path sequence DR path sequence Run-Test /Idle state DR path sequence DR path sequence JTDI (Note 1) Instruction Setup data code #0 #0 Fixed value b'110001 Specify the data register you want to inspect or set. Setup data Setup data #1 #2 JTDO (Note 2) (Note 3) (Note 3) (Note 3) Same data register can be operated on to inspect or set data continuously. (2) Continuous access to the same data register Note 1 : The setup value for each register must be entered from the JTDI pin beginning with the LSB. Note 2 : The value of each register is output from the JTDO pin beginning with the LSB. The JTDO pin outputs valid data in only "Shift-IR" state of IR path sequence and "Shift-DR" state of DR path sequence. In all other states, the JTDO pin is tristated (high impedance). Note 3 : Data can only be read out from the data register which is selected by the instruction that was set in the immediately preceding IR path sequence. Output in the selected data register's shift register stage is the value that was sampled during "Capture-DR" state. Figure 19.4.5 Continuous JTAG Access 19-13 32171 Group User's Manual (Rev.2.00) 19 JTAG 19.5 Boundary Scan Description Language 19.5 Boundary Scan Description Language The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to "Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL). BSDL helps to precisely describe the functions of standard-compliant components to be tested. For package connection test, this language is used by Automated Test Pattern Generation tools, and for synthesized test logic and verification, it is used by Electronic Design Automation tools. BSDL provides powerful extended functions usable in internal test generation and necessary to write hardware debug and diagnostics software. The primary section of BSDL contains statements of logical port description, physical pin map, instruction set, and boundary register description. • Logical port description The logical port description assigns meaningful symbol names to each pin on the chip. This determines the logic type of input, output, input/output, buffer, or link of each pin that defines the logical direction of signal flow. • Physical pin map The physical pin map correlates the chip's logical ports to the physical pins on each package. Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description. • Instruction set statement The instruction set statement writes bit patterns to be shifted in into the chip's instruction register. This bit pattern is necessary to place the chip into each test mode defined in standards. It is also possible to write instructions exclusive to the chip. • Boundary register description The boundary register description is a list of boundary register cells or shift stages. Each cell is assigned a separate number. The cell with number 0 is located closest to the test data output (JTDO) pin, and the cell with the largest number is located closest to the test data input (JTDI) pin. Cells also contain related other information which includes cell type, logical port corresponding to cell, logical function of cell, safety value, control cell number, disable value, and result value. Note: • Information on the Boundary Scan Description Language (BSDL) can be downloaded from the M32R family application engineering data in “Renesas Home Page.” The URL address of this home page is shown below. • http: //www.renesas.com/ 19-14 32171 Group User's Manual (Rev.2.00) 19 JTAG 19.6 Precautions on Board Design when Using JTAG 19.6 Precautions on Board Design when Using JTAG The JTAG pins require that wiring lengths be matched during board design in order to accomplish fast, highly reliable communication with JTAG tools. An example of how to process pins when using JTAG tools is shown below. VCCE(5V) M32R/ECU 10KΩ JTDO 10KΩ SDI connector (JTAG connector) Power 33Ω 33Ω JTAG tool TDO JTDI 10KΩ JTMS 10KΩ 33Ω JTCK 33Ω JTRST 2KΩ 0.1µF 33Ω TDI TMS TCK TRST GND User board Make sure wiring lengths are the same, and avoid bending wires as much as possible. Also, do not use through-holes within wiring. Notes: •Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. • Even when not using JTAG tools, always be sure to process each pin. The same pulldown/pullup resistance values as when using JTAG tools may be used without causing any problem. Figure 19.6.1 Example for Processing Pins when Using JTAG Tools 19-15 32171 Group User's Manual (Rev.2.00) 19 JTAG 19.7 Processing Pins when Not Using JTAG 19.7 Processing Pins when Not Using JTAG The diagram below shows how to process JTAG pins when not using these pins (i.e. for boards that do not have pins/connectors connecting to JTAG tools). VCCE(5V) M32R/ECU 0–100KΩ JTDO 0–100KΩ JTDI 0–100KΩ JTMS 0–100KΩ JTCK JTRST 0–100KΩ User board Note: • Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI,JTMS, and JTCK pins are pulled high or pulled low. Figure 19.7.1 Processing Pins when Not Using JTAG 19-16 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 20 POWER-ON/POWER-OFF SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.2 Power-on Sequence 20.3 Power-off Sequence 20 POWER-ON/POWER-OFF SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.1 Configuration of the Power Supply Circuit To allow for high-speed operation with low power consumption, the M32/ECU is designed in such a way that the external interface circuits operate with a 5 V or 3.3 V external I/O power supply, while all other circuits operate with the 3.3 V internal power supply. This requires that control timing of both 5 V and 3.3 V power supplies be considered when designing your circuit. M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 5V 3.3 V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.1.1 Configuration of the Power Supply Circuit (when external I/O power supply = 5V ) Table 20.1.1 List of Power Supply Functions Type of Power Supply External I/O Power Supply Pin Name VCCE AVCC0 VREF0 Internal Power Supply VCCI FVCC VDD OSC-VCC Function Supplies power to external I/O ports Power supply for A-D converter Reference voltage for A-D converter Supplies power to internal logic Power supply for internal flash memory Power supply for internal RAM backup Power supply for oscillator and PLL circuits 20-2 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.1 Configuration of the Power Supply Circuit M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 3.3 V 3.3 V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.1.2 Configuration of the Power Supply Circuit (when external I/O power supply = 3.3V ) 20-3 32171 Group User's Manual (Rev.2.00) 20 20.2 Power-On Sequence POWER-ON/POWER-OFF SEQUENCE 20.2 Power-on Sequence 20.2.1 Power-On Sequence When Not Using RAM Backup The diagram below shows the M32/ECU’s power supply (external I/O and internal) turn-on sequence when not using RAM backup. 5V VCCE 0V 5V AVCC0 0V 5V VREF0 RESET 0V 0V 3.3V VDD 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (1) (2) 5V (1): Turn on the external I/O power supply before turning on the internal power supply. ____________ (2): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to exit the reset state). Note: • Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.1 Power-On Sequence When Not Using RAM Backup (when external I/O power supply = 5V ) Note: • Providing the difference in voltage levels is within a range (about 0.1–0.2 V in a transient state) where no current in-flow due to diode characteristics will occur, inversion of phases ay not present a problem. To ensure stable operation, however, make sure the circuit you design satisfies the recommended operating conditions. 20-4 32171 Group User's Manual (Rev.2.00) 20 3.3V VCCE 0V 3.3V AVCC0 0V 3.3V VREF0 RESET 0V 0V 3.3V VDD 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (1) POWER-ON/POWER-OFF SEQUENCE 20.2 Power-on Sequence 3.3V ____________ (1): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to exit the reset state). Note: • Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.2 Power-On Sequence When Not Using RAM Backup (when external I/O power supply = 3.3V ) 20-5 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.2 Power-on Sequence 20.2.2 Power-On Sequence When Using RAM Backup The diagram below shows a power-on sequence(external I/O and internal power supply) of the M32R/ECU when using RAM backup. 5V VCCE 0V 5V AVCC0 0V 5V VREF0 RESET 0V 0V 3.3V VDD 2.0V 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (1) (2) 5V (1): Turn on the internal power supply after turning on the external I/O power supply. ____________ (2): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to exit the reset state). Note: • Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.3 Power-On Sequence When Using RAM Backup(when external I/O power supply = 5 V ) Note: • Providing the difference in voltage levels is within a range (about 0.1–0.2 V in a transient state) where no current in-flow due to diode characteristics will occur, inversion of phases may not present a problem. To ensure stable operation, however, make sure the circuit you design satisfies the recommended operating conditions. 20-6 32171 Group User's Manual (Rev.2.00) 20 3.3V VCCE 0V 3.3V AVCC0 0V 3.3V VREF0 RESET 0V 0V 3.3V VDD 2.0V 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (1) POWER-ON/POWER-OFF SEQUENCE 20.2 Power-on Sequence 3.3V ____________ (1): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to exit the reset state). Note: • Power-on limitations • VDD OSC-VCC VCCI FVCC • VCCE VCCI, FVCC, OSC-VCC Figure 20.2.4 Power-On Sequence When Using RAM Backup(when external I/O power supply = 3.3 V ) 20-7 32171 Group User's Manual (Rev.2.00) 20 20.3 Power-off Sequence POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence 20.3.1 Power-off Sequence When Not Using RAM Backup The diagram below shows a power-off sequence (external I/O and internal power supply) of the M32R/ECU when not using RAM backup. 5V VCCE 0V AVCC0 5V 0V VREF0 5V (1) 0V 5V RESET 0V VDD 3.3V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (2) 0V ____________ (1): Pull the RESET pin input low. ____________ (2): Turn off the external I/O and the internal power supply after the RESET pin goes low. Note: • Power-off requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.1 Power-off Sequence When Not Using RAM Backup(when external I/O power supply = 5 V ) Note: • Providing the difference in voltage levels is within a range (about 0.1–0.2 V in a transient state) where no current in-flow due to diode characteristics will occur, inversion of phases may not present a problem. To ensure stable operation, however, make sure the circuit you design satisfies the recommended operating conditions. 20-8 32171 Group User's Manual (Rev.2.00) 20 3.3V VCCE 3.3V AVCC0 3.3V VREF0 3.3V RESET 3.3V VDD 3.3V VCCI 3.3V FVCC 3.3V OSC-VCC (1) POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence 0V 0V 0V 0V 0V 0V 0V 0V ____________ (1): Turn off all power supplies after the RESET pin goes low. Note: • Power-off requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.2 Power-off Sequence When Not Using RAM Backup(when external I/O power supply = 3.3 V ) 20-9 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence 20.3.2 Power-off Sequence When Using RAM Backup The diagram below shows a power-off sequence (external I/O and internal power supply) of the M32R/ECU when using RAM backup. VCCE AVCC0 5V 0V 5V 0V VREF0 (1) (2) 5V 0V 5V P72 / HREQ 0V 5V RESET (3) 0V VDD 3.3V 3.3V VCCI 3.3V FVCC 0V 3.3V OSC-VCC 0V (3) (4) 2.0V 0V __________ (1): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. ____________ (2): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull ____________ the RESET pin input low. ____________ (3): Turn off the external I/O and the internal power supply after the RESET pin goes low. (4): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: • Power-off requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.3 Power-off Sequence When Using RAM Backup(when external I/O power supply = 5 V) Note: • Providing the difference in voltage levels is within a range (about 0.1–0.2 V in a transient state) where no current in-flow due to diode characteristics will occur, inversion of phases may not present a problem. To ensure stable operation, however, make sure the circuit you design satisfies the recommended operating conditions. 20-10 32171 Group User's Manual (Rev.2.00) 20 VCCE POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence 3.3V 0V 3.3V AVCC0 3.3V VREF0 3.3V P72 / HREQ 3.3V RESET 3.3V VDD 3.3V VCCI 3.3V FVCC 3.3V OSC-VCC 0V 0V (3) (4) (3) (1) (2) 0V 0V 0V 0V 2.0V 0V __________ (1): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. ____________ (2): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull ____________ the RESET pin input low. ____________ (3): Turn off all power supply after the RESET pin goes low. (4): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: • Power-off requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.4 Power-off Sequence When Using RAM Backup(when external I/O power supply = 3.3 V) 20-11 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 5V 3.3 V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.5 Microcomputer Ready to Run State 1 M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 3.3 V 3.3 V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.6 Microcomputer Ready to Run State 2 20-12 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 0V 3.3 V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.7 CPU Reset State 20-13 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 5V 0V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.8 CPU Stop State 1 M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 3.3 V 0V Internal power supply VCCI CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.9 CPU Stop State 2 20-14 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence M32R/ECU External I/O power supply VCCE I/O control circuit AVCC0 A-D converter circuit 0V 0V Internal power supply VCCI CPU Peripheral circuit VDD 3.3 V - 2.0V FVCC RAM Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.10 SRAM Data Backup State 20-15 32171 Group User's Manual (Rev.2.00) 20 POWER-ON/POWER-OFF SEQUENCE 20.3 Power-off Sequence * This is a blank page. * 20-16 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.2 Electrical Characteristics (VCCE = 3.3V) 21.3 AC Characteristics 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1 Electrical Characteristics (VCCE = 5V) 21.1.1 Absolute Maximum Ratings Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Symbol VCCI VDD OSC-VCC FVCC VCCE AVCC VREF Parameter Internal Logic Power Supply Voltage RAM Power Supply Voltage PLL Power Supply Voltage Flash Power Supply Voltage External I/O Buffer Voltage Analog Power Supply Voltage Analog Reference Voltage Xin, VCNT Condition VDD VDD VDD VDD VCCE VCCE VCCE VCCI VCCI VCCI VCCI FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC VREF VREF VREF Rated Value -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 -0.3 to 6.5 -0.3 to OSC-VCC+0.3 Unit V V V V V V V V AVCC AVCC AVCC VI Other Xout -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 V -0.3 to VCCE+0.3 Ta=-40 to 85oC 600 500 -40 to 125 -65 to 150 mW mW o VO Other Pd Power Dissipation Ta=-40 to 125oC TOPR Tstg Operating Ambient Temperature (Note 1) Storage Temperature C C o Note 1: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Renesas. 21-2 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter MIN VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note 1) Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2) Flash Power Supply Voltage (Note 2) Analog Power Supply Voltage (Note1) PLL Power Supply Voltage (Note 2) Analog Reference Voltage (Note1) Rated Value TYP 5.0 3.3 3.3 3.3 5.0 3.3 5.0 MAX 5.5 3.6 3.6 3.6 5.5 3.6 5.5 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 10 Unit 4.5 3.0 3.0 3.0 4.5 3.0 4.5 0.8VCCE 0.43VCCE 0 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0-P22 (Note 3) High State Average Output Current P0-P22 (Note 4) Low State Peak Output Current P0-P22 (Note 3) Low State Average Output Current P0-P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF. Note 2: Subject to conditions VDD VCCI FVCC OSC-VCC Note 3: The total amount of output current (peak) on ports must satisfy the conditions below. | Ports P0 + P1 + P2 | 80 mA | Ports P3 + P4 + P13 + P15 + P22 | 80 mA | Ports P6 + P7 + P8 + P9 + P17 | 80 mA | Ports P10 + P11 + P12 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. 21-3 32171 Group User's Manual (Rev.2.00) 21 Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Rated Value MIN TYP 5.0 3.3 3.3 3.3 5.0 3.3 5.0 MAX 5.5 3.6 3.6 3.6 5.5 3.6 5.5 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 8 Unit VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note 1) Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2) Flash Power Supply Voltage (Note 2) Analog Power Supply Voltage (Note 1) PLL Power Supply Voltage (Note 2) Analog Reference Voltage (Note 1) 4.5 3.0 3.0 3.0 4.5 3.0 4.5 0.8VCCE 0.43VCCE 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT 0 IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0-P22 (Note 3) High State Average Output Current P0-P22 (Note 4) Low State Peak Output Current P0-P22 (Note 3) Low State Average Output Current P0-P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF. Note 2: Subject to conditions VDD VCCI FVCC OSC-VCC Note 3: The total amount of output current (peak) on ports must satisfy the conditions below. | Ports P0 + P1 + P2 | 80 mA | Ports P3 + P4 + P13 + P15 + P22 | 80 mA | Ports P6 + P7 + P8 + P9 + P17 | 80 mA | Ports P10 + P11 + P12 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. 21-4 32171 Group User's Manual (Rev.2.00) 21 21.1.3 DC Characteristics 21.1.3.1 Electrical Characteristics ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX VCCE 0.15 × IOL (mA) Unit VOH VOL VDD Output High Voltage Output Low Voltage RAM Retention Power Supply Voltage High State Input Current Low State Input Current IOH IOL -5mA 5mA VCCE+0.165 × IOH(mA) V V V 0 3.0 2.0 -5 -5 When operating When back-up VCCI 3.6 5 5 1 mA 1 10 75 mA 75 See RAM retention power supply current characteristic graph IIH IIL VI=VCCE VI=0V f(XIN)=10.0MHz, When reset µA µA ICC-5V 5 V power supply (Note 1) f(XIN)=10.0MHz, When operating f(XIN)=10.0MHz, When reset f(XIN)=10.0MHz, When operating Ta=25oC ICCI-3V 3.3 V power supply (Note 2) 125 50 1500 µA IDDhold RAM Retention Power Supply Current Ta=85oC VT+ — VT- Hysteresis (Note 3) RTDCLK, RTDRXD, SCLKI0,1, RXD0,1,2, TCLK3-0, TIN0,3,16-23, RESET, FP, MOD0,1, JTMS, JTRST, JTDI VT+ — VT- Hysteresis (Note 4) SBI, HREQ VCCE=5V 1.0 V VCCE=5V 0.3 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET, FP, MOD0, 1, JTMS, JTRST, and JTDI serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-5 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX 10 Unit ICCE ICCI VCCE power supply current when operating f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ VCCI power supply current when operating IOSC-VCC OSC-VCC power supply current when operating FVCC power supply current FICC when operating (Note 1) VDD power supply current IDD when operating (Note 2) mA 120 20 50 35 3 1 mA mA mA mA mA IAVCC IVREF AVCC power supply current when operating VREF power supply current Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21-6 32171 Group User's Manual (Rev.2.00) 21 (3) Electrical characteristics when f(XIN) = 8 MHz ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX VCCE 0.15 × IOL (mA) Unit VOH VOL VDD Output High Voltage Output Low Voltage RAM Retention Power Supply Voltage High State Input Current Low State Input Current IOH IOL -5mA 5mA VCCE+0.165 × IOH(mA) V V V 0 3.0 2.0 -5 -5 When operating When back-up VCCI 3.6 5 5 1 mA 1 10 70 mA 60 See RAM retention power supply current characteristic graph IIH IIL VI=VCCE VI=0V f(XIN)=8.0MHz, When reset µA µA ICC-5V 5 V power supply (Note 1) f(XIN)=8.0MHz, When operating f(XIN)=8.0MHz, When reset f(XIN)=8.0MHz, When operating ICCI-3V 3.3 V power supply (Note 2) 110 50 4000 µA IDDhold Ta=25oC RAM Retention Power Supply Current Ta=125 C VT+ — VT- Hysteresis (Note 3) RTDCLK, RTDRXD, SCLKI0,1, RXD0,1,2, TCLK3-0, TIN0,3,16-23, RESET, FP, MOD0,1, JTMS, JTRST, JTDI VT+ — VT- Hysteresis (Note 4) SBI, HREQ o VCCE=5V 1.0 V VCCE=5V 0.3 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET, FP, MOD0, 1, JTMS, JTRST, and JTDI serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-7 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (4) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX 10 Unit ICCE VCCE power supply current when operating f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ VCCI power supply current ICCI when operating IOSC-VCC OSCVCC power supply current when operating FVCC power supply current FICC when operating (Note 1) VDD power supply current IDD when operating (Note 2) mA 105 16 50 30 3 1 mA mA mA mA mA IAVCC IVREF AVCC power supply current when operating VREF power supply current Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. RAM retention power supply current in a standard sample (reference value) 1000 Ta=125°C 100 Ta=85°C 10 IDD [µA] Ta=25°C 1 0.1 1 1.5 2 3 3.6 4 VDD [V] 21-8 32171 Group User's Manual (Rev.2.00) 21 90 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) Standard sample's ICCI-3V temperature characteristics (when operating: f = 8 MHz, 10 MHz) 80 70 60 ICCI (µA) 50 40 8MHz:25°C 90°C 110°C 130°C 10MHz:25°C 90°C 110°C 130°C 30 20 10 0 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 VCCI (V) Note: • VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V Standard sample's ICCI-3V temperature characteristics (when reset: f = 8 MHz, 10 MHz) 35 30 25 ICCI (µA) 20 15 8MHz:25°C 90°C 110°C 130°C 10MHz:25°C 90°C 110°C 130°C 10 5 0 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 VCCI (V) Note: • VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V 21-9 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX 50 40 0 70 100 Unit Ifvcc1 lfvcc2 Topr cycle tPRG tBERS FVCC Power Supply Current (when Programming) FVCC Power Supply Current (when Erasing) Flash Rewrite Ambient Temperature mA mA o C Rewrite Durability Program Time Block Erase Time times ms ms 1 Page 1 Block 8 50 120 600 21-10 32171 Group User's Manual (Rev.2.00) 21 21.1.4 A-D Conversion Characteristics ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current (Note 2) 14950 ns 8650 -5 5 µA VREF=VCCE Rated Value TYP MAX 10 ±2 Bits LSB Unit IIAN Note 1: The absolute accuracy represents the accuracy of output code including all error sources (including quantization error) of the A-D converter relative to the analog input, and is obtained by the equation below: Absolute accuracy = output code – (analog input voltage ANi/ 1 LSB) When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This referes to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 125°C, f(XIN) = 8.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current (Note 2) 18687.5 ns 10812.5 -5 5 µA VREF=VCCE Rated Value TYP MAX 10 ±2 Bits LSB Unit IIAN Note1: The absolute accuracy represents the accuracy of output code including all error sources (including quantization error) of the A-D converter relative to the analog input, and is obtained by the equation below: Absolute accuracy = output code – (analog input voltage ANi/ 1 LSB) When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This referes to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. 21-11 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) 21.2 ELECTRICAL CHARACTERISTICS (VCCE = 3.3V) 21.2.1 Absolute Maximum Ratings Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Symbol VCCI VDD OSC-VCC FVCC VCCE AVCC VREF Parameter Internal Logic Power Supply Voltage RAM Power Supply Voltage PLL Power Supply Voltage Flash Power Supply Voltage External I/O Buffer Voltage Analog Power Supply Voltage Analog Reference Voltage Xin, VCNT Condition VDD VDD VDD VDD VCCE VCCE VCCE VCCI VCCI VCCI VCCI FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC VREF VREF VREF Rated Value -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 -0.3 to 6.5 -0.3 to OSC-VCC+0.3 Unit V V V V V V V V AVCC AVCC AVCC VI Other Xout -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 V -0.3 to VCCE+0.3 Ta=-40 to 85oC 600 500 -40 to 125 -65 to 150 mW mW o VO Other Pd Power Dissipation Ta=-40 to 125 C TOPR Tstg Operating Ambient Temperature (Note 1) Storage Temperature o C C o Note 1: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Renesas. 21-12 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) 21.2.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter MIN VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage Internal Logic Power Supply Voltage RAM Power Supply Voltage Flash Power Supply Voltage Analog Power Supply Voltage PLL Power Supply Voltage Analog Reference Voltage Rated Value TYP 3.3 3.3 VCCI VCCI VCCE VCCI VCCE MAX 3.6 3.6 VCCI+0.3 VCCI+0.3 VCCE+0.3 VCCI+0.3 VCCE+0.3 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 10 3.6 3.6 3.6 3.6 3.6 Unit 3.0 3.0 3.0 3.0 3.0 3.0 3.0 VCCI-0.3 VCCI-0.3 VCCE-0.3 VCCI-0.3 VCCE-0.3 0.8VCCE 0.43VCCE 0 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0-P22 (Note 1) High State Average Output Current P0-P22 (Note 2) Low State Peak Output Current P0-P22 (Note 1) Low State Average Output Current P0-P22 (Note 2) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: The total amount of output current (peak) on ports must satisfy the conditions below. | Ports P0 + P1 + P2 | 80 mA | Ports P3 + P4 + P13 + P15 + P22 | 80 mA | Ports P6 + P7 + P8 + P9 + P17 | 80 mA | Ports P10 + P11 + P12 | 80 mA Note 2: The average output current is a value averaged during a 100 ms period. 21-13 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) Recommended Operating Conditions (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter MIN VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage Internal Logic Power Supply Voltage RAM Power Supply Voltage Flash Power Supply Voltage Analog Power Supply Voltage PLL Power Supply Voltage Analog Reference Voltage Rated Value TYP 3.3 3.3 VCCI VCCI VCCE VCCI VCCE MAX 3.6 3.6 VCCI+0.3 VCCI+0.3 VCCE+0.3 VCCI+0.3 VCCE+0.3 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 8 3.6 3.6 3.6 3.6 3.6 Unit 3.0 3.0 3.0 3.0 3.0 3.0 3.0 VCCI-0.3 VCCI-0.3 VCCE-0.3 VCCI-0.3 VCCE-0.3 0.8VCCE 0.43VCCE 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT 0 IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0-P22 (Note 1) High State Average Output Current P0-P22 (Note 2) Low State Peak Output Current P0-P22 (Note 1) Low State Average Output Current P0-P22 (Note 2) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: The total amount of output current (peak) on ports must satisfy the conditions below. | Ports P0 + P1 + P2 | 80 mA | Ports P3 + P4 + P13 + P15 + P22 | 80 mA | Ports P6 + P7 + P8 + P9 + P17 | 80 mA | Ports P10 + P11 + P12 | 80 mA Note 2: The average output current is a value averaged during a 100 ms period. 21-14 32171 Group User's Manual (Rev.2.00) 21 21.2.3 DC Characteristics 21.2.3.1 Electrical Characteristics ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition MIN VOH Output High Voltage IOH -2mA VCCE+0.5 ×IOH(mA) Rated Value TYP MAX VCCE 0.225× IOL (mA) VCCI V 2.0 -5 -5 3.6 5 5 76 mA 76 See RAM retention power supply current characteristic graph Unit V VOL Output Low Voltage IOL 2mA 0 3.0 V VDD RAM Retention Power Supply Voltage High State Input Current Low State Input Current Power supply current when reset (Note 1) When operating When back-up VI=VCCE VI=0V f(XIN)=10.0MHz, When reset IIH IIL ICCres ICC µA µA Power supply current when operating f(XIN)=10.0MHz, (Note 1) When operating RAM Retention Power Supply Current Hysteresis (Note 2) RTDCLK, RTDRXD, SCLKI0,1, RXD0,1,2, TCLK3-0, TIN0,3,16-23, RESET, FP, MOD0,1, JTMS, JTRST, JTDI Hysteresis (Note 3) SBI, HREQ Ta=25oC Ta=85oC 132 50 1500 µA IDDhold VT+ — VT- VCCE=3.3V 0.65 V VT+ — VT- VCCE=3.3V 0.2 V Note 1: Total current when VCCE = AVCC = VREF= VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 2: All these pins except RESET serve dual-functions. __________ Note 3: The HREQ pin serves dual-functions. 21-15 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition MIN ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value TYP MAX 7 Unit f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ mA 120 20 50 35 2 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21-16 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (3) Electrical characteristics when f(XIN) = 8 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition MIN VOH Output High Voltage IOH -2mA VCCE+0.5 ×IOH(mA) Rated Value TYP MAX VCCE 0.225× IOL (ma) VCCI V 2.0 -5 -5 3.6 5 5 71 mA 61 See RAM retention power supply current characteristic graph Unit V VOL Output Low Voltage IOL 2mA 0 3.0 V VDD RAM Retention Power Supply Voltage High State Input Current Low State Input Current Power supply current when reset (Note 1) When operating When back-up VI=VCCE VI=0V f(XIN)=8.0MHz, When reset IIH IIL ICCres ICC µA µA Power supply current when operating f(XIN)=8.0MHz, (Note 1) When operating RAM Retention Power Supply Current Hysteresis (Note 2) RTDCLK, RTDRXD, SCLKI0,1, RXD0,1,2, TCLK3-0, TIN0,3,16-23, RESET, FP, MOD0,1, JTMS, JTRST, JTDI Hysteresis (Note 3) SBI, HREQ Ta=25oC Ta=125 C o 117 50 4000 µA IDDhold VT+ —VT- VCCE=3.3V 0.65 V VT+ —VT- VCCE=3.3V 0.2 V Note 1: Total current when VCCE = AVCC = VREF= VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 2: All these pins except RESET serve dual-functions. __________ Note 3: The HREQ pin serves dual-functions. 21-17 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (4) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition MIN ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value TYP MAX 7 Unit f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz mA 105 16 50 30 2 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21.2.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Condition MIN Ifvcc1 lfvcc2 Topr cycle tPRG tBERS FVCC Power Supply Current (when Programming) FVCC Power Supply Current (when Erasing) Flash Rewrite Ambient Temperature Rated Value TYP MAX 50 40 0 70 100 Unit mA mA o C Rewrite Durability Program Time Block Erase Time times ms ms 1 Page 1 Block 8 50 120 600 21-18 32171 Group User's Manual (Rev.2.00) 21 21.2.4 A-D Conversion Characteristics ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 3.3 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current (Note 2) 14950 ns 8650 -5 5 µA VREF=VCCE Rated Value TYP MAX 10 ±4 Bits LSB Unit IIAN Note 1: The absolute accuracy represents the accuracy of output code including all error sources (including quantization error) of the A-D converter relative to the analog input, and is obtained by the equation below: Absolute accuracy = output code – (analog input voltage ANi/ 1 LSB) When AVCC = VREF = 3.072 V, 1 LSB = 3 mV. Note 2: This referes to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 3.3 V, Ta = -40 to 125°C, f(XIN) = 8.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current (Note 2) 18687.5 ns 10812.5 -5 5 µA VREF=VCCE Rated Value TYP MAX 10 ±4 Bits LSB Unit IIAN Note 1: The absolute accuracy represents the accuracy of output code including all error sources (including quantization error) of the A-D converter relative to the analog input, and is obtained by the equation below: Absolute accuracy = output code – (analog input voltage ANi/ 1 LSB) When AVCC = VREF = 3.072 V, 1 LSB = 3 mV. Note 2: This referes to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. 21-19 32171 Group User's Manual (Rev.2.00) 21 21.3 AC Characteristics 21.3.1 Timing Requirements • • ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Unless otherwise noted, timing conditions are VCCE = 5 V ± 0.5 V or VCCE = 3.3 V ± 0.3 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF (however, 80 pF for JTAG-related). (1) Input/output ports Symbol Parameter Condition Rated Value MIN tsu(P-E) th(E-P) Port Input Setup Time Port Input Hold Time 100 0 MAX Unit See Figure 21.3.1 ns ns 1 2 (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Condition Rated Value MIN tsu(D-CLK) th(CLK-D) MAX Unit See Figure 21.3.2 ns ns RxD Input Setup Time RxD Input Hold Time 150 50 4 5 b) CSIO mode, with external clock selected Symbol Parameter Condition Rated Value MIN tc(CLK) tw(CLKH) tw(CLKL) tsu(D-CLK) th(CLK-D) MAX Unit See Figure 21.3.2 ns ns ns ns ns CLK Input Cycle Time CLK Input High Pulse Width CLK Input Low Pulse Width RxD Input Setup Time RxD Input Hold Time 640 300 300 60 100 7 8 9 10 11 (3) SBI Symbol Parameter Condition Rated Value MIN tw(SBIL) MAX Unit See Figure 21.3.3 ns SBI Input Pulse Width 5 tc(BCLK) 2 13 21-20 32171 Group User's Manual (Rev.2.00) 21 (4) TIN Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value MIN MAX Unit See Figure 21.3.5 ns tw(TIN) TIN Input Pulse Width 7 tc(BCLK) 2 14 (5) TCLK Symbol Parameter Condition Rated Value MIN tw(TCLKH) tw(TCLKL) TCLK Input High Pulse Width TCLK Input Low Pulse Width 7 tc(BCLK) 2 7 tc(BCLK) 2 MAX Unit See Figure 21.3.6 ns ns 99 100 (6) Read and write timing Symbol Parameter Condition Rated Value MIN tsu(D-BCLKH) th(BCLKH-D) Data Input Setup Time before BCLK Data Input Hold Time after BCLK 26 0 26 0 26 0 3 tc(BCLK) -23 2 Unit Figure 21.3.7 21.3.8 21.3.9 See MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 32 33 34 78 79 43 44 45 51 56 57 68 80 81 tsu(WAITL-BCLKH) WAIT Input Setup Time before BCLK th(BCLKH-WAITL) WAIT Input Hold Time after BCLK tsu(WAITH-BCLKH) WAIT Input Setup Time before BCLK th(BCLKH-WAITH) tw(RDL) tsu(D-RDH) th(RDH-D) tw(BLWL) tw(BHWL) td(RDH-BLWL) td(RDH-BHWL) td(BLWH-RDL) td(BHWH-RDL) tw(WRL) td(RDH-BLEL) td(RDH-BHEL) td(BLEH-RDL) td(BHEH-RDL) WAIT Input Hold Time after BCLK Read Low Pulse Width Data Input Setup Time before Read Data Input Hold Time after Read Write Low Pulse Width (Byte write mode) Write Delay Time after Read Read Delay Time after Write Write Low Pulse Width (Byte enable mode) Write Delay Time after Read (Byte enable mode) Read Delay Time after Write (Byte enable mode) 30 0 tc(BCLK) -25 tc(BCLK) 2 tc(BCLK) -10 -10 2 tc(BCLK) -25 tc(BCLK) 2 tc(BCLK) -10 -10 2 21-21 32171 Group User's Manual (Rev.2.00) 21 (7) Bus arbitration timing Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value MIN MAX Unit See Figure 21.3.10 ns ns tsu(HREQL-BCLKH) HREQ Input Setup Time before BCLK th(BCLKH-HREQL) HREQ Input Hold Time after BCLK 27 0 35 36 (8) Input transition time on JTAG pin Rated Value Symbol Condition MIN Other than JTRST pin MAX See Unit Figure 21.3.11 tr Input Rising Transition Time (JTCK,JTDI,JTMS,JTDO) When using TAP When not using TAP 10 ns 10 2 ns ms ns 58 JTRST pin Other than JTRST pin (JTCK,JTDI,JTMS,JTDO) 10 tf Input Falling Transition Time JTRST pin When using TAP When not using TAP 59 10 2 ns ms Note: • Stipulated values are guaranteed values when the test pin load capacitance CL=80pF. (9) JTAG interface timing Rated Value Symbol tc(JTCK) tw(JTCKH) tw(JTCKL) tsu(JTDI-JTCK) th(JTCK-JTDI) td(JTCK-JTDOV) td(JTCK-JTDOX) tW(JTRST) Condition MIN JTCK Input Cycle Time JTCK Input High Pulse Width JTCK Input Low Pulse Width JTDI, JTMS Input Setup Time JTDI, JTMS Input Hold Time JTDO Output Delay Time after JTCK Fall JTDO Output Hi-Z Delay Time after JTCK Fall TRST Input Low Pulse Width tc(JTCK) 100 40 40 15 20 40 40 MAX See Unit Figure 21.3.12 ns ns ns ns ns ns ns ns 60 61 62 63 64 65 66 67 Note: • Stipulated values are guaranteed values when the test pin load capacitance CL=80pF. 21-22 32171 Group User's Manual (Rev.2.00) 21 (10) RTD timing ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Rated Value Symbol Parameter MIN tc(RTDCLK) tw(RTDCLKH) tw(RTDCLKL) td(RTDCLKH-RTDACK) tv(RTDCLKL-RTDACK) td(RTDCLKH-RTDTXD) th(RTDCLKH-RTDRXD) tv(RTDRXD-RTDCLKL) MAX See Unit Figure 21.3.13 ns ns ns RTDCLK Input Cycle Time RTDCLK Input High Pulse Width RTDCLK Input Low Pulse Width RTDACK Delay Time after RTDCLK Input Valid RTDACK Time after RTDCLK input RTDTXD Delay Time after RTDCLK Input RTDRXD Input Hold Time RTDRXD Input Setup Time 500 230 230 160 160 tw(RTDCLKH)+160 50 60 90 83 84 85 86 87 88 89 ns ns ns ns ns 21-23 32171 Group User's Manual (Rev.2.00) 21 21.3.2 Switching Characteristics (1) Input/output ports Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value MIN MAX 100 Unit See Figure 21.3.1 ns td(E-P) Port Data Output Delay Time 3 (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Condition Rated Value MIN td(CLK-D) th(CLK-D) TxD Output Delay Time TxD Hold Time 0 MAX 60 Unit See Figure 21.3.2 ns ns 6 82 b) CSIO mode, with external clock selected Symbol Parameter Condition Rated Value MIN td(CLK-D) TxD Output Delay Time MAX 160 Unit See Figure 21.3.2 ns 12 (3) TO Symbol Parameter Condition Rated Value MIN td(BCLK-TO) TO Output Delay Time MAX 100 Unit See Figure 21.3.4 ns 15 21-24 32171 Group User's Manual (Rev.2.00) 21 (4) Read and write timing Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value MIN MAX tc(Xin) 2 tc(BCLK) -5 2 tc(BCLK) -5 2 Unit See Figure 21.3.7 21.3.8 21.3.9 tc(BCLK) tw(BCLKH) tw(BCLKL) td(BCLKH-A) td(BCLKH-CS) tv(BCLKH-A) tv(BCLKH-CS) td(BCLKL-RDL) tv(BCLKH-RDL) td(BCLKL-BLWL) td(BCLKL-BHWL) tv(BCLKL-BLWL) td(BCLKL-D) td(BCLKL-D) tv(BCLKH-D) tpzx(BCLKL-DZ) tpxz(BCLKH-DZ) td(A-RDL) td(CS-RDL) tv(RDH-A) tv(RDH-CS) tpzx(RDH-DZ) td(A-BLWL) td(A-BHWL) td(CS-BLWL) td(CS-BHWL) tv(BLWH-A) tv(BHWH-A) tv(BLWH-CS) tv(BHWH-CS) BCLK Output Cycle Time BCLK Output High Pulse Width BCLK Output Low Pulse Width Address Delay Time after BCLK Chip Select Delay Time after BCLK Valid Address Time after BCLK Valid Chip Select Time after BCLK Read Delay Time after BCLK Valid Read Time after BCLK Write Delay Time after BCLK Valid Write Time after BCLK Data Output Delay Time after BCLK Valid Data Output Time after BCLK Data Output Enable Time after BCLK Data Output Disable Time after BCLK Address Delay Time before Read Chip Select Delay Time before Read Valid Address Time after Read Valid Chip Select Time after Read Data Output Enable Time after Read Address Delay Time before Write (Byte write mode) Chip Select Delay Time before Write (Byte write mode) Valid Address Time after Write (Byte write mode) Valid Chip Select Time after Write (Byte write mode) tc(BCLK) -15 2 tc(BCLK) -15 2 ns ns ns 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 39 40 41 42 46 47 48 49 50 24 24 -11 -11 10 -12 11 -12 18 -16 -19 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0 tc(BCLK) 2 tc(BCLK) -15 2 tc(BCLK) -15 2 tc(BCLK) -15 2 tc(BCLK) -15 2 ns ns ns 21-25 32171 Group User's Manual (Rev.2.00) 21 Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Read and write timing (continued from the preceding page) Condition Rated Value MIN td(BLWL-D) td(BHWL-D) tv(BLWH-D) tv(BHWH-D) tpxz(BLWH-DZ) tpxz(BHWH-DZ) td(A-WRL) td(CS-WRL) tv(WRH-A) tv(WRH-CS) td(BLE-WRL) td(BHE-WRL) tv(WRH-BLE) tv(WRH-BHE) td(WRL-D) Data Output Delay Time after Write (Byte write mode) Valid Data Output Time after Write (Byte write mode) Data Output Disable Time after Write (Byte write mode) Address Delay Time before Write (Byte enable mode) Chip Select Delay Time before Write (Byte enable mode) Valid Address Time after Write (Byte enable mode) Valid Chip Select Time after Write (Byte enable mode) Byte Enable Delay Time before Write (Byte enable mode) Valid Byte Enable Time after Write (Byte enable mode) Data Output Delay Time after Write (Byte enable mode) Valid Data Output Time after Write (Byte enable mode) Data Output Disable Time after Write (Byte enable mode) Read High-level Pulse Width tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 Unit Figure 21.3.7 21.3.8 21.3.9 See MAX 15 -13 tc(BCLK) 2 ns ns +5 ns ns ns ns ns ns ns 52 53 54 69 70 71 72 73 74 75 76 77 55 -15 -15 -15 -15 -15 -15 15 -13 tc(BCLK) 2 ns ns +5 ns tv(WRH-D) tpxz(WRH-DZ) tw(RDH) -3 ns (5) Bus arbitration Symbol Parameter Condition Rated Value MIN td(BCLKL-HACKL) tv(BCLKL-HACKL) HACK Delay Time after BCLK Valid HACK Time after BCLK -11 MAX 29 Unit See Figure 21.3.10 ns ns 37 38 21-26 32171 Group User's Manual (Rev.2.00) 21 21.3.3 AC Characteristics ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 0.8VCCE BCLK 1 Port input tsu(P-E) 2 th(E-P) 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE 3 td(E-P) 0.8VCCE 0.2VCCE Port output Figure 21.3.1 Input/Output Port Timing a) CSIO mode, with internal clock selected CLKOUT 6 td(CLK-D) 0.8VCCE 0.2VCCE 82 th(CLK-D) 0.8VCCE 0.2VCCE TxD 4 tsu(D-CLK) 5 th(CLK-D) 0.8VCCE 0.2VCCE RxD 0.8VCCE 0.2VCCE b) CSIO mode, with external clock selected 7 tc(CLK) 8 tw(CLKH) CLKIN 12 td(CLK-D) 0.8VCCE 0.2VCCE 9 tw(CLKL) 0.8VCCE 0.2VCCE TxD 10 tsu(D-CLK) 11 th(CLK-D) 0.8VCCE 0.2VCCE RxD 0.8VCCE 0.2VCCE Figure 21.3.2 Serial I/O Timing 21-27 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics SBI 0.2VCCE 0.2VCCE 13 tw(SBIL) Figure 21.3.3 SBI Timing BCLK 0.2VCCE 15 td(BCLK-TO) 0.8VCCE 0.2VCCE TO Figure 21.3.4 TO Timing 14 tw(TIN) 0.8VCCE 0.2VCCE TIN 0.8VCCE 0.2VCCE Figure 21.3.5 TIN Timing 99 tw(TCLKH) 0.8VCCE TCLK 0.2VCCE 100 tw(TCLKL) Figure 21.3.6 TCLK Timing 21-28 32171 Group User's Manual (Rev.2.00) 21 16 tc(BCLK) ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 17 tw(BCLKH) 18 tw(BCLKL) BCLK 0.43VCCE 0.16VCCE 20 td(BCLKH-CS) 19 td(BCLKH-A) 23 td(BCLKL-RDL) 22 tv(BCLKH-CS) 21 tv(BCLKH-A) 0.43VCCE 0.16VCCE Address (A12-A30) CS0, CS1 0.43VCCE 0.16VCCE 40 td(CS-RDL) 39 td(A-RDL) 43 tw(RDL) 41 tv(RDH-A) 42 tv(RDH-CS) RD 0.43VCCE 0.43VCCE 55 tw(RDH) 0.16VCCE 0.16VCCE 24 tv(BCLKH-RDL) 45 th(RDH-D) 0.43VCCE 0.16VCCE 44 tsu(D-RDH) Data input (D0 - D15) 0.43VCCE 0.16VCCE 31 tsu(D-BCLKH) 57 td(BHWH-RDL) td(BLWH-RDL) 32 th(BCLKH-D) 56 td(RDH-BLWL) td(RDH-BHWL) BLW BHW 0.43VCCE 0.16VCCE 29 tpzx(BCLKL-DZ) 30 tpxz(BCLKH-DZ) 46 tpzx(RDH-DZ) Data output (D0 - D15) 78 tsu(WAITH-BCLKH) 33 tsu(WAITL-BCLKH) 34 th(BCLKH-WAITL) 0.43VCCE 0.16VCCE 79 th(BCLKH-WAITH) WAIT 0.43VCCE 0.16VCCE 0.43VCCE Notes: • Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. • Input and output signals are determined high or low with respect to TTL level. Figure 21.3.7 Read Timing 21-29 32171 Group User's Manual (Rev.2.00) 21 16 tc(BCLK) ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 17 tw(BCLKH) 18 tw(BCLKL) BCLK 0.43VCCE 0.16VCCE 0.16VCCE 20 td(BCLKH-CS) 19 td(BCLKH-A) 22 tv(BCLKH-CS) 21 tv(BCLKH-A) 0.43VCCE 0.16VCCE Address (A12-A30) CS0, CS1 0.43VCCE 0.16VCCE 56 td(RDH-BHWL) td(RDH-BLWL) 23 td(BCLKL-RDL) RD 0.43VCCE 0.16VCCE tv(BCLKL-BLWL) 26 tv(BCLKL-BHWL) td(CS-BLWL) 48 td(CS-BHWL) td(BLWH-RDL) 47 td(A-BLWL) td(A-BHWL) tw(BLWL) 51 tw(BHWL) 57 td(BHWH-RDL) BLW BHW 25 td(BCLKL-BLWL) td(BCLKL-BHWL) 0.16VCCE 0.43VCCE 50 tv(BHWH-CS) 49 tv(BHWH-A) tpxz(BLWH-DZ) tv(BLWH-A) tv(BLWH-CS) 54 tpxz(BHWH-DZ) 52 td(BHWL-D) td(BLWL-D) 53 tv(BHWH-D) 28 tv(BCLKH-D) tv(BLWH-D) 27 td(BCLKL-D) Data output (D0 - D15) 0.43VCCE 0.16VCCE 29 tpzx(BCLKL-DZ) 30 tpxz(BCLKH-DZ) 78 tsu(WAITH-BCLKH) 0.43VCCE 0.16VCCE 79 th(BCLKH-WAITH) WAIT 33 tsu(WAITL-BCLKH) 34 th(BCLKH-WAITL) Notes: • Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. • Input and output signals are determined high or low with respect to TTL level. Figure 21.3.8 Write Timing 21-30 32171 Group User's Manual (Rev.2.00) 21 Address (A12-A30) CS0, CS1 0.43VCCE 0.16VCCE ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 0.43VCCE 0.16VCCE 80 td(RDH-BHEL) 0.43VCCE td(RDH-BLEL) 81 td(BHEH-RDL) td(BLEH-RDL) RD 0.16VCCE 70 td(CS-WRL) 69 td(A-WRL) 68 tw(WRL) 72 tv(WRH-CS) 71 tv(WRH-A) WR 0.16VCCE 0.16VCCE 0.43VCCE 73 td(BHEL-WRL) td(BLEL-WRL) tv(WRH-BLEL) 74 tv(WRH-BHEL) 0.43VCCE BLE , BHE 0.16VCCE 0.16VCCE 75 td(WRL-D) 77 tpxz(WRH-DZ) 76 tv(WRH-D) Data output (D0-D15) 0.43VCCE 0.16VCCE Notes: • Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. • Input and output signals are determined high or low with respect to TTL level. Figure 21.3.9 Write Timing (Byte enable mode) BCLK 0.43VCCE 0.16VCCE 35 tsu(HREQL-BCLKH) HREQ 0.16VCCE 0.16VCCE 36 th(BCLKH-HREQL) 38 tv(BCLKL-HACKL) HACK 0.16VCCE 0.16VCCE 37 td(BCLKL-HACKL) Figure 21.3.10 Bus Arbitration Timing 21-31 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 58 tr JTCK,JTDI JTMS,JTRST 0.8VCCE 0.2VCCE 59 tf 0.8VCCE 0.2VCCE Note: • Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 21.3.11 Input Transition Time on JTAG pins 60 tc(JTCK) 61 tw(JTCKH) 62 tw(JTCKL) JTCK 0.5VCCE 63 tsu(JTDI-JTCK) 64 th(JTCK-JTDI) 0.8VCCE 0.2VCCE Data input, (JTDI) JTMS 0.8VCCE 0.2VCCE 65 td(JTCK-JTDOV) 66 td(JTCK-JTDOX) 0.8VCCE 0.2VCCE Data output, (JTDO) 0.8VCCE 0.2VCCE 67 tw(JTRST) JTRST 0.2VCCE 0.2VCCE Note: • Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 21.3.12 JTAG Interface Timing 21-32 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 90 83 tc(RTDCLK) 84 tw(RTDCLKL) 0.5VCCE 0.5VCCE 0.5VCCE tw(RTDCLKH) RTDCLK 0.5VCCE 85 RTDACK td(RTDCLKH-RTDACK) 86 tv(RTDCLKH-RTDACK) 0.8VCCE 0.2VCCE 87 td(RTDCLKH-RTDTXD) RTDTXD 0.8VCCE 0.2VCCE 88 RTDRXD th(RTDCLKH-RTDRXD) 89 tsu(RTDRXD-RTDCLKL) 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE Figure 21.3.13 RTD Timing 21-33 32171 Group User's Manual (Rev.2.00) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics * This is a blank page.* 21-34 32171 Group User's Manual (Rev.2.00) CHAPTER C HAPTER 22 TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics 22 22.1 A-D Conversion Characteristics (1) Test conditions • Ta = -40°C, 27°C, 125°C • Test voltage (VCC) = 5.12 V • Normal mode, Double-speed mode TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics (2) Measured value (Reference value) Ta = -40°C Ta = 27°C Ta = 125°C Vertical axis : Conversion error (LSB) Horizontal axis : Analog input voltage ( 5.12 × N/1024 [V] ) 22-2 32171 Group User's Manual (Rev.2.00) APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing Appendix 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing Appendix 1.1 Dimensional Outline Drawing (1) 144 pin LQFP 144P6Q-A EIAJ Package Code LQFP144-P-2020-0.50 HD JEDEC Code – Weight(g) Lead Material Cu Alloy Plastic 144pin 20✕20mm body LQFP MD 144 109 1 108 b2 l2 Recommended Mount Pad Dimension in Millimeters Max Nom Min 1.7 – – 0.125 0.2 0.05 – 1.4 – 0.27 0.22 0.17 0.175 0.125 0.105 20.1 20.0 19.9 20.1 20.0 19.9 0.5 – – 22.2 22.0 21.8 22.2 22.0 21.8 0.65 0.5 0.35 1.0 – – 0.1 – – 8° 0° – – 0.225 – – – 1.0 – 20.4 – – 20.4 – HE E Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 36 73 37 72 A F L1 A2 e b y Detail F A1 L Appendix 1-2 32171 Group User's Manual (Rev.2.00) c ME D e APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time Appendix 2.1 M32R/ECU Instruction Processing Time For the M32R/ECU, the number of instruction execution cycles in E stage normally represents its instruction processing time. However, depending on pipeline operation, other stages may affect the instruction processing time. Especially when a branch instruction is executed, the processing time in the IF (instruction fetch), D (decode) and E (execution) stages of the next instruction must also be taken into account. The table below shows the instruction processing time in each pipelined stage of the M32R/ECU. Table 2.1.1 Instruction Processing Time of Each Pipeline Stage Number of execution cycles in each stage (Note 1) Instruction Load instructions (LD, LDB, LDUB, LDH, LDUH, LOCK) Store instructions (ST,STB,STH,UNLOCK) Multiply instruction (MUL) Divide/remainder instructions (DIV, DIVU,REM,REMU) Other instructions (including those for DSP function) IF R R R R R D 1 1 1 1 1 E 1 1 3 37 1 MEM R W WB 1 1 1 1 Note 1: For R and W, refer to the calculation methods described in the next page. Appendix 2-2 32171 Group User's Manual (Rev.2.00) Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time The following shows the number of memory access cycles in IF and MEM stages. Shown here are the minimum number of cycles required for memory access. Therefore, these values do not always reflect the number of cycles required for actual memory or bus access. In write access, for example, although the CPU finishes the MEM stage by only writing to the write buffer, this operation actually is followed by a write to memory. Depending on the memory or bus state before or after the CPU requested a memory access, the instruction processing may take more time than the calculated value. s R (read cycle) Cycles When existing in instruction queue ............................................................................. 1 When reading internal resource (ROM, RAM) ........................................................... 1 When reading internal resource (SFR)(byte, halfword) .............................................. 2 When reading internal resource (SFR)(word) ............................................................ 4 When reading external memory (byte, halfword) ....................................................... 5 (Note 1) When reading external memory (word) ...................................................................... 9 (Note 1) When successively fetching instructions from external memory ................................ 8 (Note 1) s W (write cycle) Cycles When writing to internal resource (RAM) ................................................................... 1 When writing to internal resource (SFR)(byte, halfword) ........................................... 2 When writing to internal resource (SFR)(word) .......................................................... 4 When writing to external memory (byte, halfword) ..................................................... 4 (Note 1) When writing to external memory (word) .................................................................... 8 (Note 1) Note 1: This applies for external access with one wait cycle. (When the M32R/ECU accesses external circuits, it requires at least one wait cycle inserted.) Appendix 2-3 32171 Group User's Manual (Rev.2.00) Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time ❊ This is a blank page. ❊ Appendix 2-4 32171 Group User's Manual (Rev.2.00) APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example for Processing Unused Pins Appendix 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example for Processing Unused Pins Appendix 3.1 Example for Processing Unused Pins An example for processing unused pins is shown below. (1) When operating in single-chip mode Table A3.1.1 Example for Processing Unused Pins when Operating in Single-chip Mode Pin name Input/output ports (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, P61-P63, P70-P77, P82-P87, P93-P97, P100-P107, P110-P117, P124-P127, P130-P137, P150, P153, P174, P175, P220, P221, P225 (Note 2) P64 / SBI (Note 3) XOUT (Note 4) A-D converter AD0IN0-AD0IN15, AVREF0, AVSS0 AVCC0 JTAG JTDO, JTMS, JTDI, JTCK JTRST Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Connect this pin to VSS (pulldown) via a 0 to 100 kΩ resistor. Connect these pins to VSS. Connect this pin to VCCE. Processing Set these pins for input mode and connect them to VSS via 1 kΩ to 10 kΩ resistors (pulldown). Connect this pin to VSS (pulldown) via a 1 to 10 kΩ resistor. Leave these pins open. Note 1: After exiting reset, the input/output ports are set for input by default. Note 2: P221 is used exclusively for CAN input. ___ Note 3: P64 is used exclusively for SBI input. Make sure that unintended falling edges due to noise, etc. will ___ not be applied. (A falling edge at P64/SBI pin causes a system break interrupt to occur). Note 4: This applies when an external clock is fed to XIN. Appendix 3-2 32171 Group User's Manual (Rev.2.00) Appendix 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example for Processing Unused Pins (2) When operating in external extension mode or processor mode Table A3.1.2 Example for Processing Unused Pins when Operating in External Extension or Processor Mode Pin name Input/output ports (Note 1) P61-P63, P70-P77, P82-P87, P93-P97, P100-P107, P110-P117, P124-P127, P130-P137, P150, P153, P174, P175, P220, P221, P225 (Note 2) P64 / SBI (Note 3) BLW/BLE, BHW/BHE, CS1 XOUT (Note 4) A-D converter AD0IN0-AD0IN15, AVREF0, AVSS0 AVCC0 JTAG JTDO, JTMS, JTDI, JTCK JTRST Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Connect this pin to VSS (pulldown) via a 0 to 100 kΩ resistor. Connect these pins to VSS. Connect these pins to VCCE. Processing Set these pins for input mode and connect them to VSS via 1 kΩ to 10 kΩ resistors (pulldown). Connect this pin to VSS (pulldown) via a 1 to 10 kΩ resistor. Leave these pins open. Leave these pins open. Note 1: After exiting reset, the input/output ports are set for input by default. Note 2: P221 is used exclusively for CAN input. ___ Note 3: P64 is used exclusively for SBI input. Make sure that unintended falling edges due to noise, etc. will ___ not be applied. (A falling edge at P64/SBI pin causes a system break interrupt to occur). Note 4: This applies when an external clock is fed to XIN. Appendix 3-3 32171 Group User's Manual (Rev.2.00) Appendix 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example for Processing Unused Pins * This is a blank page. * Appendix 3-4 32171 Group User's Manual (Rev.2.00) APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions Regarding the CPU Appendix 4.2 Precautions on Address Space Appendix 4.3 Precautions on EIT Appendix 4.4 Precautions to Be Taken When Reprogramming Flash Memory Appendix 4.5 Things To Be Considered after Exiting Reset Appendix 4.6 Precautions on Input/output Ports Appendix 4.7 Precautions about the DMAC Appendix 4.8 Precautions on Multijunction Timers Appendix 4.9 Precautions on Using A-D Converters Appendix 4.10 Precautions on Serial I/O Appendix 4.11 Precautions on RAM Backup Mode Appendix 4.12 Precautions on Processing JTAG Pins Appendix 4.13 Precautions about Noise Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions Regarding the CPU Appendix 4.1 Precautions Regarding the CPU Appendix 4.1.1 Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Data in register (R0 - R15) +0 HL LH LL D31 HH D0 Data in memory +1 HL +2 LH +3 LL D31 Word data (32 bits) D0 HH MSB (R0 - R15) LSB MSB +0 +1 L D15 +2 LSB +3 Half-word data (16 bits) D0 H L D31 D0 H MSB (R0 - R15) LSB MSB +0 LSB +1 +2 +3 Byte data (8 bits) D0 D31 D0 D7 MSB LSB MSB LSB Figure A4.1.1 Difference in Data Arrangements Appendix 4.2 Precautions on Address Space Appendix 4.2.1 Virtual flash emulation function The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can map up to two 4-Kbyte blocks of internal RAM beginning with address H’0080 6000 into one of 4-Kbyte areas (S banks) of the internal flash memory. This capability is referred to as the “virtual-flash emulation” function. For details about this function, refer to Section 6.7, “Virtual-Flash Emulation Function.” Appendix 4-2 32171 Group User's Manual (Rev.2.00) Appendix 4 Appendix 4.3 Precautions on EIT SUMMARY OF PRECAUTIONS Appendix 4.3 Precautions on EIT Address Exception requires caution because when an address exception occurs pursuant to execution of an instruction (one of the following three) that uses the “register indirect + register update” addressing mode, the value of the automatically updated register (Rsrc or Rsrc2) becomes indeterminate. Except that the values of Rsrc and Rsrc2 are indeterminate, the behavior is the same as when using other addressing modes. • Applicable instructions LD ST ST Rdest, @Rsrc+ Rsrc1, @-Rsrc2 Rsrc1, @+Rsrc2 If the above applies, because the register value becomes indeterminate as explained, consideration must be taken before continuing with system processing. (If an address exception occurs, it means that some fatal fault already occurred in the system at that point in time. Therefore, use EIT on condition that after processing by the address exception handler, the CPU will not return to the program it was executing when the exception occurred.) Appendix 4.4 Precautions to Be Taken When Reprogramming Flash Memory The following describes precautions to be taken when you reprogram the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. • When reprogramming the flash memory, a high voltage is generated inside the chip. Because this high voltage could cause the chip to break down, be careful about mode pin and power supply management not to move from one mode to another while reprogramming. • If the system uses any pin that is to be used by a general-purpose reprogramming tool, take appropriate measures to prevent adverse effects when connecting the tool. • If flash memory protection is needed when using a general-purpose reprogramming tool, set any ID in the flash memory protect ID check area (H’0000 0084–H’0000 0093). • If flash memory protection is not needed when using a general-purpose reprogramming tool, set H’FF in the entire flash memory protect ID check area (H’0000 0084–H’0000 0093). • Before using a reset by Flash Control Register 4 (FCNT4)’s FRESET bit to clear each error status in Flash Status Register 2 (FSTAT2) (initialized to H’80), check to see that Flash Status Register 1 (FSTAT1)’s FSTAT bit = 1 (Ready). Appendix 4-3 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.5 Things To Be Considered after Exiting Reset • Before changing Flash Control Register 1 (FCNT1)’s FENTRY bit from 1 to 0, check to see that Flash Status Register 1 (FSTAT1)’s FSTAT bit = 1 (Ready) or Flash Status Register 2 (FSTAT2)’s FBUSY bit = 1 (Ready). • If Flash Control Register 1 (FCNT1)’s FENTRY bit = 1 and Flash Status Register 1 (FSTAT1)’s FSTAT bit = 0 (Busy) or Flash Status Register 2 (FSTAT2)’s FBUSY bit = 0 (Busy), do not clear the FENTRY bit. Appendix 4.5 Things To Be Considered after Exiting Reset Appendix 4.5.1 Input/output ports After exiting reset, the 32171's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit. For details, refer to Section 8.3, "Input/ Output Port Related Registers." Appendix 4.6 Precautions on Input/output Ports Appendix 4.6.1 When using the ports in output mode Because the Port Data Register values immediately after reset are indeterminate, it is necessary that the initial value be written to the Port Data Register before setting the Port Direction Register for output. Conversely, if the Port Direction Register is set for output before writing to the Port Data Register, indeterminate values will be output for a while until the initial value is set in the Port Data Register. Appendix 4-4 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.7 Precautions about the DMAC Appendix 4.7 Precautions about the DMAC Appendix 4.7.1 About writing to DMAC related registers Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). When transfer is enabled, do not write to the DMAC related registers because write operation to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer Count Register which is protected in hardware, is instable. The table below shows the registers that can or cannot be accessed for write. Table A4.7.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status When transfer is enabled When transfer is disabled : Can be accessed ; ✕ : Cannot be accessed Transfer enable bit Transfer request flag Other DMAC related registers ✕ For even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. (1) DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. Note that you only can write a 0 to the transfer request flag as valid data. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case, you are writing to the DMAC related registers while DMA is enabled, but this practically does not present any problem. However, you cannot DMA-transfer to the DMAC related registers on the local channel itself in which you are currently operating. Appendix 4-5 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.7 Precautions about the DMAC Appendix 4.7.2 Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) Only if residing on other channels, you can write to the DMAC related registers by means of DMA transfer. (For example, you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0.) Appendix 4.7.3 About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write 1s to all bits but the one you want to clear. The bits to which you wrote 1s retain the previous data they had before the write. Appendix 4.7.4 About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the DMA Channel Control Register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another. Appendix 4-6 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.1 Precautions to be observed when using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Write to enable bit Internal clock Prescaler cycle Count clock Enable Delay till prescaler cycle F/F operation Figure A4.8.1 Prescaler Delay • When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. In the example below, the reload register has the initial value H'FFF8 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'0014 is written to the correction register when the counter has counted down to H'FFF0. As a result of this correction, the count overflows to H'0004 and fails to count correctly. Also, an interrupt is generated for an erroneous overcount. Appendix 4-7 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit Write to correction register Overflow occurs H'(FFF0+0014) H'FFFF H'FFF8 Indeterminate H'FFF0 Counter H'FFFF H'0004 H'0000 Actual count after overflow Reload register H'FFF8 Correction register Indeterminate H'0014 F/F output Data inverted by enable Data inverted by underflow TOP interrupt due to underflow Note: • This diagram does not show detail timing information. Figure A4.8.2 Example of Operation in TOP Single-shot Output Mode Where Count Overflows due to Correction Appendix 4-8 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.2 Precautions to be observed when using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. Reload due to underflow Count clock Enable bit "H" Reload cycle Down-count starting from reloaded register value H'AAA9 H'(AAAA-1) H'AAA8 H'(AAAA-2) Counter value H'0001 H'0000 H'FFFF Reload register H'AAAA During reload cycle, you always see H'FFFF, and not the reload register value (in this case, H'AAAA). Figure A4.8.3 Counter Value Immediately after Underflow Appendix 4-9 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.3 Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Write to enable bit Internal clock Prescaler cycle Count clock Enable F/F operation Delay till prescaler cycle Figure A4.8.4 Prescaler Delay Appendix 4-10 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.4 Precautions to be observed when using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched into the measure register. Appendix 4.8.5 Precautions to be observed when using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Appendix 4.8.6 Precautions to be observed when using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Appendix 4-11 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.7 Precautions to be observed when using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Appendix 4.8.8 Precautions to be observed when using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched to the measure register. Appendix 4-12 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.8 Precautions on Multijunction Timers Appendix 4.8.9 Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched to the measure register. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the counter cannot be written normally. Therefore, when operating with any clock other than the 1/2 internal peripheral clock, do not write to the counter. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the captured value is one that leads the actual counter value by one clock period. However, during the 1/2 internal peripheral clock interval from the count clock, this problem does not occur and the counter value is captured at exact timing. The diagram below shows the relationship between counter operation and the valid data that can be captured. When 1/2 internal peripheral clock is selected 1/2 internal peripheral clock Counter A B C D E F Capture A B C D E F When clock bus 1 is selected 1/2 internal peripheral clock Count clock Counter A B C Capture B C D Figure A4.8.5 Mistimed Counter Value and Captured Value Appendix 4-13 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.9 Precautions on Using A-D Converters Appendix 4.9 Precautions on Using A-D Converters • Forcible termination during scan operation If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP) to 1 during scan mode operation and you read the content of the A-D data register for the channel in which conversion was in progress, it shows the last conversion result that had been transferred to the A-D data register before the conversion was forcibly terminated. • Modification of A-D converter related registers If you want to change the contents of the A-D Conversion Interrupt Control Register, each Single and Scan Mode Register, or A-D Successive Approximation Register, except for the AD conversion stop bit, do your change while A-D conversion is inactive, or be sure to restart AD conversion after you changed the register contents. If the contents of these registers are changed in the middle of A-D conversion, the conversion results cannot be guaranteed. • Handling of analog input signals The A-D converters included in the 32171 do not have a sample-and-hold circuit. Therefore, make sure the analog input levels are fixed during A-D conversion. • A-D conversion completion bit readout timing If you want to read the A-D conversion completion bit (Single Mode Register 0's D5 bit or Scan Mode Register 0's D5 bit) immediately after A-D conversion has started, be sure to adjust the timing one clock cycle by, for example, inserting a NOP instruction before you read. • Rated value of absolute accuracy The rated value of absolute accuracy is that of the microcomputer alone, premised on an assumption that power supply wiring on the board where the microcomputer is mounted is stable and unaffected by noise. When designing the board, pay careful attention to its layout by, for example, separating AVCC0, AVSS0, and VREF0 from other digital power supplies or protecting the analog input pins against noise from other digital signals. Appendix 4-14 32171 Group User's Manual (Rev.2.00) Appendix 4 • Regarding the analog input pins SUMMARY OF PRECAUTIONS Appendix 4.9 Precautions on Using A-D Converters Figure A4.9.1 shows an internal equivalent circuit of the analog input unit. To obtain exact A-D conversion results, it is necessary that the A-D conversion circuit finishes charging its internal capacitor C2 within a designated time (sampling time). To meet this sampling time requirement, we recommend connecting a stabilizing capacitor, C1, external to the chip. The following shows the analog output device’s output impedance and how to determine the value of the external stabilizing capacitor to meet this timing requirement. Also shown below is the case where the analog output device’s output impedance is low and the external stabilizing capacitor C1 is unnecessary. Inside the microcomputer 10-bit AD successive Approximation Register (ADiSAR) VREF Analog Output Device 10-bit DA Converter V2 C2 ADIN n R1 E i→ C1 i1 i2 → Cin R2 Selector Comparator C1: Board's parasitic capacitance + stabilizing C VREF: Analog reference voltage C2: Comparator capacitance (approx. 2.9 pF) Cin: Input pin capacitance (approx. 10pF) Figure A4.9.1 Internal Equivalent Circuit of the Analog Input Unit (a) Example for calculating the value of an external stabilizing capacitor C1 (recommended) In Figure A4.9.1, as we calculate the capacitance of C1, we assume R1 is infinitely large, that the current needed to charge the internal capacitor C2 is sourced from C1, and that the voltage fluctuation due to C1 and C2 capacitance divisions, Vp, is 0.1 LSB or less. For the10-bit A-D converter where VREF is 5.12 V, the 1 LSB determination voltage = 5.12 V / 1024 = 5 mV. With up to 0.1 LSB voltage fluctuations considered, this equals 0.5 mV fluctuation. → R2: Selector's parastic resistance (1 - 2 kΩ) R1: Analog output device's resistance V2: Voltage across C2 E: Analog output device's voltage Appendix 4-15 32171 Group User's Manual (Rev.2.00) Appendix 4 equation: Vp = C2 C1 + C2 ✕ (E - V2) SUMMARY OF PRECAUTIONS Appendix 4.9 Precautions on Using A-D Converters The relationship between C1 and C2 capacitance divisions and Vp is obtained by the Eq. (A-1) Also, Vp is obtained by the equation: x-1 Vp = Vp1 ✕ i=0 1 2i < VREF 10 x 2 x Eq. (A-2) Notes: • Where Vp1 = voltage fluctuation in first A-D conversion. • The exponent x is 10 because of a 10-bit resolution A-D converter. When Eqs. (A-1) and (A-2) are solved, C1 = C2 E - V2 Vp1 -1 x-1 i=0 1 -1 2i Eq. (A-3) Eq. (A-4) C1 > C2 10 ✕ 2 x ✕ Thus, for 10-bit resolution A-D converters where C2 = 2.9 pF, C1 is 0.06 µF or greater. Use this for reference when determining the value of C1. (b) Maximum value of the output impedance R1 when not adding C1 In Figure A4.9.1, if the external capacitor C1 is not used, examination must be made of whether C2 can be fully charged. First, the following shows the equation to find i2 when C1 is nonexistent in Figure A4.9.1. i2 = C2 (E - V2) -t ✕ exp Cin x R1 ✕ C2 (R1 + R2) Cin ✕ R1 + C2 (R1 + R2) Eq. (B-1) 1 bit conversion time ADIN i Sampling time Comparison time Repeated for 10 bits (10 times) Figure A4.9.2 A-D Conversion Timing Diagram Appendix 4-16 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.9 Precautions on Using A-D Converters The time needed for charging C2 must be within the sampling time (in Figure A4.9.2, A-D Conversion Timing Diagram) divided by 2. Assuming t = T (time needed for charging C2) T= A-D conversion time Sampling time = 2 10 ✕ 4 Therefore, from Eq. (B-1), the time needed for charging C2 is T = (time needed for charging C2) > Cin ✕ R1 + C2 (R1 + R2) Eq. (B-2) Thus, the maximum value of R1 as an approximate guide can be obtained by the equation: R1 < A-D conversion time - C2 ✕ R2 10 ✕ 4 Cin + C2 Eq. (B-3) The table below shows an example of how to calculate the maximum value of R1 during AD conversion mode when Xin = 10 and 8 MHz. Xin BCLK period Conversion mode A-D conversion mode/Single 8MHz 62.5ns A-D conversion mode/Single Speed mode Normal Double speed Normal Double speed Conversion cycles 294 168 294 168 T (C2 charging time) in ns 367 210 459 262 Maximum value of R1 (Ω) 28,225 16,054 35,357 20,085 10MHz 50ns Note: • T he above conversion cycles do not include dummy cycles at the start and end of conversion. In comparate mode, because sampling and comparison each are performed only once, the maximum value of R1 can be derived from the equation R1 > A-D conversion time - C2 ✕ R2 4 Cin + C2 Eq. (B-4) The table below shows an example of how to calculate the maximum value of R1 during comparate mode when Xin = 10 and 8 MHz. Xin BCLK period Conversion mode Speed mode Conversion cycles 42 24 42 24 T (C2 charging time) in ns 525 300 656 375 Maximum value of R1 (Ω) 40,473 23,031 50,628 28,845 10MHz 50ns comparate mode Normal /Single Double speed 8MHz 62.5ns comparate mode Normal /Single Double speed Note: • T he above conversion cycles do not include dummy cycles at the start and end of conversion. Appendix 4-17 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.10 Precautions on Serial I/O Appendix 4.10 Precautions on Serial I/O Appendix 4.10.1 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers. • Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set does not exceed 2 Mbps. • About successive transmission To transmit multiple data successively, set the next transmit data in the SIO Transmit Buffer Register before transmission of the preceding data is completed. • About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation (by sending dummy data) even when you only want to receive data. In this case, note that if the port function is set for TXD pin (by setting the operation mode register to 1), dummy data is actually output from the pin. • About successive reception To receive multiple data successively, set data (dummy data) in the SIO Transmit Buffer Register before the transmitter starts sending data. • Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication. • About the receive-finished bit If a receive error (overrun error) occurs, the receive-finished bit cannot be cleared by reading out the receive buffer register. In this case, it can only be cleared by clearing the receive enable bit. Appendix 4-18 32171 Group User's Manual (Rev.2.00) Appendix 4 • About overrun error SUMMARY OF PRECAUTIONS Appendix 4.10 Precautions on Serial I/O If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Thereafter, although receive operation is continued, no receive data is stored in the Receive Buffer Register (the receive status bit = 1). To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag. • About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty (the transmit buffer empty flag = 1) while the transmit enable bit is set to 1 (transmit enabled), an SIO transmit buffer empty DMA transfer request is generated. • About DMA transfer request generation during SIO reception When the receive-finished bit is set to 1 (the receive buffer register full), a receive-finished DMA transfer request is generated. However, if an overrun error has occurred, this DMA transfer request is not generated. Appendix 4-19 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.10 Precautions on Serial I/O Appendix 4.10.2 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers. • Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set is equal to or greater than 7. The value written to the SIO Baud Rate Register becomes effective beginning with the next period after the BRG counter finished counting. However, when transmit and receive operations are disabled, the register value can be changed at the same time you write to the register. • Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication. • About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Once an overrun error occurs, no receive data is stored in the Receive Buffer Register although receive operation is continued. To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag. • Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit • SIO Receive Control Register receive error sum bit • SIO Receive Control Register overrun error bit • SIO Receive Control Register parity error bit • SIO Receive Control Register framing error bit The manner in which the receive-finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not, as described below. [When no overrun error has occurred] Said bits can be cleared by reading the lower byte from the receive buffer register or clearing the receive enable bit to 0. [When an overrun error has occurred] Said bits can only be cleared by clearing the receive enable bit to 0. Appendix 4-20 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.11 Precautions on RAM Backup Mode Appendix 4.11 Precautions on RAM Backup Mode Appendix 4.11.1 Precautions to Be Observed at Power-on When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port's initial output level is indeterminate. Therefore, be sure to set the output high level in the Port X Data Register before you set port X for output mode. Unless this method is followed, port output may go low at the same time port output is set after the clock oscillation has stabilized, causing the device to enter RAM backup mode. Appendix 4-21 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.12 Precautions on Processing JTAG Pins Appendix 4.12 Precautions on Processing JTAG Pins Appendix 4.12.1 Precautions on Board Design when Using JTAG The JTAG pins require that wiring lengths be matched during board design in order to accomplish fast, highly reliable communication with JTAG tools. An example of how to process pins when using JTAG tools is shown below. VCCE(5V) M32R/ECU 10KΩ 33Ω JTDO 10KΩ JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω JTRST 2KΩ 0.1µF 33Ω SDI connector (JTAG connector) Power JTAG tool TDO TDI TMS TCK TRST GND User board Make sure wiring lengths are the same, and avoid bending wires as much as possible. Also, do not use through-holes within wiring. Notes: • Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. • Even when not using JTAG tools, always be sure to process each pin. The same pulldown/ pullup resistance values as when using JTAG tools may be used without causing any problem. Figure A4.12.1 Example for Processing Pins when Using JTAG Tools Appendix 4-22 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.12 Precautions on Processing JTAG Pins Appendix 4.12.2 Processing Pins when Not Using JTAG The diagram below shows how to process JTAG pins when not using these pins (i.e. for boards that do not have pins/connectors connecting to JTAG tools). VCCE(5V) M32R/ECU 0 - 100KΩ JTDO JTDI 0 - 100KΩ 0 - 100KΩ JTMS 0 - 100KΩ JTCK JTRST 0 - 100KΩ User board Note: • Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI,JTMS, and JTCK pins are pulled high or pulled low. Figure A4.12.2 Example for Processing Pins when Not Using JTAG Appendix 4-23 32171 Group User's Manual (Rev.2.00) Appendix 4 Appendix 4.13 Precautions about Noise SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system incorporating these measures be fully evaluated before it can actually be put to use. Appendix 4.13.1 Reduction of Wiring Length Wiring on the board may serve as an antenna to draws noise into the microcomputer. Shorter the total wiring length, the smaller the possibility of drawing noise into the microcomputer. ____________ (1) Wiring of the RESET pin _____________ Reduce the length of wiring connecting to the RESET pin. Especially when connecting a _____________ capacitor between the RESET and VSS pins, make sure it is connected to each pin in the shortest distance possible (within 20 mm). Reset is a function to initialize the internal logic of the microcomputer. The width of a pulse _____________ applied to the RESET pin is important and is therefore stipulated as part of timing requirements. If a pulse in width shorter than the stipulated duration (i.e., noise) is applied to _____________ the RESET pin, the microcomputer will not be reset for a sufficient duration of time and exit the reset state before its internal logic is fully initialized, causing the program to go malfunction. Noise Reset circuit VSS Reset circuit VSS RESET VSS RESET VSS Long wiring ____________ Short wiring Figure A4.13.1 Example Wiring of the RESET Pin Appendix 4-24 32171 Group User's Manual (Rev.2.00) Appendix 4 (2) Wiring of clock input/output pins SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Use as much thick and short wiring as possible for connections to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its grounding lead wire and the OSCVSS pin on the microcomputer are connected in the shortest distance possible (within 20 mm). Also, make sure the VSS pattern used for clock oscillation is a large ground plane and is connected to GND. The microcomputer operates synchronously with the clock generated by the oscillator circuit. Inclusion of noise on the clock input/output pins causes the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. Also, if a noise-induced potential difference exists between the microcomputer's VSS level and that of the oscillator, the clock fed into the microcomputer may not be an exact clock. Noise OSC-VSS XIN XO UT VSS OSC-VSS XI N XOUT VSS Thin and long wiring Thick and short wiring Figure A4.13.2 Example Wiring of Clock Input/Output Pins Appendix 4-25 32171 Group User's Manual (Rev.2.00) Appendix 4 (3) Wiring of the VCNT pin SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Use as much thick and short wiring as possible for connections to the VCNT pin. When connecting a capacitor to VCNT, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible. Also, make sure the VSS pattern used for VCNT is a large ground plane and is connected to GND. The external circuit inserted for the VCNT pin plays the role of a low-pass filter that stabilizes the PLL's internal voltage and eliminates noise. If noise exceeding the limit of the low-pass filter penetrates into the wiring, the internal circuit may be disturbed by that noise and become unable to produce a precise clock, causing the microcomputer to operate erratically or get out of control. Noise OSC-VSS VCNT VSS OSC-VSS VCNT VSS Thin and long wiring Thick and short wiring Figure A4.13.3 Example Wiring of the VCNT Pin (4) Wiring of operation mode setup pins When connecting operation mode setup pins and the VCC or VSS pin, make sure they are connected in the shortest distance possible. The levels of operation mode setup pins affect the microcomputer's operation mode. When connecting the operation mode setup pins and the VCC or VSS pin, be careful that no noiseinduced potential difference will exist between the operation mode setup pins and the VCC or VSS pin. This is because the presence of such a potential difference makes operation mode instable, which may result in the microcomputer operating erratically or getting out of control. Noise Operation mode setup pins Operation mode setup pins VSS VSS Long wiring Short wiring Figure A4.13.4 Example Wiring of the MOD0 and MOD1 Pins Appendix 4-26 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between VSS and VCC lines in such a way as to meet the requirements described below. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are equal. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the shortest distance possible. • The VSS and VCC lines have a greater wiring width than that of other signal lines. VCC Chip Chip VSS VCC VSS VCC VSS Figure A4.13.5 Example of a Bypass Capacitor Inserted between VSS and VCC Lines Appendix 4-27 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.3 Processing Analog Input Pin Wiring Insert a resistor of about 100 to 500 Ω in series to the analog signal line connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible. The signal fed into the analog input pin (e.g., A-D converter input pin) normally is an output signal from a sensor. In many cases, a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted, so that wiring to the analog input pin is inevitably long. Because a long wiring serves as an antenna which draws noise into the microcomputer, the signal fed into the analog input pin tends to be noise-ridden. Furthermore, if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin, noise ridding on the ground line may penetrate into the microcomputer via the capacitor. Noise Sensor Microcomputer Analog input pin AVSS Figure A4.13.6 Example of a Resistor and Capacitor Inserted for the Analog Signal Line Appendix 4-28 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it less susceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator and VCNT pin) as possible. Also, make sure the circuit is protected with a GND pattern. Systems using the microcomputer contain signal lines to control, for example, a motor, LED, and thermal head. When a large current flows in these signal lines, it generates noise due to mutual inductance (M). Noise is generated by mutual inductance between the microcomputer and an adjacent signal line M OSC-VSS XIN Large current XO UT VCNT GND A signal line that conducts a large current exists near the microcomputer. M OSC-VSS XIN XO UT Large current VCNT GND Locate a signal line that conducts a large current apart from the microcomputer. Figure A4.13.7 Example Wiring of Large-current Signal Lines Appendix 4-29 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure the rapidly level-changing signal lines will not intersect the clock-related signal lines and other noise-sensitive signal lines. Rapidly level-changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls. Especially if these signal lines intersect the clock-related signal lines, they will cause the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. High-speed serial I/O High-speed timer input/output, etc. XIN XO UT VCNT Signal line intersecting the clock-related and other signal lines. High-speed serial I/O High-speed timer input/output, etc. XIN XO UT VCNT Locate the signal line away from the clock-related and other signal lines to prevent lines from intersecting one another. Figure A4.13.8 Example Wiring of Rapidly Level-changing Signal Lines Appendix 4-30 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise (3) Protection against signal lines that are the source of strong noise Do not use any pin that will probably be subject to strong noise for an adjacent port near the oscillator and VCNT pins. If the pin can be left unused, set it for input and connect to GND via a resistor, or fix it to output and leave open. If the pin needs to be used, it is recommended that it be used for input-only. For protectioon against a still stronger noise source, set the adjacent port for input and connect to GND via a resistor, and use those that belong to the same port group as much for input-only as possible. If greater stability is required, do not use those that belong to the same port group and set them for input and connect to GND via a resistor. If they need to be used, insert a limiting resistor for protection against noise. If the ports or pins adjacent to the oscillator and VCNT pins operate at high speed or are exposed to strong noise from an external source, noise may affect the oscillator circuit, causing its oscillation to become instable. XIN XO UT Oscillator External noise or switching noise Noise VCNT Adjacent pin/peripheral pin (set for output) Fast switching Switching noise from an output pin applied directly to the port Adjacent pin/peripheral pin (set for input) Noise External noise from an input pin applied directly to the port Figure A4.13.9 Example Processing of a Noise-laden Pin Appendix 4-31 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for output) Method for limiting the effect of noise in output mode Adjacent pin/peripheral pin (set for input) Noise Method for limiting noise with a resistor Noise Adjacent pin/peripheral pin (set for output) Fast switching Method for limiting switching noise with a resistor Figure A4.13.10 Example Processing of Pins Adjacent to the Oscillator and VCNT Pins Appendix 4-32 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.5 Processing Input/Output Ports For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100 Ω (or more) in series to input/output ports. Software measures • For input ports, read out data in a program two or more times to verify that levels match. • For output ports, rewrite the data register at certain intervals, because there is a possibility of the output data being inverted by noise. • Rewrite the direction register at certain intervals. Noise Data bus Direction register Noise Data register Input/output port Figure A4.13.11 Example Processing of Input/Output Ports Appendix 4-33 32171 Group User's Manual (Rev.2.00) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise * This is a blank page. * Appendix 4-34 32171 Group User's Manual (Rev.2.00) R ENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER USER’S MANUAL 32171 Group Publication Data : Published by : Rev.0.10 Apr 08, 2000 Rev.2.00 Sep 19, 2003 Sales Strategic Planning Div. Renesas Technology Corp. © 2 003. Renesas Technology Corp., All rights reserved. Printed in Japan. 32171 Group User’s Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan