32174

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/ECU Series 32170 32174 Group User's Manual http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 2.1 Revision date: Jan. 16, 2003 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • • • • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. H ow to read internal I/O register tables ➀ Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. ➁ State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column ➂.) ➂ A t read: ... read enabled ? ... read disabled (read value invalid) 0 ... Read always as 0 1 ... Read always as 1 : Write enabled ∆ : Write enable conditionally (include some conditions at write) - : Write disabled (Written value invalid) { A t write: Not implemented in the shaded portion. 1 D0 1 Abit 2 Bbit 3 Cbit Registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes). 4 2 D 0 1 Bit name Not assigned. Abit (...................) 2 Bbit (...................) 3 Cbit (...................) 0: ----1: ----0: ----1: ----0: ----1: ----Function 6 P86DT D7 P87DT MOD0DT MOD1DT D 0 Bit Name MOD0DT (MOD0 data) 1 MOD1DT (MOD1 data) 2 P82DT (Port P82 data) 3 P83DT (Port P83 data) 4 P84DT (Port P84 data) 5 P85DT (Port P85 data) 6 P86DT (Port P86 data) 7 P87DT (Port P87 data) Function 0 : MOD0 pin = low 1 : MOD0 pin = high 0 : MOD1 pin = low 1 : MOD1 pin = high Depending on how the Port Direction Register is set • When direction bit = 0 (input mode) 0: Port input pin = low 1: Port input pin = high • When direction bit = 1 (output mode) 0: Port output latch = low 1: Port output latch = high — R W — 6-24 32170/32174 Group User's Manual (Rev. 2.1) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Enter one of the following modes: • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode • Extended external mode + flash E/W enable mode FMOD(H'0080 07E0) FPMOD P8DATA(H'0080 0708) D0=MOD0DT D1=MOD1DT MOD0, 1 FP pin levels checked OK NO END Transfer E/W program to internal RAM in each mode Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 0 Switched to flash E/W program Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 1 1 µs wait (by hardware timer or software timer) Execute flash E/W command and various read commands (Note) Jump to flash memory or apply reset Switched to normal mode END Note: For details about each command, refer to Section 6.5.3, "Programming Procedure to Internal Flash Memory." Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode 6-25 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.3 Programming Procedure to the Internal Flash Memory To write to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal RAM. In flash E/W enable mode, no data can be read out from the internal flash memory as in normal mode, so you cannot execute a program that exists in the internal flash memory. Therefore, the flash write program must be prepared in the internal RAM before entering flash E/W enable mode. (Once you've entered flash E/W enable mode, you cannot use any command except flash commands to access the flash memory.) To access the internal flash memory in flash memory E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash memory E/W enable mode. Note : During flash E/W enable mode, the flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash Memory E/W Enable Mode Command Name Read Array command Page Program command Lock Bit Program command Block Erase command Erase All Unlock Block command Read Status Register command Clear Status Register command Read Lock Bit Status command Verify command (Note) Issued Command Data H'FFFF H'4141 H'7777 H'2020 H'A7A7 H'7070 H'5050 H'7171 H'D0D0 Note: This command is used in conjunction with Lock Bit Program, Block Erase, and Erase All Unlock Block operations. (1) Read Array command Read mode is entered by writing command data H'FFFF to any address of the internal flash memory. Then read the flash memory address you want to read out, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. 6-26 32170/32174 Group User's Manual (Rev. 2.1) 6 (2) Page Program command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write. With the Page Program command, you cannot write to the protected blocks. Page Program is automatically performed by the internal control circuit, and the completion of programming can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, the next programming can not be performed. (3) Lock Bit Program command Flash memory can be protected against program/erase one block at a time. The Lock Bit Program command is provided for protecting memory blocks. Write the Lock Bit Program command data H'7777 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the block you want to protect, and this memory block is protected against program/erase. To remove protection, disable lock bit-effectuated protection using the Flash Control Register 2 (FCNT2) FPROT bit (see Section 6.4.3, "Flash Control Registers") and erase the block whose protection you want to remove. (The content of this memory block is also erased.) The table below lists the target blocks and their specified addresses when writing the Verify command data. 6-27 32170/32174 Group User's Manual (Rev. 2.1) 6 Target Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.3 M32170F6 Target Blocks and Specified Addresses Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE H'000A FFFE H'000B FFFE Table 6.5.4 M32170F4 and M32174F4 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 9 10 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE 6-28 32170/32174 Group User's Manual (Rev. 2.1) 6 Target Block 0 1 2 3 4 5 6 7 8 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.5 M32170F3 and M32174F3 Target Blocks and Specified Addresses Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE 6-29 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0000 0000 H’0000 3FFF H’0000 4000 H’0000 5FFF H’0000 6000 H’0000 7FFF H’0000 8000 H’0000 FFFF H’0001 0000 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F6’s Internal Flash Memory Area (768KB) 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Uneven blocks Block 3 64KB H’0001 FFFF H’0002 0000 64KB H’0002 FFFF H’0003 0000 64KB H’0003 FFFF H’0004 0000 64KB H’0004 FFFF H’0005 0000 64KB H’0005 FFFF H’0006 0000 64KB H’0006 FFFF H’0007 0000 64KB H’0007 FFFF H’0008 0000 64KB H’0008 FFFF H’0009 0000 64KB H’0009 FFFF H’000A 0000 64KB H’000A FFFF H’000B 0000 64KB H’000B FFFF Block 4 Block 5 Block 6 Block 7 Block 8 Even blocks Block 9 Block 10 Block 11 Block 12 Block 13 Block 14 Figure 6.5.7 Block Configuration of the M32170F6 Flash Memory 6-30 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0000 0000 H’0000 3FFF H’0000 4000 H’0000 5FFF H’0000 6000 H’0000 7FFF H’0000 8000 H’0000 FFFF H’0001 0000 16KB 8KB 8KB 32KB INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F4’s and M32174F4’s Internal Flash Memory Area (512KB) Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H’0001 FFFF H’0002 0000 64KB H’0002 FFFF H’0003 0000 64KB H’0003 FFFF H’0004 0000 64KB H’0004 FFFF H’0005 0000 64KB H’0005 FFFF H’0006 0000 64KB H’0006 FFFF H’0007 0000 64KB H’0007 FFFF Block 4 Block 5 Block 6 Block 7 Even blocks Block 8 Block 9 Block 10 Figure 6.5.8 Block Configuration of the M32170F4 and M32174F4 Flash Memory 6-31 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F3’s and M32174F3’s Internal Flash Memory Area (384KB) H’0000 0000 H’0000 3FFF H’0000 4000 H’0000 5FFF H’0000 6000 H’0000 7FFF H’0000 8000 H’0000 FFFF H’0001 0000 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H’0001 FFFF H’0002 0000 64KB H’0002 FFFF H’0003 0000 64KB H’0003 FFFF H’0004 0000 64KB H’0004 FFFF H’0005 0000 64KB H’0005 FFFF Block 4 Block 5 Block 6 Even blocks Block 7 Block 8 Figure 6.5.9 Block Configuration of the M32170F3 and M32174F3 Flash Memory 6-32 32170/32174 Group User's Manual (Rev. 2.1) 6 (4) Block Erase command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to erase (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"). The content of this memory block is erased. With the Block Erase command, you cannot erase the protected blocks. Block Erase is automatically performed by the internal control circuit, and the completion of Block Erase can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, you cannot erase the next block. (5) Erase All Unlock Block command The Erase All Unlock Block command erases all memory blocks that are not protected. To erase all unlock blocks, write the command data H'A7A7 to any address of the internal flash memory. Next, write the command data H'D0D0 to any address of the internal flash memory, and all of unprotected memory blocks are erased. (6) Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory write or erase operation has terminated normally or not. To read Flash Status Register 2, write the command data H'7070 to any address of the internal flash memory. Next, read any address of the internal flash memory, and the content of Flash Status Register 2 (FSTAT2) is read out. (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 (FSTAT2) D10, D11, and D12 bits to 0. Write the command data H'5050 to any address of the internal flash memory, and Flash Status Register 2 is cleared to 0. If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition) or WRERR2 (Program operating condition 2) bit is set to 1, you cannot perform the next program or erase operation unless WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) is cleared to 0. 6-33 32170/32174 Group User's Manual (Rev. 2.1) 6 (8) Read Lock Bit Status command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory. Next, read the last even address of the block you want to check (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"), and the data you read shows whether or not the target block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit of the data you read are 0s, it means that the target memory block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit are 1s, it means that the target memory block is not protected. s Lock Bit Status Register (FLBST) FLBST0 FLBST1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D 0 1 Bit Name No functions assigned FLBST0 (Lock bit 0) 2-8 9 No functions assigned FLBST1 (Lock bit 1) 0 : Protected 1 : Not protected (Same content as FLBST0 is output.) 10 - 15 No functions assigned ? — 0 : Protected 1 : Not protected ? — — Function R ? W — — The Lock Bit Status Register is a read-only register, which contains said lock bits independently for each block. 6-34 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command (H'A7A7) to erase the memory block you want to unprotect. This is the only way to unprotect a memory block. You cannot set the lock bit alone to 1. c) Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit. (9) Execution flow of each command The diagrams below show an execution flow of each command. START Write Read Array command (H'FFFF) to any address of internal flash memory Read the internal flash memory address you want to read END Figure 6.5.10 Read Array 6-35 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Page Program command (H'4141) to any address of internal flash memory. Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address. NO Programmed for one page ? YES Written to the internal flash memory by Page Program (Note 2) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES Read any address of internal flash memory to check for program error. (Note 3) TIME OUT ? 0.5s YES Forcibly terminated NO Last address ? YES NO Go to next page END Note 1: Start writing from the beginning of a 256-byte boundary of the flash memory (lower address H'00). Note 2: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 3: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.11 Page Program 6-36 32170/32174 Group User's Manual (Rev. 2.1) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 0.5s Read any address of internal flash memory to check for program error. (Note 2) YES Forcibly terminated NO END Note 1: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.12 Lock Bit Program 6-37 32170/32174 Group User's Manual (Rev. 2.1) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 1s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.13 Block Erase 6-38 32170/32174 Group User's Manual (Rev. 2.1) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 10s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.14 Erase All Unlock Block 6-39 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any address of internal flash memory. END Figure 6.5.15 Read Status Register START Write Clear Status command (H'5050) to any address of internal flash memory. END Figure 6.5.16 Clear Status Register START Write Read Lock Bit Status command (H'7171) to any address of internal flash memory. Read the last even address of the block whose status you want to read. END Figure 6.5.17 Read Lock Bit Status Register 6-40 32170/32174 Group User's Manual (Rev. 2.1) 6 6.5.4 Flash Write Time (for Reference) INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The time required for writing to the internal flash memory is shown below for your reference. (1) M32170F6 (a) Transfer time by SIO (for a transfer data size of 768 KB) . . 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 768 KB = 150.2 [s] (b) Flash write time . 768 KB/256-byte block × 8 ms = 24.6 [s] . (c) Erase time (entire area) 50 ms × number of blocks = 750 [ms] (d) Total flash write time (entire 768 KB area) • When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: . . (a) + (c) = 151 [s] When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: . . (b) + (c) = 25 [s] (2) M32170F4 and M32174F4 (a) Transfer time by SIO (for a transfer data size of 512 KB) . . 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 512 KB = 100.2 [s] (b) Flash write time . 512 KB/256-byte block × 8 ms = 16.4 [s] . (c) Erase time (entire area) 50 ms × number of blocks = 550 [ms] (d) Total flash write time (entire 512 KB area) • When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: . . (a) + (c) = 101 [s] When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: . . (b) + (c) = 17 [s] 6-41 32170/32174 Group User's Manual (Rev. 2.1) 6 (3) M32170F3 and M32174F3 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (a) Transfer time by SIO (for a transfer data size of 384 KB) . 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 384 KB = 75.1 [s] . (b) Flash write time . 384 KB/256-byte block × 8 ms = 12.3 [s] . (c) Erase time (entire area) 50 ms × number of blocks = 450 [ms] (d) Total flash write time (entire 384 KB area) • When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: . (a) + (c) = 76 [s] . When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: . (b) + (c) = 13 [s] . 6-42 32170/32174 Group User's Manual (Rev. 2.1) 6 6.6 Boot ROM INTERNAL MEMORY 6.6 Boot ROM The table below shows boot memory specifications of the 32170 and 32174. Table 6.6.1 Boot Memory Specifications Item Capacity Location address Wait insertion Internal bus connection Read Specification 8 Kbytes H'8000 0000 - H'8000 1FFF Operates with no wait states (with 40 MHz internal CPU memory clock) Connected by 32-bit bus Can only be read when FP = 1, MOD0 = 1, and MOD1 = 0. When read in other modes,indeterminate values are read out. Cannot be accessed for write. Other Because the boot ROM area is a reserved area that can only be used in boot mode, the program cannot be modified. 6-43 32170/32174 Group User's Manual (Rev. 2.1) 6 6.7 Virtual Flash Emulation Function INTERNAL MEMORY 6.7 Virtual Flash Emulation Function This microcomputer has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4, M32170F3, M32174F4, and M32174F3) into the internal flash memory area divided in units of 8 Kbytes (L banks). Similarly, this function allows the internal RAM to be mapped in blocks of 4 Kbytes, for the M32170F6 (up to two blocks) starting from the RAM address H'0080 C000, for the M32170F4, M32170F3, M32174F4, and M32174F3 (up to two blocks) starting from the RAM address H'0080 A000 into the internal flash memory area divided in units of 4 Kbytes (S banks). When this function is used, the data placed in 8 Kbyte or 4 Kbyte blocks of internal RAM can be moved to or from the L or S banks in the flash memory that are specified by the Virtual Flash Bank Register. For applications that require modifying data during program operation, this enables dynamic modification of data using 8 Kbytes or 4 Kbytes of RAM areas. The RAM blocks allocated for virtual flash emulation can be read or written to from both internal RAM and internal flash memory areas. This function, when used in combination with the Real-Time Debugger (RTD), permits you to look up or rewrite from outside the data tables created in the internal flash memory, thus facilitating data table tuning from an external device. Before accessing the internal flash memory for programming, be sure to terminate this virtual flash emulation mode. H’0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes H’0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H’0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes H’0080 A000 RAM bank L block 3 (FELBANK3) 8 Kbytes H’0080 C000 RAM bank S block 0 (FESBANK0) 4 Kbytes RAM bank S block 1 (FESBANK1) 4 Kbytes H’0080 D000 Figure 6.7.1 Internal RAM Bank Configuration of the M32170F6 6-44 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H’0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H’0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes H’0080 A000 RAM bank S block 0 (FESBANK0) 4 Kbytes RAM bank S block 1 (FESBANK1) 4 Kbytes H’0080 B000 Figure 6.7.2 Internal RAM Bank Configuration of the M32170F4 and M3170F3 H'0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes H'0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H'0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes H'0080 A000 Areas usable for virtual-flash emulation RAM bank S block 0 (FESBANK0) 4K bytes RAM bank S block 1 (FESBANK1) 4 Kbytes H'0080 B000 H'0080 C000 H'0080 DFFF Note: The 8-Kbyte area from H'0080 C000 to H'0080 DFFF cannot be used as a virtual-flash emulation area. Figure 6.7.3 Internal RAM Bank Configuration of the M32174F4 and M32174F3 6-45 32170/32174 Group User's Manual (Rev. 2.1) 6 6.7.1 Virtual-Flash Emulation Areas INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The following shows the areas in which the virtual-flash emulation function is effective. Using the Virtual-Flash L Bank Registers (FELBANK0 – FELBANK3 for the M32170F6 or FELBANK0–FELBANK2 for the M32170F4, M32170F3, M32174F4, and M32174F3), select an arbitrary L bank area from 8-Kbyte L banks in the flash memory area (by setting the seven start address bits A12–A18 of the desired L bank in the Virtual-Flash L Bank Register LBANKAD bits). Then set the Virtual-Flash L Bank Register MODENL0–3 bits (for the M32170F6) or MODENL0–2 bits (for the M32170F4, M32170F3, M32174F4, and M32174F3) to 1. The selected L bank areas can be replaced with 8-Kbyte blocks of the internal RAM beginning with its start address, up to four blocks for the M32170F6 or up to three blocks for the M32170F4, M32170F3, M32174F4, and M32174F3. Similarly, using the Virtual-Flash S Bank Registers (FESBANK0, FESBANK1), select an arbitrary S bank area from 4-Kbyte S banks in the flash memory (by setting the eight start address bits A12– A19 of each desired S bank in the Virtual-Flash S Bank Register SBANKAD bits). Then set the Virtual-Flash S Bank Register MODENS0 and MODENS1 bits to 1. The selected S bank areas can be replaced with up to two 4-Kbyte blocks of the internal RAM beginning with address H’0080 C000 for the M32170F6 or H’0080 A000 for the M32170F4, M32170F3, M32174F4, and M32174F3. In this way, the M32170F6 can have four 8-Kbyte blocks or L banks and two 4-Kbyte blocks or S banks selected, for a total of up to six banks. For the M32170F4, M32170F3, M32174F4, and M32174F3, three 8-Kbyte blocks or L banks and two 4-Kbyte blocks or S banks can be selected, for a total of up to five banks. Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbyte) to be replaced with is selected according to the priority of Virtual-Flash Bank Registers as follows: • M32170F6 FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1 • M32170F4, M32170F3, M32174F4, and M32174F3 FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 Note 2: During virtual-flash emulation mode, the RAM can be accessed for read and write from the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF of the M32174F4 and M32174F3 cannot be used as a virtual-flash emulation area. Note 4: When performing virtual-flash read after setting Flash Control Register 1’s Virtual-Flash Emulation Mode bit to 1, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the said bit to 1. Note 5: When performing virtual-flash read after setting the Virtual-Flash Bank Register (L Bank or S Bank Register)’s Virtual-Flash Emulation Enable bit and bank address bits, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the Virtual-Flash Bank Register. 6-46 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0000 0000 H’0000 2000 H’0000 4000 L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H’0080 4000 8 Kbytes H’0080 6000 8 Kbytes H’0080 8000 8 Kbytes H’0006 4000 H’0006 6000 L bank 50 (8 Kbytes) L bank 51 (8 Kbytes) H’0080 A000 8 Kbytes 4 Kbytes 4 Kbytes H’000B C000 H’000B E000 L bank 94 (8 Kbytes) L bank 95 (8 Kbytes) Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-3, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.4 The M32170F6's Virtual Flash Emulation Area Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 4 Kbytes 4 Kbytes H'0080 C000 H'0080 D000 H'000B E000 H'000B F000 S bank 190 (4 Kbytes) S bank 191 (4 Kbytes) Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.5 The M32170F6's Virtual Flash Emulation Area Divided in Units of 4 Kbytes 6-47 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0000 0000 H’0000 2000 H’0000 4000 L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H’0080 4000 8 Kbytes H’0080 6000 8 Kbytes H’0080 8000 8 Kbytes 4 Kbytes H’0007 C000 H’0007 E000 L bank 62 (8 Kbytes) L bank 63 (8 Kbytes) 4 Kbytes Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-2, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.6 The M32170F4's Virtual Flash Emulation Area Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H'0007 E000 H'0007 F000 4 Kbytes S bank 126 (4 Kbytes) S bank 127 (4 Kbytes) 4 Kbytes H'0080 A000 H'0080 B000 Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.7 The M32170F4's Virtual Flash Emulation Area Divided in Units of 4 Kbytes 6-48 32170/32174 Group User's Manual (Rev. 2.1) 6 H’0000 0000 H’0000 2000 H’0000 4000 L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H’0080 4000 8 Kbytes H’0080 6000 8 Kbytes H’0080 8000 8 Kbytes 4 Kbytes H’0005 C000 H’0005 E000 L bank 46 (8 Kbytes) L bank 47 (8 Kbytes) 4 Kbytes Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-2, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.8 The M32170F3's Virtual Flash Emulation Area Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H'0005 E000 H'0005 F000 4 Kbytes S bank 94 (4 Kbytes) S bank 95 (4 Kbytes) 4 Kbytes H'0080 A000 H'0080 B000 Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Figure 6.7.9 The M32170F3's Virtual Flash Emulation Area Divided in Units of 4 Kbytes 6-49 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L Bank 0 (8 Kbytes) L Bank 1 (8 Kbytes) L Bank 2 (8 Kbytes) H'0080 4000 8 Kbytes H'0080 6000 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes 4 Kbytes H'0080 C000 H'0080 DFFF H'0007 C000 H'0007 E000 L Bank 62 (8 Kbytes) L Bank 63 (8 Kbytes) 8 Kbytes Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by one of Virtual-Flash L Bank Registers 0–2, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Figure 6.7.10 The M32174F4's Virtual Flash Emulation Area Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S Bank 0 (4 Kbytes) S Bank 1 (4 Kbytes) S Bank 2 (4 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H'0007 E000 H'0007 F000 S Bank 126 (4 Kbytes) S Bank 127 (4 Kbytes) 4 Kbytes 4 Kbytes 8 Kbytes H'0080 A000 H'0080 B000 H'0080 C000 H'0080 DFFF Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0 or 1, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Figure 6.7.11 The M32174F4's Virtual Flash Emulation Area Divided in Units of 4 Kbytes 6-50 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L Bank 0 (8 Kbytes) L Bank 1 (8 Kbytes) L Bank 2 (8 Kbytes) H'0080 4000 8 Kbytes H'0080 6000 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes 4 Kbytes H'0080 C000 H'0080 DFFF H'0005 C000 H'0005 E000 L Bank 46 (8 Kbytes) L Bank 47 (8 Kbytes) 8 Kbytes Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by one of Virtual-Flash L Bank Registers 0–2, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Figure 6.7.12 The M32174F3's Virtual Flash Emulation Area Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S Bank 0 (4 Kbytes) S Bank 1 (4 Kbytes) S Bank 2 (4 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H'0005 E000 H'0005 F000 S Bank 94 (4 Kbytes) S Bank 95 (4 Kbytes) 4 Kbytes 4 Kbytes 8 Kbytes H'0080 A000 H'0080 B000 H'0080 C000 H'0080 DFFF Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0 or 1, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Figure 6.7.13 The M32174F3's Virtual Flash Emulation Area Divided in Units of 4 Kbytes 6-51 32170/32174 Group User's Manual (Rev. 2.1) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H’0000 0000 (Note) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H’00 H’02 H’04 H’0000 2000 H’0000 4000 L bank 94 L bank 95 H’000B C000 H’000B E000 H’BC H’BE Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.14 Values Set in the M32170F6's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H’0000 0000 (Note) S bank address (SBANKAD) bit set value H’00 H’01 H’02 H’0000 1000 H’0000 2000 S bank 190 S bank 191 H’000B E000 H’000B F000 H’BE H’BF Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.15 Values Set in the M32170F6's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-52 32170/32174 Group User's Manual (Rev. 2.1) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H’0000 0000 (Note) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H’00 H’02 H’04 H’0000 2000 H’0000 4000 L bank 62 L bank 63 H’0007 C000 H’0007 E000 H’7C H’7E Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.16 Values Set in the M32170F4's and the M32174F4's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H’0000 0000 (Note) S bank address (SBANKAD) bit set value H’00 H’01 H’02 H’0000 1000 H’0000 2000 S bank 126 S bank 127 H’0007 E000 H’0007 F000 H’7E H’7F Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.17 Values Set in the M32170F4's and the M32174F4's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-53 32170/32174 Group User's Manual (Rev. 2.1) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H’0000 0000 (Note) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H’00 H’02 H’04 H’0000 2000 H’0000 4000 L bank 46 L bank 47 H’0005 C000 H’0005 E000 H’5C H’5E Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.18 Values Set in the M32170F3's and the M32174F3's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H’0000 0000 (Note) S bank address (SBANKAD) bit set value H’00 H’01 H’02 H’0000 1000 H’0000 2000 S bank 94 S bank 95 H’0005 E000 H’0005 F000 H’5E H’5F Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.19 Values Set in the M32170F3's and the M32174F3's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-54 32170/32174 Group User's Manual (Rev. 2.1) 6 6.7.2 Entering Virtual Flash Emulation Mode INTERNAL MEMORY 6.7 Virtual Flash Emulation Function To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function. Even during virtual-flash emulation mode, the internal RAM area (H’0080 4000 to H’0080 DFFF for the M32170F6, H’0080 4000 to H’0080 BFFF for the M32170F4 and M32170F3, or H’0080 4000 to H’0080 DFFF for the M32174F4 and M32174F3) can be accessed as internal RAM. Settings completed Write flash data to RAM Go to Virtual Flash Emulation Mode FEMMOD ← 1 Set RAM location address in Virtual Flash Bank Register LBANKADn ← Address A12-A18 SBANKADn ← Address A12-A19 Enable Virtual Flash Emulation Function MODENLn ← 1 MODENSn ← 1 Settings completed Figure 6.7.20 Virtual Flash Emulation Mode Sequence 6-55 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.3 Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx Initial value Replace area RAM block 0 RAM block 1 Data write to RAM0 (2) Program operation using RAM block 0 Flash Replace Bank xx Initial value RAM block 0 Bank xx specified RAM block 0 RAM block 1 Data write to RAM1 (3) Program operation changed from RAM block 0 to RAM block 1 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified (settings invalid) Bank xx specified RAM block 0 RAM block 1 Figure 6.7.21 Application Example of Virtual Flash Emulation (1/2) 6-56 32170/32174 Group User's Manual (Rev. 2.1) 6 (4) Program operation using RAM block 1 Flash INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 RAM block 1 Data write to RAM0 (5) Program operation changed from RAM block 1 to RAM block 0 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified RAM block 0 RAM block 1 Bank xx specified (settings invalid) (6) Go to item (2) Note : valid area Figure 6.7.22 Application Example of Virtual Flash Emulation (2/2) 6-57 32170/32174 Group User's Manual (Rev. 2.1) 6 6.8 Connecting to A Serial Programmer INTERNAL MEMORY 6.8 Connecting to A Serial Programmer When you rewrite the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32170 and 32174 shown below to make them suitable for the serial programmer. Table 6.8.1 Processing the 32170 Pins when Using a Serial Programmer Pin Name SCLKI1 RXD1 TXD1 P83 P84 FP MOD0 MOD1 RESET XIN XOUT VCNT OSC-VCC OSC-VSS VREF0 VREF1 AVCC0 AVCC1 AVSS0 AVSS1 FVCC VDD VCCE VCCI VSS Pin Number 121 120 119 117 118 156 154 155 153 19 20 23 21 18 61 227 62 228 79 5 128 170 37,51,80,114,139,157, 205 Function Transfer clock input Serial data input (receive data) Serial data output (transmit data) Transmit/receive control Transmit/receive enable output Flash memory protect Operation mode 0 Operation mode 1 Reset Clock input Clock output PLL circuit control input PLL circuit power supply PLL circuit ground A-D converter reference voltage input Analog power supply Analog ground Flash memory power supply RAM backup power supply 5 V power supply Connect to 3.3 V power supply Connect to ground Connect to 5 V power supply Connect to ground Need to be pulled high Need to be pulled high Remark Need to be pulled high Need to be pulled high Connect to 5 V power supply Connect to ground Connect to 3.3 V power supply Connect to 3.3 V power supply 98,126,137,171,195,225 3.3 V power supply 17,22,24,38,52,81,99, 115,127,129,138,158, 172,196,206,226 Ground Note: All other pins do not need to be processed. 6-58 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur. If the system uses any 32170/32174 pins which will connect to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H'0000 0084 through H'0000 0093 as an area to check ID for flash memory protection. User system circuit board Connects to 5 V power supply AVCC0, AVCC1 VCCE VREF0, VREF1 Connects to 3.3 V power supply FVCC VCCI OSC-VCC VDD Connector Various signals on flash programmer 5V (Input) RxD (Input) TxD (Output) SCLKO(Output) BUSY (Input) MOD0 (Output) FP (Output) RESET(Output) GND (Output) P83/RXD0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET VSS AVSS0, AVSS1 OSCVSS To system circuit Set microcomputer operating conditions MOD1 XIN XOUT VCNT 32170 32174 Note 1 : Turn on the power to the user system before you write to the flash memory. Note 2 : If the system circuit uses P83-P87, consideration must be taken for connection of a serial programmer. Note 3 : P83 must have a high-level signal applied to it. Note 4 : P64/SBI must be fixed high or low to ensure that interrupts will not be generated. Note 5 : The pullup resistances of P83, P84, P86, and P87 must be set to suit system design conditions. Note 6 : The typical pullup resistances of P83, P84, P86, and P87 are 4.7 to 10 kΩ. Note 7 : All other ports, whether high or low, do not affect flash memory programming. Figure 6.8.1 Pin Connection Diagram 6-59 32170/32174 Group User's Manual (Rev. 2.1) 6 INTERNAL MEMORY 6.9 Precautions to Be Taken When Rewriting Flash Memory 6.9 Precautions to Be Taken When Rewriting Flash Memory The following describes precautions to be taken when you rewrite the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. • When you use the pins with the system that are used by a serial programmer, take measures not to affect the system when connecting a serial programmer. • If the flash memory needs to be protected, set an appropriate ID in the flash memory protect ID verification area (H'0000 0084 through H'0000 0093). • If the flash memory does not require protection, fill the entire flash memory protect ID verification area (H'0000 0084 through H'0000 0093) with H'FF. • Do not use wait function when entering the flash E/W mode because it may validate wait state if a low-level signal is applied to the WAIT# pin. 6-60 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State Immediately after Reset Release 7.4 Things To Be Considered after Reset Release 7 7.1 Outline of Reset _____ RESET 7.1 Outline of Reset The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out _____ of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry. 7.2 Reset Operation 7.2.1 Reset at Power-on _____ When powering on the device, hold the RESET input low until its internal multiply-by-4 clock generator becomes oscillating stably. 7.2.2 Reset during Operation _____ To reset the device during operation, hold the RESET input low for more than four clock periods of XIN signal. 7.2.3 Reset Vector Relocation during Flash Rewrite When placed in boot mode, the reset vector entry address is moved to the start address of the boot program space (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." 7-2 32170/32174 Group User's Manual (Rev. 2.1) 7 RESET 7.3 Internal State Immediately after Reset Release 7.3 Internal State Immediately after Reset Release The table below lists the register state of the device immediately after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Reset Register PSW (CR0) CBR (CR1) SPI (CR2) State after Reset Release B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = indeterminate) H'0000 0000 (C bit = 0) Indeterminate Indeterminate Indeterminate H'0000 0000 (Executed beginning with address H'0000 0000) (Note) SPU (CR3) BPC (CR6) PC ACC (accumulator) Indeterminate Note: When in boot mode, this changes to the start address of the boot program space (H'8000 0000). 7-3 32170/32174 Group User's Manual (Rev. 2.1) 7 Table 7.3.2 Pin Status When Reset Pin name Mode Single chip Input Input Output — RESET 7.3 Internal State Immediately after Reset Release External extension Input Input Output — Microprocessor Input Input Output — Boot Input Input Output — Reset, MOD0, MOD1, and FP XIN XOUT VCNT (Note 1) P00 - P07, P10 - P17, P61 - P67, P70 - P77, P82 - P87, P93 - P97, P100 - P107, P110 - P117, P124 - P127, P130 - P137, P140 - P147, P150 - P157, P160 - P167, P172 - P177, P180 - P187, P190 - P197, P200 - P203, P210 - P217, P220 - P225 P20 - P27, P30 - P37, P41 - P47 A-D converter AD0IN0 - 7 AD1IN0 - 7 JTAG JTDI, JTMS, Input Input Input Input Port Input Input Hi-Z Input Input Input Input Input (Note 2) JTCK, JTRST Input Indeterminate Input Indeterminate High output Low-level output Low-level output High-level output Indeterminate Input Indeterminate High output Low-level output Low-level output High-level output Indeterminate Input Indeterminate High output Low-level output Low-level output High-level output Indeterminate JTDO DBI (Note 3) (Note 4) High output Low-level output EVENT[0:1] (Note 4) TRCLK (Note 4) Low-level output TRSYNC(Note 4) High-level output TRDATA[0:7] (Note 4) Indeterminate Note 1: The VCNT pin is used to control the PLL circuit. Note 2: The JTAG pin is not initialized by a reset. It can be reset by pulling JTRST low. Note 3: The DBI pin is pulled high internally. Note 4: This applies only when using 255FBAG (not available when using 240QFP). 7-4 32170/32174 Group User's Manual (Rev. 2.1) 7 RESET 7.4 Things To Be Considered after Reset Release 7.4 Things To Be Considered after Reset Release • Input/output ports After reset release, the 32170's and 32174's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit. For details, refer to Section 8.3, "Input/Output Port Related Registers." 7-5 32170/32174 Group User's Manual (Rev. 2.1) 7 RESET 7.4 Things To Be Considered after Reset Release ❊ This is a blank page. ❊ 7-6 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits 8.5 Precautions on Input/output Ports 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports This microcomputer has a total of 157 input/output ports from P0 to P22 (of which P5 is reserved for future use, however). These input/output ports can be set for input or output mode by a direction register. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line. Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. (If any internal peripheral I/O has still another function, you need to set the register provided for that peripheral I/O.) As a new function, the 32170 internally contains a Port Input Function Enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite. To use any ports in input mode, you need to set the Port Input Function Enable bit accordingly. The input/output ports are outlined in the next pages. 8-2 32170/32174 Group User's Manual (Rev. 2.1) 8 Item Number of ports Specification Total 157 lines P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 : : : : : : : : : : : : : : : : : : : : : INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of Input/Output Ports P00 - P07 P10 - P17 P20 - P27 P30 - P37 P41 - P47 P61 - P67 P70 - P77 P82 - P87 P93 - P97 P100 - P107 P110 - P117 P124 - P127 P130 - P137 P140 - P147 P150 - P157 P160 - P167 P172 - P177 P180 - P187 P190 - P197 P200 - P203 P210 - P217 P220 - P225 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (7 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (8 lines) (8 lines) (8 lines) (6 lines) (8 lines) (8 lines) (4 lines) (8 lines) (6 lines) P22 : Port function The input/output ports can individually be set for input or output mode using the ___ Direction Control Register provided for each input/output port. (However, P64 is an SBI input-only port and P221 is a CAN input-only port.) Pin function Shared with peripheral I/O or extended external signals to serve dual functions (or with two or more peripheral I/O functions to serve multiple functions) Pin function switchover P0 - P4, P224, P225 : Depends on CPU operation mode (determined by setting MOD0 and MOD1 pins) P6 - P22 : As set by each input/output port's Operation Mode Register (However, peripheral I/O pin functions are selected by peripheral I/O registers.) 8-3 32170/32174 Group User's Manual (Rev. 2.1) 8 8.2 Selecting Pin Functions INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. P0-P4, P224, and P225, when the CPU is set to operate in extended external mode or processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined by setting the MOD0 and MOD1 pins (see the table below). Table 8.2.1 CPU Operation Mode and Pin Functions of P0-P4, P224, and P225 MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCCE Operation Mode Single-chip mode Extended external mode Extended external signal pin Processor mode Reserved (Use inhibited) — Pin Functions of P0-P4, P224, and P225 input/output port pin Note: VCCE and VSS are connected to +5 V and GND, respectively. P6-P22 (except P64, P221, P224, and P225) have their pin functions switched between input/ output port pins and internal peripheral I/O pins by setting each port's Operation Mode Register. If any internal peripheral I/O has multiple pin functions, you need to set the register provided for that peripheral I/O to select the desired pin function. Note that settings of FP pin and MOD1 pin during internal flash memory write operation do not affect the pin functions. 8-4 32170/32174 Group User's Manual (Rev. 2.1) 8 0 P0 P1 Settings of CPU operation mode P2 (Note 1) P3 P4 (Reserved) DB0 DB8 A23 A15 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 DB9 A24 A16 BLW/ BLE 2 DB2 DB10 A25 A17 BHW/ BHE 3 DB3 DB11 A26 A18 RD 4 DB4 DB12 A27 A19 CS0 5 DB5 DB13 A28 A20 CS1 6 DB6 DB14 A29 A21 A13 7 DB7 DB15 A30 A22 A14 P5 P6 P7 P8 P9 P10 P11 P12 TO8 TO0 TO9 TO1 TO10 TO2 BCLK/ WR (P61) WAIT (P62) HREQ TXD0 (P63) SBI SCLKI4/ SCLKI5/ SCLKO4 SCLKO5 ADTRG HACK RTDTXD RTDRXD RTDACK RTDCLK RXD0 TO16 TO11 TO3 SCLKI0/ SCLKO0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 TIN13 TIN5 TO26 RXD2 TO34 TIN31 RXD1 TO19 TO14 TO6 TCLK2 TIN22 TIN14 TIN6 TO27 TXD3 TO35 TIN32 SCLKI1/ SCLKO1 TO17 TO12 TO4 TCLK0 TO20 TO15 TO7 TCLK3 TIN23 TIN15 TIN7 TO28 RXD3 TO36 TIN33 P13 Settings of input/ output port Operation Mode P14 Register P15 P16 P17 P18 P19 P20 P21 P22 TIN16 TIN8 TIN0 TO21 TIN17 TIN9 TIN1 TO22 TIN18 TIN10 TIN2 TO23 TIN24 TIN19 TIN11 TIN3 TO24 TIN25 TO32 TIN29 RXD5 TO40 (P223) TIN20 TIN12 TIN4 TO25 TXD2 TO33 TIN30 TO29 TIN26 TXD4 TO37 CTX TO30 TIN27 RXD4 TO38 CRX TO31 TIN28 TXD5 TO39 (P222) TO41 A11 (Note 2) TO42 A12 (Note 2) TO43 TO44 Note 1: Pin functions are switched over by setting MOD0 and MOD1 pins. Note 2: Pin functions are switched over by setting MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. Figure 8.2.1 Input/Output Ports and Pin Function Assignments 8-5 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers Included in the 32170 as input/output port related registers are the Port Data Registers, Port Direction Registers, and Port Operation Mode Registers. Of these, the Port Operation Mode Registers are provided for only P6-P22. Ports P0-P4, P224, and P225 have their pin functions determined by setting the CPU operation mode (FP, MOD0, and MOD1 pins). Port P5 is reserved for future use. The tables below show an input/output port related register map. Address D0 +0 Address D7 D8 +1 Address D15 H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) Blank addresses are reserved. Figure 8.3.1 Input/Output Port Related Register Map (1/2) 8-6 32170/32174 Group User's Manual (Rev. 2.1) 8 Address D0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +0 Address D7 D8 +1 Address D15 H'0080 0744 H'0080 0746 P6 Operation Mode Register (P6MOD) H'0080 0748 P8 Operation Mode Register (P8MOD) Port Input Function Enable Register (PIEN) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) H'0080 074A P10 Operation Mode Register (P10MOD) P11 Operation Mode Register (P11MOD) H'0080 074C P12 Operation Mode Register (P12MOD) P13 Operation Mode Register (P13MOD) H'0080 074E P14 Operation Mode Register (P14MOD) P15 Operation Mode Register (P15MOD) H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 P16 Operation Mode Register (P16MOD) P17 Operation Mode Register (P17MOD) P18 Operation Mode Register (P18MOD) P19 Operation Mode Register (P19MOD) P20 Operation Mode Register (P20MOD) P21 Operation Mode Register (P21MOD) P22 Operation Mode Register (P22MOD) Blank addresses are reserved. 8.3.2 Input/Output Port Related Register Map (2/2) 8-7 32170/32174 Group User's Manual (Rev. 2.1) 8 8.3.1 Port Data Registers s P0 Data Register (P0DATA) s P1 Data Register (P1DATA) s P2 Data Register (P2DATA) s P3 Data Register (P3DATA) s P4 Data Register (P4DATA) s P6 Data Register (P6DATA) s P7 Data Register (P7DATA) s P8 Data Register (P8DATA) s P9 Data Register (P9DATA) s P10 Data Register (P10DATA) s P11 Data Register (P11DATA) s P12 Data Register (P12DATA) s P13 Data Register (P13DATA) s P14 Data Register (P14DATA) s P15 Data Register (P15DATA) s P16 Data Register (P16DATA) s P17 Data Register (P17DATA) s P18 Data Register (P18DATA) s P19 Data Register (P19DATA) s P20 Data Register (P20DATA) s P21 Data Register (P21DATA) s P22 Data Register (P22DATA) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers D0 ( D8 Pn0DT 1 9 Pn1DT 2 10 Pn2DT 3 11 Pn3DT 4 12 Pn4DT 5 13 Pn5DT 6 14 Pn6DT D7 D15 ) Pn7DT Note: n = 0 to 22 (except for P5) 8-8 32170/32174 Group User's Manual (Rev. 2.1) 8 D 0 1 2 3 4 5 6 7 Bit Name Pn0DT (Port Pn0 data) Pn1DT (Port Pn1 data) Pn2DT (Port Pn2 data) Pn3DT (Port Pn3 data) Pn4DT (Port Pn4 data) Pn5DT (Port Pn5 data) Pn6DT (Port Pn6 data) Pn7DT (Port Pn7 data) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Function Depending on how the Port Direction Register is set • When direction bit = 0 (input mode) 0: Port input pin = low 1: Port input pin = high • When direction bit = 1 (output mode) 0: Port output latch = low 1: Port output latch = high R W Note 1: The following bits have no functions assigned (when read, the bit = 0; writing to the bit has no effect). P40, P60, P90-P92, P120-P123, P170, P171, P204-P207, P226, P227 Note 2: Port P64 is input mode-only. Writing to the P64DT bit has no effect. Note 3: Port P221 is input mode-only. Writing to the P221DT bit has no effect. Note 4: Ports P80 and P81 are input mode-only. Writing to the P80DT and P81DT bits has no effect. When read out, P80 shows the MOD0 pin level and P81 shows the MOD1 pin level. The P80DT and P81DT bits are write-protected. 8-9 32170/32174 Group User's Manual (Rev. 2.1) 8 8.3.2 Port Direction Registers s P0 Direction Register (P0DIR) s P1 Direction Register (P1DIR) s P2 Direction Register (P2DIR) s P3 Direction Register (P3DIR) s P4 Direction Register (P4DIR) s P6 Direction Register (P6DIR) s P7 Direction Register (P7DIR) s P8 Direction Register (P8DIR) s P9 Direction Register (P9DIR) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P10 Direction Register (P10DIR) s P11 Direction Register (P11DIR) s P12 Direction Register (P12DIR) s P13 Direction Register (P13DIR) s P14 Direction Register (P14DIR) s P15 Direction Register (P15DIR) s P16 Direction Register (P16DIR) s P17 Direction Register (P17DIR) s P18 Direction Register (P18DIR) s P19 Direction Register (P19DIR) s P20 Direction Register (P20DIR) s P21 Direction Register (P21DIR) s P22 Direction Register (P22DIR) D0 ( D8 Pn0DIR 1 9 Pn1DIR 2 10 Pn2DIR 3 11 Pn3DIR 4 12 Pn4DIR 5 13 Pn5DIR 6 14 Pn6DIR D7 D15 ) Pn7DIR Note: n = 0 to 22 (except for P5) 8-10 32170/32174 Group User's Manual (Rev. 2.1) 8 D 0 1 2 3 4 5 6 7 Bit Name INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers D 0-4 5 Bit Name No functions assigned P65MOD (Port P65 operation mode) 6 P66MOD (Port P66 operation mode) 7 P67MOD (Port P67 operation mode) Note 1: Port 60 is not accommodated. Note 2: Ports P61-P63 are always input/output ports (single-function pins). ___ Function R 0 W — 0 : P65 1 : SCLKI4 / SCLKO4 0 : P66 1 : SCLKI5 / SCLKO5 0 : P67 _____ 1 : ADTRG Note 3: Port P64 is an SBI input-only pin. The pin level can be verified by reading the P64 Data Register. 8-12 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P7 Operation Mode Register (P7MOD) D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 __ R W 1 : BCLK / WR 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK 8-13 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P8 Operation Mode Register (P8MOD) D 0, 1 2 Bit Name No functions assigned P82MOD (Port P82 operation mode) 3 P83MOD (Port P83 operation mode) 4 P84MOD (Port P84 operation mode) 5 P85MOD (Port P85 operation mode) 6 P86MOD (Port P86 operation mode) 7 P87MOD (Port P87 operation mode) 0 : P82 1 : TXD0 0 : P83 1 : RXD0 0 : P84 1 : SCLKI0 / SCLKO0 0 : P85 1 : TXD1 0 : P86 1 : RXD1 0 : P87 1 : SCLKI1 / SCLKO1 Function R 0 W — Note : Ports P80 and P81 are not accommodated. 8-14 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P9 Operation Mode Register (P9MOD) D 8 - 10 11 Bit Name No functions assigned P93MOD (Port P93 operation mode) 12 P94MOD (Port P94 operation mode) 13 P95MOD (Port P95 operation mode) 14 P96MOD (Port P96 operation mode) 15 P97MOD (Port P97 operation mode) 0 : P93 1 : TO16 0 : P94 1 : TO17 0 : P95 1 : TO18 0 : P96 1 : TO19 0 : P97 1 : TO20 Function R 0 W — Note : Ports P90 - P92 are not accommodated. 8-15 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P10 Operation Mode Register (P10MOD) D 0 Bit Name P100MOD (Port P100 operation mode) 1 P101MOD (Port P101 operation mode) 2 P102MOD (Port P102 operation mode) 3 P103MOD (Port P103 operation mode) 4 P104MOD (Port P104 operation mode) 5 P105MOD (Port P105 operation mode) 6 P106MOD (Port P106 operation mode) 7 P107MOD (Port P107 operation mode) Function 0 : P100 1 : TO8 0 : P101 1 : TO9 0 : P102 1 : TO10 0 : P103 1 : TO11 0 : P104 1 : TO12 0 : P105 1 : TO13 0 : P106 1 : TO14 0 : P107 1 : TO15 R W 8-16 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P11 Operation Mode Register (P11MOD) D 8 Bit Name P110MOD (Port P110 operation mode) 9 P111MOD (Port P111 operation mode) 10 P112MOD (Port P112 operation mode) 11 P113MOD (Port P113 operation mode) 12 P114MOD (Port P114 operation mode) 13 P115MOD (Port P115 operation mode) 14 P116MOD (Port P116 operation mode) 15 P117MOD (Port P117 operation mode) Function 0 : P110 1 : TO0 0 : P111 1 : TO1 0 : P112 1 : TO2 0 : P113 1 : TO3 0 : P114 1 : TO4 0 : P115 1 : TO5 0 : P116 1 : TO6 0 : P117 1 : TO7 R W 8-17 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P12 Operation Mode Register (P12MOD) D 0-3 4 Bit Name No functions assigned P124MOD (Port P124 operation mode) 5 P125MOD (Port P125 operation mode) 6 P126MOD (Port P126 operation mode) 7 P127MOD (Port P127 operation mode) 0 : P124 1 : TCLK0 0 : P125 1 : TCLK1 0 : P126 1 : TCLK2 0 : P127 1 : TCLK3 Function R 0 W — Note : Ports P120 - P123 are not accommodated. 8-18 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P13 Operation Mode Register (P13MOD) D 8 Bit Name P130MOD (Port P130 operation mode) 9 P131MOD (Port P131 operation mode) 10 P132MOD (Port P132 operation mode) 11 P133MOD (Port P133 operation mode) 12 P134MOD (Port P134 operation mode) 13 P135MOD (Port P135 operation mode) 14 P136MOD (Port P136 operation mode) 15 P137MOD (Port P137 operation mode) Function 0 : P130 1 : TIN16 0 : P131 1 : TIN17 0 : P132 1 : TIN18 0 : P133 1 : TIN19 0 : P134 1 : TIN20 0 : P135 1 : TIN21 0 : P136 1 : TIN22 0 : P137 1 : TIN23 R W 8-19 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P14 Operation Mode Register (P14MOD) D 0 Bit Name P140MOD (Port P140 operation mode) 1 P141MOD (Port P141 operation mode) 2 P142MOD (Port P142 operation mode) 3 P143MOD (Port P143 operation mode) 4 P144MOD (Port P144 operation mode) 5 P145MOD (Port P145 operation mode) 6 P146MOD (Port P146 operation mode) 7 P147MOD (Port P147 operation mode) Function 0 : P140 1 : TIN8 0 : P141 1 : TIN9 0 : P142 1 : TIN10 0 : P143 1 : TIN11 0 : P144 1 : TIN12 0 : P145 1 : TTIN13 0 : P146 1 : TIN14 0 : P147 1 : TIN15 R W 8-20 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P15 Operation Mode Register (P15MOD) D 8 Bit Name P150MOD (Port P150 operation mode) 9 P151MOD (Port P151 operation mode) 10 P152MOD (Port P152 operation mode) 11 P153MOD (Port P153 operation mode) 12 P154MOD (Port P154 operation mode) 13 P155MOD (Port P155 operation mode) 14 P156MOD (Port P156 operation mode) 15 P157MOD (Port P157 operation mode) Function 0 : P150 1 : TIN0 0 : P151 1 : TIN1 0 : P152 1 : TIN2 0 : P153 1 : TIN3 0 : P154 1 : TIN4 0 : P155 1 : TIN5 0 : P156 1 : TIN6 0 : P157 1 : TIN7 R W 8-21 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P16 Operation Mode Register (P16MOD) D 0 Bit Name P160MOD (Port P160 operation mode) 1 P161MOD (Port P161 operation mode) 2 P162MOD (Port P162 operation mode) 3 P163MOD (Port P163 operation mode) 4 P164MOD (Port P164 operation mode) 5 P165MOD (Port P165 operation mode) 6 P166MOD (Port P166 operation mode) 7 P167MOD (Port P167 operation mode) Function 0 : P160 1 : TO21 0 : P161 1 : TO22 0 : P162 1 : TO23 0 : P163 1 : TO24 0 : P164 1 : TO25 0 : P165 1 : TO26 0 : P166 1 : TO27 0 : P167 1 : TO28 R W 8-22 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P17 Operation Mode Register (P17MOD) D 8, 9 10 Bit Name No functions assigned P172MOD (Port P172 operation mode) 11 P173MOD (Port P173 operation mode) 12 P174MOD (Port P174 operation mode) 13 P175MOD (Port P175 operation mode) 14 P176MOD (Port P176 operation mode) 15 P177MOD (Port P177 operation mode) 0 : P172 1 : TIN24 0 : P173 1 : TIN25 0 : P174 1 : TXD2 0 : P175 1 : RXD2 0 : P176 1 : TXD3 0 : P177 1 : RXD3 Function R 0 W — Note : Ports P170 and P171 are not accommodated. 8-23 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P18 Operation Mode Register (P18MOD) D 0 Bit Name P180MOD (Port P180 operation mode) 1 P181MOD (Port P181 operation mode) 2 P182MOD (Port P182 operation mode) 3 P183MOD (Port P183 operation mode) 4 P184MOD (Port P184 operation mode) 5 P185MOD (Port P185 operation mode) 6 P186MOD (Port P186 operation mode) 7 P187MOD (Port P187 operation mode) Function 0 : P180 1 : TO29 0 : P181 1 : TO30 0 : P182 1 : TO31 0 : P183 1 : TO32 0 : P184 1 : TO33 0 : P185 1 : TO34 0 : P186 1 : TO35 0 : P187 1 : TO36 R W 8-24 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P19 Operation Mode Register (P19MOD) D 8 Bit Name P190MOD (Port P190 operation mode) 9 P191MOD (Port P191 operation mode) 10 P192MOD (Port P192 operation mode) 11 P193MOD (Port P193 operation mode) 12 P194MOD (Port P194 operation mode) 13 P195MOD (Port P195 operation mode) 14 P196MOD (Port P196 operation mode) 15 P197MOD (Port P197 operation mode) Function 0 : P190 1 : TIN26 0 : P191 1 : TIN27 0 : P192 1 : TIN28 0 : P193 1 : TIN29 0 : P194 1 : TIN30 0 : P195 1 : TIN31 0 : P196 1 : TIN32 0 : P197 1 : TIN33 R W 8-25 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P20 Operation Mode Register (P20MOD) D 0 Bit Name P200MOD (Port P200 operation mode) 1 P201MOD (Port P201 operation mode) 2 P202MOD (Port P202 operation mode) 3 P203MOD (Port P203 operation mode) 4-7 No functions assigned Function 0 : P200 1 :TXD4 0 : P201 1 : RXD4 0 : P202 1 : TXD5 0 : P203 1 : RXD5 0 — R W Note : Ports P204 - P207 are not accommodated. 8-26 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P21 Operation Mode Register (P21MOD) D 8 Bit Name P210MOD (Port P210 operation mode) 9 P211MOD (Port P211 operation mode) 10 P212MOD (Port P212 operation mode) 11 P213MOD (Port P213 operation mode) 12 P214MOD (Port P214 operation mode) 13 P215MOD (Port P215 operation mode) 14 P216MOD (Port P216 operation mode) 15 P217MOD (Port P217 operation mode) Function 0 : P210 1 : TO37 0 : P211 1 : TO38 0 : P212 1 : TO39 0 : P213 1 : TO40 0 : P214 1 : TO41 0 : P215 1 : TO42 0 : P216 1 : TO43 0 : P217 1 : TO44 R W 8-27 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P22 Operation Mode Register (P22MOD) D 0 Bit Name P220MOD (Port P220 operation mode) 1-3 4 No functions assigned P224MOD (Port P224 operation mode) 5 P225MOD (Port P225 operation mode) 6-7 No functions assigned 0 : P224 1 : Use inhibited 0 : P225 1 : Use inhibited 0 — Function 0 : P220 1 : CTX 0 — R W Note 1: P221 is a CAN input-only pin. Note 2: P222-P223 are always input/output ports (single-function pins). Note 3: P224 and P225 have their pin functions changed depending on how the MOD0 and MOD1 pins are set. Also, use of these ports requires caution because they have a debug event function. Note 4: P226 and P227 are not accommodated. 8-28 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s Port Input Function Enable Register (PIEN) D 8 - 14 15 Bit Name No functions assigned PIEN0 (Port input function enable bit) 0 : Disables input (to prevent current from flowing in) 1 : Enables input Function R 0 W — This register is provided to prevent current from flowing into the port input pin. Because after reset this register is set to disable input, it must be set to 1 before input can be processed. During boot mode, all pins shared with serial I/O function are enabled for input, so that when rewriting the flash memory via serial communication, you can set this register to 0 to prevent current from flowing in from any pins other than serial I/O function. The next page lists the pins that can be controlled by the Port Input Function Enable Register in each mode. 8-29 32170/32174 Group User's Manual (Rev. 2.1) 8 Mode Name INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Controllable Pins P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 Noncontrollable Pins P64, P221, FP Single chip P65 - P67, P70 - P77, P82 - P87 P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137, P140 - P147 P150 - P157, P160 - P167, P172 - P177 P180 - P187, P190 - P197, P200 - P203 P210 - P217, P220, P222 - P225 P61 - P63, P65 - P67, P70 - P77 P82 - P87, P93 -P97, P100 - P107 P00 - P07, P10 - P17 P20 - P27, P30 - P37 P41 - P47, P64, P221, P224 P225, FP Extended external Microprocessor P110 - P117, P124 - P127, P130 - P137 P140 - P147, P150 - P157, P160 - P167 P172 - P177, P180 - P187, P190 - P197 P200 - P203, P210 - P217, P220 P222 - P223 P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 P64, P65, P66, P82 - P87 P174 - P177, P200 - P203 P221, FP Boot (single chip) P67, P70 - P77, P93 - P97 P100 - P107, P110 - P117, P124 - P127 P130 - P137, P140 - P147, P150 - P157 P160 - P167, P172 - P173, P180 - P187 P190 - P197, P210 - P217, P220 P222 - P225 8-30 32170/32174 Group User's Manual (Rev. 2.1) 8 8.4 Port Peripheral Circuits INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) P20 - P27 (A23-A30) P30 - P37 (A15-A22) ___ ___ Direction register Data bus (DB0 - DB15) Port output latch P41 (BLW / BLE) ___ ___ P42 (BHW / BHE) __ P43 (RD) ___ P44 (CS0) ___ P45 (CS1) P46 - P47 (A13-A14) P61 - P63 P224 - P225 (A11-A12) P222 - P223 Input function enable Note 1: Ports P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, and P224-P225 when operating in extended external mode or processor mode, function as external bus interface control signals, but their functional description in this block diagram is omitted. _____ P67 (ADTRG) P75 (RTDRXD) P77 (RTDCLK) P83 (RXD0) Data bus P86 (RXD1) (DB0 - DB15) P124 - P127 (TCLK0-TCLK3) P130 - P137 (TIN16-TIN23) P140 - P147 (TIN8-TIN15) P150 - P157 (TIN0-TIN7) P172, P173 (TIN24, TIN25) P175 (RXD2) Peripheral P177 (RXD3) function input P190 - P197 (TIN26-TIN33) P201 (RXD4) P203 (RXD5) Direction register Port output latch Operation mode register Input function enable Note 2: denotes pins. Note 3: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 4: The input capacitance of each pin is approximately 10 pF. Figure 8.4.1 Port Peripheral Circuit Diagram (1) 8-31 32170/32174 Group User's Manual (Rev. 2.1) 8 ___ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P64 (SBI) P221 / CRX Data bus (DB0 - DB15) SBI ____ P72 (HREQ) Data bus (DB0 - DB15) Direction register Port output latch Operation mode register HREQ Input function enable Note 1: Note 2: denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 3: The input capacitance of each pin is approximately 10 pF. Figure 8.4.2 Port Peripheral Circuit Diagram (2) 8-32 32170/32174 Group User's Manual (Rev. 2.1) 8 ____ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P71 (WAIT) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register WAIT Input function enable __ P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) P76 (RTDACK) P82 (TXD0) P85 (TXD1) P93 - P97 (TO16-TO20) P100 - P107 (TO8-TO15) P110 - P117 (TO0-TO7) P160 - P167 (TO21-TO28) P174 (TXD2) P176 (TXD3) P180 - P187 (TO29-TO36) P200 (TXD4) P202 (TXD5) P210 - P217 (TO37-TO44) P220 (CTX) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register Peripheral function input Input function enable Note 1: denotes pins. Note 2: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 3: The input capacitance of each pin is approximately 10 pF. Figure 8.4.3 Port Peripheral Circuit Diagram (3) 8-33 32170/32174 Group User's Manual (Rev. 2.1) 8 P84(SCLKI0,SCLKO0) P87(SCLKI1,SCLKO1) P65(SCLKI4,SCLKO4) P66(SCLKI5,SCLKO5) Data bus (DB0 - DB15) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Direction register Port output latch Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function enable MOD0 MOD1 MOD0, MOD1 FP FP JTDI JTCK JTMS JTDI, JTCK, JTMS JTDO JTDO RESET XIN JTRST RESET, XIN, JTRST OSC-VCC VCCI VCCE VDD OSC-VCC, VCCI, VCCE, VDD Note 1: Note 2: denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Figure 8.4.4 Port Peripheral Circuit Diagram (4) 8-34 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/output Ports 8.5 Precautions on Input/output Ports • When using the ports in output mode Because the Port Data Register values immediately after a reset are indeterminate, it is necessary that the initial value be written to the Port Data Register before setting the Port Direction Register for output. Conversely, if the Port Direction Register is set for output before writing to the Port Data Register, indeterminate values will be output for a while until the initial value is set in the Port Data Register. 8-35 32170/32174 Group User's Manual (Rev. 2.1) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/output Ports ❊ This is a blank page. ❊ 8-36 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 9 DMAC 9.1 Outline of the DMAC 9.2 DMAC Related Registers 9.3 Functional Description of the DMAC 9.4 Precautions about the DMAC 9 9.1 Outline of the DMAC DMAC 9.1 Outline of the DMAC This microcomputer contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Number of channel Transfer request Description 10 channels • Software trigger • Request from internal peripheral I/Os: A-D converter,multijunction timer, serial I/O (reception completed, transmit buffer empty) • Transfer operation can be cascaded between DMA channels (Note) 256 times Maximum number of times transferred Transferable address space • 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, between internal RAMs are supported 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination: • Address fixed • Address incremental • Ring buffered Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 >channel 7 > channel 8 > channel 9 (Priority is fixed) 13.3 Mbytes per second (with 20 MHz internal peripheral clock) Group interrupt request can be generated when each transfer count register underflows. 64 Kbytes from H'0080 0000 to H'0080 FFFF (Transferable in the entire internal RAM/SFR area) Transfer data size Transfer method Transfer mode Direction of transfer Channel priority Maximum transfer rate Interrupt request Transfer area Note: Transfer operation can be cascaded between DMA channels as shown below. Completion of one transfer in channel 0 starts DMA transfer in channel 1 Completion of one transfer in channel 1 starts DMA transfer in channel 2 Completion of one transfer in channel 2 starts DMA transfer in channel 0 Completion of one transfer in channel 3 starts DMA transfer in channel 4 Completion of one transfer in channel 5 starts DMA transfer in channel 6 Completion of one transfer in channel 6 starts DMA transfer in channel 7 Completion of one transfer in channel 7 starts DMA transfer in channel 5 Completion of one transfer in channel 8 starts DMA transfer in channel 9 Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer in channel 5 9-2 32170/32174 Group User's Manual (Rev. 2.1) 9 DMA channel 0 Software start One DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) DMA request selector Source address register Destination address register Transfer count udf register DMAC 9.1 Outline of the DMAC DMA channel 1 Software start MJT (output event bus 0) MJT (TIN13 input signal) One DMA0 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 2 Software start MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) DMA request selector Source Destination Transfer count DMA start Determination block Software start One DMA7 transfer completed All DMA0 transfers completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 6 Software start Serial I/O1 (transmit buffer empty) MJT (TIN1 input signal) One DMA5 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 5 DMA request selector Source Destination Transfer count udf udf Interrupt request Internal bus arbitration DMA channel 7 Software start Serial I/O2 (transmit buffer empty) MJT (TIN2 input signal) One DMA6 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 8 Software start MJT (input event bus 0) Serial I/O3 (reception completed) MJT (TIN7 input signal) DMA request selector Source Destination Transfer count udf DMA channel 9 Software start Serial I/O3 (transmit buffer empty) MJT (TIN8 input signal) One DMA8 transfer completed DMA request selector Source Destination Transfer count DMA start Determination block udf Interrupt request Internal bus arbitration Figure 9.1.1 Block Diagram of the DMAC 9-3 32170/32174 Group User's Manual (Rev. 2.1) Internal bus 9 9.2 DMAC Related Registers DMAC 9.2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers. Address H'0080 0400 D0 +0 Address D7 D8 +1 Address DMA0-4 Interrupt Mask Register (DM04ITMK) D15 DMA0-4 Interrupt Request Status Register (DM04ITST) H'0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) Blank addresses are reserved. Note: The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.1 DMAC Related Register Map (1/2) 9-4 32170/32174 Group User's Manual (Rev. 2.1) 9 Address H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA9 Channel Control Register (DM9CNT) DMA4 Channel Control Register (DM4CNT) DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D0 +0 Address DMA3 Channel Control Register (DM3CNT) D7 D8 +1 Address DMA3 Transfer Count Register (DM3TCT) D15 DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) Blank addresses are reserved. Note: The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.2 DMAC Related Register Map (2/2) 9-5 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.1 DMA Channel Control Register s DMA0 Channel Control Register (DM0CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL0 (Selects DMA0 transfer mode) 1 TREQF0 (DMA0 transfer request flag) 2, 3 REQSL0 (Selects cause of DMA0 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start or one DMA2 transfer completed 01 : A-D0 conversion completed 10 : MJT (TIO8_udf) 11 : MJT (input event bus 2) 4 TENL0 (Enables DMA0 transfer) 5 TSZSL0 (Selects DMA0 transfer size) 6 SADSL0 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA0 source address direction) 1 : Incremental 7 DADSL0 (Selects DMA0 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-6 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA1 Channel Control Register (DM1CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL1 (Selects DMA1 transfer mode) 1 TREQF1 (DMA1 transfer request flag) 2, 3 REQSL1 (Selects cause of DMA1 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (output event bus 0) 10 : MJT (TIN13 input signal) 11 : One DMA0 transfer completed 4 TENL1 (Enables DMA1 transfer) 5 TSZSL1 (Selects DMA1 transfer size) 6 SADSL1 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA1 source address direction) 1 : Incremental 7 DADSL1 (Selects DMA1 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-7 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA2 Channel Control Register (DM2CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL2 (Selects DMA2 transfer mode) 1 TREQF2 (DMA2 transfer request flag) 2, 3 REQSL2 (Selects cause of DMA2 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (output event bus 1) 10 : MJT (TIN18 input signal) 11 : One DMA1 transfer completed 4 TENL2 (Enables DMA2 transfer) 5 TSZSL2 (Selects DMA2 transfer size) 6 SADSL2 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA2 source address direction) 1 : Incremental 7 DADSL2 (Selects DMA2 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-8 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA3 Channel Control Register (DM3CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL3 (Selects DMA3 transfer mode) 1 TREQF3 (DMA3 transfer request flag) 2, 3 REQSL3 (Selects cause of DMA3 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O0 (transmit buffer empty) 10 : Serial I/O1 (reception completed) 11 : MJT (TIN0 input signal) 4 TENL3 (Enables DMA3 transfer) 5 TSZSL3 (Selects DMA3 transfer size) 6 SADSL3 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA3 source address direction) 1 : Incremental 7 DADSL3 (Selects DMA3 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-9 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA4 Channel Control Register (DM4CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL4 (Selects DMA4 transfer mode) 1 TREQF4 (DMA4 transfer request flag) 2, 3 REQSL4 (Selects cause of DMA4 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : One DMA3 transfer completed 10 : Serial I/O0 (reception completed) 11 : MJT (TIN19 input signal) 4 TENL4 (Enables DMA4 transfer) 5 TSZSL4 (Selects DMA4 transfer size) 6 SADSL4 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA4 source address direction) 1 : Incremental 7 DADSL4 (Selects DMA4 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-10 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA5 Channel Control Register (DM5CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL5 (Selects DMA5 transfer mode) 1 TREQF5 (DMA5 transfer request flag) 2, 3 REQSL5 (Selects cause of DMA5 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start or one DMA7 transfer completed 01 : All DMA0 transfers completed 10 : Serial I/O2 (reception completed) 11 : MJT (TIN20 input signal) 4 TENL5 (Enables DMA5 transfer) 5 TSZSL5 (Selects DMA5 transfer size) 6 SADSL5 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA5 source address direction) 1 : Incremental 7 DADSL5 (Selects DMA5 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-11 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA6 Channel Control Register (DM6CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL6 (Selects DMA6 transfer mode) 1 TREQF6 (DMA6 transfer request flag) 2, 3 REQSL6 (Selects cause of DMA6 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O1 (transmit buffer empty) 10 : MJT (TIN1 input signal) 11 : One DMA5 transfer completed 4 TENL6 (Enables DMA6 transfer) 5 TSZSL6 (Selects DMA6 transfer size) 6 SADSL6 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA6 source address direction) 1 : Incremental 7 DADSL6 (Selects DMA6 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-12 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA7 Channel Control Register (DM7CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL7 (Selects DMA7 transfer mode) 1 TREQF7 (DMA7 transfer request flag) 2, 3 REQSL7 (Selects cause of DMA7 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O2 (transmit buffer empty) 10 : MJT (TIN2 input signal) 11 : One DMA6 transfer completed 4 TENL7 (Enables DMA7 transfer) 5 TSZSL7 (Selects DMA7 transfer size) 6 SADSL7 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA7 source address direction) 1 : Incremental 7 DADSL7 (Selects DMA7 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-13 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL8 (Selects DMA8 transfer mode) 1 TREQF8 (DMA8 transfer request flag) 2, 3 REQSL8 (Selects cause of DMA8 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : MJT (input event bus 0) 10 : Serial I/O3 (reception completed) 11 : MJT (TIN7 input signal) 4 TENL8 (Enables DMA8 transfer) 5 TSZSL8 (Selects DMA8 transfer size) 6 SADSL8 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA8 source address direction) 1 : Incremental 7 DADSL8 (Selects DMA8 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-14 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA9 Channel Control Register (DM9CNT) DMAC 9.2 DMAC Related Registers D 0 Bit Name MDSEL9 (Selects DMA9 transfer mode) 1 TREQF9 (DMA9 transfer request flag) 2, 3 REQSL9 (Selects cause of DMA9 request) Function 0 : Normal mode 1 : Ring buffer mode 0 : Not requested 1 : Requested 00 : Software start 01 : Serial I/O3 (transmit buffer empty) 10 : MJT (TIN8 input signal) 11 : One DMA8 transfer completed 4 TENL9 (Enables DMA9 transfer) 5 TSZSL9 (Selects DMA9 transfer size) 6 SADSL9 0 : Disables transfer 1 : Enables transfer 0 : 16 bits 1 : 8 bits 0 : Fixed R W (Selects DMA9 source address direction) 1 : Incremental 7 DADSL9 (Selects DMA9 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-15 32170/32174 Group User's Manual (Rev. 2.1) 9 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA transfer, and set the transfer size and the source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal mode or ring buffer mode. Normal mode is selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). No interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn transfer request flag) bit (D1) This flag is set to 1 when a DMA transfer request occurs. Reading this flag helps to know DMA transfer requests in each channel. The generated DMA request is cleared by writing a 0 to this bit. If you write a 1, the value you wrote is ignored and the bit retains its previous value. If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1, the next DMA transfer request is not accepted until the transfer under way in that channel is completed. (3) REQSLn (cause of DMAn request select) bits (D2, D3) These bits select the cause of DMA request in each DMA channel. (4) TENLn (DMAn transfer enable) bit (D4) Transfer is enabled by setting this bit to 1, so that the channel is ready for DMA transfer. Conversely, transfer is disabled by setting this bit to 0. However, if a transfer request has already been accepted, transfer in that channel is not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn transfer size select) bit (D5) This bit selects the number of bits to be transferred in one DMA transfer operation (unit of one transfer). The unit of one transfer is 16 bits when TSZSL = 0 or 8 bits when TSZSL = 1. (6) SADSLn (DMAn source address direction select) bit (D6) This bit selects the direction in which the source address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. (7) DADSLn (DAMn destination address direction select) bit (D7) This bit selects the direction in which the destination address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. 9-16 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.2 DMA Software Request Generation Registers s DMA0 Software Request Generation Register (DM0SRI) s DMA1 Software Request Generation Register (DM1SRI) s DMA2 Software Request Generation Register (DM2SRI) s DMA3 Software Request Generation Register (DM3SRI) s DMA4 Software Request Generation Register (DM4SRI) s DMA5 Software Request Generation Register (DM5SRI) s DMA6 Software Request Generation Register (DM6SRI) s DMA7 Software Request Generation Register (DM7SRI) s DMA8 Software Request Generation Register (DM8SRI) s DMA9 Software Request Generation Register (DM9SRI) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SRI - DM9SRI D 0 - 15 Bit Name DM0SRI - DM9SRI Function DMA transfer request is generated R ? W (Generates DMA software request) by writing any data Note: This register can be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when "Software start" has been selected for the cause of DMA request. DM0SRI - DM9SRI (DMA software request generate) bit A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "Software" is selected as the cause of DMA transfer request (by setting the DMA Channel Control Register D2, D3 bits to "00"). 9-17 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.3 DMA Source Address Registers s DMA0 Source Address Register (DM0SA) s DMA1 Source Address Register (DM1SA) s DMA2 Source Address Register (DM2SA) s DMA3 Source Address Register (DM3SA) s DMA4 Source Address Register (DM4SA) s DMA5 Source Address Register (DM5SA) s DMA6 Source Address Register (DM6SA) s DMA7 Source Address Register (DM7SA) s DMA8 Source Address Register (DM8SA) s DMA9 Source Address Register (DM9SA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SA - DM9SA D 0 - 15 Bit Name DM0SA - DM9SA Function A16-A31 of the source address (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. R W The DMA Source Address Register is used to set the source address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Source Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0SA-DM9SA (A16-A31 of the source address) By setting this register, specify the source address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the source address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the source address (with D0 corresponding to A16, and D15 corresponding to A31). 9-18 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.4 DMA Destination Address Registers s DMA0 Destination Address Register (DM0DA) s DMA1 Destination Address Register (DM1DA) s DMA2 Destination Address Register (DM2DA) s DMA3 Destination Address Register (DM3DA) s DMA4 Destination Address Register (DM4DA) s DMA5 Destination Address Register (DM5DA) s DMA6 Destination Address Register (DM6DA) s DMA7 Destination Address Register (DM7DA) s DMA8 Destination Address Register (DM8DA) s DMA9 Destination Address Register (DM9DA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0DA - DM9DA D 0 - 15 Bit Name DM0DA - DM9DA Function A16-A31 of the destination address (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. R W The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because access to this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same destination address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Destination Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0DA-DM9DA (A16-A31 of the destination address) By setting this register, specify the destination address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the destination address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the destination address (with D0 corresponding to A16, and D15 corresponding to A31). 9-19 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.5 DMA Transfer Count Registers s DMA0 Transfer Count Register (DM0TCT) s DMA1 Transfer Count Register (DM1TCT) s DMA2 Transfer Count Register (DM2TCT) s DMA3 Transfer Count Register (DM3TCT) s DMA4 Transfer Count Register (DM4TCT) s DMA5 Transfer Count Register (DM5TCT) s DMA6 Transfer Count Register (DM6TCT) s DMA7 Transfer Count Register (DM7TCT) s DMA8 Transfer Count Register (DM8TCT) s DMA9 Transfer Count Register (DM9TCT) D8 9 10 11 12 13 DMAC 9.2 DMAC Related Registers 14 D15 DM0TCT - DM9TCT D 8 - 15 Bit Name DM0TCT - DM9TCT Function DMA transfer count (ignored during 32-channel ring buffer mode) R W The DMA Transfer Count Register is used to set the number of times data is transferred in each channel. However, the value in this register is ignored during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the value you get by reading this register is always the current value. (However, if you read this register in a cycle immediately after transfer, the value you get is the value that was in the count register before the transfer began.) When transfer finishes, this count register underflows, so that the read value you get is H'FF. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts. 9-20 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.6 DMA Interrupt Request Status Registers s DMA0-4 Interrupt Request Status Register (DM04ITST) DMAC 9.2 DMAC Related Registers D 0-2 3 4 5 6 7 W= Bit Name No functions assigned DMITST4 (DMA4 interrupt request status) DMITST3 (DMA3 interrupt request status) DMITST2 (DMA2 interrupt request status) DMITST1 (DMA1 interrupt request status) DMITST0 (DMA0 interrupt request status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt requested Function R 0 W — The DMA0-4 Interrupt Request Status Register lets you know the status of interrupt requests in channels 0-4. If the DMAn interrupt request status bit (n = 0 to 4) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 0 to 4) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "Interrupt cause bit" of the DMA Interrupt Control Register that the interrupt controller has. When writing to the DMA0-4 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-21 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA5-9 Interrupt Request Status Register (DM59ITST) DMAC 9.2 DMAC Related Registers D 0-2 3 4 5 6 7 W= Bit Name No functions assigned DMITST9 (DMA9 interrupt request status) DMITST8 (DMA8 interrupt request status) DMITST7 (DMA7 interrupt request status) DMITST6 (DMA6 interrupt request status) DMITST5 (DMA5 interrupt request status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt requested Function R 0 W — The DMA5-9 Interrupt Request Status Register lets you know the status of interrupt requests in channels 5-9. If the DMAn interrupt request status bit (n = 5 to 9) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 5 to 9) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "Interrupt cause bit" of the DMA Interrupt Control Register that the interrupt controller has. When writing to the DMA5-9 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-22 32170/32174 Group User's Manual (Rev. 2.1) 9 9.2.7 DMA Interrupt Mask Registers s DMA0-4 Interrupt Mask Register (DM04ITMK) DMAC 9.2 DMAC Related Registers D 8 - 10 11 12 13 14 15 Bit Name No functions assigned DMITMK4 (DMA4 interrupt request mask) DMITMK3 (DMA3 interrupt request mask) DMITMK2 (DMA2 interrupt request mask) DMITMK1 (DMA1 interrupt request mask) DMITMK0 (DMA0 interrupt request mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — The DMA0-4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0-4. DMITMKn (DMAn interrupt request mask) bit (n = 0 to 4) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-23 32170/32174 Group User's Manual (Rev. 2.1) 9 s DMA5-9 Interrupt Mask Register (DM59ITMK) DMAC 9.2 DMAC Related Registers D 8 - 10 11 12 13 14 15 Bit Name No functions assigned DMITMK9 (DMA9 interrupt request mask) DMITMK8 (DMA8 interrupt request mask) DMITMK7 (DMA7 interrupt request mask) DMITMK6 (DMA6 interrupt request mask) DMITMK5 (DMA5 interrupt request mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — The DMA5-9 Interrupt Mask Register is used to mask interrupt requests in DMA channels 5-9. DMITMKn (DMAn interrupt request mask) bit (n = 5 to 9) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-24 32170/32174 Group User's Manual (Rev. 2.1) 9 DM04ITST DMA4UDF Data bus b3 b11 DMITST4 F/F DMITMK4 F/F DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 0 (Level) DMA3UDF DMITST3 b4 b12 F/F DMITMK3 F/F DMA2UDF DMITST2 b5 b13 F/F DMITMK2 F/F DMA1UDF DMITST1 b6 b14 F/F DMITMK1 F/F DMA0UDF DMITST0 b7 b15 F/F DMITMK0 F/F Figure 9.2.3 Block Diagram of DMA Transfer Interrupt 0 9-25 32170/32174 Group User's Manual (Rev. 2.1) 9 DM59ITST DMA9UDF Data bus b3 b11 DMITST9 F/F DMITMK9 F/F DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 1 (Level) DMA8UDF DMITST8 b4 b12 F/F DMITMK8 F/F DMA7UDF DMITST7 b5 b13 F/F DMITMK7 F/F DMA6UDF DMITST6 b6 b14 F/F DMITMK6 F/F DMA5UDF DMITST5 b7 b15 F/F DMITMK5 F/F Figure 9.2.4 Block Diagram of DMA Transfer Interrupt 1 9-26 32170/32174 Group User's Manual (Rev. 2.1) 9 9.3 Functional Description of the DMAC 9.3.1 Cause of DMA Request DMAC 9.3 Functional Description of the DMAC For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources. There are various causes (or sources) of DMA transfer, so that DMA transfer can be started by a request from internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers in a DMA channel (cascade mode). The cause of DMA request is selected using the cause of request select bit provided for each channel, REQSLn (DMAn Channel Control Register bits D2, D3). The table below lists the causes of DMA requests in each channel. Table 9.3.1 Causes of DMA Requests in DMA0 and Generation Timings REQSL0 0 0 Cause of DMA Request Software start or one DMA2 transfer completed DMA Request Generation Timing When any data is written to DMA0 Software Request Generation Register (software start) or one DMA2 transfer is completed (cascade mode) 0 1 1 1 0 1 A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) When A-D0 conversion is completed When MJT TIO8 underflow occurs When MJT's input event bus 2 signal is generated Table 9.3.2 Causes of DMA Requests in DMA1 and Generation Timings REQSL1 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA1 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 0) MJT (TIN13 input signal) One DMA0 transfer completed When MJT's output event bus 0 signal is generated When MJT's TIN13 input signal is generated When one DMA0 transfer is completed (cascade mode) 9-27 32170/32174 Group User's Manual (Rev. 2.1) 9 REQSL2 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings DMA Request Generation Timing When any data is written to DMA2 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed When MJT's output event bus 1 signal is generated When MJT's TIN18 input signal is generated When one DMA1 transfer is completed (cascade mode) Table 9.3.4 Causes of DMA Requests in DMA3 and Generation Timings REQSL3 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA3 Software Request Generation Register 0 1 1 1 0 1 Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) When serial I/O0 transmit buffer is emptied When serial I/O1 reception is completed When MJT's TIN0 input signal is generated Table 9.3.5 Causes of DMA Requests in DMA4 and Generation Timings REQSL4 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA4 Software Request Generation Register 0 1 1 1 0 1 One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) When one DMA3 transfer is completed (cascade mode) When serial I/O0 reception is completed When MJT's TIN19 input signal is generated 9-28 32170/32174 Group User's Manual (Rev. 2.1) 9 REQSL5 0 0 Cause of DMA Request Software start or one DMA7 transfer completed DMAC 9.3 Functional Description of the DMAC Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings DMA Request Generation Timing When any data is written to DMA5 Software Request Generation Register or one DMA7 transfer is completed (cascade mode) 0 1 1 1 0 1 All DMA0 transfers completed Serial I/O2 (reception completed) MJT (TIN20 input signal) When all DMA0 transfers are completed (cascade mode) When serial I/O2 reception is completed When MJT's TIN20 input signal is generated Table 9.3.7 Causes of DMA Requests in DMA6 and Generation Timings REQSL6 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA6 Software Request Generation Register 0 1 1 1 0 1 Serial I/O1 (transmit buffer empty) MJT (TIN1 input signal) One DMA5 transfer completed When serial I/O1 transmit buffer is emptied When MJT's TIN1 input signal is generated When one DMA5 transfer is completed (cascade mode) Table 9.3.8 Causes of DMA Requests in DMA7 and Generation Timings REQSL7 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA7 Software Request Generation Register 0 1 1 1 0 1 Serial I/O2 (transmit buffer empty) MJT (TIN2 input signal) One DMA6 transfer completed When serial I/O2 transmit buffer is emptied When MJT's TIN2 input signal is generated When one DMA6 transfer is completed (cascade mode) 9-29 32170/32174 Group User's Manual (Rev. 2.1) 9 REQSL8 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.9 Causes of DMA Requests in DMA8 and Generation Timings DMA Request Generation Timing When any data is written to DMA8 Software Request Generation Register 0 1 1 1 0 1 MJT (input event bus 0) Serial I/O3 (reception completed) MJT (TIN7 input signal) When MJT's input event bus 0 signal is generated When serial I/O3 reception is completed When MJT's TIN7 input signal is generated Table 9.3.10 Causes of DMA Requests in DMA9 and Generation Timings REQSL9 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA9 Software Request Generation Register 0 1 1 1 0 1 Serial I/O3 (transmit buffer empty) MJT (TIN8 input signal) One DMA8 transfer completed When serial I/O3 transmit buffer is emptied When MJT's TIN8 input signal is generated When one DMA8 transfer is completed (cascade mode) 9-30 32170/32174 Group User's Manual (Rev. 2.1) 9 9.3.2 DMA Transfer Processing Procedure DMAC 9.3 Functional Description of the DMAC Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0. DMA transfer processing starts Setting interrupt controller related registers Set the interrupt controller's DMA0-4 Interrupt Control Register • Interrupt priority level Set DMA0 Channel Control Register • Transfers disabled Set DMA0-4 Interrupt Request Status Register • Clears interrupt request status bit • Enables interrupt request Set DMA0-4 Interrupt Mask Register Setting DMAC related registers Set DMA0 Source Address Register • Source address of transfer Set DMA0 Destination Address Register • Address Set DMA0 Count Register • Number of times DMA transfer performed • Transfer mode, cause of request, transfer size, address direction, and transfer enable Set DMA0 Channel Control Register Starting DMA transfer DMA transfer starts as requested by internal peripheral I/O Transfer count register underflows DMA transfer completed Interrupt request generated DMA operation completed Figure 9.3.1 Example of a DMA Transfer Processing Procedure 9-31 32170/32174 Group User's Manual (Rev. 2.1) 9 9.3.3 Starting DMA DMAC 9.3 Functional Description of the DMAC Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1. Note: If the requesting source selected with the REQSL (DMA request source select) bit is MJT (TIN input signal), it takes at least three cycles (e.g., 150 ns when the internal peripheral clock is operating with 20 MHz) before DMA transfer begins after detecting the rising or falling edge or both edges of the TIN input signal. Or, depending on the bus usage condition before or after that, up to six cycles (e.g., 300 ns when the internal peripheral clock is operating with 20 MHz) may be needed. (Note, however, that this applies to the case where external bus, HOLD, and LOCK instruction are unused.) To ensure that changes of the TIN input signal are detected correctly, apply a TIN input signal in pulse width of 7 tc (BCLK)/2 or more. (For details, see Section 21.5, “ AC Characteristics.”) 9.3.4 Channel Priority Channel 0 has the highest priority. The priority of this and other channels is shown below. Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are requested, the channel that has the highest priority is selected. Channel selection is made every transfer cycle (one DMA bus cycle consisting of three machine cycles). 9-32 32170/32174 Group User's Manual (Rev. 2.1) 9 DMAC 9.3 Functional Description of the DMAC 9.3.5 Gaining and Releasing Control of the Internal Bus For any channel, control of the internal bus is gained and released in "single transfer DMA" mode. In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA operation in single transfer DMA. Requested Internal bus arbitration (control requested by DMAC) Gained Requested Gained Requested Gained CPU Internal bus DMAC R W Released Released Released R W R W One DMA transfer One DMA transfer R: Read W: Write One DMA transfer Figure 9.3.2 Gaining and Releasing Control of the Internal Bus 9.3.6 Transfer Units Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one each time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. 9-33 32170/32174 Group User's Manual (Rev. 2.1) 9 9.3.8 Address Space DMAC 9.3 Functional Description of the DMAC The address space in which data can be transferred by DMA is the internal peripheral I/O or 64 Kbytes of RAM space (H'0080 0000 through H'0080 FFFF) for either source or destination. To set the source and destination addresses in each channel, use the DMA Source Address Register and DMA Destination Address Register. 9.3.9 Transfer Operation (1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is temporarily taken into the DMA's internal temporary register.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, the same applies to both bus protocol and bus timing as in peripheral module access from the CPU. (3) Transfer rate The maximum transfer rate is calculated using the equation below: Maximum transfer rate [bytes/second] = 2 bytes × 1 1 / f (BCLK) × 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Address fixed Transfer Unit 8 bits 16 bits Address incremental 8 bits 16 bits Address Change for One DMA 0 0 +1 +2 9-34 32170/32174 Group User's Manual (Rev. 2.1) 9 (5) Transfer count value DMAC 9.3 Functional Description of the DMAC The transfer count value is decremented by one at a time irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit = 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) When the transfer unit = 8 bits, the LSB of the address register (D15 of the address register) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid transfer byte positions. + 0 8 bits + 1 8 bits + 0 + 1 D0 D7 D8 D15 D0 D7 D8 16 bits D15 Source Destination 8 bits 8 bits 16 bits Figure 9.3.3 Transfer Byte Positions 9-35 32170/32174 Group User's Manual (Rev. 2.1) 9 (7) Ring buffer mode DMAC 9.3 Functional Description of the DMAC When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B'00000. The address increment operation in ring buffer mode is described below. (a) When the transfer unit = 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B'11111, they are recycled to B'00000 by the next increment operation, thus returning to the start address again. (b) When the transfer unit = 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B'111110, they are recycled to B'000000 by the next increment operation, thus returning to the start address again. When the source address has been set to be incremented, it is the source address that recycles to the start address; when the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially being B'00000. During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to (to disable transfer). Transfer count 1 2 3 | 31 32 ↓ 1 2 | Transfer address H'0080 1000 H'0080 1001 H'0080 1002 | H'0080 101E H'0080 101F ↓ H'0080 1000 H'0080 1001 | Transfer count 1 2 3 | 31 32 ↓ 1 2 | Transfer address H'0080 1000 H'0080 1002 H'0080 1004 | H'0080 103C H'0080 103E ↓ H'0080 1000 H'0080 1002 | Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode 9-36 32170/32174 Group User's Manual (Rev. 2.1) 9 9.3.10 End of DMA and Interrupt DMAC 9.3 Functional Description of the DMAC In normal mode, DMA transfer is terminated when the transfer count register underflows. When transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, this interrupt is not generated for channels where interrupt requests have been masked by the DMA Interrupt Mask Register. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to 0 (to disable transfer). In this case, therefore, the DMA transfer-completed interrupt request is not generated. Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 Status of Each Register after Completion of DMA Transfer When DMA transfer is completed, the status of the source address and destination address registers becomes as follows: (1) Address fixed • The value set in the address register before DMA transfer started remains intact (fixed). (2) Address incremental • For 8-bit transfer, the value of the address register is the last transfer address + 1. • For 16-bit transfer, the value of the address register is the last transfer address + 2. The transfer count register when DMA transfer completed is in an underflow state (H'FF). Therefore, to perform another DMA transfer, set the transfer count register newly again, except when you are performing transfers 256 times (H'FF). 9-37 32170/32174 Group User's Manual (Rev. 2.1) 9 9.4 Precautions about the DMAC • About writing to DMAC related registers DMAC 9.4 Precautions about the DMAC Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). When transfer is enabled, do not write to the DMAC related registers because write operation to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer Count Register which is protected in hardware, is instable. The table below shows the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status When transfer is enabled When transfer is disabled : Can be accessed ; ✕ : Cannot be accessed Transfer enable bit Transfer request flag Other DMAC related registers ✕ For even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. (a) DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. Note that you only can write a 0 to the transfer request flag as valid data. (b) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. (c) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case, you are writing to the DMAC related registers while DMA is enabled, but this practically does not present any problem. However, you cannot DMA-transfer to the DMAC related registers on the local channel itself in which you are currently operating. 9-38 32170/32174 Group User's Manual (Rev. 2.1) 9 DMAC 9.4 Precautions about the DMAC • Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) Only if residing on other channels, you can write to the DMAC related registers by means of DMA transfer. (For example, you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0.) • About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write 1s to all bits but the one you want to clear. The bits to which you wrote 1s retain the previous data they had before the write. • About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the DMA Channel Control Register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another. 9-39 32170/32174 Group User's Manual (Rev. 2.1) 9 DMAC 9.4 Precautions about the DMAC * This is a blank page.* 9-40 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.2 Common Units of Multijunction Timer 10.3 TOP (Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16bit Timer) 10.5 TMS (Input-related 16-bit Timer) 10.6 TML (Input-related 32-bit Timer) 10.7 TID (Input-related 16-bit Timer) 10.8 TOD (Output-related 16-bit Timer) 10.9 TOM (Output-related 16-bit Timer) 10 10.1 Outline of Multijunction Timers MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event bus at multiple points that they are called the "multijunction" timers. This microcomputer has seven types of multijunction timers as listed in the table below, providing a total of 64 channels of timers. Table 10.1.1 Outline of Multijunction Timers (1/2) Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) Number of Channels Description 11 One of three output modes can be selected by software. • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TIO (Timer Input Output) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) Input-related 16-bit timer (up-counter) Input-related 32-bit timer (up-counter) 8 32-bit input measure timer 8 16-bit input measure timer 10-2 32170/32174 Group User's Manual (Rev. 2.1) 10 Table 10.1.1 Outline of Multijunction Timers (2/2) Name TID (Timer Input Derivation) Type Input-related 16-bit timer (up/down-counter) Number of Channels 3 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Description One of three input modes can be selected by software. • Fixed period mode • Event count mode • Multiply-by-4 event count mode TOD (Timer Output Derivation) Output-related 16-bit timer (down-counter) 16 One of four output modes can be selected by software. • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TOM (Timer Output Modification) Output-related 16-bit timer (down-counter) 8 One of four output modes can be selected by software. • PWM output mode • Single-shot PWM output mode • Single-shot output mode • Continuous output mode Table 10.1.2 MJT Interrupt Generation Functions of the M32170 Signal Name IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Source of MJT Interrupt Requested TIN30 - TIN33 input TID2 output TOD1_0 - TOD1_7 output, TOM0_0 - TOM0_7 output TID1 output TID0 output TOD0_0 - TOD0_7 output TIN3 - TIN6 input TIN20 - TIN23 input TIN12 - TIN19 input TIN0 - TIN2 input TIN7 - TIN11 input TMS0, TMS1 output TOP8, TOP9 output TOP10 output TIO4 - 7 output TIO8, TIO9 output TOP0 - 5 output TOP6, TOP7 output TIO0 - 3 output TID1 output interrupt TID0 output interrupt TOD0 output interrupt MJT input interrupt 4 MJT input interrupt 3 MJT input interrupt 2 MJT input interrupt 1 MJT input interrupt 0 MJT output interrupt 7 MJT output interrupt 6 MJT output interrupt 5 MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 MJT output interrupt 0 1 1 8 4 4 8 3 5 2 2 1 4 2 6 2 4 Interrupt Controller (ICU) Input TML1 input interrupt TID2 output interrupt TOD1+TOM0 output interrupt ICU Cause Input 4 1 16 10-3 32170/32174 Group User's Manual (Rev. 2.1) 10 Signal Name DRQ0 DRQ1 DRQ2 DRQ3 DRQ4 DRQ5 DRQ6 DRQ7 DRQ8 DRQ9 DRQ10 DRQ11 DRQ12 DRQ13 Source of DMA Request Generated TIO8 underflow Input event bus 2 Output event bus 0 TIN13 input Output event bus 1 TIN18 input TIN19 input TIN0 input TIN1 input TIN2 input TIN7 input TIN8 input TIN20 input Input event bus 0 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Table 10.1.3 DMA Transfer Request Generation by MJT DMAC Input Channel Channel 0 Channel 0 Channel 1 Channel 1 Channel 2 Channel 2 Channel 4 Channel 3 Channel 6 Channel 7 Channel 8 Channel 9 Channel 5 Channel 8 Table 10.1.4 A-D Conversion Start Request by MJT Signal Name AD0TRG AD1TRG Source of A-D Conversion Start Requested Output event bus 3 TID1 overflow/underflow A-D Converter Can be input to A-D0 conversion start trigger Can be input to A-D1 conversion start trigger 10-4 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus S TCLK0 TCLK0S (Note 1) 3 21 0 3 21 0 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus IRQ2 0 12 3 clk clk clk en en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 TOP 7 udf IRQ2 udf IRQ2 udf IRQ2 udf IRQ2 clk clk udf IRQ2 udf IRQ1 udf IRQ1 clk udf IRQ6 clk clk clk en en en en/cap en/cap en/cap en/cap en/cap TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf IRQ6 udf IRQ5 udf IRQ0 clk udf IRQ0 udf IRQ0 udf IRQ0 udf IRQ4 udf S F/F14 TO 14 S F/F13 TO 13 S F/F12 TO 12 S F/F11 TO 11 S F/F10 TO 10 S F/F9 TO 9 S F/F8 TO 8 S F/F7 TO 7 S F/F5 F/F6 TO 5 TO 6 F/F4 TO 4 F/F2 F/F3 TO 2 TO 3 F/F1 TO 1 F/F0 TO 0 IRQ9 TIN0 TIN0S DRQ7 S clk IRQ9 TIN1 TIN1S DRQ8 IRQ9 TIN2 TIN2S DRQ9 IRQ12 TIN3 TIN4 TIN5 TIN3S TIN4S TIN5S IRQ12 IRQ12 S S S S S clk S S clk S clk S clk IRQ12 TIN6 1/2 internal peripheral clock TCLK1 TIN7 TCLK2 TIN8 TIN6S PRS0 PRS1 PRS2 TCLK1S TIN7S TCLK2S IRQ8 TIN8S DRQ11 IRQ8 TIN9 TIN9S IRQ8 TIN10 TIN10S IRQ8 TIN11 TIN11S 3 21 0 3 21 0 DRQ10 S S clk S F/F15 TO 15 AD0TRG (To A-D0 converter) S IRQ4 IRQ8 S S IRQ4 S S S S S S IRQ3 S S 0 123 clk en/cap TIO 5 udf S F/F16 TO 16 clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 clk en/cap TIO 7 udf DRQ0 IRQ3 S F/F18 TO 18 clk en/cap TIO 8 udf S F/F19 TO 19 clk en/cap TIO 9 udf F/F20 TO 20 PRS0 - 5 : Prescaler F/F : Output flip-flop S : Selector Note 1: IRQ0-18 denote interrupt signals, of which the same number indicates the same group of interrupts. (See Table 10.1.2.) DRQ0-13 denote DMA request signals fed to the DMAC. (See Table 10.1.3.) AD0TRG and AD1TRG denote trigger signals to A-D0 and A-D1 converters, respectively. Note 2: Indicates timer input pin edge selection output. Note 3: Indicates input signals from peripheral circuits (AD and SIO). Figure 10.1.1 Block Diagram of MJT (1/4) 10-5 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3 21 0 3 21 0 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0 12 3 TCLK3 TIN12 TIN13 TIN14 TCLK3S IRQ10 TIN12S IRQ10 TIN13S DRQ3 IRQ10 TIN14S IRQ10 TIN15S S S clk cap3 TMS 0 cap2 cap1 IRQ7 cap0 ovf S S TIN15 S S IRQ10 TIN16 TIN16S IRQ10 TIN17 TIN17S IRQ10 TIN18 TIN18S DRQ5 IRQ10 TIN19 1/2 internal peripheral clock TIN20 TIN21 TIN22 TIN23 1/2 internal peripheral clock TIN30 TIN31 TIN32 TIN33 TIN20S TIN21S TIN22S TIN23S TIN19S DRQ6 DRQ12 IRQ11 IRQ11 S S S clk cap3 TMS 1 cap2 cap1 cap0 ovf IRQ7 S S S clk cap3 TML0 cap2 cap1 cap0 S IRQ11 S IRQ11 S S IRQ18 TIN30S TIN31S TIN32S TIN33S S IRQ18 clk cap3 TML1 cap2 cap1 cap0 S IRQ18 S IRQ18 S 3 21 0 3 21 0 0 12 3 S : Selector Figure 10.1.2 Block Diagram of MJT (2/4) 10-6 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3 2 1 0 3 21 0 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers (Note) IRQ13 clk clk clk clk TOD0_0 TOD0_1 TOD0_2 TOD0_3 TOD0_4 TOD0_5 TOD0_6 TOD0_7 udf IRQ13 udf IRQ13 udf IRQ13 udf IRQ13 udf IRQ13 clk clk clk udf udf IRQ13 udf ovf udf IRQ14 Output event bus 0 12 3 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 1/2 internal peripheral clock PRS3 clk IRQ13 F/F27 F/F28 clk CLK1 CLK2 TID0 TIN24 TIN25 clk clk clk clk clk PRS4 clk clk clk en en en en en en en en TOD1_0 TOD1_1 TOD1_2 TOD1_3 TOD1_4 TOD1_5 TOD1_6 TOD1_7 TID1 IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ15 ovf udf IRQ16 clk clk clk clk clk PRS5 clk clk clk en en en en en en en en TOM0_0 TOM0_1 TOM0_2 TOM0_3 TOM0_4 TOM0_5 TOM0_6 TOM0_7 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf ovf udf IRQ17 F/F44 TO44 F/F43 TO43 F/F42 TO42 F/F41 TO41 F/F40 TO40 F/F39 TO39 F/F38 TO38 F/F37 TO37 F/F36 TO36 F/F35 TO35 F/F34 TO34 F/F33 TO33 F/F32 TO32 F/F31 TO31 F/F30 TO30 F/F29 TO29 1/2 internal peripheral clock clk CLK1 CLK2 TIN26 TIN27 AD1TRG (To A-D1 converter) 1/2 internal peripheral clock clk CLK1 CLK2 TID2 TIN28 TIN29 3 21 0 3 2 1 0 01 2 3 S : Selector Figure 10.1.3 Block Diagram of MJT (3/4) 10-7 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3 21 0 3 2 1 0 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0 123 (Note 3) AD0 completed TIO8-udf (Note 3) S DMA0 udf end DMAIRQ0 TIN13 (Note 2) S DMA1 udf end DMAIRQ0 TIN18 (Note 2) (Note 3) S DMA2 udf end DMAIRQ0 TIN0 (Note 2) SIO0-TXD SIO1-RXD (Note 3) (Note 3) S DMA3 udf end DMAIRQ0 SIO0-RXD TIN19 (Note 2) (Note 3) S DMA4 udf DMAIRQ0 TIN20 (Note 2) SIO2-RXD S DMA5 udf end DMAIRQ1 (Note 3) SIO1-TXD TIN1 (Note 2) (Note 3) S DMA6 udf end DMAIRQ1 SIO2-TXD TIN2 (Note 2) (Note 3) S DMA7 udf end DMAIRQ1 SIO3-RXD TIN7 (Note 2) (Note 3) S DMA8 udf end DMAIRQ1 TIN8 (Note 2) SIO3-TXD S DMA9 udf DMAIRQ1 3 21 0 3 21 0 0 12 3 Figure 10.1.4 Block Diagram of MJT (4/4) 10-8 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2 Common Units of Multijunction Timer The common units of the multijunction timer include the following: • Prescaler unit • Clock bus/input-output event bus control unit • Input processing control unit • Output flip-flop control unit • Interrupt control unit 10.2.1 Timer Common Register Map The diagrams in the next pages show a map of registers in the common units of the multijunction timer. 10-9 32170/32174 Group User's Manual (Rev. 2.1) 10 Address H’0080 0200 H’0080 0202 H’0080 0204 D0 +0 Address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D7 D8 +1 Address Clock Bus & Input Event Bus Control Register (CKIEBCR) D15 Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) H’0080 0210 H’0080 0212 H’0080 0214 H’0080 0216 H’0080 0218 H’0080 021A TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 1 (TINCR1) TIN Input Processing Control Register 2 (TINCR2) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) H’0080 0220 H’0080 0222 H’0080 0224 H’0080 0226 H’0080 0228 H’0080 022A F/F Source Select Register 0 (FFS0) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 2 (TINIR2) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 3 (TINIR3) TIN Interrupt Control Register 5 (TINIR5) TIN Interrupt Control Register 7 (TINIR7) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) TOD0 Interrupt Status Register (TOD0IST) H’0080 0230 H’0080 0232 H’0080 0234 H’0080 0236 H’0080 0238 H’0080 023A H’0080 023C H’0080 023E H’0080 07D0 H’0080 07D2 H’0080 07D4 H’0080 07D6 H’0080 07D8 H’0080 07DA H’0080 07DC H’0080 07DE Prescaler Register 3 (PRS3) TOD0 Interrupt Mask Register (TOD0IMA) F/F Protect Register 2 (FFP2) F/F Data Register 2 (FFD2) TOD0 Control Register (TOD0CR) TOD0 Enable Protect Register (TOD0PRO) TOD0 Count Enable Register (TOD0CEN) Blank addresses are reserved. Note: The registers included in thick frames must always be accessed in halfwords. Figure 10.2.1 Timer Common Register Map (1/2) 10-10 32170/32174 Group User's Manual (Rev. 2.1) 10 Address H’0080 0BD0 H’0080 0BD2 H’0080 0BD4 H’0080 0BD6 D0 +0 Address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D7 D8 +1 Address D15 Prescaler Register 4 (PRS4) TOD1 Interrupt Mask Register (TOD1IMA) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) TOD1 Interrupt Status Register (TOD1IST) F/F Protect Register 3 (FFP3) F/F Data Register 3 (FFD3) H’0080 0CD0 H’0080 0CD2 H’0080 0CD4 H’0080 0CD6 Prescaler Register 5 (PRS5) TOM0 Interrupt Mask Register (TOM0IMA) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 4 (FFP4) F/F Data Register 4 (FFD4) Blank addresses are reserved. Note: The registers included in thick frames must always be accessed in halfwords. Figure 10.2.2 Timer Common Register Map (2/2) 10-11 32170/32174 Group User's Manual (Rev. 2.1) 10 10.2.2 Prescaler Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The prescalers PRS0-5 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID, TOD, and TOM) from the divide-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripheral clock = 20 MHz). The values of prescaler registers are initialized to H'00 when reset. Also, when you rewrite the set value of any prescaler register, the device starts operating with the new value simultaneously when the prescaler underflows. Values H'00 to H'FF can be set in the counter registers of prescalers. The prescalers' divide-by ratios are given by the equation below. 1 Prescaler divide-by ratio = ————— Prescaler set value + 1 s Prescaler Register 0 (PRS0) s Prescaler Register 1 (PRS1) s Prescaler Register 2 (PRS2) s Prescaler Register 3 (PRS3) s Prescaler Register 4 (PRS4) s Prescaler Register 5 (PRS5) D0 ( D8 1 9 2 10 3 11 4 12 5 13 6 14 D7 D15 ) PRS0 - PRS5 D 8, 9 Bit Name IEB3S Function 0X : Selects external input 3 (TIN3) R W (input event bus 3 input selection) 10 : Selects output event bus 2 11 : Selects TIO7 output 10, 11 IEB2S 00 : Selects external input 0 (TIN0) (input event bus 2 input selection) 01 : Selects external input 2 (TIN2) 1X : Selects external input 4 (TIN4) 12 IEB1S 0 : Selects external input 5 (TIN5) (input event bus 1 input selection) 1 : Selects TIO6 output 13 IEB0S 0 : Selects external input 6 (TIN6) (input event bus 0 input selection) 1 : Selects TIO5 output 14 15 No functions assigned CKB2S (Clock Bus 2 input selection) 0 : Selects prescaler 2 1 : Selects external clock 3 (TCLK3) 0 — The register CKIEBCR is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus. 10-16 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s Output Event Bus Control Register (OEBCR) D8 OEB3S 9 10 11 OEB2S 12 13 OEB1S D 8, 9 Bit Name OEB3S Function 00 : Selects TOP8 output R W (output event bus 3 input selection) 01 : Selects TIO3 output 10 : Selects TIO4 output 11 : Selects TIO8 output 10 11 No functions assigned OEB2S 0 : Selects TOP9 output 0 — (output event bus 2 input selection) 1 : Selects TIO2 output 12 13 No functions assigned OEB1S 0 : Selects TOP7 output 0 — (output event bus 1 input selection) 1 : Selects TIO1 output 14 15 No functions assigned OEB0S 0 : Selects TOP6 output 0 — (output event bus 0 input selection) 1 : Selects TIO0 output The register OEBCR is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus. 10-17 32170/32174 Group User's Manual (Rev. 2.1) 10 10.2.4 Input Processing Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The input processing control unit processes the TCLK and TIN signals fed into the MJT. In the TCLK input processing unit, selection is made of the source of TCLK signal, or for external input, the active edge (rising or falling or both) or level (high or low) of the signal, with or at which to generate the clock signal fed to the clock bus. In the TIN input processing unit, selection is made of the active edge (rising or falling or both) or level (high or low) of the signal at which to generate the enable, measure or count source signal for each timer or the signal fed to each event bus. Following input processing control registers are included: • TCLK Input Processing Control Register (TCLKCR) • TIN Input Processing Control Register 0 (TINCR0) • TIN Input Processing Control Register 1 (TINCR1) • TIN Input Processing Control Register 2 (TINCR2) • TIN Input Processing Control Register 3 (TINCR3) • TIN Input Processing Control Register 4 (TINCR4) 10-18 32170/32174 Group User's Manual (Rev. 2.1) 10 Item 1/2 internal peripheral clock MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (1) Functions of TCLK input processing control registers Function 1/2 internal peripheral clock Count clock Rising clock edge TCLK Count clock Falling clock edge TCLK Count clock Both edges TCLK Count clock Low level TCLK 1/2 internal peripheral clock Count clock High level TCLK 1/2 internal peripheral clock Count clock 10-19 32170/32174 Group User's Manual (Rev. 2.1) 10 Item Rising edge TIN MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (2) Functions of TIN input processing control registers Function Internal edge signal Falling edge TIN Internal edge signal Both edges TIN Internal edge signal Low level TIN PRS × clock width or TCLK × input Internal edge signal High level TIN PRS × clock width or TCLK × input Internal edge signal 10-20 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TLCK Input Processing Control Register (TCLKCR) D0 1 2 3 4 5 6 TCLK2S D 0, 1 2, 3 Bit Name No functions assigned TCLK3S (TCLK3 input processing selection) 00 : 1/2 internal peripheral clock 01 : Rising edge 10 : Falling edge 11 : Both edges 4 5-7 No functions assigned TCLK2S (TCLK2 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8 9 - 11 No functions assigned TCLK1S (TCLK1 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 12, 13 14, 15 No functions assigned TCLK0S (TCLK0 input processing selection) 00 : 1/2 internal peripheral clock 01 : Rising edge 10 : Falling edge 11 : Both edges Note: This register must always be accessed in halfwords. 0 — 0 — 0 — Function R 0 W — 10-21 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 0 (TINCR0) D0 1 2 TIN4S D 0 1-3 Bit Name No functions assigned TIN4S (TIN4 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 4 5-7 No functions assigned TIN3S (TIN3 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8, 9 10, 11 No functions assigned TIN2S (TIN2 input processing selection) 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges 12, 13 TIN1S (TIN1 input processing selection) 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges 14, 15 TIN0S (TIN0 input processing selection) 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges Note: This register must always be accessed in halfwords. 0 — 0 — Function R 0 W — 10-22 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 1 (TINCR1) D0 1 2 TIN8S D 0 1-3 Bit Name No functions assigned TIN8S (TIN8 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 4 5-7 No functions assigned TIN7S (TIN7 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8 9 - 11 No functions assigned TIN6S (TIN6 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 12 13 - 15 No functions assigned TIN5S (TIN5 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level Note: This register must always be accessed in halfwords. 0 — 0 — 0 — Function R 0 W — 10-23 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 2 (TINCR2) D0 1 2 3 4 5 6 TIN11S D 0-4 5-7 Bit Name No functions assigned TIN11S (TIN11 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8 9 - 11 No functions assigned TIN10S (TIN10 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 12 13 - 15 No functions assigned TIN9S (TIN9 input processing selection) 000 : Invalidates input 001 : Rising edge 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level Note: This register must always be accessed in halfwords. 0 — 0 — Function R 0 W — 10-24 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TIN Input Processing Control Register 3 (TINCR3) D0 1 2 3 4 5 6 7 8 9 10 11 D 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN19S (TIN19 input processing selection) TIN18S (TIN18 input processing selection) TIN17S (TIN17 input processing selection) TIN16S (TIN16 input processing selection) TIN15S (TIN15 input processing selection) TIN14S (TIN14 input processing selection) TIN13S (TIN13 input processing selection) TIN12S (TIN12 input processing selection) Function 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges R W Note: This register must always be accessed in halfwords. s TIN Input Processing Control Register 4 (TINCR4) D0 1 2 3 4 5 6 7 8 9 10 11 D 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN33S (TIN33 input processing selection) TIN32S (TIN32 input processing selection) TIN31S (TIN31 input processing selection) TIN30S (TIN30 input processing selection) TIN23S (TIN23 input processing selection) TIN22S (TIN22 input processing selection) TIN21S (TIN21 input processing selection) TIN20S (TIN20 input processing selection) Function 00 : Invalidates input 01 : Rising edge 10 : Falling edge 11 : Both edges R W Note: This register must always be accessed in halfwords. 10-25 32170/32174 Group User's Manual (Rev. 2.1) 10 10.2.5 Output Flip-Flop Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. Following flip-flop control registers are included: • F/F Source Select Register 0 (FFS0) • F/F Source Select Register 1 (FFS1) • F/F Protect Register 0 (FFP0) • F/F Protect Register 1 (FFP1) • F/F Protect Register 2 (FFP2) • F/F Protect Register 3 (FFP3) • F/F Protect Register 4 (FFP4) • F/F Data Register 0 (FFD0) • F/F Data Register 1 (FFD1) • F/F Data Register 2 (FFD2) • F/F Data Register 3 (FFD3) • F/F Data Register 4 (FFD4) Timings at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5 below. (Note that signals are generated at different timings than those fed to the output event bus.) 10-26 32170/32174 Group User's Manual (Rev. 2.1) 10 Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML TID (16-bit measure input) (32-bit measure input) Fixed period count mode Event count mode Multiply-by-4 event count mode TOD PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TOM PWM output mode Single-shot PWM output mode Single-shot output mode Continuous output mode MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Table 10.2.5 Timings at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timings at which signals are generated to the output flip-flop When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows When counter underflows When counter underflows When counter underflows When counter is enabled and when underflows When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows No signal generation function No signal generation function No signal generation function No signal generation function No signal generation function When counter is enabled and when underflows When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows When counter is enabled and when underflows When counter underflows When counter is enabled and when underflows When counter is enabled and when underflows 10-27 32170/32174 Group User's Manual (Rev. 2.1) 10 TOP TIO TOD TOM F/F source selection (FFn) udf MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Port operation mode register(PnMOD) F/F Internal edge signal Output event bus 0 Output event bus 1 Output event bus 2 Output event bus 3 Dn F/Fn output data (FDn) F/F Output control (ON/OFF) WR F/F protect (FPn) Dn F/F TOn Note: Dn denotes the data bus. Figure 10.2.4 Configuration of the F/F Output Circuit 10-28 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Source Select Register 0 (FFS0) D0 1 2 3 4 5 6 7 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0-2 3 Bit Name No functions assigned FF15 (F/F15 source selection) 0 : TIO4 output 1 : Output event bus 0 4 FF14 (F/F14 source selection) 0 : TIO3 output 1 : Output event bus 0 5 FF13 (F/F13 source selection) 0 : TIO2 output 1 : Output event bus 3 6 FF12 (F/F12 source selection) 0 : TIO1 output 1 : Output event bus 2 7 FF11 (F/F11 source selection) 0 : TIO0 output 1 : Output event bus 1 8, 9 FF10 (F/F10 source selection) 0X : TOP10 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF9 (F/F9 source selection) 0X : TOP9 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF8 (F/F8 source selection) 00 : TOP8 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 2 14 FF7 (F/F7 source selection) 0 : TOP7 output 1 : Output event bus 0 15 FF6 (F/F6 source selection) 0 : TOP6 output 1 : Output event bus 1 Note: This register must always be accessed in halfwords. Function R 0 W — 10-29 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Source Select Register 1 (FFS1) D8 FF19 9 10 FF18 11 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8, 9 Bit Name FF19 (F/F19 source selection) Function 0X : TIO8 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF18 (F/F18 source selection) 0X : TIO7 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF17 (F/F17 source selection) 0X : TIO6 output 10 : Output event bus 0 11 : Output event bus 1 14, 15 FF16 (F/F16 source selection) 00 : TIO5 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 3 R W The registers FFS0 and FFS1 are used to select the signal sources fed to each output F/F (flipflop). For these signal sources, you can choose signals from the internal output bus or underflow output from each timer. 10-30 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Protect Register 0 (FFP0) D0 1 2 3 4 5 6 FP9 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FP15 (F/F15 protect) FP14 (F/F14 protect) FP13 (F/F13 protect) FP12 (F/F12 protect) FP11 (F/F11 protect) FP10 (F/F10 protect) FP9 (F/F9 protect) FP8 (F/F8 protect) FP7 (F/F7 protect) FP6 (F/F6 protect) FP5 (F/F5 protect) FP4 (F/F4 protect) FP3 (F/F3 protect) FP2 (F/F2 protect) FP1 (F/F1 protect) FP0 (F/F0 protect) Function 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit R W Note: This register must always be accessed in halfwords. This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. 10-31 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Protect Register 1 (FFP1) D8 9 10 11 FP20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 - 10 11 12 13 14 15 Bit Name No functions assigned FP20 (F/F20 protect) FP19 (F/F19 protect) FP18 (F/F18 protect) FP17 (F/F17 protect) FP16 (F/F16 protect) 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit Function R 0 W — s F/F Protect Register 2 (FFP2) D8 FP21 9 FP22 10 FP23 11 FP24 12 FP25 13 FP26 D 8 9 10 11 12 13 14 15 Bit Name FP21 (F/F21 protect) FP22 (F/F22 protect) FP23 (F/F23 protect) FP24 (F/F24 protect) FP25 (F/F25 protect) FP26 (F/F26 protect) FP27 (F/F27 protect) FP28 (F/F28 protect) Function 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit R W This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. 10-32 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Protect Register 3 (FFP3) D8 FP29 9 FP30 10 FP31 11 FP32 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 9 10 11 12 13 14 15 Bit Name FP29 (F/F29 protect) FP30 (F/F30 protect) FP31 (F/F31 protect) FP32 (F/F32 protect) FP33 (F/F33 protect) FP34 (F/F34 protect) FP35 (F/F35 protect) FP36 (F/F36 protect) Function 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit R W s F/F Protect Register 4 (FFP4) D8 FP37 9 FP38 10 FP39 11 FP40 12 FP41 13 FP42 D 8 9 10 11 12 13 14 15 Bit Name FP37 (F/F37 protect) FP38 (F/F38 protect) FP39 (F/F39 protect) FP40 (F/F40 protect) FP41 (F/F41 protect) FP42 (F/F42 protect) FP43 (F/F43 protect) FP44 (F/F44 protect) Function 0 : Enables write to F/F output bit 1 : Disables write to F/F output bit R W This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. 10-33 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Data Register 0 (FFD0) D0 1 2 3 4 5 6 FD9 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FD15 (F/F15 output data) FD14 (F/F14 output data) FD13 (F/F13 output data) FD12 (F/F12 output data) FD11 (F/F11 output data) FD10 (F/F10 output data) FD9 (F/F9 output data) FD8 (F/F8 output data) FD7 (F/F7 output data) FD6 (F/F6 output data) FD5 (F/F5 output data) FD4 (F/F4 output data) FD3 (F/F3 output data) FD2 (F/F2 output data) FD1 (F/F1 output data) FD0 (F/F0 output data) Function 0 : F/F output data = 0 1 : F/F output data = 1 R W Note: This register must always be accessed in halfwords. This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. 10-34 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Data Register 1 (FFD1) D8 9 10 11 FD20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 - 10 11 12 13 14 15 Bit Name No functions assigned FD20 (F/F20 output data) FD19 (F/F19 output data) FD18 (F/F18 output data) FD17 (F/F17 output data) FD16 (F/F16 output data) 0 : F/F output data = 0 1 : F/F output data = 1 Function R 0 W — s F/F Data Register 2 (FFD2) D8 FD21 9 FD22 10 FD23 11 FD24 12 FD25 13 FD26 D 8 9 10 11 12 13 14 15 Bit Name FD21 (F/F21 output data) FD22 (F/F22 output data) FD23 (F/F23 output data) FD24 (F/F24 output data) FD25 (F/F25 output data) FD26 (F/F26 output data) FD27 (F/F27 output data) FD28 (F/F28 output data) Function 0 : F/F output data = 0 1 : F/F output data = 1 R W This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. 10-35 32170/32174 Group User's Manual (Rev. 2.1) 10 s F/F Data Register 3 (FFD3) D8 FD29 9 FD30 10 FD31 11 FD32 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 8 9 10 11 12 13 14 15 Bit Name FD29 (F/F29 output data) FD30 (F/F30 output data) FD31 (F/F31 output data) FD32 (F/F32 output data) FD33 (F/F33 output data) FD34 (F/F34 output data) FD35 (F/F35 output data) FD36 (F/F36 output data) Function 0 : F/F output data = 0 1 : F/F output data = 1 R W s F/F Data Register 4 (FFD4) D8 FD37 9 FD38 10 FD39 11 FD40 12 FD41 13 FD42 D 8 9 10 11 12 13 14 15 Bit Name FD37 (F/F37 output data) FD38 (F/F38 output data) FD39 (F/F39 output data) FD40 (F/F40 output data) FD41 (F/F41 output data) FD42 (F/F42 output data) FD43 (F/F43 output data) FD44 (F/F44 output data) Function 0 : F/F output data = 0 1 : F/F output data = 1 R W This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. 10-36 32170/32174 Group User's Manual (Rev. 2.1) 10 10.2.6 Interrupt Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer. Following 22 timer interrupt control registers are provided for each timer. • TOP Interrupt Control Register 0 (TOPIR0) • TOP Interrupt Control Register 1 (TOPIR1) • TOP Interrupt Control Register 2 (TOPIR2) • TOP Interrupt Control Register 3 (TOPIR3) • TIO Interrupt Control Register 0 (TIOIR0) • TIO Interrupt Control Register 1 (TIOIR1) • TIO Interrupt Control Register 2 (TIOIR2) • TMS Interrupt Control Register (TMSIR) • TIN Interrupt Control Register 0 (TINIR0) • TIN Interrupt Control Register 1 (TINIR1) • TIN Interrupt Control Register 2 (TINIR2) • TIN Interrupt Control Register 3 (TINIR3) • TIN Interrupt Control Register 4 (TINIR4) • TIN Interrupt Control Register 5 (TINIR5) • TIN Interrupt Control Register 6 (TINIR6) • TIN Interrupt Control Register 7 (TINIR7) • TOD0 Interrupt Mask Register (TOD0IMA) • TOD0 Interrupt Status Register (TOD0IST) • TOD1 Interrupt Mask Register (TOD1IMA) • TOD1 Interrupt Status Register (TOD1IST) • TOM0 Interrupt Mask Register (TOM0IMA) • TOM0 Interrupt Status Register (TOM0IST) For interrupts which have only one source of interrupt in one interrupt table, no interrupt control registers are provided in the timer, and the interrupt status flags are automatically managed within the interrupt controller. For details, refer to Chapter 14, "Interrupt Controller." • TOP10 • TID0 • TID1 • TID2 MJT Output Interrupt 5 (IRQ5) TID0 Output Interrupt (IRQ14) TID1 Output Interrupt (IRQ15) TID2 Output Interrupt (IRQ17) 10-37 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer For interrupts which have two or more sources of interrupt in one interrupt table, interrupt control registers are provided, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the interrupt controller function only as a bit to show whether an interrupt-enabled interrupt request occurred and cannot be written to. (1) Interrupt request status bit This status bit shows whether an interrupt request occurred. When an interrupt request is generated, this bit is set in hardware (but cannot be set in software). The status bit is cleared by writing a 0, but not affected by writing a 1, in which case the bit holds the status intact. Because the status bit is unaffected by interrupt mask bits, it can also be used to check the operation of peripheral function. In interrupt processing, make sure that among grouped interrupt flags, only the flag for the serviced interrupt is cleared. Clearing flags for unserviced interrupts results in the pending interrupt requests also being cleared. (2) Interrupt mask bit This bit is used to disable unnecessary interrupts among grouped interrupt requests. Set this bit to 0 to enable interrupts or 1 to disable interrupts. Group interrupt Each timer or TIN input interrupt request Set Data = 0 clear Interrupt status F/F F/F Interrupt enable Interrupt controller Data bus Figure 10.2.5 Interrupt Status Register and Mask Register 10-38 32170/32174 Group User's Manual (Rev. 2.1) 10 Example for clearing the interrupt status MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Interrupt status flag b4 5 0 6 0 b7 0 Initial state 0 b6 event occurred 0 0 1 0 Interrupt request b4 event occurred Write to the interrupt status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only b6 cleared b4 data retained Figure 10.2.6 Example for Clearing the Interrupt Status 10-39 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller. Table 10.2.6 Interrupt Signals Generated by MJT Signal Name Source of Interrupt Generated IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 TIO0, TIO1, TIO2, TIO3 TOP6, TOP7 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TIO8, TIO9 TIO4, TIO5, TIO6, TIO7 TOP8, TOP9 TMS0, TMS1 TIN7, TIN8, TIN9, TIN10, TIN11 TIN0, TIN1, TIN2 TIN12, TIN13, TIN14, TIN15, TIN16, TIN17, TIN18, TIN19 IRQ11 IRQ12 IRQ13 TIN20, TIN21, TIN22, TIN23 TIN3, TIN4, TIN5, TIN6 TOD0_0, TOD0_1, TOD0_2, TOD0_3, TOD0_4, TOD0_5, TOD0_6, TOD0_7 IRQ16 TOD1_0, TOD1_1, TOD1_2, TOD1_3, TOD1_4, TOD1_5, TOD1_6, TOD1_7, TOM0_0, TOM0_1, TOM0_2, TOM0_3, TOM0_4, TOM0_5, TOM0_6, TOM0_7 IRQ18 TIN30, TIN31, TIN32, TIN33 TML1 input interrupt 4 TOD1 + TOM0 output interrupt 16 MJT input interrupt 3 MJT input interrupt 4 TOD0 output interrupt 4 4 8 Interrupt Sources Input to ICU (Note 1) Number of Input Sources MJT output interrupt 0 MJT output interrupt 1 MJT output interrupt 2 MJT output interrupt 3 MJT output interrupt 4 MJT output interrupt 6 MJT output interrupt 7 MJT input interrupt 0 MJT input interrupt 1 MJT input interrupt 2 4 2 6 2 4 2 2 5 3 8 Note 1: Refer to Chapter 5, "Interrupt Controller (ICU)." Note 2: For TOP10 and TID0-2, there are no interrupt status and mask bits in MJT interrupt control registers because they only have one source of interrupt in the group. (They are controlled directly by the interrupt controller.) 10-40 32170/32174 Group User's Manual (Rev. 2.1) 10 D0 1 2 TOPIS5 3 TOPIS4 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TOP Interrupt Control Register 0 (TOPIR0) 4 TOPIS3 5 TOPIS2 D 0, 1 2 3 4 5 6 7 W= Bit Name No functions assigned TOPIS5 (TOP5 interrupt status) TOPIS4 (TOP4 interrupt status) TOPIS3 (TOP3 interrupt status) TOPIS2 (TOP2 interrupt status) TOPIS1 (TOP1 interrupt status) TOPIS0 (TOP0 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt request generated Function R 0 W — s TOP Interrupt Control Register 1 (TOPIR1) D8 9 10 TOPIM5 11 TOPIM4 12 TOPIM3 13 TOPIM2 D 8, 9 10 11 12 13 14 15 Bit Name No functions assigned TOPIM5 (TOP5 interrupt mask) TOPIM4 (TOP4 interrupt mask) TOPIM3 (TOP3 interrupt mask) TOPIM2 (TOP2 interrupt mask) TOPIM1 (TOP1 interrupt mask) TOPIM0 (TOP0 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — 10-41 32170/32174 Group User's Manual (Rev. 2.1) 10 TOPIR0 TOP5udf Data bus b2 b10 TOPIS5 F/F TOPIM5 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 6-source inputs MJT output interrupt 2 IRQ2 (Level) TOP4udf TOPIS4 b3 b11 F/F TOPIM4 F/F TOP3udf b4 b12 TOPIS3 F/F TOPIM3 F/F TOP2udf b5 b13 TOPIS2 F/F TOPIM2 F/F TOP1udf TOPIS1 b6 b14 F/F TOPIM1 F/F TOP0udf TOPIS0 b7 b15 F/F TOPIM0 F/F Figure 10.2.7 Block Diagram of MJT Output Interrupt 2 10-42 32170/32174 Group User's Manual (Rev. 2.1) 10 D0 1 2 TOPIS7 3 TOPIS6 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TOP Interrupt Control Register 2 (TOPIR2) 4 5 D 0, 1 2 3 4, 5 6 7 W= Bit Name No functions assigned TOPIS7 (TOP7 interrupt status) TOPIS6 (TOP6 interrupt status) No functions assigned TOPIM7 (TOP7 interrupt mask) TOPIM6 (TOP6 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TOPIR2 D 8, 9 10 11 12, 13 14 15 W= Bit Name No functions assigned TOPIS9 (TOP9 interrupt status) TOPIS8 (TOP8 interrupt status) No functions assigned TOPIM9 (TOP9 interrupt mask) TOPIM8 (TOP8 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. Note: For TOP10, there are no interrupt status and mask bits in MJT interrupt control registers because it only has one source of interrupt in the group. (It is controlled directly by the interrupt controller.) TOPIR3 D 0 1 2 3 4 5 6 7 W= Bit Name TIOIS3 (TIO3 interrupt status) TIOIS2 (TIO2 interrupt status) TIOIS1 (TIO1 interrupt status) TIOIS0 (TIO0 interrupt status) TIOIM3 (TIO3 interrupt mask) TIOIM2 (TIO2 interrupt mask) TIOIM1 (TIO1 interrupt mask) TIOIM0 (TIO0 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. TIOIR0 D 8 9 10 11 12 13 14 15 W= Bit Name TIOIS7 (TIO7 interrupt status) TIOIS6 (TIO6 interrupt status) TIOIS5 (TIO5 interrupt status) TIOIS4 (TIO4 interrupt status) TIOIM7 (TIO7 interrupt mask) TIOIM6 (TIO6 interrupt mask) TIOIM5 (TIO5 interrupt mask) TIOIM4 (TIO4 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. TIOIR1 TIO7udf Data bus b8 b12 TIOIS7 F/F TIOIM7 F/F (Level) 4-source inputs MJT output interrupt 4 IRQ4 Function 0 : No interrupt request 1 : Interrupt request generated R W 0 : Enables interrupt request 1 : Masks (disables) interrupt request TIO6udf TIOIS6 b9 b13 F/F TIOIM6 F/F TIO5udf TIOIS5 b10 b14 F/F TIOIM5 F/F TIO4udf TIOIS4 b11 b15 F/F TIOIM4 F/F Figure 10.2.11 Block Diagram of MJT Output Interrupt 4 10-46 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO Interrupt Control Register 2 (TIOIR2) D0 1 2 TIOIS9 3 TIOIS8 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0, 1 2 3 4, 5 6 7 W= Bit Name No functions assigned TIOIS9 (TIO9 interrupt status) TIOIS8 (TIO8 interrupt status) No functions assigned TIOIM9 (TIO9 interrupt mask) TIOIM8 (TIO8 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TIOIR2 D 8, 9 10 11 12, 13 14 15 W= Bit Name No functions assigned TMSIS1 (TMS1 interrupt status) TMSIS0 (TMS0 interrupt status) No functions assigned TMSIM1 (TMS1 interrupt mask) TMSIM0 (TMS0 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 : No interrupt request 1 : Interrupt request generated 0 — Function R 0 W — : Only writing a 0 is effective; when you write a 1, the previous value is retained. TMSIR D 0 1 2 3 4 5 6 7 W= Bit Name No functions assigned TINIS2 (TIN2 interrupt status) TINIS1 (TIN1 interrupt status) TINIS0 (TIN0 interrupt status) No functions assigned TINIM2 (TIN2 interrupt mask) TINIM1 (TIN1 interrupt mask) TINIM0 (TIN0 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request 0 — 0 : No interrupt request 1 : Interrupt request generated Function R 0 W — TINIR0 D 8 9 10 11 12 13 14 15 W= Bit Name TINIS6 (TIN6 interrupt status) TINIS5 (TIN5 interrupt status) TINIS4 (TIN4 interrupt status) TINIS3 (TIN3 interrupt status) TINIM6 (TIN6 interrupt mask) TINIM5 (TIN5 interrupt mask) TINIM4 (TIN4 interrupt mask) TINIM3 (TIN3 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W TINIR1 D 0,1,2 3 4 5 6 7 W= Bit Name No functions assigned TINIS11 (TIN11 interrupt status) TINIS10 (TIN10 interrupt status) TINIS9 (TIN9 interrupt status) TINIS8 (TIN8 interrupt status) TINIS7 (TIN7 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : No interrupt request 1 : Interrupt request generated Function R 0 W — s TIN Interrupt Control Register 3 (TINIR3) D8 9 10 11 TINIM11 12 TINIM10 13 TINIM9 D 8,9,10 11 12 13 14 15 Bit Name No functions assigned TINIM11 (TIN11 interrupt mask) TINIM10 (TIN10 interrupt mask) TINIM9 (TIN9 interrupt mask) TINIM8 (TIN8 interrupt mask) TINIM7 (TIN7 interrupt mask) 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function R 0 W — 10-51 32170/32174 Group User's Manual (Rev. 2.1) 10 TINIR2 TINIR3 TIN11edge Data bus b3 b11 TINIS11 F/F TINIM11 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 5-source inputs (Level) MJT input interrupt 0 IRQ8 TIN10edge TINIS10 b4 b12 F/F TINIM10 F/F TIN9edge TINIS9 b5 b13 F/F TINIM9 F/F TIN8edge TINIS8 b6 b14 F/F TINIM8 F/F TIN7edge TINIS7 b7 b15 F/F TINIM7 F/F Figure 10.2.16 Block Diagram of MJT Input Interrupt 0 10-52 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIN Interrupt Control Register 4 (TINIR4) D0 TINIS19 1 TINIS18 2 TINIS17 3 TINIS16 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 W= Bit Name TINIS19 (TIN19 interrupt status) TINIS18 (TIN18 interrupt status) TINIS17 (TIN17 interrupt status) TINIS16 (TIN16 interrupt status) TINIS15 (TIN15 interrupt status) TINIS14 (TIN14 interrupt status) TINIS13 (TIN13 interrupt status) TINIS12 (TIN12 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. Function 0 : No interrupt request 1 : Interrupt request generated R W s TIN Interrupt Control Register 5 (TINIR5) D8 TINIM19 9 TINIM18 10 TINIM17 11 TINIM16 12 TINIM15 13 TINIM14 D 8 9 10 11 12 13 14 15 Bit Name TINIM19 (TIN19 interrupt mask) TINIM18 (TIN18 interrupt mask) TINIM17 (TIN17 interrupt mask) TINIM16 (TIN16 interrupt mask) TINIM15 (TIN15 interrupt mask) TINIM14 (TIN14 interrupt mask) TINIM13 (TIN13 interrupt mask) TINIM12 (TIN12 interrupt mask) Function 0 : Enables interrupt request 1 : Masks (disables) interrupt request R W 10-53 32170/32174 Group User's Manual (Rev. 2.1) 10 TINIR4 TIN19edge Data bus b0 b8 TINIS19 F/F TINIM19 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 8-source inputs MJT input interrupt 2 IRQ10 (Level) TIN18edge TINIS18 b1 b9 TIN17edge TINIS17 b2 b10 TIN16edge TINIS16 b3 b11 TIN15edge TINIS15 b4 b12 TIN14edge TINIS14 b5 b13 TIN13edge TINIS13 b6 b14 TIN12edge TINIS12 b7 b15 F/F TINIM12 F/F F/F TINIM13 F/F F/F TINIM14 F/F F/F TINIM15 F/F F/F TINIM16 F/F F/F TINIM17 F/F F/F TINIM18 F/F Figure 10.2.17 Block Diagram of MJT Input Interrupt 2 10-54 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIN Interrupt Control Register 6 (TINIR6) D0 TINIS23 1 TINIS22 2 TINIS21 3 TINIS20 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 W= Bit Name TINIS23 (TIN23 interrupt status) TINIS22 (TIN22 interrupt status) TINIS21 (TIN21 interrupt status) TINIS20 (TIN20 interrupt status) TINIM23 (TIN23 interrupt mask) TINIM22 (TIN22 interrupt mask) TINIM21 (TIN21 interrupt mask) TINIM20 (TIN20 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W TINIR6 D 8 9 10 11 12 13 14 15 W= Bit Name TINIS33 (TIN33 interrupt status) TINIS32 (TIN32 interrupt status) TINIS31 (TIN31 interrupt status) TINIS30 (TIN30 interrupt status) TINIM33 (TIN33 interrupt mask) TINIM32 (TIN32 interrupt mask) TINIM31 (TIN31 interrupt mask) TINIM30 (TIN30 interrupt mask) : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Enables interrupt request 1 : Masks (disables) interrupt request Function 0 : No interrupt request 1 : Interrupt request generated R W Note : For TIN24-TIN29, there are no interrupt status and mask bits in MJT interrupt control registers because they do not have interrupt functions. TINIR7 D 0 1 2 3 4 5 6 7 Bit Name TOD07IMA (TOD0_7 interrupt mask) TOD06IMA (TOD0_6 interrupt mask) TOD05IMA (TOD0_5 interrupt mask) TOD04IMA (TOD0_4 interrupt mask) TOD03IMA (TOD0_3 interrupt mask) TOD02IMA (TOD0_2 interrupt mask) TOD01IMA (TOD0_1 interrupt mask) TOD00IMA (TOD0_0 interrupt mask) Function 0 : Enables interrupt request 1 : Masks (disables) interrupt request R W s TOD0 Interrupt Status Register (TOD0IST) D8 9 10 11 12 13 D 8 9 10 11 12 13 14 15 W= Bit Name TOD07IST (TOD0_7 interrupt status) TOD06IST (TOD0_6 interrupt status) TOD05IST (TOD0_5 interrupt status) TOD04IST (TOD0_4 interrupt status) TOD03IST (TOD0_3 interrupt status) TOD02IST (TOD0_2 interrupt status) TOD01IST (TOD0_1 interrupt status) TOD00IST (TOD0_0 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. Function 0 : No interrupt request 1 : Interrupt request generated R W 10-57 32170/32174 Group User's Manual (Rev. 2.1) 10 TOD0IMA TOD07udf Data bus b8 b0 TOD07IST F/F TOD07IMA F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 8-source inputs (Level) TOD0 output interrupt 2 IRQ13 TOD06udf TOD06IST b9 b1 F/F TOD06IMA F/F TOD05udf TOD05IST b10 b2 F/F TOD05IMA F/F TOD04udf TOD04IST b11 b3 F/F TOD04IMA F/F TOD03udf TOD03IST b12 b4 F/F TOD03IMA F/F TOD02udf TOD02IST b13 b5 F/F TOD02IMA F/F TOD01udf TOD01IST b14 b6 TOD00udf TOD00IST b15 b7 F/F TOD00IMA F/F F/F TOD01IMA F/F Figure 10.2.20 Block Diagram of TOD0 Output Interrupt 10-58 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1 Interrupt Mask Register (TOD1IMA) D0 1 2 3 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer D 0 1 2 3 4 5 6 7 Bit Name TOD17IMA (TOD1_7 interrupt mask) TOD16IMA (TOD1_6 interrupt mask) TOD15IMA (TOD1_5 interrupt mask) TOD14IMA (TOD1_4 interrupt mask) TOD13IMA (TOD1_3 interrupt mask) TOD12IMA (TOD1_2 interrupt mask) TOD11IMA (TOD1_1 interrupt mask) TOD10IMA (TOD1_0 interrupt mask) Function 0 : Enables interrupt request 1 : Masks (disables) interrupt request R W s TOD1 Interrupt Status Register (TOD1IST) D8 9 10 11 12 13 D 8 9 10 11 12 13 14 15 W= Bit Name TOD17IST (TOD1_7 interrupt status) TOD16IST (TOD1_6 interrupt status) TOD15IST (TOD1_5 interrupt status) TOD14IST (TOD1_4 interrupt status) TOD13IST (TOD1_3 interrupt status) TOD12IST (TOD1_2 interrupt status) TOD11IST (TOD1_1 interrupt status) TOD10IST (TOD1_0 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. Function 0 : No interrupt request 1 : Interrupt request generated R W 10-59 32170/32174 Group User's Manual (Rev. 2.1) 10 D0 1 2 3 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer s TOM0 Interrupt Mask Register (TOM0IMA) 4 5 D 0 1 2 3 4 5 6 7 Bit Name TOM07IMA (TOM0_7 interrupt mask) TOM06IMA (TOM0_6 interrupt mask) TOM05IMA (TOM0_5 interrupt mask) TOM04IMA (TOM0_4 interrupt mask) TOM03IMA (TOM0_3 interrupt mask) TOM02IMA (TOM0_2 interrupt mask) TOM01IMA (TOM0_1 interrupt mask) TOM00IMA (TOM0_0 interrupt mask) Function 0 : Enables interrupt request 1 : Masks (disables) interrupt request R W s TOM0 Interrupt Status Register (TOM0IST) D8 9 10 11 12 13 D 8 9 10 11 12 13 14 15 W= Bit Name TOM07IST (TOM0_7 interrupt status) TOM06IST (TOM0_6 interrupt status) TOM05IST (TOM0_5 interrupt status) TOM04IST (TOM0_4 interrupt status) TOM03IST (TOM0_3 interrupt status) TOM02IST (TOM0_2 interrupt status) TOM01IST (TOM0_1 interrupt status) TOM00IST (TOM0_0 interrupt status) : Only writing a 0 is effective; when you write a 1, the previous value is retained. Function 0 : No interrupt request 1 : Interrupt request generated R W 10-60 32170/32174 Group User's Manual (Rev. 2.1) 10 TOD1IMA TOD17udf Data bus b8 b0 TOD17IST F/F TOD17IMA F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 16-source inputs TOD1 + TOM0 output interrupt IRQ16 (Level) TOD16udf b9 b1 TOD16IST F/F TOD16IMA F/F TOD15udf b10 b2 TOD15IST F/F TOD15IMA F/F TOD14udf b11 b3 TOD14IST F/F TOD14IMA F/F TOD13udf b12 b4 TOD13IST F/F TOD13IMA F/F TOD12udf b13 b5 TOD12IST F/F TOD12IMA F/F TOD11udf b14 b6 TOD10udf b15 b7 TOD10IST F/F TOD10IMA F/F To 8 input sources in the next page TOD11IST F/F TOD11IMA F/F Figure 10.2.21 Block Diagram of TOD1 + TOM0 Output Interrupt (1/2) 10-61 32170/32174 Group User's Manual (Rev. 2.1) 10 TOM0IMA TOM07udf Data bus b8 b0 TOM06udf b9 b1 TOM05udf TOM05IST b10 b2 TOM04udf TOM04IST b11 b3 F/F TOM04IMA F/F F/F TOM05IMA F/F TOM06IST F/F TOM06IMA F/F TOM07IST F/F TOM07IMA F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer To the preceding page TOM03udf TOM03IST b12 b4 F/F TOM03IMA F/F TOM02udf TOM02IST b13 b5 F/F TOM02IMA F/F TOM01udf TOM01IST b14 b6 F/F TOM01IMA F/F TOM00udf TOM00IST b15 b7 F/F TOM00IMA F/F Figure 10.2.22 Block Diagram of TOD1 + TOM0 Output Interrupt (2/2) 10-62 32170/32174 Group User's Manual (Rev. 2.1) 10 10.3 TOP (Output-related 16-bit Timer) 10.3.1 Outline of TOP MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP (Timer Output) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Single-shot output mode • Delayed single-shot output mode • Continuous output mode The table below shows specifications of TOP. The diagram in the next page shows a block diagram of TOP. Table 10.3.1 Specifications of TOP (Output-related 16-bit Timer) Item Number of channels Counter Reload register Correction register Timer startup Specification 11 channels 16-bit down-counter 16-bit reload register 16-bit correction register Started by writing to enable bit in software or by enabling with external input (rising or falling edge or both) Mode selection • Single-shot output mode • Delayed single-shot output mode • Continuous output mode Interrupt generation Can be generated by a counter underflow 10-63 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Output event bus 0123 TOP 0 Reload register clk udf IRQ2 Down-counter F/F0 TO 0 S Correction register (16 bits) en IRQ2 TCLK0 TCLK0S IRQ9 clk clk S DRQ7 en en en en en en en TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 udf IRQ2 F/F1 F/F2 IRQ2 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 udf udf IRQ2 TIN0 TIN0S clk clk clk clk F/F3 F/F4 IRQ2 udf udf IRQ1 F/F5 S IRQ1 IRQ9 S S udf F/F6 TIN1 TIN1S DRQ8 clk S TOP 7 udf IRQ6 S F/F7 TO 7 IRQ9 S S clk clk clk en en en TOP 8 TOP 9 TOP 10 udf IRQ6 S S IRQ5 F/F8 F/F9 F/F10 TO 8 TO 9 TO 10 TIN2 TIN2S DRQ9 udf udf S 3210 3210 0123 F/F : Output flip-flop S : Selector Figure 10.3.1 Block Diagram of TOP (Output-related 16-bit Timer) 10-64 32170/32174 Group User's Manual (Rev. 2.1) 10 10.3.2 Outline of Each Mode of TOP MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops without performing any operation. When after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), the content of the reload register is loaded into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1) . Also, an interrupt can be generated when the counter underflows first time and next. (3) Continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). 10-65 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. 10-66 32170/32174 Group User's Manual (Rev. 2.1) 10 10.3.3 TOP Related Register Map MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) The diagram below shows a TOP-related register map. Address D0 +0 Address D7 D8 +1 Address D15 H’0080 0240 H’0080 0242 H’0080 0244 H’0080 0246 TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) TOP0 Correction Register (TOP0CC) H’0080 0250 H’0080 0252 H’0080 0254 H’0080 0256 TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) TOP1 Correction Register (TOP1CC) H’0080 0260 H’0080 0262 H’0080 0264 H’0080 0266 TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) TOP2 Correction Register (TOP2CC) H’0080 0270 H’0080 0272 H’0080 0274 H’0080 0276 TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) TOP3 Correction Register (TOP3CC) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed . in halfwords. Figure 10.3.2 TOP Related Register Map (1/3) 10-67 32170/32174 Group User's Manual (Rev. 2.1) 10 Address D0 +0 Address MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D7 D8 +1 Address D15 H’0080 0280 H’0080 0282 H’0080 0284 H’0080 0286 TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) TOP4 Correction Register (TOP4CC) H’0080 0290 H’0080 0292 H’0080 0294 H’0080 0296 H’0080 0298 H’0080 029A H’0080 029C TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) TOP5 Correction Register (TOP5CC) TOP0-5 Control Register 0 (TOP05CR0) TOP0-5 Control Register 1 (TOP05CR1) H’0080 02A0 H’0080 02A2 H’0080 02A4 H’0080 02A6 H’0080 02A8 H’0080 02AA TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) TOP6 Correction Register (TOP6CC) TOP6,7 Control Register (TOP67CR) H’0080 02B0 H’0080 02B2 H’0080 02B4 H’0080 02B6 TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) TOP7 Correction Register (TOP7CC) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.3.3 TOP Related Register Map (2/3) 10-68 32170/32174 Group User's Manual (Rev. 2.1) 10 Address D0 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H’0080 02C0 H’0080 02C2 H’0080 02C4 H’0080 02C6 TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) TOP8 Correction Register (TOP8CC) H’0080 02D0 H’0080 02D2 H’0080 02D4 H’0080 02D6 TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) TOP9 Correction Register (TOP9CC) H’0080 02E0 H’0080 02E2 H’0080 02E4 H’0080 02E6 H’0080 02E8 H’0080 02EA TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) TOP10 Correction Register (TOP10CC) TOP8-10 Control Register (TOP810CR) H’0080 02FA H’0080 02FC H’0080 02FE TOP0-10 External Enable Enable Register (TOPEEN) TOP0-10 Enable Protect Register (TOPPRO) TOP0-10 Count Enable Register (TOPCEN) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.3.4 TOP Related Register Map (3/3) 10-69 32170/32174 Group User's Manual (Rev. 2.1) 10 10.3.4 TOP Control Registers MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) The TOP control registers are used to select operation modes of TOP0-10 (single-shot, delayed single-shot, or continuous mode), as well as select the counter enable and counter clock sources. Following four TOP control registers are provided for each timer group. • TOP0-5 Control Register 0 (TOP05CR0) • TOP0-5 Control Register 1 (TOP05CR1) • TOP6, 7 Control Register (TOP67CR) • TOP8-10 Control Register (TOP810CR) 10-70 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOP0-5 Control Register 0 (TOP05CR0) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0,1 2,3 4,5 6,7 8 9-10 Bit Name TOP3M (TOP3 operation mode selection) TOP2M (TOP2 operation mode selection) TOP1M (TOP1 operation mode selection) TOP0M (TOP0 operation mode selection) No functions assigned TOP05ENS (TOP0-5 enable source selection) 0XX: External TIN0 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 14,15 No functions assigned TOP05CKS (TOP0-5 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. 0 – 0 – Function 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode R W 10-71 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOP0-5 Control Register 1 (TOP05CR1) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 8-11 12,13 14,15 Bit Name No functions assigned TOP5M (TOP5 operation mode selection) TOP4M (TOP4 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – Clock bus 3210 Input event bus 3210 S clk en TOP 0 TOP 1 clk en en clk TOP 2 clk en TOP 3 clk en TOP 4 clk TIN0 TIN0S S en TOP 5 S : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted . Figure 10.3.5 Outline Diagram of TOP0-5 Clock/Enable Inputs 10-72 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOP6,7 Control Register (TOP67CR) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0 1 Bit Name No functions assigned TOP7ENS (TOP7 enable source selection) 2,3 TOP7M (TOP7 operation mode selection) 0: Result selected by TOP67ENS bit 1: TOP6 output 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 4,5 6,7 No functions assigned TOP6M (TOP6 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 8 9-11 No functions assigned TOP67ENS (TOP6, TOP7 enable source selection) 0XX: External TIN1 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 14,15 No functions assigned TOP67CKS (TOP6, TOP7 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. 0 – 0 – 0 – Function R 0 W – 10-73 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 3210 3210 S clk en TOP 6 udf clk TIN1 TIN1S S S en TOP 7 udf S : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.6 Outline Diagram of TOP6, TOP7 Clock/Enable Inputs 10-74 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOP8-10 Control Register (TOP810CR) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0,1 2,3 4,5 6,7 8-10 11 Bit Name No functions assigned TOP10M (TOP10 operation mode selection) 00: Single-shot output mode TOP9M (TOP9 operation mode selection) TOP8M (TOP8 operation mode selection) No functions assigned TOP810ENS (TOP8-10 enable source selection) 12,13 14,15 No functions assigned TOP810CKS (TOP8-10 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 01: Clock bus 3 Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. 0: External TIN2 input 1: Input event bus 3 0 – 01: Delayed single-shot output mode 1X: Continuous output mode 0 – Function R 0 W – 10-75 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Input event bus 3210 S clk en en TOP 8 clk clk TIN2 TIN2S S TOP 9 en TOP 10 S : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.7 Outline Diagram of TOP8-10 Clock/Enable Inputs 10-76 32170/32174 Group User's Manual (Rev. 2.1) 10 10.3.5 TOP Counters (TOP0CT-TOP10CT) s TOP0 Counter (TOP0CT) s TOP1 Counter (TOP1CT) s TOP2 Counter (TOP2CT) s TOP3 Counter (TOP3CT) s TOP4 Counter (TOP4CT) s TOP5 Counter (TOP5CT) s TOP6 Counter (TOP6CT) s TOP7 Counter (TOP7CT) s TOP8 Counter (TOP8CT) s TOP9 Counter (TOP9CT) s TOP10 Counter (TOP10CT) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN D 0-4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned Function R 0 W – TOP10EEN (TOP10 external enable permit) 0: Disables external enable TOP9EEN (TOP9 external enable permit) TOP8EEN (TOP8 external enable permit) TOP7EEN (TOP7 external enable permit) TOP6EEN (TOP6 external enable permit) TOP5EEN (TOP5 external enable permit) TOP4EEN (TOP4 external enable permit) TOP3EEN (TOP3 external enable permit) TOP2EEN (TOP2 external enable permit) TOP1EEN (TOP1 external enable permit) TOP0EEN (TOP0 external enable permit) 1: Enables external enable Note: This register must always be accessed in halfwords. The TOP0-10 External Enable Permit Register controls enable operation from sources external to the TOP counter by enabling or disabling it. 10-80 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) s TOP0-10 Enable Protect Register (TOPPRO) D0 1 2 3 4 5 6 7 8 9 10 11 D 0-4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TOP10PRO (TOP10 enable protect) TOP9PRO (TOP9 enable protect) TOP8PRO (TOP8 enable protect) TOP7PRO (TOP7 enable protect) TOP6PRO (TOP6 enable protect) TOP5PRO (TOP5 enable protect) TOP4PRO (TOP4 enable protect) TOP3PRO (TOP3 enable protect) TOP2PRO (TOP2 enable protect) TOP1PRO (TOP1 enable protect) TOP0PRO (TOP0 enable protect) 0: Enables rewrite 1: Disables rewrite Function R 0 W – Note: This register must always be accessed in halfwords. The TOP0-10 Enable Protect Register controls rewriting of the TOP0-10 count enable bits shown in the next page by enabling or disabling rewrite. 10-81 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOP0-10 Count Enable Register (TOPCEN) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) D 0-4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TOP10CEN (TOP10 count enable) TOP9CEN (TOP9 count enable) TOP8CEN (TOP8 count enable) TOP7CEN (TOP7 count enable) TOP6CEN (TOP6 count enable) TOP5CEN (TOP5 count enable) TOP4CEN (TOP4 count enable) TOP3CEN (TOP3 count enable) TOP2CEN (TOP2 count enable) TOP1CEN (TOP1 count enable) TOP0CEN (TOP0 count enable) 0: Stops count 1: Enables count Function R 0 W – Note: This register must always be accessed in halfwords. The TOP0-10 Count Enable Register controls the operation of TOP counter. To enable the counter in software, enable the relevant TOP0-10 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOP0-10 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOP0-10 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-82 32170/32174 Group User's Manual (Rev. 2.1) 10 TOPm external enable (TOPmEEN) F/F Edge selection TINnS Event bus Dn TOPm enable protect (TOPmPRO) F/F WR F/F WR EN-ON MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOPm enable (TOPmCEN) TOP enable control Figure 10.3.8 Configuration of the TOP Enable Circuit 10-83 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOP single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload register value + 1) only once and stops without performing any operation. When after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of the reload register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload register set value + 1). In the case shown below, for example, if the reload register value = 7, then the count value = 8. Because all internal circuits operate synchronously with the count clock, a finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Count value =8 1 Count clock Enable Counter 2 3 4 5 6 7 8 (Note 1) (7) 6 5 4 3 2 1 0 H’FFFF Reload register 7 F/F output Interrupt * A finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7. Note 2: This diagram does not show detail timing information. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode 10-84 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the reload register has the initial value H'A000 set in it. (The initial value of the counter can be indeterminate, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter causing it to start counting. Thereafter, it continues counting down clock pulses until it underflows after reaching the minimum count. Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit H’FFFF Starts counting down from the reload register set value H’A000 Counter H’FFFF H’0000 Reload register H’A000 Correction register (Not used) F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode 10-85 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts. Count value =(7+1)+(3+1)=12 1 2 3 4 5 6 7 8 9 10 11 12 Count clock Prescaler delay Enable (Note 1) (7) 6 6 4 3 +3 Counter 5 5 4 3 2 1 0 H’FFFF Reload register 7 Correction register Interrupt 3 Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7 . Note 2: This diagram does not show detail timing information. Figure 10.3.11 Example of Counting in TOP Single-shot Output Mode When Count is Corrected 10-86 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. In the example below, the reload register has the initial value H'8000 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'4000 is written to the correction register when the counter has counted down to H'5000. As a result of this correction, the count has been increased to H'9000, so that the counter stops after counting a total of (H'8000 + 1 + H'4000 + 1) counts. 10-87 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Disabled (by underflow) Count clock Enable bit Write to correction register H’FFFF H’FFFF H’5000+H’4000 Counter H’8000 H’5000 H’0000 Reload register H’8000 Correction register Indeterminate H’4000 F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.3.12 Example of Counting in TOP Single-shot Output Mode When Count is Corrected 10-88 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Write to enable bit Internal clock Prescaler cycle Count clock Enable F/F operation Delay till prescaler cycle Figure 10.3.13 Prescaler Delay • When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. In the example below, the reload register has the initial value H'FFF8 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'0014 is written to the correction register when the counter has counted down to H'FFF0. As a result of this correction, the count overflows to H'0004 and fails to count correctly. Also, an interrupt is generated for an erroneous overcount. 10-89 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit Write to correction register Overflow occurs H’(FFF0+0014) H’FFFF H’FFF8 H’FFFF Indeterminate H’FFF0 Counter H’0004 H’0000 Actual count after overflow Reload register H’FFF8 Correction register Indeterminate H’0014 F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.3.14 Example of Operation in TOP Single-shot Output Mode Where Count Overflows due to Correction 10-90 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOP delayed single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function) In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Count value =(4+1)+(5+1)=11 1 2 3 4 5 6 7 8 9 1 0 1 1 Count clock Prescaler delay Enable Counter (Note 2) (5) 4 2 1 0 H’FFFF (Note 1) (4) 3 3 2 1 0 H’FFFF Reload register F/F output Interrupt 5 Underflow Underflow Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note 3: This diagram does not show detail timing information. Figure 10.3.15 Example of Counting in TOP Delayed Single-shot Output Mode 10-91 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'F000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register. Then when the counter underflows next time while continuing downcount, it stops. Enabled (by writing to enable bit or by external input) Underflow (first time) Underflow (second time) Count clock Enable bit H’FFFF H’F000 Down-count starting from counter’s set value H’(F000-1) Down-count starting from reload register’s set value H’FFFF H’A000 Counter H’0000 Reload register H’F000 Correction register (Not used) F/F output Data inverted by underflow Data inverted by underflow TOP interrupt due to underflow Note: This diagram does not show detail timing information. Figure 10.3.16 Typical Operation in TOP Delayed Single-shot Output 10-92 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP delayed single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts after reload. Count value after reload =(7+1)+(3+1)=12 1 2 3 4 5 6 7 8 9 10 11 12 Count clock Enable = "H" (Note 1) (7) 6 6 4 3 Counter 0 5 5 4 3 2 1 0 H’FF +3 Reload register 7 Correction register Interrupt 3 Underflow Note 1: What you actually see in the cycle immediately after reload is the previous counter valu and not 7. Note 2: This diagram does not show detail timing information. Figure 10.3.17 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. 10-93 32170/32174 Group User's Manual (Rev. 2.1) 10 Underflow (first time) MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Underflow (second time) Count clock Enable bit Write to correction register H’FFFF H’(F000+0008+1) H’F000 Counter corrected Counter H’A000 H’0000 Reload register Correction register Indeterminate H’F000 H’0008 F/F output Data inverted by underflow TOP interrupt due to underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.3.18 Typical Operation in TOP Delayed Single-shot Output Mode when Correction Applied 10-94 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. Reload due to underflow Count clock Enable bit "H" Reload cycle Counter value H’0001 H’0000 H’FFFF Down-count starting from reloaded register value H’AAA9 H’(AAAA-1) H’AAA8 H’(AAAA-2) Reload register H’AAAA During reload cycle, you always see H’FFFF, and not the reload register value (in this case, H’AAAA). Figure 10.3.19 Counter Value Immediately after Underflow 10-95 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOP continuous output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. 10-96 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Count value =5 1 2 3 4 5 1 Count value =6 2 3 4 5 6 1 Count value =6 2 3 4 5 6 Count clock Prescaler delay Enable Counter (Note 1) (4) 3 (Note 2) (5) 4 2 1 0 3 (Note 2) (5) 4 2 1 0 (Note 2) (5) 3 2 1 0 H’FFFF Reload register 5 F/F output Interrupt Underflow Underflow Underflow Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note 3: This diagram does not show detail timing information. Figure 10.3.20 Example of Counting in TOP Continuous Output Mode 10-97 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'E000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register and continues counting down. Enabled (by writing to enable bit Underflow (first time) or by external input) Underflow (second time) Count clock Enable bit H’FFFF H’FFFF H’E000 Down-count starting from counter’s set value H’(E000-1) Down-count starting from reload register set value H’(E000-1) Down-count starting from reload register set value H’FFFF H’A000 Counter H’0000 Reload register H’E000 Correction register (Not used) F/F output Data inverted by enable TOP interrupt due to underflow Data inverted by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.3.21 Typical Operation in TOP Continuous Output Mode 10-98 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Write to enable bit Internal clock Prescaler cycle Count clock Enable F/F operation Delay till prescaler cycle Figure 10.3.22 Prescaler Delay 10-99 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.1 Outline of TIO TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Measure clear input mode • Measure free-run input mode • Nose processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode The table below shows specifications of TIO. The diagram in the next page shows a block diagram of TIO. Table 10.4.1 Specifications of TIO (Input/Output-related 16-bit Timer) Item Number of channels Counter Reload register Measure register Timer startup Specification 10 channels 16-bit down-counter 16-bit reload register 16-bit capture register Started by writing to enable bit in software or by enabling with external input (rising/falling edge or both or high/low level) Mode selection • Measure clear input mode • Measure free-run input mode • Nose processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode Interrupt generation Can be generated by a counter underflow 10-100 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) O TIO 0 Reload 0/measure register IRQ0 utput event bus 0123 S clk Down-counter Reload 1 register (note) udf S F/F11 TO 11 IRQ12 (16 bits) en/cap S TIN3 TIN3S IRQ12 IRQ0 clk TIN4 TIN5 TIN4S TIN5S IRQ12 en/cap en/cap en/cap en/cap TIO 1 TIO 2 TIO 3 TIO 4 udf IRQ0 S S IRQ0 F/F12 F/F13 F/F14 TO 12 TO 13 TO 14 S clk S clk udf udf S IRQ4 IRQ12 S S clk udf S TIN6 TIN6S F/F15 TO 15 1/2 internal clock PRS0 PRS1 PRS2 S IRQ4 TCLK1 TIN7 TCLK2 TIN8 TCLK1S TIN7S IRQ8 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 DRQ10 TCLK2S TIN8S IRQ8 S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 DRQ11 IRQ8 S S clk en/cap TIO 7 udf IRQ3 S DRQ0 F/F18 TO 18 TIN9 TIN9S IRQ8 S S clk TIN10 TIN10S IRQ8 en/cap TIO 8 udf IRQ3 S F/F19 TO 19 S S 3210 3210 clk TIN11 TIN11S en/cap TIO 9 udf F/F20 TO 20 0123 PRS0 ~ 2 : Prescaler F/F : Output flip-flop S : Selector Note: Reload 1 Register is used in only PWM output mode. Figure 10.4.1 Block Diagram of TIO (Input/Output-related 16-bit Timer) 10-101 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.2 Outline of Each Mode of TIO MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to a register called the "measure register." Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. In measure free-run mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Note that an interrupt can be generated by a counter underflow or execution of measure operation. (2) Noise processing input mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt can be generated by a counter underflow. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. 10-102 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. 10-103 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. 10-104 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.3 TIO Related Register Map MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) The diagram below shows a TIO related register map. Address D0 +0 Address D7 D8 +1 Address D15 H’0080 0300 H’0080 0302 H’0080 0304 H’0080 0306 TIO0 Counter (TIO0CT) TIO0 Reload 1 Register (TIO0RL) TIO0 Reload 0/ Measure Register (TIO0RL0) H’0080 0310 H’0080 0312 H’0080 0314 H’0080 0316 H’0080 0318 H’0080 031A H’0080 031C TIO1 Counter (TIO1CT) TIO1 Reload 1 Register (TIO1RL1) TIO1 Reload 0/ Measure Register (TIO1RL0) TIO0-3 Control Register 0 (TIO03CR0) TIO0-3 Control Register 1 (TIO03CR1) H’0080 0320 H’0080 0322 H’0080 0324 H’0080 0326 TIO2 Counter (TIO2CT) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) H’0080 0330 H’0080 0332 H’0080 0334 H’0080 0336 TIO3 Counter (TIO3CT) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.4.2 TIO Related Register Map (1/3) 10-105 32170/32174 Group User's Manual (Rev. 2.1) 10 Address D0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H’0080 0340 H’0080 0342 H’0080 0344 H’0080 0346 H’0080 0348 H’0080 034A TIO4 Counter (TIO4CT) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) TIO4 Control Register (TIO4CR) TIO5 Control Register (TIO5CR) H’0080 0350 H’0080 0352 H’0080 0354 H’0080 0356 TIO5 Counter (TIO5CT) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) H’0080 0360 H’0080 0362 H’0080 0364 H’0080 0366 H’0080 0368 H’0080 036A TIO6 Counter (TIO6CT) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR) H’0080 0370 H’0080 0372 H’0080 0374 H’0080 0376 TIO7 Counter (TIO7CT) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.4.3 TIO Related Register Map (2/3) 10-106 32170/32174 Group User's Manual (Rev. 2.1) 10 Address D0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H’0080 0380 H’0080 0382 H’0080 0384 H’0080 0386 H’0080 0388 H’0080 038A TIO8 Counter (TIO8CT) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/ Measure Register (TIO8RL0) TIO8 Control Register (TIO8CR) TIO9 Control Register (TIO9CR) H’0080 0390 H’0080 0392 H’0080 0394 H’0080 0396 TIO9 Counter (TIO9CT) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) H’0080 03BC H’0080 03BE TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.4.4 TIO Related Register Map (3/3) 10-107 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.4 TIO Control Registers MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) The TIO control registers are used to select TIO0-9 operation modes (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output, or continuous output mode), as well as select the counter enable and counter clock sources. Following eight TIO control registers are provided for each timer group. • TIO0-3 Control Register 0 (TIO03CR0) • TIO0-3 Control Register 1 (TIO03CR1) • TIO4 Control Register (TIO4CR) • TIO5 Control Register (TIO5CR) • TIO6 Control Register (TIO6CR) • TIO7 Control Register (TIO7CR) • TIO8 Control Register (TIO8CR) • TIO9 Control Register (TIO9CR) 10-108 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO0-3 Control Register 0 (TIO3CR0) D0 TIO3 EEN MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0 Bit Name TIO3EEN (TIO3 external input enable) (Note 2) 1-3 TIO3M (TIO3 operation mode selection) Function 0: Disables external input 1: Enables external input 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode 4 TIO2ENS (TIO2 enable/ measure input source selection) 5-7 TIO2M (TIO2 operation mode selection) 0: No selection 1: External input TIN5 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode 8 TIO1ENS (TIO1 enable/ measure input source selection) 0: No selection 1: External input TIN4 (Continues to the next page) Note 1: To select the TIO3 enable/measure input source, use the TIO4 Control Register's TIO34ENS (TIO3, TIO4 enable/measure input source selection) bit. Note 2: During measure free-run/clear input mode, even if this bit is set to 0 (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. However, because in measure clear input mode, if this bit = 0 (external input disabled), the counter value is not initialized (H'FFFF) upon capture, we recommend that this bit be set to 1 (external input enabled) when using measure clear input mode. Note 3: This register must always be accessed in halfwords. Note 4: Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-109 32170/32174 Group User's Manual (Rev. 2.1) 10 (Continued from the preceding page) D 9-11 Bit Name TIO1M (TIO1 operation mode selection) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Function 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode R W 12 TIO0ENS (TIO0 enable/ measure input source selection) 0: No selection 1: External input TIN3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode 13-15 TIO0M (TIO0 operation mode selection) Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. Clock bus Input event bus 3210 3210 S clk TIN3 TIN4 TIN5 TIN3S TIN4S TIN5S S clk S clk S clk en/cap TIO 3 en/cap TIO 2 en/cap TIO 1 en/cap TIO 0 S TIN6 TIN6S 3210 3210 clk en/cap TIO 4 S S : Selector Note: This diagram is shown for the explanation of TIO control registers, and is partly omitted. Figure 10.4.5 Outline Diagram of TIO0-4 Clock/Enable Inputs 10-110 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO0-3 Control Register 1 (TIO03CR1) D8 9 10 11 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8-13 14,15 Bit Name No functions assigned TIO03CKS (TIO0-3 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Function R 0 W – 10-111 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO4 Control Register (TIO4CR) D0 TIO4CKS 1 2 TIO4EEN 3 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0, 1 Bit Name TIO4CKS (TIO4 clock source selection) Function 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2 TIO4EEN (Note 1) (TIO4 external input enable) 3,4 TIO34ENS (TIO3,4 enable/measure input source selection) 5-7 TIO4M (TIO4 operation mode selection) 0: Disables external input 1: Enables external input 0X: External input TIN6 10: Input event bus 2 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to 0 (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. However, because in measure clear input mode, if this bit = 0 (external input disabled), the counter value is not initialized (H'FFFF) upon capture, we recommend that this bit be set to 1 (external input enabled) when using measure clear input mode. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-112 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Input event bus 3210 3210 TCLK1 TIN7 TCLK1S TIN7S S S clk en/cap TIO 5 TCLK2 TIN8 TCLK2S TIN8S S S clk en/cap TIO 6 S TIN9 TIN9S S clk en/cap TIO 7 S TIN10 TIN10S S clk en/cap TIO 8 S TIN11 TIN11S 3210 3210 clk S en/cap TIO 9 S : Selector Note: This is an outline diagram shown for the explanation of TIO Control Register Figure 10.4.6 Outline Diagram of TIO5-9 Clock/Enable Inputs 10-113 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO5 Control Register (TIO5CR) D8 9 TIO5CKS 10 11 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8-10 Bit Name TIO5CKS (TIO5 clock source selection) Function 0XX: External input TCLK1 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11,12 TIO5ENS (TIO5 enable/measure input source selection) 13-15 TIO5M (TIO5 operation mode selection) 0X: No selection 10: External input TIN7 11: Input event bus 3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-114 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO6 Control Register (TIO6CR) D0 1 TIO6CKS 2 3 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0-2 Bit Name TIO6CKS (TIO6 clock source selection) Function 0XX: External input TCLK2 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3,4 TIO6ENS (TIO6 enable/measure input source selection) 00: No selection 01: External input TIN8 10: Input event bus 2 11: Input event bus 3 5-7 TIO6M (TIO6 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-115 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO7 Control Register (TIO7CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8 9,10 Bit Name No functions assigned TIO7CKS (TIO7 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO7ENS (TIO7 enable/measure input source selection) 00: No selection 01: External input TIN9 10: Input event bus 0 11: Input event bus 3 13-15 TIO7M (TIO7 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – 10-116 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO8 Control Register (TIO8CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0,1 Bit Name TIO8CKS (TIO8 clock source selection) Function 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2-4 TIO8ENS (TIO8 enable/measure input source selection) 0XX: No selection 100: External input TIN10 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5-7 TIO8M (TIO8 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. R W 10-117 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO9 Control Register (TIO9CR) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 8 9,10 Bit Name No functions assigned TIO9CKS (TIO9 clock source selection) 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO9ENS (TIO9 enable/measure input source selection) 00: No selection 01: External input TIN1 10: Input event bus 1 11: Input event bus 3 13-15 TIO9M (TIO9 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. Function R 0 W – 10-118 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.5 TIO Counter (TIO0CT-TIO9CT) s TIO0 Counter (TIO0CT) s TIO1 Counter (TIO1CT) s TIO2 Counter (TIO2CT) s TIO3 Counter (TIO3CT) s TIO4 Counter (TIO4CT) s TIO5 Counter (TIO5CT) s TIO6 Counter (TIO6CT) s TIO7 Counter (TIO7CT) s TIO8 Counter (TIO8CT) s TIO9 Counter (TIO9CT) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TIO0CT-TIO9CT D 0-15 W= Bit Name TIO0CT-TIO9CT Function 16-bit counter value R W : Write to this register is not accepted is disabled in PWM output mode. Note: This register must always be accessed in halfwords. The TIO Counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. The counter cannot be written to during PWM output mode. 10-119 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.6 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0) 9 10 11 12 13 14 D15 s TIO0 Reload 0/ Measure Register (TIO0RL0) s TIO1 Reload 0/ Measure Register (TIO1RL0) s TIO2 Reload 0/ Measure Register (TIO2RL0) s TIO3 Reload 0/ Measure Register (TIO3RL0) s TIO4 Reload 0/ Measure Register (TIO4RL0) s TIO5 Reload 0/ Measure Register (TIO5RL0) s TIO6 Reload 0/ Measure Register (TIO6RL0) s TIO7 Reload 0/ Measure Register (TIO7RL0) s TIO8 Reload 0/ Measure Register (TIO8RL0) s TIO9 Reload 0/ Measure Register (TIO9RL0) D0 1 2 3 4 5 6 7 8 TIO0RL0-TIO9RL0 D 0-15 W= Bit Name TIO0RL0-TIO9RL0 Function 16-bit reload register value R W : Write to this register is not accepted is disabled in PWM output mode. Note: This register must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading TIO Count Registers (TIO0CT-TIO9CT) with data, and as a measure register during measure input mode. These registers are disabled against write during measure input mode. It is in the following cases that the content of reload 0 register is loaded into the counter: • When after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows • When the counter is enabled in single-shot mode • When the counter underflowed in delayed single-shot or continuous mode • When the counter is enabled in PWM mode and when the counter value set by reload 1 register underflowed Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. When used as a measure register, the counter value is latched into the measure register by an event input. 10-120 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO0 Reload 1 Register (TIO0RL1) s TIO1 Reload 1 Register (TIO1RL1) s TIO2 Reload 1 Register (TIO2RL1) s TIO3 Reload 1 Register (TIO3RL1) s TIO4 Reload 1 Register (TIO4RL1) s TIO5 Reload 1 Register (TIO5RL1) s TIO6 Reload 1 Register (TIO6RL1) s TIO7 Reload 1 Register (TIO7RL1) s TIO8 Reload 1 Register (TIO8RL1) s TIO9 Reload 1 Register (TIO9RL1) D0 1 2 3 4 5 6 7 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) 8 9 10 11 12 13 14 D15 TIO0RL1-TIO9RL1 D 0-15 Bit Name TIO0RL1-TIO9RL1 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload the TIO Counter Registers (TIO0CT-TIO9CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter: • When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. 10-121 32170/32174 Group User's Manual (Rev. 2.1) 10 10.4.8 TIO Enable Control Registers MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) s TIO0-9 Enable Protect Register (TIOPRO) D 0-5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TIO9PRO (TIO9 Enable Protect) TIO8PRO (TIO8 Enable Protect) TIO7PRO (TIO7 Enable Protect) TIO6PRO (TIO6 Enable Protect) TIO5PRO (TIO5 Enable Protect) TIO4PRO (TIO4 Enable Protect) TIO3PRO (TIO3 Enable Protect) TIO2PRO (TIO2 Enable Protect) TIO1PRO (TIO1 Enable Protect) TIO0PRO (TIO0 Enable Protect) 0: Enables rewrite 1: Disables rewrite Function R 0 W – Note: This register must always be accessed in halfwords. The TIO0-9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling rewrite. 10-122 32170/32174 Group User's Manual (Rev. 2.1) 10 s TIO0-9 Count Enable Register (TIOCEN) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) D 0-5 6 7 8 9 10 11 12 13 14 15 Bit Name No functions assigned TIO9CEN (TIO9 count enable) TIO8CEN (TIO8 count enable) TIO7CEN (TIO7 count enable) TIO6CEN (TIO6 count enable) TIO5CEN (TIO5 count enable) TIO4CEN (TIO4 count enable) TIO3CEN (TIO3 count enable) TIO2CEN (TIO2 count enable) TIO1CEN (TIO1 count enable) TIO0CEN (TIO0 count enable) 0: Stops count 1: Enables count Function R 0 W – Note: This register must always be accessed in halfwords. The TIO0-9 Count Enable Register controls operation of TIO counters. To enable the counter in software, enable the relevant TIO0-9 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TIO0-9 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TIO0-9 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-123 32170/32174 Group User's Manual (Rev. 2.1) 10 TIOm external enable (TIOmEEN or TIOmENS) F/F Edge selection TINnS Event bus Dn TIOm enable protect (TIOmPRO) F/F MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) EN-ON TIOm enable (TIOmCEN) F/F WR TIO enable control WR Figure 10.4.7 Configuration of the TIO Enable Circuit 10-124 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.9 Operation in TIO Measure Free-run/Clear Input Modes (1) Outline of TIO measure free-run/clear input modes In TIO measure free-run/clear input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. An interrupt can be generated by a counter underflow or execution of measure operation. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. When the counter underflows after reaching the minimum count, it starts counting down from H'FFFF again. In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. 10-125 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Measure event Enabled (capture) (by writing to enable bit) occurs Measure event (capture) occurs Count clock Enable bit H’FFFF H’9000 Counter H’7000 H’0000 Measure register Indeterminate H’7000 H’9000 TIN interrupt TIN interrupt by external event input TIO interrupt TIO interrupt by underflow Note: This diagram does not show detail timing information. TIN interrupt by external event input Figure 10.4.8 Typical Operation in Measure Free-run Input Mode 10-126 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit) Measure event (capture) occurs Count clock Enable bit H’FFFF Counter H’7000 H’0000 Measure register Indeterminate H’7000 TIN interrupt TIN interrupt by external event input TIO interrupt TIO interrupt by underflow Note: This diagram does not show detail timing information. Figure 10.4.9 Typical Operation in Measure Clear Input Mode 10-127 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Precautions to be observed when using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched into the measure register. 10-128 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.10 Operation in TIO Noise Processing Input Mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The valid count value is (reload 0 register set value + 1). The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt can be generated by a counter underflow. Enabled (by writing to enable bit or by external input) Count clock Disabled by underflow Enable bit External input (noise processing) Invalid H’FFFF Invalid Valid signal width H’A000 Counter H’0000 Reload 0 register H’A000 TIO interrupt Note: This diagram does not show detail timing information. TIO interrupt by underflow Figure 10.4.10 Typical Operation in Noise Processing Input Mode 10-129 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TIO PWM output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.11 Operation in TIO PWM Output Mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TIO's PWM output mode does not have the correction function. 10-130 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit Underflow (first time) or by external input) Underflow (second time) Count clock Enable bit Down-count starting from reload 0 register set value H’C000 Down-count starting from reload 1 register set value H’(C000-1) Down-count starting from reload 0 register set value H’FFFF H’(A000-1) H’A000 H’A000 Counter H’0000 Reload 0 register H’A000 Reload 1 register H’C000 F/F output Data inverted by enable TIO interrupt by underflow PWM output period Data inverted by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.4.11 Typical Operation in PWM Output Mode 10-131 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Internal bus Reload 1 TIOnRL1 Reload1WR Reload0WR Reload 1 Buffer TIOnRL0 PWM mode control Prescaler output 16-bit counter F/F TO Figure 10.4.12 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. 10-132 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’8000 H’9000 Old PWM output period F/F output New PWM output period Operation by new reload value written Enlarged view New PWM output period Count clock Counter H’0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output Timing at which reload 1 and reload 0 registers are updated PWM period latched H’1000 H’2000 H’2000 H’8000 H’9000 H’9000 H’0000 H’FFFF H’7FFF H’7FFE Note: This diagram does not show detail timing information. (b) When reload register updates take effect in the next period (reflected one period later) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’9000 H’8000 Old PWM output period F/F output Old PWM output period Operation by old reload value Enlarged view Old PWM output period Count clock Counter Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output PWM period latched Timing at which reload 1 and reload 0 registers are updated H’2000 H’2000 H’1000 H’9000 H’9000 H’800 0 H’000 1 H’000 0 H’ FFFF H’0FFF H’0FFE Note: This diagram does not show detail timing information. Figure 10.4.13 Reload 0 and Reload 1 Register Updates in PWM Output Mode 10-133 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TIO single-shot output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.9, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-134 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled (by writing to enable bit or by external input) Count clock Disabled (by underflow) Enable bit H’FFFF H’A000 Counter Counts down starting from reload 0 register set value H’0000 Reload 0 register H’A000 Reload 1 register (Not used) F/F output Data inverted by enable TIO interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.4.14 Typical Operation in TIO Single-shot Output Mode (without Correction Function) 10-135 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.10, "Operation in TOP Delayed Single-shot Output Mode (With Correction Function)." (2) Precautions to be observed when using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. 10-136 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) Count clock MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Underflow (first time) Underflow (second time) Enable bit H’FFFF H’F000 H’EFFF Down-count starting from reload 0 register set value H’A000 Counter Down-count starting from counter set value H’0000 Reload 0 register H’F000 Reload 1 register (Not used) F/F output Data inverted by underflow TIO interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.4.15 Typical Operation in TIO Deleted Single-shot Output Mode (without Correction Function) 10-137 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TIO continuous output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output M10.4 TIO (Input/Output-related 16-bit Timer) (2) Precautions to be observed when using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-138 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) Count clock Enable bit H’FFFF H’E000 H’A000 Down-count starting from counter set value MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Underflow (first time) Underflow (second time) H’DFFF Down-count starting from reload 0 register set value H’DFFF Down-count starting from reload 0 register set value Counter H’0000 Reload 0 register H’E000 Reload 1 register (Not used) F/F output Data inverted by enable TIO interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.4.16 Typical Operation in TIO Continuous Output Mode (without Correction Function) 10-139 32170/32174 Group User's Manual (Rev. 2.1) 10 10.5 TMS (Input-related 16-bit Timer) 10.5.1 Outline of TMS MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total eight channels. The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS. Table 10.5.1 Specifications of TMS (Input-related 16-bit Timer) Item Number of channels Counter Measure register Timer startup Interrupt generation Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) 16-bit up-counter × 2 16-bit measure register × 8 Started by writing to enable bit in software Can be generated by a counter overflow 10.5.2 Outline of TMS Operation In TMS, when the timer is started by writing to the enable bit in software, the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. A TIN interrupt can be generated by entering an external measure signal. Also, a TMS interrupt can be generated by a counter overflow. 10-140 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) Output event bus 0123 TMS 0 ovf TCLK3 TCLK3S S clk Counter (16 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ10 IRQ7 cap3 S cap2 cap1 cap0 TIN12 TIN12S IRQ10 TIN13 TIN13S DRQ3 IRQ10 S TIN14 TIN14S IRQ10 S TIN15 TIN15S S IRQ7 S IRQ10 clk cap3 S TMS 1 cap2 cap1 ovf cap0 TIN16 TIN16S IRQ10 TIN17 TIN17S DRQ5 IRQ10 S TIN18 TIN18S DRQ6 IRQ10 S TIN19 TIN19S 3210 3210 S 0123 S : Selector Figure 10.5.1 Block Diagram of TMS (Input-related 16-bit Timer) 10-141 32170/32174 Group User's Manual (Rev. 2.1) 10 10.5.3 TMS Related Register Map The diagram below shows a TMS related register map. MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) Address D0 +0 Address D7 D8 +1 Address D15 H’0080 03C0 H’0080 03C2 H’0080 03C4 H’0080 03C6 H’0080 03C8 H’0080 03CA TMS Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) TMS1 Control Register (TMS1CR) H’0080 03D0 H’0080 03D2 H’0080 03D4 H’0080 03D6 H’0080 03D8 TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. . Figure 10.5.2 TMS Related Register Map 10-142 32170/32174 Group User's Manual (Rev. 2.1) 10 10.5.4 TMS Control Registers MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) The TMS control registers are used to select TMS0/1 input events and the counter clock source, as well as control counter startup. Following two TMS control registers are included: • TMS0 Control Register (TMS0CR) • TMS1 Control Register (TMS1CR) s TMS0 Control Register (TMS0CR) D 0 Bit Name TMS0SS0 (TMS0 measure 0 source selection) 1 TMS0SS1 (TMS0 measure 1 source selection) 2 TMS0SS2 (TMS0 measure 2 source selection) 3 TMS0SS3 (TMS0 measure 3 source selection) 4,5 TMS0CKS (TMS0 clock source selection) Function 0: External input TIN15 1: Input event bus 0 0: External input TIN14 1: Input event bus 1 0: External input TIN13 1: Input event bus 2 0: External input TIN12 1: Input event bus 3 00: External input TCLK3 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 7 No functions assigned TMS0CEN (TMS0 count enable) 0: Count stops 1: Count starts 0 – R W 10-143 32170/32174 Group User's Manual (Rev. 2.1) 10 s TMS1 Control Register (TMS1CR) MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) D 8 Bit Name TMS1SS0 (TMS1measure 0 source selection) 9 TMS1SS1 (TMS1 measure 1 source selection) 10 TMS1SS2 (TMS1 measure 2 source selection) 11 TMS1SS3 (TMS1 measure 3 source selection) 12 13 No functions assigned TMS1CKS (TMS1 clock source selection) 14 15 No functions assigned TMS1CEN (TMS1 count enable) 0: Count stops 1: Count starts 0: Clock bus 0 1: Clock bus 3 0 – Function 0: External input TIN19 1: Input event bus 0 0: External input TIN18 1: Input event bus 1 0: External input TIN17 1: Input event bus 2 0: External input TIN16 1: Input event bus 3 0 – R W 10-144 32170/32174 Group User's Manual (Rev. 2.1) 10 10.5.5 TMS Counter (TMS0CT, TMS1CT) s TMS0 Counter (TMS0CT) s TMS1 Counter (TMS1CT) D0 1 2 3 4 5 6 7 8 9 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10 11 12 13 14 D15 TMS0CT, TMS1CT D 0-15 Bit Name TMS0CT, TMS1CT Function 16-bit counter value R W Note: This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counter can be read on-the-fly. 10-145 32170/32174 Group User's Manual (Rev. 2.1) 10 s TMS0 Measure 3 Register (TMS0MR3) s TMS0 Measure 2 Register (TMS0MR2) s TMS0 Measure 1 Register (TMS0MR1) s TMS0 Measure 0 Register (TMS0MR0) s TMS1 Measure 3 Register (TMS1MR3) s TMS1 Measure 2 Register (TMS1MR2) s TMS1 Measure 1 Register (TMS1MR1) s TMS1 Measure 0 Register (TMS1MR0) MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TMS0MR3-0, TMS1MR3-0 D 0-15 Bit Name TMS0MR3-TMS0MR0 TMS1MR3-TMS1MR0 Note 1: This register is a read-only register. Note 2: This register can be accessed in either byte or halfword. Function 16-bit reload register value R W – The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. 10-146 32170/32174 Group User's Manual (Rev. 2.1) 10 10.5.7 Operation of TMS Measure Input (1) Outline of TMS measure input MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) In TMS measure input, the counter starts counting up clock pulses when the timer is actuated by writing to the enable bit in software. When event input is entered to TMS while the timer is operating, the counter value is latched into measure registers 0-3. The timer stops at the same time count is disabled by writing to the enable bit. A TIN interrupt can be generated by entering a measure signal from an external device. Also, when the counter overflows, a TMS interrupt can be generated. Enabled Measure Measure (by writing to event 0 event 1 Overflow enable bit) occurs occurs occurs Count clock Measure event 0 occurs Measure event 1 occurs Enable bit H’FFFF H’D000 H’C000 Counter H’8000 Indeterminate value H’0000 H’6000 Measure 0 register Initial value (indeterminate) H’8000 H’6000 TIN15 interrupt Measure 1 register Initial value (indeterminate) H’C000 H’D000 TIN14 interrupt TMS interrupt by overflow Note: This diagram does not show detail timing information. Figure 10.5.3 Typical Operation in TMS Measure Input 10-147 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) (2) Precautions to be observed when using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched to the measure register. 10-148 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6 TML (Input-related 32-bit Timer) 10.6.1 Outline of TML MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML. The diagram in the next page shows a block diagram of TML. Table 10.6.1 Specifications of TML (Input-related 32-bit Timer) Item Number of channels Input clock Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Divided-by-2 frequency of the internal peripheral operating clock (e.g., 10.0 MHz when using 20 MHz internal peripheral operating clock) or clock bus 1 input Counter Measure register Timer startup 32-bit up-counter × 2 32-bit measure register × 8 Starts counting after leaving reset 10-149 32170/32174 Group User's Manual (Rev. 2.1) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) Output event bus 0123 TML0 1/2 internal peripheral clock S clk Counter (32 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 cap3 IRQ11 cap2 cap1 cap0 TIN20 TIN21 TIN22 TIN23 TIN20S IRQ11 S S IRQ11 TIN21S TIN22S IRQ11 S S TML1 S clk Counter (32 bits) Measure register 3 Measure register 2 Measure register 1 Measure register 0 TIN23S IRQ18 cap3 S cap2 cap1 cap0 TIN30 TIN31 TIN32 TIN33 TIN30S IRQ18 TIN31S IRQ18 S S IRQ18 TIN32S TIN33S S 3210 3210 0123 S : Selector Figure 10.6.1 Block Diagram of TML (Input-related 32-bit Timer) 10.6.2 Outline of TML Operation In TML, the counter starts counting upon deassertion of reset. The counter is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When reset input is deasserted, the counter starts operating with a divided-by-2 frequency of the internal peripheral clock, and cannot be stopped once it has started. The counter is idle only when the device remains reset. A TIN interrupt can be generated by entering an external measure signal. However, no TML counter overflow interrupts are available. 10-150 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6.3 TML Related Register Map The diagram below shows a TML related register map. Address D0 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) +0 Address D7 D8 +1 Address D15 H’0080 03E0 H’0080 03E2 TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) H’0080 03EA TML0 Control Register (TML0CR) H’0080 03F0 H’0080 03F2 H’0080 03F4 H’0080 03F6 H’0080 03F8 H’0080 03FA H’0080 03FC H’0080 03FE TML0 Measure 3 Register, High (TML0MR3H) TML0 Measure 3 Register, Low (TML0MR3L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 0 Register, High (TML0MR0H) TML0 Measure 0 Register, Low (TML0MR0L) H’0080 0FE0 H’0080 0FE2 TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) H’0080 0FEA TML1 Control Register (TML1CR) H’0080 0FF0 H’0080 0FF2 H’0080 0FF4 H’0080 0FF6 H’0080 0FF8 H’0080 0FFA H’0080 0FFC H’0080 0FFE TML1 Measure 3 Register, High (TML1MR3H) TML1 Measure 3 Register, Low (TML1MR3L) TML1 Measure 2 Register, High (TML1MR2H) TML1 Measure 2 Register, Low (TML1MR2L) TML1 Measure 1 Register, High (TML1MR1H) TML1 Measure 1 Register, Low (TML1MR1L) TML1 Measure 0 Register, High (TML1MR0H) TML1 Measure 0 Register, Low (TML1MR0L) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.6.2 TML Related Register Map 10-151 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6.4 TML Control Registers s TML0 Control Register (TML0CR) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D 8 Bit Name TML0SS0 (TML0 measure 0 source selection) 9 TML0SS1 (TML0 measure 1 source selection) 10 TML0SS2 (TML0 measure 2 source selection) 11 TML0SS3 (TML0 measure 3 source selection) 12-14 15 No functions assigned TML0CKS (TML0 clock source selection) 0: 1/2 internal peripheral clock 1: Clock bus 1 Function 0: External input TIN23 1: Input event bus 0 0: External input TIN22 1: Input event bus 1 0: External input TIN21 1: Input event bus 2 0: External input TIN20 1: Input event bus 3 0 – R W The TML0 Control Register is used to select TML0 input event and the counter clock source. Note: The counter can be written to normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. 10-152 32170/32174 Group User's Manual (Rev. 2.1) 10 s TML1 Control Register (TML1CR) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D 8 Bit Name TML1SS0 (TML1 measure 0 source selection) 9 TML1SS1 (TML1 measure 1 source selection) 10 TML1SS2 (TML1 measure 2 source selection) 11 TML1SS3 (TML1 measure 3 source selection) 12-14 15 No functions assigned TML1CKS (TML1 clock source selection) 0: 1/2 internal peripheral clock 1: Clock bus 1 Function 0: External input TIN33 1: Input event bus 0 0: External input TIN32 1: Input event bus 1 0: External input TIN31 1: Input event bus 2 0: External input TIN30 1: Input event bus 3 0 – R W The TML1 Control Register is used to select TML1 input event and the counter clock source. Note: The counter can be written to normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. 10-153 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6.5 TML Counters s TML0 Counter, High (TML0CTH) s TML0 Counter, Low (TML0CTL) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTH (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTL (16 low-order bits) D 0-15 Bit Name TML0CTH TML0CTL Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W Note: This register must always be accessed in words (32 bits) beginning with the address of TML0CTH. The TML0 Counter is a 32-bit up-counter, which starts counting upon deassertion of reset. The TML0CTH register accommodates the 16 high-order bits, and the TML0CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read on-the-fly. 10-154 32170/32174 Group User's Manual (Rev. 2.1) 10 s TML1 Counter, High (TML1CTH) s TML1 Counter, Low (TML1CTL) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTH (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTL (16 low-order bits) D 0-15 Bit Name TML1CTH TML1CTL Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W Note: This register must always be accessed in words (32 bits) beginning with the address of TML1CTH. The TML1 Counter is a 32-bit up-counter, which starts counting upon deassertion of reset. The TML1CTH register accommodates the 16 high-order bits, and the TML1CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read on-the-fly. 10-155 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6.6 TML Measure Registers s TML0 Measure 3 Register (TML0MR3H) s TML0 Measure 3 Register (TML0MR3L) s TML0 Measure 2 Register (TML0MR2H) s TML0 Measure 2 Register (TML0MR2L) s TML0 Measure 1 Register (TML0MR1H) s TML0 Measure 1 Register (TML0MR1L) s TML0 Measure 0 Register (TML0MR0H) s TML0 Measure 0 Register (TML0MR0L) MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0MR3H-TML0MR0H (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0MR3L-TML0MR0L (16 low-order bits) D 0-15 Bit Name TML0MR3H-0H TML0MR3L-0L Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W – Note 1: These registers are a read-only register. Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary. The TML0 Measure Registers are used to latch counter contents upon event input. The TML0 Measure Registers are configured with 32 bits, the TML0MR3H-0H accommodating the 16 highorder bits, and the TML0MR3L-0L accommodating the 16 low-order bits. The TML0 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. 10-156 32170/32174 Group User's Manual (Rev. 2.1) 10 s TML1 Measure 3 Register (TML1MR3H) s TML1 Measure 3 Register (TML1MR3L) s TML1 Measure 2 Register (TML1MR2H) s TML1 Measure 2 Register (TML1MR2L) s TML1 Measure 1 Register (TML1MR1H) s TML1 Measure 1 Register (TML1MR1L) s TML1 Measure 0 Register (TML1MR0H) s TML1 Measure 0 Register (TML1MR0L) D0 1 2 3 4 5 6 7 8 9 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10 11 12 13 14 D15 TML1MR3H-TML1MR0H (16 high-order bits) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1MR3L-TML1MR0L (16 low-order bits) D 0-15 Bit Name TML1MR3H-0H TML1MR3L-0L Function 32-bit counter value (16 high-order bits) 32-bit counter value (16 low-order bits) R W – Note 1: These registers are a read-only register. Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary. The TML1 Measure Registers are used to latch counter contents upon event input. The TML1 Measure Registers are configured with 32 bits, the TML1MR3H-0H accommodating the 16 highorder bits, and the TML1MR3L-0L accommodating the 16 low-order bits. The TML1 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. 10-157 32170/32174 Group User's Manual (Rev. 2.1) 10 10.6.7 Operation of TML Measure Input (1) Outline of TML measure input MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) In TML measure input, the counter starts counting up clock pulses upon deassertion of reset. When event input is entered to measure registers 0-3, the counter value is latched into the measure registers. A TIN interrupt can be generated by entering an external measure signal. (No TML counter overflow interrupts are available.) Enabled Measure Measure (by deassertion event 0 event 1 Overflow of reset) occurs occurs occurs Count clock Reset H’FFFF FFFF Measure event 0 occurs Measure event 1 occurs H’C000 0000 H’D000 0000 Counter (32 bits) H’8000 0000 H’6000 0000 Indeterminate value H’0000 0000 Measure 0 register Initial value (indeterminate) H’8000 0000 H’6000 0000 TIN23 interrupt Measure 1 register H’C000 0000 H’D000 0000 Initial value (indeterminate) TIN22 interrupt Note: This diagram does not show detail timing information. Figure 10.6.3 Typical Operation in TML Measure Input 10-158 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) (2) Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched to the measure register. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the counter cannot be written to normally. Therefore, when operating with any clock other than the 1/2 internal peripheral clock, do not write to the counter. • If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the captured value is one that leads the actual counter value by one clock period. However, during the 1/2 internal peripheral clock interval from the count clock, this problem does not occur and the counter value is captured at exact timing. The diagram below shows the relationship between counter operation and the valid data that can be captured. When 1/2 internal peripheral clock is selected 1/2 internal peripheral clock Counter A B C D E F Capture A B C D E F When clock bus 1 is selected 1/2 internal peripheral clock Count clock Counter A B C Capture B C D Figure 10.6.4 Mistimed Counter Value and Captured Value 10-159 32170/32174 Group User's Manual (Rev. 2.1) 10 10.7 TID (Input-related 16-bit Timer) 10.7.1 Outline of TID MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Fixed period count mode • Event count mode • Multiply-by-4 event count mode The table below shows specifications of TID. The diagram in the next page shows a block diagram of TID. Table 10.7.1 Specifications of TID (Input-related 16-bit Timer) Item Number of channels Counter Reload register Timer startup Mode selection Specification 3 channels 16-bit up/down-counter 16-bit reload register Started by writing to enable bit in software • Fixed period count mode • Event count mode • Multiply-by-4 event count mode Interrupt generation Can be generated by a counter underflow and overflow 10-160 32170/32174 Group User's Manual (Rev. 2.1) 10 TID0 Built-in edge control circuit S MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) Reload register TIN24 TIN25 1/2 internal peripheral clock PRS3 CLK1 CLK2 clk Up/down-counter IRQ14 TOD0_0 - 7 TID1 Built-in edge control circuit S Reload register IRQ15 TIN26 TIN27 1/2 internal peripheral clock PRS4 CLK1 CLK2 clk Up/down-counter AD1TRG (To A-D1 converter) TOD1_0 - TOD1_7 Enable signal TOD1_0 - 7 TID2 Reload register TIN28 TIN29 1/2 internal peripheral clock PRS5 Built-in edge CLK1 control circuit S CLK2 clk Up/down-counter IRQ17 TOM0_0 - TOM0_7 Enable signal TOM0_0 - 7 PRS3 - 5 : Prescaler Figure 10.7.1 Block Diagram of TID (Input-related 16-bit Timer) 10-161 32170/32174 Group User's Manual (Rev. 2.1) 10 10.7.2 TID Related Register Map The diagram below shows a TID related register map. MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) Address H’0080 078C H’0080 078E D0 +0 Address D7 D8 TID0 Counter (TID0CT) +1 Address D15 TID0 Reload Register (TID0RL) H’0080 07D0 Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) H’0080 0B8C H’0080 0B8E TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) H’0080 0BD0 Prescaler Register 4 (PRS4) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) H’0080 0C8C H’0080 0C8E TID2 Counter (TID2CT) TID2 Reload Register (TID2RL) H’0080 0CD0 Prescaler Register 5 (PRS5) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.7.2 TID Related Register Map 10-162 32170/32174 Group User's Manual (Rev. 2.1) 10 10.7.3 TID Control &Prescaler Enable Registers MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) s TID0 Control &Prescaler 3 Enable Register (TID0PRS3EN) D 8 9, 10 Bit Name No functions assigned TID0M (TID0 operation mode selection) 0X : Fixed period count mode 10 : Multiply-by-4 event count mode 11 : Event count mode 11 TID0CEN (TID0 count enable) 12 - 14 15 No functions assigned PRS3EN (Prescaler 3 enable) 0 : Count stops 1 : Count starts 0 : Count stops 1 : Count starts 0 — Function R 0 W — Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID0 Control & Prescaler 3 Enable Register selects TID0 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 3 startup. 10-163 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) s TID1 Control &Prescaler 4 Enable Register (TID1PRS4EN) D 8 9, 10 Bit Name No functions assigned TID1M (TID1 operation mode selection) 0X : Fixed period count mode 10 : Multiply-by-4 event count mode 11 : Event count mode 11 TID1CEN (TID1 count enable) 12 13 No functions assigned TID1ENO (TID1 enable output enable) 14 15 No functions assigned PRS4EN (Prescaler 4 enable) 0 : Count stops 1 : Count starts 0 : Disables enable output to TOD1_0-7 1 : Enables enable output to TOD1_0-7 0 — 0 : Count stops 1 : Count starts 0 — Function R 0 W — Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID1 Control & Prescaler 4 Enable Register selects TID1 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 4 startup. 10-164 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) s TID2 Control &Prescaler 5 Enable Register (TID2PRS5EN) D 8 9, 10 Bit Name No functions assigned TID2M (TID2 operation mode selection) 0X : Fixed period count mode 10 : Multiply-by-4 event count mode 11 : Event count mode 11 TID2CEN (TID2 count enable) 12 13 No functions assigned TID2ENO (TID2 enable output enable) 14 15 No functions assigned PRS5EN (Prescaler 5 enable) 0 : Count stops 1 : Count starts 0 : Disables enable output to TOM0_0-7 1 : Enables enable output to TOM0_0-7 0 — 0 : Count stops 1 : Count starts 0 — Function R 0 W — Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID2 Control & Prescaler 5 Enable Register selects TID2 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 5 startup. 10-165 32170/32174 Group User's Manual (Rev. 2.1) 10 10.7.4 TID Counters (TID0CT, TID1CT, TID2CT) s TID0 Counter (TID0CT) s TID1 Counter (TID1CT) s TID2 Counter (TID2CT) D0 1 2 3 4 5 6 7 8 9 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) D 0, 1 Bit Name TOD00M (TOD0_0 operation mode selection) 2, 3 TOD01M (TOD0_1 operation mode selection) 4, 5 TOD02M (TOD0_2 operation mode selection) 6, 7 TOD03M (TOD0_3 operation mode selection) 8, 9 TOD04M (TOD0_4 operation mode selection) 10, 11 TOD05M (TOD0_5 operation mode selection) 12, 13 TOD06M (TOD0_6 operation mode selection) 14, 15 TOD07M (TOD0_7 operation mode selection) Function 00 : Single-shot output mode 01 :Delayed single-shot output mode 10 : Continuous output mode 11 : PWM output mode R W The TOD0 Control Register is used to select TOD0_0-7 operation modes (PWM output, single-shot output, delayed single-shot output, or continuous output mode). 10-180 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1 Control Registers (TOD1CR) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D 0, 1 Bit Name TOD10M (TOD1_0 operation mode selection) 2, 3 TOD11M (TOD1_1 operation mode selection) 4, 5 TOD12M (TOD1_2 operation mode selection) 6, 7 TOD13M (TOD1_3 operation mode selection) 8, 9 TOD14M (TOD1_4 operation mode selection) 10, 11 TOD15M (TOD1_5 operation mode selection) 12, 13 TOD16M (TOD1_6 operation mode selection) 14, 15 TOD17M (TOD1_7 operation mode selection) Function 00 : Single-shot output mode 01 :Delayed single-shot output mode 10 : Continuous output mode 11 : PWM output mode R W The TOD1 Control Register is used to select TOD1_0-7 operation modes (PWM output, single-shot output, delayed single-shot output, or continuous output mode). 10-181 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.5 TOD Counters s TOD0_0 Counter (TOD00CT) s TOD0_1 Counter (TOD01CT) s TOD0_2 Counter (TOD02CT) s TOD0_3 Counter (TOD03CT) s TOD0_4 Counter (TOD04CT) s TOD0_5 Counter (TOD05CT) s TOD0_6 Counter (TOD06CT) s TOD0_7 Counter (TOD07CT) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOD00CT - TOD07CT D 0 - 15 Bit Name TOD00CT - TOD07CT Function 16-bit counter value R W W= : Write to this register is accepted in all but PWM output mode. Note: This register must always be accessed in halfwords. The TOD0 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software), it starts counting synchronously with the count clock. During PWM output mode, this counter is disabled against write. 10-182 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1_0 Counter (TOD10CT) s TOD1_1 Counter (TOD11CT) s TOD1_2 Counter (TOD12CT) s TOD1_3 Counter (TOD13CT) s TOD1_4 Counter (TOD14CT) s TOD1_5 Counter (TOD15CT) s TOD1_6 Counter (TOD16CT) s TOD1_7 Counter (TOD17CT) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOD10CT - TOD17CT D 0 - 15 Bit Name TOD10CT - TOD17CT Function 16-bit counter value R W W= : Write to this register is accepted in all but PWM output mode. Note: This register must always be accessed in halfwords. The TOD1 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting synchronously with the count clock. During PWM output mode, this counter is disabled against write. 10-183 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (1) TOD timer counter write enable/disable conditions Whether TOD timer counter is enabled for or disabled against write is determined depending on a combination of TOD timers and a combination of their operation modes. These counter write enable/disable conditions are described below. Also, Figure 10.8.5 schematically shows a TOD0/TOD1 counter write circuit configuration. (a) Table 10.8.2 shows the relationship of each timer in cases where writing to the counter is enabled or disabled by a combination of timers. Whether writing to the counter in software is enabled or disabled depends on a combination of timers in Table 10.8.2 and a combination of their operation modes in Table 10.8.3. Table 10.8.2 Relationship of Each Timer Target timer TOD0-2 TOD0-4 TOD0-6 TOD1-2 TOD1-4 TOD1-6 Related timer TOD0-1 TOD0-2 TOD0-3 TOD1-1 TOD1-2 TOD1-3 Table 10.8.3 Behavior by a Combination of Timer Operation Modes Operation mode of the target timer PWM output Operation mode of a related timer Single-shot output Delayed single-shot output Continuous output Single-shot output Delayed single-shot output Continuous output PWM output Writing in software is disabled Whether writing to the target timer’s counter in software is enabled or disabled Writing in software is enabled 10-184 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (b) For cases other than the combinations in Tables 10.8.2 and 10.8.3, whether writing to the counter in software is enabled or disabled depends on operation mode of the target timer. Table 10.8.4 Writes to Counter Enabled/Disabled by Timer Operation Modes Operation mode of the target timer Whether writing to the target timer’s counter in software is enabled or disabled PWM output Single-shot output Delayed single-shot output Continuous output Writing in software is disabled Writing in software is enabled Write control signal: PWM output mode: Low Other modes: High TODn-0 TODn-1 Timer mode select circuit Write control signal T O D n-1 write signal Timer mode select circuit Write control signal T O D n-2 write signal Timer mode select circuit Write control signal T O D n-3 write signal TO Dn-3 Write signal T O D n-1 counter TODn-2 Write signal T O D n-2 counter Write signal T O D n-3 counter TODn-4 Write signal T O D n-4 counter TODn-5 TODn-6 T O D n-4 write signal Write signal T O D n-6 counter TODn-7 T O D n-6 write signal Note: TODn denotes TOD0 and TOD1. Figure 10.8.5 Configuration of TOD Timer Counter Write Circuit 10-185 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.6 TOD Reload 0 Registers s TOD0_0 Reload 0 Register (TOD00RL0) s TOD0_1 Reload 0 Register (TOD01RL0) s TOD0_2 Reload 0 Register (TOD02RL0) s TOD0_3 Reload 0 Register (TOD03RL0) s TOD0_4 Reload 0 Register (TOD04RL0) s TOD0_5 Reload 0 Register (TOD05RL0) s TOD0_6 Reload 0 Register (TOD06RL0) s TOD0_7 Reload 0 Register (TOD07RL0) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOD00RL0 - TOD07RL0 D 0 - 15 Bit Name TOD00RL0 - TOD07RL0 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOD0 Reload 0 Register is used to reload the TOD0 Counter Registers (TOD00CT-TOD07CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter: • When the counter is enabled in single-shot output or PWM output mode • When the counter underflowed in delayed single-shot output or continuous output mode • When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. 10-186 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1_0 Reload 0 Register (TOD10RL0) s TOD1_1 Reload 0 Register (TOD11RL0) s TOD1_2 Reload 0 Register (TOD12RL0) s TOD1_3 Reload 0 Register (TOD13RL0) s TOD1_4 Reload 0 Register (TOD14RL0) s TOD1_5 Reload 0 Register (TOD15RL0) s TOD1_6 Reload 0 Register (TOD16RL0) s TOD1_7 Reload 0 Register (TOD17RL0) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOD10RL0 - TOD17RL0 D 0 - 15 Bit Name TOD10RL0 - TOD17RL0 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOD1 Reload 0 Register is used to reload the TOD1 Counter Registers (TOD10CT-TOD17CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter: • When the counter is enabled in single-shot output or PWM output mode • When the counter underflowed in delayed single-shot output or continuous output mode • When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. 10-187 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.7 TOD Reload 1 Registers s TOD0_0 Reload 1 Register (TOD00RL1) s TOD0_1 Reload 1 Register (TOD01RL1) s TOD0_2 Reload 1 Register (TOD02RL1) s TOD0_3 Reload 1 Register (TOD03RL1) s TOD0_4 Reload 1 Register (TOD04RL1) s TOD0_5 Reload 1 Register (TOD05RL1) s TOD0_6 Reload 1 Register (TOD06RL1) s TOD0_7 Reload 1 Register (TOD07RL1) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOD00RL1 - TOD07RL1 D 0 - 15 Bit Name TOD00RL1 - TOD07RL1 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOD0 Reload 1 Register is used to reload the TOD0 Counter Registers (TOD00CT-TOD07CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter: • When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. 10-188 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1_0 Reload 1 Register (TOD10RL1) s TOD1_1 Reload 1 Register (TOD11RL1) s TOD1_2 Reload 1 Register (TOD12RL1) s TOD1_3 Reload 1 Register (TOD13RL1) s TOD1_4 Reload 1 Register (TOD14RL1) s TOD1_5 Reload 1 Register (TOD15RL1) s TOD1_6 Reload 1 Register (TOD16RL1) s TOD1_7 Reload 1 Register (TOD17RL1) MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD10RL1 - TOD17RL1 D 0 - 15 Bit Name TOD10RL1 - TOD17RL1 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOD1 Reload 1 Register is used to reload the TOD1 Counter Registers (TOD10CT-TOD17CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter: • When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. 10-189 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.8 TOD Enable Protect Registers s TOD0 Enable Protect Register (TOD0PRO) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D 8 Bit Name TOD00PRO (TOD0_0 enable protect) 9 TOD01PRO (TOD0_1 enable protect) 10 TOD02PRO (TOD0_2 enable protect) 11 TOD03PRO (TOD0_3 enable protect) 12 TOD04PRO (TOD0_4 enable protect) 13 TOD05PRO (TOD0_5 enable protect) 14 TOD06PRO (TOD0_6 enable protect) 15 TOD07PRO (TOD0_7 enable protect) Function 0 : Enables rewrite 1 :Disables rewrite R W The TOD0 Enable Protect Register controls rewriting of the TOD0 counter enable bit described in Section 10.8.9 by enabling or disabling rewrite. 10-190 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1 Enable Protect Register (TOD1PRO) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D 8 Bit Name TOD10PRO (TOD1_0 enable protect) 9 TOD11PRO (TOD1_1 enable protect) 10 TOD12PRO (TOD1_2 enable protect) 11 TOD13PRO (TOD1_3 enable protect) 12 TOD14PRO (TOD1_4 enable protect) 13 TOD15PRO (TOD1_5 enable protect) 14 TOD16PRO (TOD1_6 enable protect) 15 TOD17PRO (TOD1_7 enable protect) Function 0 : Enables rewrite 1 :Disables rewrite R W The TOD1 Enable Protect Register controls rewriting of the TOD1 counter enable bit described in Section 10.8.9 by enabling or disabling rewrite. 10-191 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.9 TOD Cout Enable Registers s TOD0 Count Enable Register (TOD0CEN) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D 8 Bit Name TOD00CEN (TOD0_0 count enable) 9 TOD01CEN (TOD0_1 count enable) 10 TOD02CEN (TOD0_2 count enable) 11 TOD03CEN (TOD0_3 count enable) 12 TOD04CEN (TOD0_4 count enable) 13 TOD05CEN (TOD0_5 count enable) 14 TOD06CEN (TOD0_6 count enable) 15 TOD07CEN (TOD0_7 count enable) Function 0 : Stops count 1 :Enables count R W The TOD0 Count Enable Register controls operation of TOD0 counters. To enable the counter in software, enable the relevant TOD0 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOD0 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and delayed single-shot output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOD0 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-192 32170/32174 Group User's Manual (Rev. 2.1) 10 s TOD1 Count Enable Register (TOD0CEN) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) D 8 Bit Name TOD10CEN (TOD1_0 count enable) 9 TOD11CEN (TOD1_1 count enable) 10 TOD12CEN (TOD1_2 count enable) 11 TOD13CEN (TOD1_3 count enable) 12 TOD14CEN (TOD1_4 count enable) 13 TOD15CEN (TOD1_5 count enable) 14 TOD16CEN (TOD1_6 count enable) 15 TOD17CEN (TOD1_7 count enable) Function 0 : Stops count 1 :Enables count R W The TOD1 Count Enable Register controls operation of TOD1 counters. To enable the counter in software, enable the relevant TOD1 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOD1 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and delayed single-shot output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOD1 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-193 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD0m enable (TOD0mCEN) Dn TOD0m enable protect (TOD0mPRO) F/F F/F WR TOD0m enable control WR Figure 10.8.6 Configuration of TOD0 Enable Circuit TID1 enable output enable (TID1EN0) F/F EN-ON TID1 output TOD1m enable (TOD1mCEN) Dn TOD1m enable protect (TOD1mPRO) F/F F/F WR TOD1m enable control WR Figure 10.8.7 Configuration of TOD1 Enable Circuit 10-194 32170/32174 Group User's Manual (Rev. 2.1) 10 10.8.10 Operation in TOD PWM Output Mode (1) Outline of TOD PWM output mode MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TOD's PWM output mode does not have the correction function. 10-195 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled (by writing to enable bit Underflow (first time) or by external input) Underflow (second time) Count clock Enable bit Down-count starting from reload 0 register set value Down-count starting from reload 1 register set value H’(C000-1) Down-count starting from reload 0 register set value H’FFFF H’C000 H’(A000-1) Counter H’A000 H’A000 H’0000 Reload 0 register H’A000 Reload 1 register H’C000 F/F output Data inverted by enable TOD interrupt by underflow PWM output period Note: This diagram does not show detail timing information. Data inverted by underflow Data inverted by underflow Figure 10.8.8 Typical Operation in PWM Output Mode 10-196 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (2) Reload register updates in TOD PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Internal bus Reload 1 TODnRL1 Reload1WR Reload0WR Reload 0 Buffer TODnRL0 PWM mode control Prescaler output 16-bit counter F/F TO Figure 10.8.9 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. In this case when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. 10-197 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’8000 H’9000 Old PWM output period F/F output New PWM output period Operation by new reload value written Enlarged view New PWM output period Count clock Counter H’0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output Timing at which reload 1 and reload 0 registers are updated PWM period latched H’1000 H’2000 H’2000 H’8000 H’9000 H’9000 H’0000 H’FFFF H’7FFF H’7FFE Note: This diagram does not show detail timing information. (b) When reload register updates take effect in the next period (reflected one period later) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’9000 H’8000 Old PWM output period F/F output Old PWM output period Operation by old reload value Enlarged view Old PWM output period Count clock Counter H’0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output PWM period latched Timing at which reload 1 and reload 0 registers are updated H’2000 H’2000 H’1000 H’9000 H’9000 H’8000 H’0000 H’FFFF H’0FFF H’0FFE Note: This diagram does not show detail timing information. Figure 10.8.10 Reload 0 and Reload 1 Register Updates in PWM Output Mode 10-198 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOD single-shot output mode MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.11 Operation in TOD Single-shot Output Mode (without Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.11, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TOD single-shot output mode The following describes precautions to be observed when using TOD single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that countis enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-199 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Disabled (by underflow) Count clock Enable bit H’FFFF H’A000 Counts down starting from reload 0 register set value Counter H’0000 Reload 0 register H’A000 Reload 1 register (Not used) F/F output Data inverted by enable TOD interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.8.11 Typical Operation in TOD Single-shot Output Mode (without Correction Function) 10-200 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOD delayed single-shot output mode MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.12 Operation in TOD Delayed Single-shot Output Mode (without Correction Function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.12, "Operation in TOP Delayed Single-shot Output Mode (With Correction Function)." (2) Precautions to be observed when using TOD delayed single-shot output mode The following describes precautions to be observed when using TOD delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the prescaler output, a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-201 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Underflow (first time) Underflow (second time) Count clock Enable bit H’FFFF H’F000 Down-count starting from counter set value H’EFFF Down-count starting from reload 0 register set value H’A000 Counter H’0000 Reload 0 register H’F000 Reload 1 register (Not used) F/F output Data inverted by underflow TOD interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.8.12 Typical Operation in TOD Delayed Single-shot Output Mode (without Correction Function) 10-202 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOD continuous output mode MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output Mode (Without Correction Function)." (2) Precautions to be observed when using TOD continuous output mode The following describes precautions to be observed when using TOD continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-203 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled (by writing to enable bit Underflow (first time) or by external input) Underflow (second time) Count clock H’FFFF H’E000 Down-count starting from counter set value H’DFFF Down-count starting from reload 0 register set value H’DFFF Down-count starting from reload 0 register set value H’A000 Counter H’0000 Reload 0 register H’E000 Reload 1 register (Not used) F/F output Data inverted by enable Data inverted by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.8.13 Typical Operation in TOD Continuous Output Mode (without Correction Function) 10-204 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9 TOM (Output-related 16-bit Timer) 10.9.1 Outline of TOM MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TOM (Timer Output Modification) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software. • PWM output mode • Single-shot output mode • Single-shot PWM output mode • Continuous output mode The table below shows specifications of TOM. The diagram in the next page shows a block diagram of TOM. Table 10.9.1 Specifications of TOM (Output-related 16-bit Timer) Item Number of channels Counter Reload register Timer startup Mode selection Specification 8 channels 16-bit down-counter 16-bit reload register Started by writing to enable bit in software or by TID2 timer underflow/overflow signal • PWM output mode • Single-shot output mode • Single-shot PWM output mode • Continuous output mode Interrupt generation Can be generated by a counter underflow 10-205 32170/32174 Group User's Manual (Rev. 2.1) 10 clk clk clk clk 1/2 internal peripheral clock PRS5 clk clk TOM0_0 TOM0_1 TOM0_2 TOM0_3 TOM0_4 TOM0_5 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) en en en en en en udf udf udf udf udf udf F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 TO 37 TO 38 TO 39 TO 40 TO 41 TO 42 clk en TOM0_6 udf F/F43 TO 43 clk en TOM0_7 udf F/F44 TO 44 IRQ16 clk TIN28 TIN29 PRS5 CLK1 CLK2 TID2 udf ovf IRQ17 : Prescaler F/F : Output flip-flop Figure 10.9.1 TOM (Output-related 16-bit Timer) 10-206 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.2 Outline of Each Mode of TOM MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Each mode of TOM is outlined below. For each TOM channel, only one of the following modes can be selected. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. (2) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by using TID2 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. 10-207 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (3) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Then when the counter underflows next time, it stops. The valid count values are the (reload 0 register set value + 1) and (reload 1 register set value + 1) each. To stop the timer in software, disable count by writing to the enable bit. The timer stops at the same time count is disabled (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output levels change from low to high, or vice versa) upon each underflow. (Unlike in PWM output mode, F/F output is not inverted at counter startup.) An interrupt can be generated when the counter underflows second time after being enabled. (4) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. 10-208 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.3 TOM Related Register Map MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) The diagram below shows a TOM related register map. Address D0 +0 Address D7 D8 +1 Address D15 H’0080 0C90 H’0080 0C92 H’0080 0C94 H’0080 0C96 H’0080 0C98 H’0080 0C9A H’0080 0C9C H’0080 0C9E H’0080 0CA0 H’0080 0CA2 H’0080 0CA4 H’0080 0CA6 H’0080 0CA8 H’0080 0CAA H’0080 0CAC H’0080 0CAE H’0080 0CB0 H’0080 0CB2 H’0080 0CB4 H’0080 0CB6 H’0080 0CB8 H’0080 0CBA H’0080 0CBC H’0080 0CBE TOM0_0 Counter (TOM00CT) TOM0_0 Reload 1 Register (TOM00RL1) TOM0_0 Reload 0 Register (TOM00RL0) TOM0_1 Counter (TOM01CT) TOM0_1 Reload 1 Register (TOM01RL1) TOM0_1 Reload 0 Register (TOM01RL0) TOM0_2 Counter (TOM02CT) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_2 Reload 0 Register (TOM02RL0) TOM0_3 Counter (TOM03CT) TOM0_3 Reload 1 Register (TOM03RL1) TOM0_3 Reload 0 Register (TOM03RL0) TOM0_4 Counter (TOM04CT) TOM0_4 Reload 1 Register (TOM04RL1) TOM0_4 Reload 0 Register (TOM04RL0) TOM0_5 Counter (TOM05CT) TOM0_5 Reload 1 Register (TOM05RL1) TOM0_5 Reload 0 Register (TOM05RL0) Blank addresses are reserved. Note: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.9.2 TOM Related Register Map (1/2) 10-209 32170/32174 Group User's Manual (Rev. 2.1) 10 Address D0 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) +0 Address D7 D8 +1 Address D15 H’0080 0CC0 H’0080 0CC2 H’0080 0CC4 H’0080 0CC6 H’0080 0CC8 H’0080 0CCA H’0080 0CCC H’0080 0CCE H’0080 0CD0 H’0080 0CD2 H’0080 0CD4 H’0080 0CD6 H’0080 0CD8 H’0080 0CDA H’0080 0CDC H’0080 0CDE TOM0_6 Counter (TOM06CT) TOM0_6 Reload 1 Register (TOM06RL1) TOM0_6 Reload 0 Register (TOM06RL0) TOM0_7 Counter (TOM07CT) TOM0_7 Reload 1 Register (TOM07RL1) TOM0_7 Reload 0 Register (TOM07RL0) Prescaler Register 5 (PRS5) TOM0 Interrupt Mask Register (TOM0IMA) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) (Note 1) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 4 (FFP4) F/F Data Register 4 (FFD4) TOM0 Control Register (TOM0CR) TOM0 Enable Protect Register (TOM0PRO) TOM0 Count Enable Register (TOM0CEN) Blank addresses are reserved. Note 1: Prescaler Register 5 is shared with TOM0_0-7 and TID2, and TID2 Control & Prescaler 5 Enable Register is used in TID2 control. Note 2: The registers enclosed in thick frames must always be accessed in halfwords. Figure 10.9.3 TOM Related Register Map (2/2) 10-210 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.4 TOM Control Registers s TOM0 Control Register (TOM0CR) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) D 0,1 Bit Name TOM00M (TOM0_0 operation mode selection) 2,3 TOM01M (TOM0_1 operation mode selection) 4,5 TOM02M (TOM0_2 operation mode selection) 6,7 TOM03M (TOM0_3 operation mode selection) 8,9 TOM04M (TOM0_4 operation mode selection) 10,11 TOM05M (TOM0_5 operation mode selection) 12,13 TOM06M (TOM0_6 operation mode selection) 14,15 TOM07M (TOM0_7 operation mode selection) Function 00: Single-shot output mode 01: Single-shot PWM output mode 10: Continuous output mode 11: PWM output mode R W The TOM0 Control Register is used to select TOM0_0-7 operation modes (PWM output, singleshot output, single-shot PWM output, or continuous output mode). 10-211 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.5 TOM Counters s TOM0_0 Counter (TOM00CT) s TOM0_1 Counter (TOM01CT) s TOM0_2 Counter (TOM02CT) s TOM0_3 Counter (TOM03CT) s TOM0_4 Counter (TOM04CT) s TOM0_5 Counter (TOM05CT) s TOM0_6 Counter (TOM06CT) s TOM0_7 Counter (TOM07CT) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOM00CT-TOM07CT D 0-15 W= Bit Name TOM00CT-TOM07CT Function 16-bit counter value R W : Whether writing to the counter is enabled or disabled depends on a combination of timers and timer operation modes. For details, see (1) TOM timer counter write enable/disable conditions. Note: This register must always be accessed in halfwords. The TOM0 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting synchronously with the count clock. During PWM output and single-shot PWM output modes, this counter is disabled against write. 10-212 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (1) TOM timer counter write enable/disable conditions Whether TOM timer counter is enabled for or disabled against write is determined depending on a combination of TOM timers and a combination of their operation modes. These counter write enable/disable conditions are described below. Also, Figure 10.9.4 schematically shows a configuration of the TOM timer counter write circuit. (a) Table 10.9.2 shows the relationship of each timer in cases where writing to the counter is enabled or disabled by a combination of timers. Whether writing to the counter in software is enabled or disabled depends on a combination of timers in Table 10.9.2 and a combination of their operation modes in Table 10.9.3. Table 10.9.2 Relationship of Each Timer Target timer TOM0-2 TOM0-4 TOM0-6 Related timer TOM0-1 TOM0-2 TOM0-3 Table 10.9.3 Behavior by a Combination of Timer Operation Modes Operation mode of the target timer PWM output Single-shot PWM output Single-shot output Continuous output Operation mode of a related timer Single-shot output Continuous output PWM output Single-shot PWM output Writing in software is disabled Whether writing to the target timer’s counter in software is enabled or disabled Writing in software is enabled (b) For cases other than the combinations in Tables 10.9.2 and 10.9.3, whether writing to the counter in software is enabled or disabled depends on operation mode of the target timer. Table 10.9.4 Writes to Counter Enabled/Disabled by Timer Operation Modes Operation mode of the target timer Whether writing to the target timer’s counter in software is enabled or disabled PWM output Single-shot PWM output Single-shot output Continuous output Writing in software is enabled Writing in software is disabled 10-213 32170/32174 Group User's Manual (Rev. 2.1) 10 Write control signal: PWM/single-shot PWM output mode: Low Other modes: High MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TOM 0 - 0 TOM 0 - 1 Write signal T O M 0-1 counter T O M 0-1 write signal Timer mode select circuit Write control signal T O M 0-2 write signal Timer mode select circuit Write control signal T O M 0-3 write signal TOM 0 - 2 Write signal T O M 0-2 counter Timer mode select circuit Write control signal TOM 0 - 3 Write signal T O M 0-3 counter TOM 0 - 4 Write signal T O M 0-4 counter TOM 0 - 5 TOM 0 - 6 Write signal T O M 0-6 counter TOM 0 - 7 T O M 0-4 write signal T O M 0-6 write signal Figure 10.9.4 Configuration of TOM Timer Counter Write Circuit 10-214 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.6 TOM Reload 0 Registers s TOM0_0 Reload 0 Register (TOM00RL0) s TOM0_1 Reload 0 Register (TOM01RL0) s TOM0_2 Reload 0 Register (TOM02RL0) s TOM0_3 Reload 0 Register (TOM03RL0) s TOM0_4 Reload 0 Register (TOM04RL0) s TOM0_5 Reload 0 Register (TOM05RL0) s TOM0_6 Reload 0 Register (TOM06RL0) s TOM0_7 Reload 0 Register (TOM07RL0) D0 1 2 3 4 5 6 7 8 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 9 10 11 12 13 14 D15 TOM00RL0-TOM07RL0 D 0-15 Bit Name TOM00RL0-TOM07RL0 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOM0 Reload 0 Registers are used to reload the TOM0 Counter Registers (TOM00CTTOM07CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter: • When the counter is enabled in single-shot output, PWM output, or single-shot PWM output mode • When the counter underflowed in continuous output mode • When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. 10-215 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.7 TOM Reload 1 Registers s TOM0_0 Reload 1 Register (TOM00RL1) s TOM0_1 Reload 1 Register (TOM01RL1) s TOM0_2 Reload 1 Register (TOM02RL1) s TOM0_3 Reload 1 Register (TOM03RL1) s TOM0_4 Reload 1 Register (TOM04RL1) s TOM0_5 Reload 1 Register (TOM05RL1) s TOM0_6 Reload 1 Register (TOM06RL1) s TOM0_7 Reload 1 Register (TOM07RL1) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOM00RL1-TOM07RL1 D 0-15 Bit Name TOM00RL1-TOM07RL1 Function 16-bit reload register value R W Note: This register must always be accessed in halfwords. The TOM0 Reload 1 Registers are used to reload the TOM0 Counter Registers (TOM00CTTOM07CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter: • When the count value set by reload 1 register underflowed in PWM output mode. Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. 10-216 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.8 TOM Enable Protect Registers s TOM0 Enable Protect Register (TOM0PRO) D8 9 10 11 12 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) D 8 Bit Name TOM00PRO (TOM0_0 enable protect) 9 TOM01PRO (TOM0_1 enable protect) 10 TOM02PRO (TOM0_2 enable protect) 11 TOM03PRO (TOM0_3 enable protect) 12 TOM04PRO (TOM0_4 enable protect) 13 TOM05PRO (TOM0_5 enable protect) 14 TOM06PRO (TOM0_6 enable protect) 15 TOM07PRO (TOM0_7 enable protect) Function 0: Enables rewrite 1: Disables rewrite R W The TOM0 Enable Protect Register controls rewriting of the TOM0 counter enable bit described in the next page by enabling or disabling rewrite. 10-217 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.9 TOM Count Enable Registers s TOM0 Count Enable Register (TOM0CEN) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) D 8 Bit Name TOM00CEN (TOM0_0 count enable) 9 TOM01CEN (TOM0_1 count enable) 10 TOM02CEN (TOM0_2 count enable) 11 TOM03CEN (TOM0_3 count enable) 12 TOM04CEN (TOM0_4 count enable) 13 TOM05CEN (TOM0_5 count enable) 14 TOM06CEN (TOM0_6 count enable) 15 TOM07CEN (TOM0_7 count enable) Function 0: Stops count 1: Enables count R W The TOM0 Count Enable Register controls operation of TOM0 counters. To enable the counter in software, enable the relevant TOM0 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOM0 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and single-shot PWM output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOM0 Count Enable Register is the status that indicates the counter's operating status (active or idle). 10-218 32170/32174 Group User's Manual (Rev. 2.1) 10 TID2 enable output enable (TID2EN0) F/F EN-ON TID2 output MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TOM0m enable (TOM0mCEN) Dn TOM0m enable protect (TOM0mPRO) F/F F/F WR TOM0m enable control WR Figure 10.9.5 Configuration of the TOM Enable Circuit 10-219 32170/32174 Group User's Manual (Rev. 2.1) 10 10.9.10 Operation in TOM PWM Output Mode (1) Outline of TOM PWM output mode MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TOM's PWM output mode does not have the correction function. 10-220 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit Underflow (first time) or by external input) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Underflow (second time) Count clock Enable bit Down-count starting from reload 0 register set value H’C000 Down-count starting from reload 1 register set value H’(C000-1) Down-count starting from reload 0 register set value H’FFFF H’(A000-1) H’A000 H’A000 Counter H’0000 Reload 0 register H’A000 Reload 1 register H’C000 F/F output Data inverted by enable TOM interrupt by underflow PWM output period Data inverted by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.9.6 Typical Operation in PWM Output Mode 10-221 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (2) Reload register updates in TOM PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Internal bus Reload 1 TOM0nRL1 Reload1WR Reload0WR Reload 0 Buffer TOM0nRL0 PWM mode control Prescaler output 16-bit counter F/F TO Figure 10.9.7 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. When you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. 10-222 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’8000 H’9000 Old PWM output period F/F output New PWM output period Operation by new reload value written Enlarged view New PWM output period Count clock Counter H’0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output Timing at which reload 1 and reload 0 registers are updated PWM period latched H’1000 H’2000 H’2000 H’8000 H’9000 H’9000 H’0000 H’FFFF H’7FFF H’7FFE Note: This diagram does not show detail timing information. (b) When reload register updates take effect in the next period (reflected one period later) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register Reload 1 register H’1000 H’2000 H’9000 H’8000 Old PWM output period F/F output Old PWM output period Operation by old reload value Enlarged view Old PWM output period Count clock Counter H’0001 Interrupt by underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output PWM period latched Timing at which reload 1 and reload 0 registers are updated H’1000 H’2000 H’2000 H’9000 H’9000 H’8000 H’0000 H’FFFF H’0FFF H’0FFE Note: This diagram does not show detail timing information. Figure 10.9.8 Reload 0 and Reload 1 Register Updates in PWM Output Mode 10-223 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOM single-shot output mode MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.11 Operation in TOM Single-shot Output Mode (without Correction Function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.11, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TOM single-shot output mode The following describes precautions to be observed when using TOM single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops). • If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled). • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-224 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Disabled (by underflow) Count clock Enable bit H’FFFF H’A000 Counts down starting from reload 0 register set value Counter H’0000 Reload 0 register H’A000 Reload 1 register (Not used) F/F output Data inverted by enable TOM interrupt by underflow Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.9.9 Typical Operation in TOM Single-shot Output Mode (without Correction Function) 10-225 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOM single-shot PWM output mode MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.12 Operation in TOM Single-shot PWM Output Mode (without Correction Function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Then when the counter underflows next time, it stops. The valid count values are the (reload 0 register set value + 1) and (reload 1 register set value + 1) each. To stop the timer in software, disable count by writing to the enable bit. The timer stops at the same time count is disabled (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output levels change from low to high, or vice versa) upon each underflow. (Unlike in PWM output mode, F/F output is not inverted at counter startup.) An interrupt can be generated when the counter underflows second time after being enabled. Note that TOM's single-shot PWM output mode does not have the correction function. 10-226 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit or by external input) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Underflow (first time) Underflow (second time) Count clock Enable bit H’FFFF H’F000 Down-count starting from reload 0 register set value H’EFFF Down-count starting from reload 1 register set value H’A000 Counter H’0000 Reload 0 register H’A000 Reload 1 register H’F000 F/F output Data inverted by underflow TOM interrupt by underflow PWM output period Data inverted by underflow Note: This diagram does not show detail timing information. Figure 10.9.10 Typical Operation in TOM Single-shot PWM Output Mode (without Correction Function) 10-227 32170/32174 Group User's Manual (Rev. 2.1) 10 (1) Outline of TOM continuous output mode MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.13 Operation in TOM Continuous Output Mode (Without Correction Function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output Mode (Without Correction Function)." (2) Precautions to be observed when using TOM continuous output mode The following describes precautions to be observed when using TOM continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled). • When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. • Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. 10-228 32170/32174 Group User's Manual (Rev. 2.1) 10 Enabled (by writing to enable bit Underflow (first time) or by external input) MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Underflow (second time) Count clock Enable bit H’FFFF H’E000 Down-count starting from counter set value H’DFFF Down-count starting from reload 0 register set value H’DFFF Down-count starting from reload 0 register set value H’A000 Counter H’0000 Reload 0 register H’E000 Reload 1 register (Not used) F/F output Data inverted by enable TOM interrupt by underflow Note: This diagram does not show detail timing information. Data inverted by underflow Data inverted by underflow Figure 10.9.11 Typical Operation in TOM Continuous Output Mode (Without Correction F unction) 10-229 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.14 Example Application for Using the 32170 in Motor Control The 16-bit timer TOM incorporated in the 32170 helps to reduce software burdens during motor control. The following shows an example application for using the 32170 in motor control. The three-phase motor control waveform is materialized by starting TOM in 20 kHz fixed cycles generated by TID2. The new single-shot PWM output function of TOM enables the output waveform to be configured easily by storing waveform data only when the data needs to be rewritten. Note that the high/low transistor shorting prevention time can be provided by changing the set time of TOM in software. Circuit board TOM TOM U /U V /V W /W Power-MOS Motor M32R/E#4 TOM TOM TOM TOM TMS TMS TMS Figure 10.9.12 System Configuration Diagram clk Startup clk clk clk PSC5 clk clk Single-shot PWM EN EN EN EN EN EN TOM0_0 TOM0_1 TOM0_2 TOM0_3 TOM0_4 TOM0_5 udf udf udf udf udf udf F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 TOM(U) TOM(/U) TOM(V) TOM(/V) TOM(W) TOM(/W) Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Fixed cycle clk TID2 20 kHz generated udf Figure 10.9.13 Timer Connections When Used for Three-phase Motor Control 10-230 32170/32174 Group User's Manual (Rev. 2.1) 10 TOM start Delay 20KHz MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Single-shot : Shorting prevention time U V W TOM(U) Delay TOM(/U) Single-shot TOM(V) TOM(/V) TOM(W) TOM(/W) Figure 10.9.14 Diagram of Control Image 10-231 32170/32174 Group User's Manual (Rev. 2.1) 10 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) ❊ This is a blank page. ❊ 10-232 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 11 A-D CONVERTERS 11.1 Outline of A-D Converters 11.2 A-D Converter Related Registers 11.3 Functional Description of A-D Converters 11.4 Precautions on Using A-D Converters 11 11.1 Outline of A-D Converter A-D CONVERTERS 11.1 Outline of A-D Converters The 32170 contains two 10-bit A-D converters of a successive approximation type (A-D0 and A-D1 converters). These converters have 32 analog input pins (channels) AD0IN0 to AD0IN15 and AD1IN0 to AD1IN 15. The A-D conversion results can be read out in either 8 bits or 10 bits. For A-D conversion, there are following conversion modes and operation modes: (1) Conversion mode • A-D conversion mode: Ordinary mode in which analog input voltages are converted into digital quantities. • Comparator mode (Note): A mode in which analog input voltage is compared with a preset comparison voltage to only find the relative magnitude of two quantities. (Single mode only) (2) Operation mode • Single mode: Analog input voltage in one channel is A-D converted once or comparated(note) with a given quantity. • Scan mode: Analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. (3) Types of scan modes • Single-shot scan mode: Scan operation is performed for one machine cycle. • Continuous scan mode: Scan operation is performed repeatedly until stopped. (4) Special operation mode • Forcible single mode execution during scan mode: Conversion is forcibly executed in single mode during scan operation. • Scan mode start after single mode execution: Scan operation is started subsequently after executing conversion in single mode. • Conversion restart: A-D conversion being executed in single or scan mode is restarted. The A-D conversion and comparate rates can be selected between normal and double rate. An AD conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation. Note: T o discriminate between the comparison operation performed internally by the successive approximation-type A-D converter and the operation in comparator mode performed using the A-D converter as a comparator, the comparison operation in comparator mode in this manual is referred to as "comparate." 11-2 32170/32174 Group User's Manual (Rev. 2.1) 11 and A-D1 converters, respectively. A-D CONVERTERS 11.1 Outline of A-D Converters Table 11.1.1 outlines the A-D converters. Figures 11.1.1 and 11.1.2 show block diagrams of A-D0 Table 11.1.1 Outline of A-D Converters Item Analog input A-D conversion method Resolution Absolute accuracy (Note1) (Conditions : Ta = -40 to 125°C, AVCC0,1=VREF0,1=5.12V) Conversion mode Operation mode Scan mode Conversion start trigger A-D conversion mode, comparator mode Single mode, scan mode Single-shot scan mode, continuous scan mode Software start Hardware start Started by setting A-D converter start bit to 1 A-D0 converter started by MJT output event bus 3, A-D1 converter started by TID1 overflow or underflow (Note 2) _____ Started by external ADTRG pin input Conversion rate f(BCLK): Internal peripheral clock operating frequency Interrupt request generation function During single mode (shortest time) Normal rate Double rate 299 × 1/f(BCLK) (Note 3) 173 × 1/f(BCLK) 47 × 1/f(BCLK) 29 × 1/f(BCLK) Content 16 channels × 2 Successive approximation method 10 bits (Conversion results can be read out in either 8 bits or 10 bits) Normal mode Double-speed mode ±2LSB ±2LSB During comparator mode Normal rate (shortest time) Double rate Generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation DMA transfer request generation function (Note 4) Generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation Note 1: The rated value of conversion accuracy here is that of the microcomputer’s own as a single unit, which can only be obtained in an environment where the power supply wiring on the board is stable and the microcomputer is unaffected by noise. Note 2: Refer to Chapter 10, "Multijunction Timers." Note 3: When BCLK = 20 MHz, this is 1/f(BCLK) = 50 ns. Note 4: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1 converter does not have this function. 11-3 32170/32174 Group User's Manual (Rev. 2.1) 11 Internal data bus 8-bit readout 10-bit readout Shifter A-D CONVERTERS 11.1 Outline of A-D Converters AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 AD0CMP P67/ADTRG AVCC0 AVSS0 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 A-D Comparate Data Register A-D Control Circuit 10-bit A-D Successive Approximation Register (AD0SAR) AD0SIM0,1 AD0SCM0,1 A-D0 Single Mode Register A-D0 Scan Mode Register Output event bus 3 (multijunction timer) VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 10-bit A-D Converter Comparator Mode selection Channel selection interrupt request Conversion time selection Flag control DMA transfer request Interrupt control Selector Successive Approximation -type A-D Converter Unit Figure 11.1.1 Block Diagram of A-D0 Converter 11-4 32170/32174 Group User's Manual (Rev. 2.1) 11 Internal data bus 8-bit readout 10-bit readout Shifter A-D CONVERTERS 11.1 Outline of A-D Converters AD1DT0 AD1DT1 AD1DT2 AD1DT3 AD1DT4 AD1DT5 AD1DT6 AD1DT7 AD1DT8 AD1DT9 AD1DT10 AD1DT11 AD1DT12 AD1DT13 AD1DT14 AD1DT15 AD1CMP P67/ADTRG AVCC1 AVSS1 10-bit A-D1 Data Register 0 10-bit A-D1 Data Register 1 10-bit A-D1 Data Register 2 10-bit A-D1 Data Register 3 10-bit A-D1 Data Register 4 10-bit A-D1 Data Register 5 10-bit A-D1 Data Register 6 10-bit A-D1 Data Register 7 10-bit A-D1 Data Register 8 10-bit A-D1 Data Register 9 10-bit A-D1 Data Register 10 10-bit A-D1 Data Register 11 10-bit A-D1 Data Register 12 10-bit A-D1 Data Register 13 10-bit A-D1 Data Register 14 10-bit A-D1 Data Register 15 A-D Comparate Data Register A-D Control Circuit 10-bit A-D Successive Approximation Register (AD1SAR) AD1SIM0,1 AD1SCM0,1 A-D1 Single Mode Register A-D1 Scan Mode Register TID1 underflow /overflow VREF1 10-bit A-D Converter Comparator Mode selection Channel selection interrupt request Conversion time selection Flag control Interrupt control AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1N10 AD1IN11 AD1IN12 AD1IN13 AD1IN14 AD1IN15 Selector Successive Approximation -type A-D Converter Unit Figure 11.1.2 Block Diagram of A-D0 Converter 11-5 32170/32174 Group User's Manual (Rev. 2.1) 11 11.1.1 Conversion Modes A-D CONVERTERS 11.1 Outline of A-D Converters The A-D converters have two conversion modes: "A-D conversion mode" and "Comparator mode." (1) A-D conversion mode In A-D conversion mode, the analog input voltage in a specified channel is converted into digital quantity. In single mode, A-D conversion is performed on a channel selected by the Single Mode Register 1 analog input pin select bit. In scan mode, A-D conversion is performed on channels selected by Scan Mode Register 1 according to settings of Scan Mode Register 0. The conversion result is stored in each channel's corresponding 10-bit A-D Data Register. Also, 8-bit A-D conversion results can be read from each 8-bit A-D Data Register. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion when in single mode, or when operating in scan mode, at completion of one cycle of scan loop. (2) Comparator mode In comparator mode, the analog input voltage in a specified channel is "comparated" (compared) with the Successive Approximation Register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged (1 or 0) by setting or resetting the A-D Comparate Data Register bit that corresponds to the selected channel. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of comparate operation. 11-6 32170/32174 Group User's Manual (Rev. 2.1) 11 11.1.2 Operation Modes A-D CONVERTERS 11.1 Outline of A-D Converters The A-D converters operate in two modes: "Single mode" and "Scan mode." (1) Single mode In single mode, the analog input voltage in one selected channel is A-D converted once or comparated with a given quantity. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion. A-D conversion interrupt request or DMA transfer request (Note 2) Conversion starts (Note 1) ANiINn Completed i=0,1 n=0-15 ADiDTn 10-bit A-Di data register Note 1: A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1 _____ Hardware trigger → Started by output event bus 3 or ADTRG signal input A-D1 conversion start: Software trigger → Started by setting A-D1 conversion start_____ bit to 1 Hardware trigger → Started by TID1 overflow/underflow or ADTRG signal input Note 2: DMA transfer request: Can be generated for only the A-D0 converter. Figure 11.1.3 Operation in Single Mode (A-D Conversion) A-D successive approximation register ADiSAR A-D conversion interrupt request or DMA transfer request (Note 2) Conversion starts (Note 1) ADiINn Completed i=0,1 n=0-15 ADiCMP A-Di comparate data register Comparate result ADiCMP=0 (ANn>ADiSAR) ADiCMP=1 (ANn D 0,1 2 Bit Name No functions assigned __________ Function R 0 W – AD0STRG (A-D0 hardware trigger selection) 0: ADTRG signal input 1: Output event bus 3 0: Software trigger 1: Hardware trigger 0: A-D0 interrupt request 1: DMA transfer request 0: A-D0 conversion/comparate in progress 1: A-D0 conversion/comparate completed 0: Performs no operation 1: Stops A-D0 conversion 0: Performs no operation 1: Starts A-D0 conversion 0 0 – 3 AD0SSEL (A-D0 conversion start trigger selection) 4 AD0SREQ (Interrupt request/DMA transfer request selection) 5 AD0SCMP (A-D0 conversion/comparate completed) 6 AD0SSTP (A-D0 conversion stop) 7 AD0SSTT (A-D0 conversion start) A-D0 Single Mode Register 0 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-19 32170/32174 Group User's Manual (Rev. 2.1) 11 s A-D1 Single Mode Register 0 (AD1SIM0) D0 1 2 3 4 A-D CONVERTERS 11.2 A-D Converter Related Registers D 0,1 2 Bit Name No functions assigned __________ Function R 0 W – AD1STRG (A-D1 hardware trigger selection) 0: ADTRG signal input 1: TID1 overflow/underflow 0: Software trigger 1: Hardware trigger 0: Enables A-D1 interrupt request 1: Disables A-D1 interrupt request 0: A-D1 conversion/comparate in progress 1: A-D1 conversion/comparate completed 0: Performs no operation 1: Stops A-D1 conversion 0: Performs no operation 1: Starts A-D1 conversion 0 0 – 3 AD1SSEL (A-D1 conversion start trigger selection) 4 AD1SREQ (Interrupt request) 5 AD1SCMP (A-D1 conversion/comparate completed) 6 AD1SSTP (A-D1 conversion stop) 7 AD1SSTT (A-D1 conversion start) A-D1 Single Mode Register 0 is used to control operation of the A-D1 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-20 32170/32174 Group User's Manual (Rev. 2.1) 11 (1) ADnSTRG (A-Dn hardware trigger selection) bit A-D CONVERTERS 11.2 A-D Converter Related Registers (D2) When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use _____ external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/ underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL (A-Dn conversion start trigger selection) bit is set to choose a software trigger._____using the When _____ ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input is held low, new A-D conversion is not started. (2) ADnSSEL (A-Dn conversion start trigger selection) bit (D3) This bit selects whether to use a software or hardware trigger to start A-Dn conversion during single mode. When you choose a software trigger, A-D conversion is started by setting the ADnSSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D conversion is started for the cause of start selected by the ADnSTRG (hardware trigger selection) bit. (3) ADnSREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4) For the A-D0 converter (AD0SIM0), this bit selects whether to request an A-D0 conversion interrupt or DMA transfer when single mode operation (A-D conversion or comparate) is completed. For the A-D1 converter (AD1SIM0), this bit selects whether to enable or disable an AD0 conversion interrupt when single mode operation (A-D conversion or comparate) is completed. (4) ADnSCMP (A-Dn conversion/comparate completion) bit (D5) This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing single mode operation (A-D conversion or comparate) and set to 1 when the operation is completed. This bit also is set to 1 when A-D conversion or comparate operation is forcibly terminated by setting the ADnSSTT (A-Dn conversion stop) bit to 1 during A-D conversion or comparate operation. (5) ADnSSTP (A-Dn conversion stop) bit (D6) Single mode operation (A-D conversion or comparate) of the A-Dn converter can be halted by setting this bit to 1 while the operation is in progress. Manipulation of this bit is ignored when single mode is idle or when scan mode operation is under way. Operation is halted immediately by a write to this bit, and when you read the A-Dn Successive Approximation Register after being halted, the content you get is the value in the middle of conversion. (Not transferred to the A-Dn Data Register.) If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the ADn conversion stop bit has priority. If this bit is set to 1 while operating in single mode during special mode "Forcible single mode execution during scan mode," only single mode conversion is halted and scan mode operation is restarted. 11-21 32170/32174 Group User's Manual (Rev. 2.1) 11 (6) ADnSSTT (A-Dn conversion start) bit (D7) A-D CONVERTERS 11.2 A-D Converter Related Registers When this bit is set to 1 while a software trigger has been selected by the ADnSSEL (A-Dn conversion start trigger selection) bit, the A-Dn converter starts A-D conversion. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the ADn conversion stop bit has priority. If this bit is set to 1 again during single mode conversion, special operation mode "Forcible single mode execution during scan mode" is entered into, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode A-D conversion is restarted beginning with the canceled channel. 11-22 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.2 A-D Single Mode Register 1 s A-D0 Single Mode Register 1 (AD0SIM1) D8 9 10 11 12 A-D CONVERTERS 11.2 A-D Converter Related Registers D 8 Bit Name AD0SMSL (A-D0 conversion mode selection) 9 AD0SSPD (A-D0 conversion rate selection) 10,11 12-15 No functions assigned AN0SEL (Analog input pin selection) 0000: Selects AD0IN0 0001: Selects AD0IN1 0010: Selects AD0IN2 0011: Selects AD0IN3 0100: Selects AD0IN4 0101: Selects AD0IN5 0110: Selects AD0IN6 0111: Selects AD0IN7 1000: Selects AD0IN8 1001: Selects AD0IN9 1010: Selects AD0IN10 1011: Selects AD0IN11 1100: Selects AD0IN12 1101: Selects AD0IN13 1110: Selects AD0IN14 1111: Selects AD0IN15 W= : Only writing a 0 is effective; when you write a 1, device operation cannot be guaranteed. Function 0: A-D0 conversion mode 1: Comparator mode 0: Normal rate 1: Double rate 0 R W A-D0 Single Mode Register 0 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-23 32170/32174 Group User's Manual (Rev. 2.1) 11 s A-D1 Single Mode Register 1 (AD1SIM1) A-D CONVERTERS 11.2 A-D Converter Related Registers D 8 Bit Name AD1SMSL (A-D1 conversion mode selection) 9 AD1SSPD (A-D1 conversion rate selection) 10,11 12-15 No functions assigned AN1SEL (Analog input pin selection) 0000: Selects AD1IN0 0001: Selects AD1IN1 0010: Selects AD1IN2 0011: Selects AD1IN3 0100: Selects AD1IN4 0101: Selects AD1IN5 0110: Selects AD1IN6 0111: Selects AD1IN7 1000: Selects AD1IN8 1001: Selects AD1IN9 1010: Selects AD1IN10 1011: Selects AD1IN11 1100: Selects AD1IN12 1101: Selects AD1IN13 1110: Selects AD1IN14 1111: Selects AD1IN15 W= : Only writing a 0 is effective; when you write a 1, device operation cannot be guaranteed. Function 0: A-D1 conversion mode 1: Comparator mode 0: Normal rate 1: Double rate 0 R W A-D1 Single Mode Register 0 is used to control operation of the A-D1 converter during single mode (including special mode "Forcible single mode execution during scan mode"). 11-24 32170/32174 Group User's Manual (Rev. 2.1) 11 (1) ADnSMSL (A-Dn conversion mode selection) bit A-D CONVERTERS 11.2 A-D Converter Related Registers (D8) This bit selects A-D conversion mode for the A-Dn converter during single mode. Setting this bit to 0 selects A-D conversion mode, and setting this bit to 1 selects comparator mode. (2) ADnSSPD (A-Dn conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-Dn converter during single mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed). (3) ANnSEL (analog input pin selection) bits (D12-D15) These bits select analog input pins for the A-Dn converter during single mode. It is the channels selected by these bits that are operated on for A-D conversion or comparate operation. When you read these bits, they show the values written to them. 11-25 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.3 A-D Scan Mode Register 0 s A-D0 Scan Mode Register 0 (AD0SCM0) D0 1 2 3 4 A-D CONVERTERS 11.2 A-D Converter Related Registers D 0 1 Bit Name No functions assigned AD0CMSL (A-D0 scan mode selection) 2 AD0CTRG (A-D0 hardware trigger selection) 3 AD0CSEL (A-D0 conversion start trigger selection) 4 AD0CREQ (Interrupt request/DMA request selection) 5 AD0CCMP (A-D0 conversion completed) 6 AD0CSTP (A-D0 conversion stop) 7 AD0CSTT (A-D0 conversion start) 0: Single-shot mode 1: Continuous mode _________ Function R 0 W – 0: ADTRG signal input 1: Output event bus 3 0: Software trigger 1: Hardware trigger 0: Requests A-D0 interrupt 1: Requests DMA transfer 0: A-D0 conversion in progress 1: A-D0 conversion completed 0: Performs no operation 1: Stops A-D0 conversion 0: Performs no operation 1: Starts A-D0 conversion 0 0 – A-D0 Scan Mode Register 0 is used to control operation of the A-D0 converter during scan mode. 11-26 32170/32174 Group User's Manual (Rev. 2.1) 11 s A-D1 Scan Mode Register 0 (AD1SCM0) A-D CONVERTERS 11.2 A-D Converter Related Registers D 0 1 Bit Name No functions assigned AD1CMSL (A-D1 scan mode selection) 2 AD1CTRG (A-D1 hardware trigger selection) 3 AD1CSEL (A-D1 conversion start trigger selection) 4 AD1CREQ (Interrupt request selection) 5 AD1CCMP (A-D1 conversion completed) 6 AD1CSTP (A-D1 conversion stop) 7 AD1CSTT (A-D1 conversion start) 0: Single-shot mode 1: Continuous mode _________ Function R 0 W – 0: ADTRG signal input 1: TID1 overflow/underflow 0: Software trigger 1: Hardware trigger 0: Enables A-D1 interrupt request 1: Disables A-D1 interrupt request 0: A-D1 conversion in progress 1: A-D1 conversion completed 0: Performs no operation 1: Stops A-D1 conversion 0: Performs no operation 1: Starts A-D1 conversion 0 0 – A-D1 Scan Mode Register 0 is used to control operation of the A-D1 converter during scan mode. 11-27 32170/32174 Group User's Manual (Rev. 2.1) 11 (1) ADnCMSL (A-Dn scan mode selection) bit (D1) A-D CONVERTERS 11.2 A-D Converter Related Registers This bit selects scan mode of the A-Dn converter between single-shot scan and continuous scan. Setting this bit to 0 selects single-shot scan mode, so that the channels selected by the ANnSCAN (scan loop selection) bits are sequentially A-D converted and when A-D conversion in all selected channels are completed, the conversion operation stops. Setting this bit to 1 selects continuous scan mode, so that when operation in single-shot scan mode is completed, the selected channels are A-D converted beginning with the first channel again. This A-D conversion is continued until halted by setting the ADnCSTP (A-Dn conversion stop) bit to 1. (2) ADnCTRG (A-Dn hardware trigger selection) bit (D2) When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/ underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL (A-Dn conversion start trigger selection) bit is set to choose a software trigger. When using the ____________ ____________ ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input is held low, new A-D conversion is not started. (3) ADnCSEL (A-Dn conversion start trigger selection) bit (D3) This bit selects whether to use a software or hardware trigger to start A-D conversion of the A-Dn converter during scan mode. When you choose a software trigger, A-D conversion is started by setting the ADnCSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D conversion is started for the cause of start selected by the ADnCTRG (hardware trigger selection) bit. (4) ADnCREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4) For the A-D0 converter (AD0SCM0), this bit selects whether to request an A-D0 conversion interrupt or DMA transfer when one cycle of scan operation is completed. For the A-D1 converter (AD1SCM0), this bit selects whether to enable or disable an A-D0 conversion interrupt when one cycle of scan operation is completed. (5) ADnCCMP (A-Dn conversion completion) bit (D5) This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing scan mode A-D conversion and set to 1 when single-shot scan mode is completed, or when continuous scan mode is halted by setting ADnCSTT (A-Dn conversion stop) bit to 1. 11-28 32170/32174 Group User's Manual (Rev. 2.1) 11 (6) ADnCSTP (A-Dn conversion stop) bit (D6) A-D CONVERTERS 11.2 A-D Converter Related Registers Scan mode A-D conversion of the A-Dn converter can be halted by setting this bit to 1 while the operation is in progress. This bit is effective only when operating in scan mode. If single mode and scan mode both are active in special operation mode, manipulation of this bit does not affect single mode operation. Scan mode operation is halted immediately by a write to this bit, and the A-D conversion being executed in a channel is aborted in the middle, without transfer to the A-D data register. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the ADn conversion stop bit has priority. (7) ADnCSTT (A-Dn conversion start) bit (D7) This bit is used to start scan mode operation of the A-Dn converter in software. This bit is effective only when a software trigger has been selected by the ADnCSEL (A-Dn conversion start trigger selection) bit, and starts A-D conversion when it is set to 1. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the ADn conversion stop bit has priority. If this bit is set to 1 again during scan mode conversion, special operation mode "Conversion restart" is entered into, so that scan operation is restarted according to the contents set by Scan Mode Register 0 and Scan Mode Register 1. If this bit is set to 1 again during single mode A-D conversion, special operation mode "Scan mode start after single mode execution" is entered into, so that scan mode operation is started subsequently after single mode is completed. 11-29 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.4 A-D Scan Mode Register 1 s A-D0 Scan Mode Register 1 (AD0SCM1) D8 9 AD0CSPD 10 11 12 A-D CONVERTERS 11.2 A-D Converter Related Registers D 8 9 Bit Name No functions assigned AD0CSPD (A-D0 conversion rate selection) 10,11 12-15 No functions assigned AN0SCAN (A-D0 scan loop selection) 01XX: 4-channel scan 10XX: 8-channel scan 11XX: 16-channel scan 00XX: 16-channel scan 0: Normal 1: × 2 0 – Function R 0 W – 0000: Converting AD0IN0 0001: Converting AD0IN1 0010: Converting AD0IN2 0011: Converting AD0IN3 0100: Converting AD0IN4 0101: Converting AD0IN5 0110: Converting AD0IN6 0111: Converting AD0IN7 1000: Converting AD0IN8 1001: Converting AD0IN9 1010: Converting AD0IN10 1011: Converting AD0IN11 1100: Converting AD0IN12 1101: Converting AD0IN13 1110: Converting AD0IN14 1111: Converting AD0IN15 A-D0 Scan Mode Register 1 is used to control operation of the A-D0 converter during scan mode. 11-30 32170/32174 Group User's Manual (Rev. 2.1) 11 s A-D1 Scan Mode Register 1 (AD1SCM1) D8 9 AD1CSPD 10 11 12 A-D CONVERTERS 11.2 A-D Converter Related Registers D 8 9 Bit Name No functions assigned AD1CSPD (A-D1 conversion rate selection) 10,11 12-15 No functions assigned AN1SCAN (A-D1 scan loop selection) 01XX: 4-channel scan 10XX: 8-channel scan 11XX: 16-channel scan 00XX: 16-channel scan 0: Normal 1: × 2 0 – Function R 0 W – 0000: Converting AD1IN0 0001: Converting AD1IN1 0010: Converting AD1IN2 0011: Converting AD1IN3 0100: Converting AD1IN4 0101: Converting AD1IN5 0110: Converting AD1IN6 0111: Converting AD1IN7 1000: Converting AD1IN8 1001: Converting AD1IN9 1010: Converting AD1IN10 1011: Converting AD1IN11 1100: Converting AD1IN12 1101: Converting AD1IN13 1110: Converting AD1IN14 1111: Converting AD1IN15 A-D1 Scan Mode Register 1 is used to control operation of the A-D1 converter during scan mode. 11-31 32170/32174 Group User's Manual (Rev. 2.1) 11 (1) ADnCSPD (A-Dn conversion rate selection) bit A-D CONVERTERS 11.2 A-D Converter Related Registers (D9) This bit selects an A-D conversion rate for the A-Dn converter during scan mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed). (2) ANnSCAN (A-Dn scan loop selection) bits (D12-D15) The ANnSCAN (A-Dn scan loop selection) bits set the channels to be scanned during scan mode of the A-Dn converter. In this case, writes to D14 and D15 have no effect. The ANnSCAN (A-Dn scan loop selection) bits when read during scan operation show the status of the A-Dn converter, indicating the channel it is converting. The value read from these bits during single mode are always "B'0000." If A-D conversion is halted by setting Scan Mode Register 0 ADnCSTP (A-Dn conversion stop) bit to 1 during scan mode execution, the bits when read at this time show the value of the channel in which the A-D conversion has been canceled. Also, if halted during single mode conversion in special operation mode "Forcible single mode execution during scan mode," the bits when read at this time show the value of the channel in which the A-D conversion has been canceled in the middle of scan. 11-32 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.5 A-D Successive Approximation Register A-D CONVERTERS 11.2 A-D Converter Related Registers s A-D0 Successive Approximation Register (AD0SAR) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 AD1SAR D 0-5 6-15 Bit Name No functions assigned AD1SAR (A-D1 successive approximation value/comparison value) • A-D successive approximation value (A-D conversion mode) • Comparison value (comparator mode) Function R 0 W – Note: This register must always be accessed in halfwords. The A-D1 Successive Approximation Register (AD1SAR), when in A-D conversion mode, is used to read out the conversion result of the A-D1 converter, and when in comparator mode, it is used to write a comparison value. In A-D conversion mode, the successive approximation method is used to perform A-D conversion. With this method, the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning with the high-order side, and the comparison result is set in the AD1Successive Approximation Register (AD1SAR) bits (D6-D15). After the A-D conversion is completed, the value of this register is transferred to the 10-bit A-D1 Data Register (AD1DTn) corresponding to the converted channel. When you read this register in the middle of A-D conversion, you see the result in the middle of conversion. In comparator mode, write a comparison value (the value to be compared in comparate operation) to this register. Simultaneously with a write to this register, comparate operation with the analog input pin that has been set by Single Mode Register 1 starts. After comparate operation, the result is stored in the A-D1 Comparate Data Register (AD1CMP). Use the calculation formula shown below to find the comparison value to be written to the AD1Successive Approximation Register (AD1SAR) during comparator mode. Comparison value = H'3FF × Comparate comparison voltage [V] VREF1 input voltage [V] 11-34 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.6 A-D0 Comparate Data Register s A-D0 Comparate Data Register (AD0CMP) D0 AD0 CMP0 A-D CONVERTERS 11.2 A-D Converter Related Registers 9 10 11 12 13 14 D15 AD0DT0-AD0DT15 D 0-5 6-15 Bit Name No functions assigned AD0DT0-AD0DT15 (A-D0 data) Note: This register must always be accessed in halfwords. A-D conversion result Function R 0 W – – In single mode of the A-D0 converter, the result of A-D conversion is stored in the 10-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 10-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-37 32170/32174 Group User's Manual (Rev. 2.1) 11 s 10-bit A-D1 Data Register 0 (AD1DT0) s 10-bit A-D1 Data Register 1 (AD1DT1) s 10-bit A-D1 Data Register 2 (AD1DT2) s 10-bit A-D1 Data Register 3 (AD1DT3) s 10-bit A-D1 Data Register 4 (AD1DT4) s 10-bit A-D1 Data Register 5 (AD1DT5) s 10-bit A-D1 Data Register 6 (AD1DT6) s 10-bit A-D1 Data Register 7 (AD1DT7) s 10-bit A-D1 Data Register 8 (AD1DT8) s 10-bit A-D1 Data Register 9 (AD1DT9) s 10-bit A-D1 Data Register 10 (AD1DT10) s 10-bit A-D1 Data Register 11 (AD1DT11) s 10-bit A-D1 Data Register 12 (AD1DT12) s 10-bit A-D1 Data Register 13 (AD1DT13) s 10-bit A-D1 Data Register 14 (AD1DT14) s 10-bit A-D1 Data Register 15 (AD1DT15) D0 1 2 3 4 5 6 7 8 A-D CONVERTERS 11.2 A-D Converter Related Registers 9 10 11 12 13 14 D15 AD1DT0-AD1DT15 D 0-5 6-15 Bit Name No functions assigned AD1DT0-AD1DT15 (A-D1 data) Note: This register must always be accessed in halfwords. A-D conversion result Function R 0 W – – In single mode of the A-D1 converter, the result of A-D conversion is stored in the 10-bit A-D1 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D1 Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 10-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-38 32170/32174 Group User's Manual (Rev. 2.1) 11 11.2.8 8-bit A-D Data Registers s 8-bit A-D0 Data Register 0 (AD08DT0) s 8-bit A-D0 Data Register 1 (AD08DT1) s 8-bit A-D0 Data Register 2 (AD08DT2) s 8-bit A-D0 Data Register 3 (AD08DT3) s 8-bit A-D0 Data Register 4 (AD08DT4) s 8-bit A-D0 Data Register 5 (AD08DT5) s 8-bit A-D0 Data Register 6 (AD08DT6) s 8-bit A-D0 Data Register 7 (AD08DT7) s 8-bit A-D0 Data Register 8 (AD08DT8) s 8-bit A-D0 Data Register 9 (AD08DT9) s 8-bit A-D0 Data Register 10 (AD08DT10) s 8-bit A-D0 Data Register 11 (AD08DT11) s 8-bit A-D0 Data Register 12 (AD08DT12) s 8-bit A-D0 Data Register 13 (AD08DT13) s 8-bit A-D0 Data Register 14 (AD08DT14) s 8-bit A-D0 Data Register 15 (AD08DT15) D8 9 10 11 12 A-D CONVERTERS 11.2 A-D Converter Related Registers 13 14 D15 AD08DT0-AD08DT15 D 8-15 Bit Name AD08DT0-AD08DT15 (8-bit A-D0 data) Function 8-bit A-D conversion result R W – This A-D data register stores the 8-bit conversion data from the A-D0 converter. In single mode of the A-D0 converter, the result of A-D conversion is stored in the 8-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 8-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-39 32170/32174 Group User's Manual (Rev. 2.1) 11 s 8-bit A-D1 Data Register 0 (AD18DT0) s 8-bit A-D1 Data Register 1 (AD18DT1) s 8-bit A-D1 Data Register 2 (AD18DT2) s 8-bit A-D1 Data Register 3 (AD18DT3) s 8-bit A-D1 Data Register 4 (AD18DT4) s 8-bit A-D1 Data Register 5 (AD18DT5) s 8-bit A-D1 Data Register 6 (AD18DT6) s 8-bit A-D1 Data Register 7 (AD18DT7) s 8-bit A-D1 Data Register 8 (AD18DT8) s 8-bit A-D1 Data Register 9 (AD18DT9) s 8-bit A-D1 Data Register 10 (AD18DT10) s 8-bit A-D1 Data Register 11 (AD18DT11) s 8-bit A-D1 Data Register 12 (AD18DT12) s 8-bit A-D1 Data Register 13 (AD18DT13) s 8-bit A-D1 Data Register 14 (AD18DT14) s 8-bit A-D1 Data Register 15 (AD18DT15) D8 9 10 11 12 A-D CONVERTERS 11.2 A-D Converter Related Registers 13 14 D15 AD18DT0-AD18DT15 D 8-15 Bit Name AD18DT0-AD18DT15 (8-bit A-D1 data) Function 8-bit A-D1 conversion result R W – This A-D data register stores the 8-bit conversion data from the A-D1 converter. In single mode of the A-D1 converter, the result of A-D conversion is stored in the 8-bit A-D1 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D1 Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 8-bit AD Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. 11-40 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3 Functional Description of A-D Converters 11.3.1 How to Find Along Input Voltages The A-D converters use a 10-bit successive approximation method, and find the actual analog input voltage from the value (digital quantity) obtained through execution of A-D conversion by performing the following calculation. A-D conversion result × VREF input voltage [V] 1024 Analog input voltage [V] = The A-D converters are a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A-D converter is the voltage applied to the VREF pin, make sure an exact and stable constant-voltage power supply is connected to VREF. Also, make sure the analog circuit power supply and ground (AVCC, AVSS) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated. For details about the conversion accuracy, refer to Section 11.3.5, "Accuracy of A-D Conversion." 10-bit A-Di data register A-Di comparate data register ADiDT0-15 ADiCMP i=0, 1 AVCCi AVSSi 10-bit A-Di successive approximation register (ADiSAR) Vref A-D control circuit VREFi 10-bit A-D converter VIN Comparator ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 ADiIN15 Selector Successive approximation-type A-D converter unit Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A-D Converter Unit 11-41 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.2 A-D Conversion by Successive Approximation Method The A-D converter has A-D convert operation started by an A-D conversion start trigger (in software or hardware). Once A-D conversion begins, the following operation is automatically executed. (a) During single mode, Single Mode Register 0's A-D conversion/comparate completion bit is cleared to 0. During scan mode, Can Mode Register 0's A-D conversion completion bit is cleared to 0. (b) The content of the A-D Successive Approximation Register is cleared to "H'0000." (c) The A-D Successive Approximation Register's most significant bit (D6) is set to 1. (d) The comparison voltage, Vref(note), is fed from the D-A converter into the comparator. (e) The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in D6. If Vref < VIN, then D6 = 1 If Vref > VIN, then D6 = 0 (f) Operations in steps (c) through (e) above are executed for all other bits from D7 to D15. (g) The value stored in the A-D Successive Approximation Register at completion of the comparison of D15 is the final A-D conversion result. A-D Successive Approximation Register (ADiSAR) D6 1st comparison 1 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 D15 0 0 Vref > VIN then nX=0 2nd comparison n9 1 0 0 0 0 0 0 0 0 Vref < VIN then nX=1 i=0,1 Result of 1st comparison 3rd comparison n9 n8 1 0 0 0 0 0 0 0 Result of 2nd comparison 10th comparison n9 n8 n7 n6 n5 n4 n3 n2 n1 1 Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation Note: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref. • When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0 • When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) x (content of the A-D Successive Approximation Register - 0.5) 11-42 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.3 Functional Description of A-D Converters The comparison result finally is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each converted channel. Also, the 8-bit A-D Data Register (AD08DTn, AD18DTn) contains the 8 high-order bits of the 10-bit A-D conversion result. The following shows the procedure for A-D conversion by successive approximation in each operation mode. (1) Single mode The convert operation stops when comparison of the A-D Successive Approximation Register's D15 bit is completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred to the 10-bit A-D Data Registers 0-15 for the converted channel. (2) Single-shot scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (b) to (g) above are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A-D conversion for one specified scan loop is completed. (3) Continuous scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (b) to (g) above are reexecuted for the next channel to be converted. During continuous scan mode, the convert operation is executed continuously until scan operation is forcibly halted by setting the A-D conversion stop bit (Scan Mode Register 0's D6 bit) to 1. 11-43 32170/32174 Group User's Manual (Rev. 2.1) 11 11.3.3 Comparator Operation A-D CONVERTERS 11.3 Functional Description of A-D Converters When comparator mode (single mode only) is selected, the A-D converter functions as a comparator that compares analog input voltages with a preset comparison voltage. When a comparison value is written to the successive approximation register, the A-D converter starts 'comparating' the analog input voltage selected by the Single Mode Register 1 analog input selection bit with the value written to the successive approximation register. Once comparate begins, the following operation is automatically executed. (a) The Single Mode Register 0 or Scan Mode Register 0's A-D conversion/comparate completion flag is cleared to 0. (b) The comparison voltage, Vref(note), is fed from the D-A converter into the comparator. (c) The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in the comparate result flag (A-D Comparate Data Register's D15). If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 (d) The comparate operation stops after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP, AD1CMP)'s corresponding bit. Note: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref. • When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0 • When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) × (content of the A-D Successive Approximation Register - 0.5) 11-44 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.4 Calculation of the A-D Conversion Time The A-D conversion time is expressed by the sum of dummy cycle time and the actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. (a) Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D converter starts A-D conversion (b) A-D conversion execution cycle time (c) Comparate execution cycle time (d) End dummy time A time from when the A-D converter finished A-D conversion to when the CPU can stably read out this conversion result from the A-D data register (e) Scan to scan dummy time A time during single-shot or continuous scan mode from when the A-D converter finished A-D conversion in a channel to when it starts A-D conversion in the next channel The equation to calculate the A-D conversion time is as follows: A-D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: Shown in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. 11-45 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D conversion Convert operation begins start trigger A-D CONVERTERS 11.3 Functional Description of A-D Converters Transferred to A-D Completed data register Start dummy Execution cycle End dummy (Channel 0) Start dummy Execution cycle Scan to scan dummy (Channel 1) Execution cycle (Last channel) ..... Scan to scan dummy Execution cycle End dummy Figure 11.3.3 Conceptual Diagram of A-D Conversion Time Table 11.3.1 List of Conversion Clock Periods Transfer rate Normal rate Double rate Start dummy (Note 1) (Note 2) (Note 3) 4 4 4 4 4 4 A-D conversion Comparate execuexecution cycle tion cycle 294 168 42 24 End dummy 1 1 Unit: BCLK Scan to scan dummy (Note 4) 4 4 Note 1: This applies to a software triggered case. Note 2: This applies to a hardware triggered case. Note 3: This applies to a comparator mode case where a value is written to the A-D Successive Approximation Register. Note 4: This applies to only scan mode, and is added to the execution time for each channel. 11-46 32170/32174 Group User's Manual (Rev. 2.1) 11 Table 11.3.2 Total A-D Conversion Time Conversion started by Software trigger (Note 2) Conversion rate Normal A-D CONVERTERS 11.3 Functional Description of A-D Converters Conversion mode (Note 1) Single mode Single-shot scan /Continuous Conversion time [BCLK] 299 4-channel scan 8-channel scan 16-channel scan 1193 2385 4769 47 173 Comparator mode ×2 Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode Hardware trigger (Note 3) Normal Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode ×2 Single mode Single-shot scan /Continuous 4-channel scan 8-channel scan 16-channel scan Comparator mode 689 1377 2753 27 299 1193 2385 4769 47 173 689 1377 2753 27 Note 1: For single and comparator modes, this shows the time for A-D conversion in one channel or for comparate operation. For single-shot and continuous scan modes, this shows the time for A-D conversion in one scan loop. Note 2: This shows the time from when a write-to-register cycle is completed to when an A-D conversion interrupt request is generated. _____ Note 3: This shows the time from when the ADTRG pin input is asserted low or output event bus 3 is actuated _____ (for the A-D0 converter) or from when the ADTRG pin input is asserted low or TID1 overflow/underflow occurs (for the A-D1 converter) to when an A-D conversion interrupt request is generated. 11-47 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.5 Definition of the A-D Conversion Accuracy The accuracy of the A-D Converter is expressed by absolute accuracy. Absolute accuracy refers to the difference, expressed in terms of LSB, between the output code actually obtained by converting analog input voltages into digital quantities and the output code that can be expected from an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are chosen to be the midpoint values of voltage width at which an A-D converter with ideal characteristics will produce the same output code. For example, when VREF0 = 5.12 V, the width of 1 LSB of a 10-bit A-D converter is 5 mV, so that the middle points of analog input voltages are chosen to be 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, and so on. If the absolute accuracy of an A-D converter is said to be ±2 LSB, it means that if the input voltage is 25 mV, for example, then the actual A-D conversion result is in the range of H’003 to H’007, whereas the output code that can be expected from an ideal A-D converter is H’005. Note that absolute accuracy includes a zero error and full-scale error. Although when actually using the A-D Converter, the analog input voltages are in the range of AVSS0 to VREF0, excessively lowering the VREF0 voltage requires caution because resolution may be degraded. Note also that output codes for analog input voltages from VREF0 to AVCC0 are always H’3FF. A-D conversion result (hex) H’3FF H’3FE Ideal A-D conversion characteristic H’003 H’002 A-D conversion characteristic with infinite resolution H’001 H’000 0 VREF 1024 X1 VREF 1024 X2 VREF 1024 X3 VREF 1024 X1022 Analog input voltage [V] VREF 1024 X1023 VREF 1024 X1024 Figure 11.3.4 Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter's Analog Input Voltages 11-48 32170/32174 Group User's Manual (Rev. 2.1) 11 → Output code (hexadecimal) A-D CONVERTERS 11.3 Functional Description of A-D Converters H’00B Ideal A-D conversion characteristic H’00A H’009 H’008 H’007 H’006 H’005 H’004 H’003 H’002 H’001 H’000 0 5 10 15 20 25 30 35 40 45 50 55 A-D conversion characteristic with infinite resolution +2 LSB -2 LSB → Analog input voltage [mV] Figure 11.3.5 Absolute Accuracy of an A-D Converter 11-49 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.4 Precautions on Using A-D Converters 11.4 Precautions on Using A-D Converters • Forcible termination during scan operation If A-D conversion is halted by setting the A-D conversion stop bit (AD0CSTP, AD1CSTP) to 1 during scan mode operation and you read the content of the A-D data register for the channel in which conversion was in progress, it shows the last conversion result that had been transferred to the A-D data register before the conversion was forcibly terminated. _____ • ADTRG signal and input/output port _____ If you selected the ADTRG signal for an A-D conversion start trigger, do not use the ADTRG pin as an input/output port (P67). • Modification of A-D converter related registers If you want to change the contents of the A-D Conversion Interrupt Control Register, each Single and Scan Mode Register, or A-D Successive Approximation Register, except for the A-D conversion stop bit, do your change while A-D conversion is inactive, or be sure to restart A-D conversion after you changed the register contents. If the contents of these registers are changed in the middle of A-D conversion, the conversion results cannot be guaranteed. • Handling of analog input signals The A-D converters included in the 32170 do not have a sample-and-hold circuit. Therefore, make sure the analog input levels are fixed during A-D conversion. • A-D conversion completion bit readout timing If you want to read the A-D conversion completion bit (Single Mode Register 0's D5 bit or Scan Mode Register 0's D5 bit) immediately after A-D conversion has started, be sure to adjust the timing one clock cycle by, for example, inserting a NOP instruction before you read. • Regarding analog input pins Figure 11.4.1 shows an internal equivalent circuit of the analog input unit. For A-D conversions to be performed correctly, the microcomputer must finish charging the internal capacitor C2 within the designated time (i.e., the sampling time). Make sure the conditions shown below are met when determining the analog output device’s output impedance and the value of an external stabilizing capacitor. Condition 1: Sampling time ( AD conversion time 10 × 4 ) > C1 × R1 Condition 2: The peak current of i2 be minimized. 11-50 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.4 Precautions on Using A-D Converters Inside the microcomputer 10-bit AD successive approximation register (ADiSAR) VREF 10-bit DA converter Analog output device i R1 → C2 i2 i1 ↓ ADIN n Cin → Comparator R2 C1 E Selector • Time needed to change C2 1-bit conversion time • Peak current of i2 i2(peak) = C2 × (E-VREF) C1 × R1 ADIN i Sampling time Note: Increasing the value C1 × R1 helps to reduce the peak current. Evaluation time For a 10-bit converter conversion time = 1-bit conversion time ×10 Refer to the equation below as an approximate guide. AD conversion time > C1 × R1 10 × 4 Note: For A-D conversions to be performed correctly, the microcomputer must finish charging C2 within the sampling period. C1 : parasitic capacitance of board + stabilizing C R1 : resistance of analog output device Cin : input pin capacitance (approx. 10 pF) R2 : parasitic resistance of selector, etc. (1 to 2 kΩ) C2 : comparator capacitance (approx. 2.9 pF) E : input voltage Figure 11.4.1 Internal Equivalent Circuit of the Analog Input Unit 11-51 32170/32174 Group User's Manual (Rev. 2.1) 11 A-D CONVERTERS 11.4 Precautions on Using A-D Converters * This is a blank page. * 11-52 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O 12.2 Serial I/O Related Registers 12.3 Transmit Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.5 Precautions on Using CSIO Mode 12.6 Transmit Operation in UART Mode 12.7 Receive Operation in UART Mode 12.8 Fixed Period Clock Output Function 12.9 Precautions on Using UART Mode 12 12.1 Outline of Serial I/O SERIAL I/O 12.1 Outline of Serial I/O The 32170 contains a total of six channels of serial I/O-SIO0, SIO1, SIO2, SIO3, SIO4, and SIO5. SIO0, SIO1, SIO4, and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O). SIO2 and SIO3 are UART mode only. • CSIO mode (clock-synchronous serial I/O) Communication is performed synchronously with transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed). • UART mode (asynchronous serial I/O) Communication is performed asynchronously. The transfer data length can be selected from 7 bits, 8 bits, and 9 bits. Serial I/O0-3 each have a transmit DMA transfer and a receive DMA transfer request. These transfer requests, when combined with the internal DMAC, allow serial communication to be performed at high speed, as well as reduce the CPU burdens imposed by data communication. Serial I/O is outlined in the pages to follow. 12-2 32170/32174 Group User's Manual (Rev. 2.1) 12 Table 12.1.1 Outline of Serial I/O Item Number of channels Content CSIO/UART : 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock SERIAL I/O 12.1 Outline of Serial I/O During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transfer mode BRG count source Transmit half-duplex, receive half-duplex, transmit/receive full-duplex f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (when internal peripheral clock selected) (Note 2) f(BCLK) : Internal peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (when added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate CSIO mode : 152 bits/sec to 2M bits/sec (at f(BCLK) = 20 MHz) UART mode : 19 bits/sec to 156K bits/sec (at f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun error, parity error, framing error (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock function When using SIO0, SIO1, SIO4 and SIO5 as UART, this function outputs a dividedby-2 BRG clock from the SCLK pin. Note 1: The maximum input frequency of external clock during CSIO mode is 1/16 of f(BCLK). Note 2: When f(BCLK) is selected as the BRG count source, the BRG set value is subject to limitations. 12-3 32170/32174 Group User's Manual (Rev. 2.1) 12 Table 12.1.2 Serial I/O Interrupt Request Generation Function Serial I/O Interrupt Request SIO0 transmit buffer empty interrupt SIO0 receive-finished or receive error interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 receive-finished or receive error interrupt (selectable) SIO2 transmit buffer empty interrupt SIO2 receive-finished or receive error interrupt (selectable) SIO3 transmit buffer empty interrupt SIO3 receive-finished or receive error interrupt (selectable) SIO4 transmit buffer empty interrupt SIO4 receive-finished or receive error interrupt (selectable) SIO5 transmit buffer empty interrupt SIO5 receive-finished or receive error interrupt (selectable) SIO1 transmit interrupt SIO1 receive interrupt ICU Interrupt Cause SIO0 transmit interrupt SIO0 receive interrupt SERIAL I/O 12.1 Outline of Serial I/O SIO2, 3 transmit/receive interrupt (group interrupt) SIO2, 3 transmit/receive interrupt (group interrupt) SIO2, 3 transmit/receive interrupt (group interrupt) SIO2, 3 transmit/receive interrupt (group interrupt) SIO4, 5 transmit/receive interrupt (group interrupt) SIO4, 5 transmit/receive interrupt (group interrupt) SIO4, 5 transmit/receive interrupt (group interrupt) SIO4, 5 transmit/receive interrupt (group interrupt) Table 12.1.3 Serial I/O DMA Transfer Request Generation Function Serial I/O DMA Transfer Request SIO0 transmit buffer empty SIO0 receive-finished SIO1 transmit buffer empty SIO1 receive-finished SIO2 transmit buffer empty SIO2 receive-finished SIO3 transmit buffer empty SIO3 receive-finished DMAC Input Channel Channel 3 Channel 4 Channel 6 Channel 3 Channel 7 Channel 5 Channel 9 Channel 8 12-4 32170/32174 Group User's Manual (Rev. 2.1) 12 SIO0 SIO0 Transmit Buffer Register Transmit interrupt SERIAL I/O 12.1 Outline of Serial I/O TXD0 SIO0 Transmit Shift Register Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller To DMAC3 To DMAC4 RXD0 SIO0 Receive Shift Register SIO0 Receive Buffer Register UART mode CSIO mode When external clock selected When internal clock selected BCLK Clock divider Baud rate generator (BRG) CSIO mode When internal clock selected When UART mode selected SIO1 TXD1 SIO1 Transmit Shift Register Transmit/receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 1/16 1 (Set value + 1) 1/2 SCLKI0/ SCLKO0 To interrupt controller To DMAC6 To DMAC3 SCLKI1/ SCLKO1 RXD1 SIO1 Receive Shift Register SIO2 TXD2 Transmit interrupt Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request SIO2 Transmit Shift Register RXD2 SIO2 Receive Shift Register To DMAC7 To DMAC5 SIO3 Transmit interrupt To interrupt controller TXD3 SIO3 Transmit Shift Register Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMAC9 To DMAC8 RXD3 SIO3 Receive Shift Register SIO4 TXD4 SIO4 Transmit Shift Register Transmit/receive control circuit Transmit interrupt Receive interrupt RXD4 SIO4 Receive Shift Register SCLKI4 / SCLKO4 SIO5 TXD5 SIO5 Transmit Shift Register Transmit/receive control circuit Transmit interrupt Receive interrupt To interrupt controller RXD5 SIO5 Receive Shift Register SCLKI5 / SCLKO5 Note 1 : When BCLK is selected, the BRG set value is subject to limitations. Note 2 : SIO2 and SIO3 do not have the SCLKI/SCLKO function. Figure 12.1.1 Block Diagram of SIO0-SIO5 12-5 32170/32174 Group User's Manual (Rev. 2.1) 12 12.2 Serial I/O Related Registers The diagram below shows a serial I/O related register map. +0 Address SERIAL I/O 12.2 Serial I/O Related Registers Address H’0080 0100 H’0080 0102 D0 D7 D8 +1 Address D15 SIO23 Interrupt Status Register (SI23STAT) SIO03 Cause of Receive Interrupt Select Register (SI03SEL) SIO0 Transmit Control Register (S0TCNT) SIO03 Interrupt Mask Register (SI03MASK) H’0080 0110 H’0080 0112 H’0080 0114 H’0080 0116 SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register (S0RCNT) SIO1 Transmit Control Register (S1TCNT) SIO0 Baud Rate Register (S0BAUR) H’0080 0120 H’0080 0122 H’0080 0124 H’0080 0126 SIO1 Transmit/Receive Mode Register (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register (S1RCNT) SIO2 Transmit Control Register (S2TCNT) SIO1 Baud Rate Register (S1BAUR) SIO2 Transmit/Receive Mode Register (S2MOD) H’0080 0130 H’0080 0132 H’0080 0134 H’0080 0136 SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register (S2RCNT) SIO2 Baud Rate Register (S2BAUR) H’0080 0140 H’0080 0142 H’0080 0144 H’0080 0146 SIO3 Transmit Control Register (S3TCNT) SIO3 Transmit/Receive Mode Register (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register (S3RCNT) SIO45 Interrupt Status Register (SI45STAT) SIO45 Cause of Receive Interrupt Select Register (SI45SEL) SIO4 Transmit Control Register (S4TCNT) SIO3 Baud Rate Register (S3BAUR) SIO45 Interrupt Mask Register (SI45MASK) H’0080 0A00 H’0080 0A02 H’0080 0A10 H’0080 0A12 H’0080 0A14 H’0080 0A16 SIO4 Transmit/Receive Mode Register (S4MOD) SIO4 Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register (S4RCNT) SIO4 Baud Rate Register (S4BAUR) SIO5 Transmit/Receive Mode Register (S5MOD) H’0080 0A20 H’0080 0A22 H’0080 0A24 H’0080 0A26 SIO5 Transmit Control Register (S5TCNT) SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) SIO5 Receive Control Register (S5RCNT) SIO5 Baud Rate Register (S5BAUR) Blank addresses are reserved. Figure 12.2.1 Serial I/O Related Register Map 12-6 32170/32174 Group User's Manual (Rev. 2.1) 12 12.2.1 SIO Interrupt Related Registers (1) Selecting the cause of interrupt SERIAL I/O 12.2 Serial I/O Related Registers Interrupt signals sent from each SIO to the ICU (Interrupt Controller) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty. Receive interrupts are either receive-finished interrupts or receive error interrupts as selected by the Cause of Receive Interrupt Select Register (SI03SEL, SI45SEL). Note 1: No interrupt signals are generated unless interrupts are enabled by the SIO Interrupt Mask Register after enabling the TEN (transmit enable) bit or REN (receive enable) bit for the corresponding SIO. Note 2: SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5. (2) Precautions on using transmit interrupts Transmit interrupts are generated when the corresponding TEN (transmit enable) bit is enabled while the SIO Interrupt Mask Register is set to enable interrupts. (3) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a receive-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO's corresponding TEN (transmit enable) bit or REN (receive enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMAC before enabling the TEN or REN bits. When a receive error occurs, no receive-finished DMA transfer requests are generated. • Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (transmit enable bit) TBE (transmit buffer empty bit) Transmit DMA transfer request Figure 12.2.2 Transmit DMA Transfer Request 12-7 32170/32174 Group User's Manual (Rev. 2.1) 12 • Receive-finished DMA transfer request SERIAL I/O 12.2 Serial I/O Related Registers DMA transfer request is generated when the receive buffer is filled. RFIN (receive-completed bit) Receive DMA transfer request Note: When a receive error occurs, no receive-finished DMA transfer requests are generated. Figure 12.2.3 Receive-finished DMA Transfer Request 12-8 32170/32174 Group User's Manual (Rev. 2.1) 12 12.2.2 SIO Interrupt Control Registers s SIO23 Interrupt Status Register (SI23STAT) D0 1 2 3 4 IRQT2 SERIAL I/O 12.2 Serial I/O Related Registers D 0-3 4 Bit Name No functions assigned IRQT2 (SIO2 transmit-finished 0 : Interrupt not requested Function R 0 W — interrupt request status bit) 1 : Interrupt requested 5 IRQR2 (SIO2 receive interrupt request status bit) 6 IRQT3 (SIO3 transmit-finished 0 : Interrupt not requested 1 : Interrupt requested 0 : Interrupt not requested interrupt request status bit) 1 : Interrupt requested 7 IRQR3 (SIO3 receive interrupt request status bit) W= 0 : Interrupt not requested 1 : Interrupt requested : Only writing a 0 is effective; when you write a 1, the previous value is retained. Transmit/receive interrupt requests from SIO2 and SIO3 are described below. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing a 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write. 12-9 32170/32174 Group User's Manual (Rev. 2.1) 12 s SIO45 Interrupt Status Register (SI45STAT) D0 IRQT4 1 IRQR4 2 IRQT5 3 IRQR5 4 SERIAL I/O 12.2 Serial I/O Related Registers D 0 Bit Name IRQT4 (SIO4 transmit-finished Function 0 : Interrupt not requested R W interrupt request status bit) 1 : Interrupt requested 1 IRQR4 (SIO4 receive interrupt request status bit) 2 IRQT5 (SIO5 transmit-finished 0 : Interrupt not requested 1 : Interrupt requested 0 : Interrupt not requested interrupt request status bit) 1 : Interrupt requested 3 IRQR5 (SIO5 receive interrupt request status bit) 4-7 W= No functions assigned : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Interrupt not requested 1 : Interrupt requested 0 — Transmit/receive interrupt requests from SIO4 and SIO5 are described below. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing a 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write. 12-10 32170/32174 Group User's Manual (Rev. 2.1) 12 s SIO03 Interrupt Mask Register (SI03MASK) D8 9 10 11 12 SERIAL I/O 12.2 Serial I/O Related Registers D 8 Bit Name T0MASK (SIO0 transmit interrupt mask bit) 9 R0MASK (SIO0 receive interrupt mask bit) 10 T1MASK (SIO1 transmit interrupt mask bit) 11 R1MASK (SIO1 receive interrupt mask bit) 12 T2MASK (SIO2 transmit interrupt mask bit) 13 R2MASK (SIO2 receive interrupt mask bit) 14 T3MASK (SIO3 transmit interrupt mask bit) 15 R3MASK (SIO3 receive interrupt mask bit) Function 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request R W This register enables or disables interrupt requests generated by each SIO. Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1. 12-11 32170/32174 Group User's Manual (Rev. 2.1) 12 s SIO45 Interrupt Mask Register (SI45MASK) D8 9 10 11 12 SERIAL I/O 12.2 Serial I/O Related Registers D 8 Bit Name T4MASK (SIO4 transmit interrupt mask bit) 9 R4MASK (SIO4 receive interrupt mask bit) 10 T5MASK (SIO5 transmit interrupt mask bit) 11 R5MASK (SIO5 receive interrupt mask bit) 12 - 15 No functions assigned Function 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 : Masks (disables) interrupt request 1 : Enables interrupt request 0 — R W This register enables or disables interrupt requests generated by each SIO. Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1. 12-12 32170/32174 Group User's Manual (Rev. 2.1) 12 SERIAL I/O 12.2 Serial I/O Related Registers s SIO03 Cause of Receive Interrupt Select Register (SI03SEL) D 0-3 4 Bit Name No functions assigned ISR0 (SIO0 receive interrupt cause select bit) 5 ISR1 (SIO1 receive interrupt cause select bit) 6 ISR2 (SIO2 receive interrupt cause select bit) 7 ISR3 (SIO3 receive interrupt cause select bit) 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt Function R 0 W — This register selects the cause of an interrupt generated at completion of receive operation. [When set to 0] Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts occur for receive errors (except an overrun error), as well as for completion of receive operation. [When set to 1] Receive error interrupt is selected. The following lists the types of errors detected for reception errors. • CSIO mode : Overrun error • UART mode : Overrun error, parity error, and framing error 12-13 32170/32174 Group User's Manual (Rev. 2.1) 12 SERIAL I/O 12.2 Serial I/O Related Registers s SIO45 Cause of Receive Interrupt Select Register (SI45SEL) D 0-3 4 Bit Name No functions assigned ISR4 (SIO4 receive interrupt cause select bit) 5 ISR5 (SIO5 receive interrupt cause select bit) 6-7 No functions assigned 0 : Receive-finished interrupt 1 : Receive error interrupt 0 : Receive-finished interrupt 1 : Receive error interrupt 0 — Function R 0 W — This register selects the cause of an interrupt generated at completion of receive operation. [When set to 0] Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts occur for receive errors (except an overrun error), as well as for completion of receive operation. [When set to 1] Receive error interrupt is selected. The following lists the types of errors detected for reception errors. • CSIO mode : Overrun error • UART mode : Overrun error, parity error, and framing error 12-14 32170/32174 Group User's Manual (Rev. 2.1) 12 TXD2 Data bus b4 b12 RXD2 receive-finished RXD2 receive error ISR2 b6 F/F IRQT2 F/F T2MASK F/F SERIAL I/O 12.2 Serial I/O Related Registers 4-source inputs SIO2,3 transmit/receive interrupts (Level) b5 b13 TXD3 b6 b14 IRQR2 F/F R2MASK F/F IRQT3 F/F T2MASK F/F RXD3 receive-finished RXD3 receive error ISR3 b7 F/F b7 b15 IRQR3 F/F R2MASK F/F Figure 12.2.4 Block Diagram of SIO2,3 Transmit Interrupts TXD4 Data bus b0 b8 RXD4 receive-finished RXD4 receive error ISR4 b4 F/F IRQT4 F/F T4MASK F/F 4-source inputs SIO4,5 transmit/receive interrupts (Level) b1 b9 TXD5 b2 b10 IRQR4 F/F R2MASK F/F IRQT5 F/F T2MASK F/F RXD5 receive-finished RXD5 receive error ISR5 b5 F/F b3 b11 IRQR5 F/F R2MASK F/F Figure 12.2.5 Block Diagram of SIO4,5 Transmit Interrupts 12-15 32170/32174 Group User's Manual (Rev. 2.1) 12 12.2.3 SIO Transmit Control Registers s SIO0 Transmit Control Register (S0TCNT) s SIO1 Transmit Control Register (S1TCNT) s SIO2 Transmit Control Register (S2TCNT) s SIO3 Transmit Control Register (S3TCNT) s SIO4 Transmit Control Register (S4TCNT) s SIO5 Transmit Control Register (S5TCNT) D0 1 2 CDIV 3 4 SERIAL I/O 12.2 Serial I/O Related Registers 5 TSTAT 6 TBE D7 TEN 10 11 RDATA 12 13 14 D15 D 0-6 8 - 15 Bit Name No functions assigned RDATA (Receive data) Stores receive data. Function R 0 W — — The SIOn Receive Buffer Register is used to store the receive data. When the serial I/O finishes receiving data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. This register is a read-only register. For 7-bit data (UART mode only), data is set in bits D9-D15, with D8 and D7 always set to 0. For 8bit data, data is set in bits D8-D15, with D7 always set to 0. After reception is completed, you may read out the content of the SIO Receive Buffer Register, but if the serial I/O finishes receiving the next data before you read the previous data, an overrun error occurs. In this case, the data received thereafter is not transferred to the Receive Buffer Register. To restart reception normally, clear the Receive Control Register's REN (receive enable) bit to 0. Note: For 7-bit and 8-bit data, the register can be accessed bytewise. 12-22 32170/32174 Group User's Manual (Rev. 2.1) 12 12.2.7 SIO Receive Control Registers s SIO0 Receive Control Register (S0RCNT) s SIO1 Receive Control Register (S1RCNT) s SIO2 Receive Control Register (S2RCNT) s SIO3 Receive Control Register (S3RCNT) s SIO4 Receive Control Register (S4RCNT) s SIO5 Receive Control Register (S5RCNT) D0 1 RSTAT 2 RFIN 3 REN 4 OVR SERIAL I/O 12.2 Serial I/O Related Registers 5 PTY 6 FLM D7 ERS D 0-3 4 Bit Name No functions assigned RBO (Return bus off) 5 TSR (Time stamp Counter reset) 6-7 TSP (Time stamp prescaler) 0: Enables normal operation 1: Requests clearing of error counter 0: Enables count operation 1: Initializes count (by setting H'0000) D6 D7 0 0 : Selects CAN bus bit clock Function R 0 W – 0 1 : Selects CAN bus bit clock divided by 2 1 0 : Selects CAN bus bit clock divided by 3 1 1 : Selects CAN bus bit clock divided by 4 8-9 10 11 No functions assigned No functions assigned (Always set this bit to 0) FRST (Forcible reset) 12 BCM (BasicCAN mode) 13 14 No functions assigned LBM (Loopback mode) 15 RST (CAN reset) W= 0: Disables loopback function 1: Enables loopback function 0: Negates reset 1: Requests reset 0: Negates rest 1: Forcibly resets 0: Disables BasicCAN function 1: BasicCAN mode 0 – 0 0 – – : Only writing a 1 is effective. Automatically cleared to 0 in hardware. 13-8 32170/32174 Group User's Manual (Rev. 2.1) 13 (1) RBO (Return Bus Off) bit (D4) CAN MODULE 13.2 CAN Module Related Registers Setting this bit to 1 clears the Receive Error Counter (CAN0REC) and Transmit Error Counter (CAN0TEC) and forcibly places the CAN module into an error active state. This bit is cleared when an error active state is entered. Note: After clearing the error counter, transmission becomes possible when 11 consecutive recessive bits are detected on the CAN bus. (2) TSR (Time Stamp Counter Reset) bit (D5) Setting this bit to 1 clears the value of the CAN Time Stamp Counter Register (CAN0TSTMP) to H'0000. This bit is cleared when the value of the CAN Time Stamp Counter Register (CAN0TSTMP) is cleared to H'0000. (3) TSP (Time Stamp Prescaler) bits (D6, D7) These bits select the count clock source for the time stamp counter. Note: Do not change settings of TSP bits while CAN is operating (CAN Status Register CRS bit = 0). (4) FRST (Forcible Reset) bit (D11) When the FRST bit is set to 1, the CAN module is separated from the CAN bus regardless of whether or not the CAN module is communicating and the protocol control unit is reset. Note 1: To restart CAN communication, the FRST and RST bits must be cleared to 0. Note 2: If the FRST bit is set to 1 during communication, the CTX pin output goes high immediately after that. Therefore, setting the FRST bit to 1 while transmitting CAN frame may cause a CAN bus error. Note 3: The CAN Message Slot Control Register’s transmit/receive requests are not cleared by setting the FRST or RST bit. (5) BCM (BasicCAN Mode) bit (D12) By setting this bit to 1, the CAN module can be operated in BasicCAN mode. • Operation during BasicCAN mode In BasicCAN mode, two local slots-slots 14 and 15-are used as double buffers, and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15. Used for this acceptance filtering when slot 14 is active (next receive frame to be stored in slot 14) are the ID set for slot 14 and local mask A, and those used when slot 15 is active are the ID set for slot 15 and local mask B. Two types of frames-data frame and remote frame-can be received in this mode. 13-9 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers By using the same ID and setting the same value in mask registers for the two slots, the possibility of a message-lost trouble when, for example, receiving frames which have many IDs can be reduced. • Procedure for entering BasicCAN mode Follow the procedure below during initialization: (a) Set the IDs for slots 14 and 15 and local mask registers A and B. (We recommend setting the same value.) (b) Set the frame types handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type.) (c) Set the Message Slot Control Register for slots 14 and 15 to for data frame reception. (d) Set the BCM bit to 1. Note 1: Do not change settings of BCM bit when CAN is operating (CAN Status Register CRS bit = 0). Note 2: The first slot that is active after clearing the RST bit is slot 14. Note 3: Even during BasicCAN mode, slots 0 to 13 can be used as in normal operation. (6) LBM (Loopback Mode) bit (D14) When the LBM bit is set to 1, if a receive slot exists whose ID matches that of the frame sent by the CAN module itself, then the frame can be received. Note 1: No ACK is returned for the transmit frame. Note 2: Do not change settings of LBM bit when CAN is operating (CAN Status Register CRS bit = 0). (7) RST (CAN Reset) bit (D15) When the RST bit is cleared to 0, the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits. Also, the CAN Time Stamp Count Register thereby starts counting. When the RST bit is set to 1, the CAN module is reset so that after sending a frame from the slot which has had a transmit request set, the protocol control unit is reset and the CAN module is disconnected from the CAN bus. Frames received during this time are processed normally. Note 1: It is inhibited to set a new transmit request for a while from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset. Note 2: When the protocol control unit is reset by setting the RST bit to 1, the CAN Time Stamp Count Register and CAN Transmit/Receive Error Count Registers are initialized to 0. Note 3: To restart CAN communication, the FRST and RST bits must be cleared to 0. 13-10 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.2 CAN Status Register s CAN0 Status Register (CAN0STAT) D0 1 2 3 4 5 0 6 7 8 9 CAN MODULE 13.2 CAN Module Related Registers D 0 1 Bit Name No functions assigned BOS (Bus off status) 2 EPS (Error passive status) 3 CBS (CAN bus error) 4 BCS (BasicCAN status) 5 6 No functions assigned LBS (Loopback status) 7 CRS (CAN reset status) 8 RSB (Receive status) 9 TSB (Transmit status) 10 RSC (Receive complete status) 11 TSC (Transmit complete status) 0: Normal mode 1: Loopback mode 0: Operating 1: Reset 0: Not receiving 1: Receiving 0: Not transmitting 1: Transmitting 0: Reception not completed yet 1: Reception completed 0: Transmission not completed yet 1: Transmission completed – – – – – 0: Not Bus off 1: Bus off state 0: Not error passive 1: Error passive state 0: No error occurred 1: Error occurred 0: Normal mode 1: BasicCAN mode 0 – – – – – Function R 0 W – – 13-11 32170/32174 Group User's Manual (Rev. 2.1) 13 D 12-15 Bit Name MSN (Message slot number) Function CAN MODULE 13.2 CAN Module Related Registers R W Number of message slot which has finished sending or receiving 0000 : Slot0 0001 : Slot1 0010 : Slot2 0011 : Slot3 0100 : Slot4 0101 : Slot5 0110 : Slot6 0111 : Slot7 1000 : Slot8 1001 : Slot9 1010 : Slot10 1011 : Slot11 1100 : Slot12 1101 : Slot13 1110 : Slot14 1111 : Slot15 – (1) BOS (Bus Off Status) bit (D1) When BOS bit = 1, it means that the CAN module is in a bus-off state. [Set condition] This bit is set to 1 when the transmit error counter value exceeded 255 and a bus-off state is entered. [Clear condition] This bit is cleared when restored from the bus-off state. (2) EPS (Error Passive Status) bit (D2) When EPS bit = 1, it means that the CAN module is in an error passive state. [Set condition] This bit is set to 1 when the transmit or receive error counter value exceeded 127 and an error passive state is entered. [Clear condition] This bit is cleared when restored from the error passive state. 13-12 32170/32174 Group User's Manual (Rev. 2.1) 13 (3) CBS (CAN Bus Error) bit (D3) [Set condition] CAN MODULE 13.2 CAN Module Related Registers This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when normally transmitted or received. (4) BCS (BasicCAN Status) bit (D4) When BCS bit = 1, it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to 1 when operating in BasicCAN mode. Conditions for operating in BasicCAN mode • The CAN Control Register BCM bit must be set to 1. • Slots 14 and 15 both must be set for data frame reception. [Clear condition] This bit is cleared by clearing the BCM bit to 0. (5) LBS (Loopback Status) bit (D6) When LBS bit = 1, it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to 1 by setting the CAN Control Register LBM (loopback mode) bit to 1. [Clear condition] This bit is cleared by clearing the LBM bit to 0. (6) CRS (CAN Reset Status) bit (D7) When CRS bit = 1, it means that the protocol control unit is in a reset state. [Set condition] This bit is set to 1 when the CAN module's protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) bit to 0. 13-13 32170/32174 Group User's Manual (Rev. 2.1) 13 (7) RSB (Receive Status) bit (D8) CAN MODULE 13.2 CAN Module Related Registers [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module started operating as a transmit node or entered a bus idle state. (8) TSB (Transmit Status) bit (D9) [Set condition] This bit is set to 1 when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module started operating as a receive node or entered a bus idle state. (9) RSC (Receive Complete Status) bit (D10) [Set condition] This bit is set to 1 when the CAN module finished receiving normally (regardless of whether any slot exists that meets receive conditions). [Clear condition] This bit is cleared when the CAN module finished transmitting normally. (10) TSC (Transmit Complete Status) bit (D11) [Set condition] This bit is set to 1 when the CAN module finished transmitting normally. [Clear condition] This bit is cleared when the CAN module finished receiving normally. (11) MSN (Message Slot Number) bits (D12-D15) These bits show the relevant slot number when the CAN module finished transmitting or finished storing received data. This bit cannot be cleared to 0 in software. Note: If during loopback mode the CAN module receives the frame it itself transmitted, the MSN bit behaves as follows: The bit indicates the transmit slot number when the module finishes sending and is then cleared to 0 when the module stores the received data. 13-14 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.3 CAN Extended ID Register s CAN0 Extended ID Register (CAN0EXTID) D0 IDE0 CAN MODULE 13.2 CAN Module Related Registers D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name IDE0 (Extended ID0) IDE1 (Extended ID1) IDE2 (Extended ID2) IDE3 (Extended ID3) IDE4 (Extended ID4) IDE5 (Extended ID5) IDE6 (Extended ID6) IDE7 (Extended ID7) IDE8 (Extended ID8) IDE9 (Extended ID9) IDE10 (Extended ID10) IDE11 (Extended ID11) IDE12 (Extended ID12) IDE13 (Extended ID13) IDE14 (Extended ID14) IDE15 (Extended ID15) Function 0: Standard ID format 1: Extended ID format R W This register selects the format of frames handled in message slots corresponding to each bit. The standard ID format is selected when a message slot's corresponding bit is set to 0, or the extended ID format is selected when the bit is set to 1. Note: Settings of each bit of this register can only be changed when the corresponding slot does not have transmit or receive requests set. 13-15 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.4 CAN Configuration Register s CAN0 Configuration Register (CAN0CONF) D0 SJW 1 2 3 PH2 4 5 6 PH1 7 8 9 CAN MODULE 13.2 CAN Module Related Registers D 0-1 Bit Name SJW (reSynchronization Jump Width) Function Sets reSynchronization Jump Width 00: SJW = 1Tq 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq 2-4 PH2 (Phase Segment2) Sets Phase Segment2 000: Settings inhibited 001: Phase Segment2 = 2Tq 010: Phase Segment2 = 3Tq 011: Phase Segment2 = 4Tq 100: Phase Segment2 = 5Tq 101: Phase Segment2 = 6Tq 110: Phase Segment2 = 7Tq 111: Phase Segment2 = 8Tq 5-7 PH1 (Phase Segment1) Sets Phase Segment1 000: Phase Segment1 = 1Tq 001: Phase Segment1 = 2Tq 010: Phase Segment1 = 3Tq 011: Phase Segment1 = 4Tq 100: Phase Segment1 = 5Tq 101: Phase Segment1 = 6Tq 110: Phase Segment1 = 7Tq 111: Phase Segment1 = 8Tq R W 13-16 32170/32174 Group User's Manual (Rev. 2.1) 13 D 8-10 Bit Name PRB (Propagation Segment) CAN MODULE 13.2 CAN Module Related Registers D 0-15 Bit Name CANSTMP Function 16-bit counter value R W – The CAN module contains a 16-bit counter. The count period can be chosen to be the CAN bus bit period divided by 1, 2, 3, or 4 by setting the CAN Control Register (CAN0CNT)'s TSP (Time Stamp Prescaler) bits. When the CAN module finishes transmitting or receiving, it captures the counter value and stores it in a message slot. The counter is made to start counting by clearing the CAN Control Register (CAN0CNT)'s RST bit to 0. Note 1: The protocol control unit is reset and the counter is initialized to H'0000 by setting the CAN Control Register (CAN0CNT)'s RST (CAN Reset) bit to 1. Also, the counter can be initialized to H'0000 while the CAN module is operating by setting TSR (Time Stamp Counter Reset) bit to 1. Note 2: During loopback mode, if an ID-matching slot exists, the CAN module stores the time stamp value in the corresponding slot when it finished receiving. (No time stamp value is stored this way when the CAN module finished transmitting.) 13-19 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.6 CAN Error Count Registers s CAN0 Receive Error Count Register (CAN0REC) D0 1 2 3 REC 4 CAN MODULE 13.2 CAN Module Related Registers D 0-7 Bit Name REC (Receive error counter) Function Receive error count value R W – In an error-active/error-passive state, a receive error count is stored in this register. When received normally, the counter counts down; when an error occurs, the counter counts up. When received normally while REC 128 (error-passive), REC is set to 127. In a bus-off state, an indeterminate value is stored in this register. The count is reset to H'00 upon returning to an error-active state. s CAN0 Transmit Error Count Register (CAN0TEC) D8 9 10 11 TEC 12 13 D 8-15 Bit Name TEC (Transmit error counter) Function Transmit error count value R W – In an error-active/error-passive state, a transmit error count is stored in this register. When transmitted normally, the counter counts down; when an error occurs, the counter counts up. In a bus-off state, an indeterminate value is stored in this register. The count is reset to H'00 upon returning to an error-active state. 13-20 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.7 CAN Baud Rate Prescaler s CAN0 Baud Rate Prescaler (CAN0BRP) D0 1 2 3 CANBRP 4 CAN MODULE 13.2 CAN Module Related Registers D 0-7 Bit Name BRP Function Selects baud rate prescaler value R W This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq's for 1 bit). Tq period = (CANBRP + 1)/ CPU clock CAN transfer baud rate = 1 Tq period × number of Tq's for 1 bit Progagation Segment + Phase Segment 1 + Phase Segment 2 Note 1: Setting H'00 (divided by 1) is inhibited. Note 2: During CAN operation (CAN Status Register CRS bit = 0), do not alter settings of the CAN Baud Rate Prescaler (CAN0BRP). Number of Tq's for 1 bit = Synchronization Segment + 13-21 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.8 CAN Interrupt Related Registers CAN MODULE 13.2 CAN Module Related Registers s CAN0 Slot Interrupt Status Register (CAN0SLIST) D0 1 2 3 4 5 6 7 8 9 10 11 D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name SSB0 (Slot 0 interrupt request status) SSB1 (Slot 1 interrupt request status) SSB2 (Slot 2 interrupt request status) SSB3 (Slot 3 interrupt request status) SSB4 (Slot 4 interrupt request status) SSB5 (Slot 5 interrupt request status) SSB6 (Slot 6 interrupt request status) SSB7 (Slot 7 interrupt request status) SSB8 (Slot 8 interrupt request status) SSB9 (Slot 9 interrupt request status) SSB10 (Slot 10 interrupt request status) SSB11 (Slot 11 interrupt request status) SSB12 (Slot 12 interrupt request status) SSB13 (Slot 13 interrupt request status) SSB14 (Slot 14 interrupt request status) SSB15 (Slot 15 interrupt request status) Function 0: No interrupt request 1: Interrupt requested R W W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 13-22 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers When using CAN interrupts, this register lets you know which slot requested an interrupt. • Slots set for transmission The bit is set to 1 when the CAN module finished transmitting. The bit is cleared by writing a 0 in software. • Slots set for reception The bit is set to 1 when the CAN module finished receiving and finished storing the received message in the message slot. The bit is cleared by writing a 0 in software. When writing to the CAN slot interrupt status, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write. Note 1: If the automatic response function is enabled for remote frame receive slots, the status is set after the CAN module received a remote frame and when it transmitted a data frame. Note 2: For remote frame transmit slots, the status is set after the CAN module transmitted a remote frame and when it received a data frame. Note 3: If the status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the status is set. 13-23 32170/32174 Group User's Manual (Rev. 2.1) 13 D0 IRB0 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Slot Interrupt Mask Register (CAN0SLIMK) 1 IRB1 D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name IRB0 (Slot 0 interrupt request mask) IRB1 (Slot 1 interrupt request mask) IRB2 (Slot 2 interrupt request mask) IRB3 (Slot 3 interrupt request mask) IRB4 (Slot 4 interrupt request mask) IRB5 (Slot 5 interrupt request mask) IRB6 (Slot 6 interrupt request mask) IRB7 (Slot 7 interrupt request mask) IRB8 (Slot 8 interrupt request mask) IRB9 (Slot 9 interrupt request mask) IRB10 (Slot 10 interrupt request mask) IRB11 (Slot 11 interrupt request mask) IRB12 (Slot 12 interrupt request mask) IRB13 (Slot 13 interrupt request mask) IRB14 (Slot 14 interrupt request mask) IRB15 (Slot 15 interrupt request mask) Function 0: Masks (disables) interrupt request 1: Enables interrupt request R W This register controls interrupt requests generated at completion of data transmission or reception in each corresponding slot by enabling or disabling them. When IRBn (n = 0-15) is set to 1, interrupt requests to be generated at completion of transmission or reception in the corresponding slot are enabled. The CAN Slot Interrupt Status Register (CAN0SLIST) shows you which slot has requested the interrupt. 13-24 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Error Interrupt Status Register (CAN0ERIST) D0 1 2 3 4 5 EIS s CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) D0 1 2 3 SID0M 4 SID1M 5 SID2M 6 SID3M D7 SID4M s CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) D8 9 10 SID5M 11 SID6M 12 SID7M 13 SID8M 14 SID9M D15 SID10M s CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) D0 1 2 3 4 EID0M 5 EID1M 6 EID2M D7 EID3M s CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) D8 EID4M 9 EID5M 10 EID6M 11 EID7M 12 EID8M 13 EID9M 14 EID10M D15 EID11M s CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) D 0,1 2-7 Bit Name No functions assigned EID12M-EID17M (Extended ID12 to extended ID17) 0: ID not checked 1: ID checked Function R 0 W – Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively. • When a bit in this register is set to 0, its corresponding ID bit is masked (assumed to have matched) during acceptance filtering. • When a bit in this register is set to 1, its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot, the received data is stored in it. Note 1: EID0M corresponds to the MSB of extended ID. Note 2: The Global Mask Register can only be changed when none of slots 0-13 have receive requests set. Note 3: The Local Mask Register A can only be changed when slot 14 does not have a receive request set. Note 4: The Local Mask Register B can only be changed when slot 15 does not have a receive request set. 13-33 32170/32174 Group User's Manual (Rev. 2.1) 13 13.2.10 CAN Message Slot Control Registers CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot0 Control Registers (C0MSL0CNT) s CAN0 Message Slot1 Control Registers (C0MSL1CNT) s CAN0 Message Slot2 Control Registers (C0MSL2CNT) s CAN0 Message Slot3 Control Registers (C0MSL3CNT) s CAN0 Message Slot4 Control Registers (C0MSL4CNT) s CAN0 Message Slot5 Control Registers (C0MSL5CNT) s CAN0 Message Slot6 Control Registers (C0MSL6CNT) s CAN0 Message Slot7 Control Registers (C0MSL7CNT) s CAN0 Message Slot8 Control Registers (C0MSL8CNT) s CAN0 Message Slot9 Control Registers (C0MSL9CNT) s CAN0 Message Slot10 Control Registers (C0MSL10CNT) s CAN0 Message Slot11 Control Registers (C0MSL11CNT) s CAN0 Message Slot12 Control Registers (C0MSL12CNT) s CAN0 Message Slot13 Control Registers (C0MSL13CNT) s CAN0 Message Slot14 Control Registers (C0MSL14CNT) s CAN0 Message Slot15 Control Registers (C0MSL15CNT) D0(D8) TR 1 RR 2 RM 3 RL 4 RA 5 ML 6 TRSTAT D7(D15) TRFIN 6 SID3 D7 SID4 D 0-2 3-7 Bit Name Function R 0 W – No functions assigned. (Always set these bits to 0) SID0-SID4 (Standard ID0 to standard ID4) Standard ID0 to standard ID4 These registers are the transmit frame/receive frame memory space. 13-38 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) s CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) s CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) s CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) s CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) s CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) s CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) s CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) s CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) s CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) s CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) s CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) s CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) s CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) s CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) s CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) D8 9 10 SID5 11 SID6 12 SID7 13 SID8 14 SID9 D15 SID10 D 8,9 10-15 Bit Name Function R 0 W – No functions assigned. (Always set these bits to 0) SID5-SID10 (Standard ID5 to standard ID10) Standard ID5 to standard ID10 These registers are the transmit frame/receive frame memory space. 13-39 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) s CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) s CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) s CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) s CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) s CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) s CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) s CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) s CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) s CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) s CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) s CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) s CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) s CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) s CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) s CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) D0 1 2 3 4 EID0 5 EID1 6 EID2 D7 EID3 D 0-3 4-7 Bit Name Function R 0 W – No functions assigned. (Always set these bits to 0) EID0-EID3 (Extended ID0 to extended ID3) Extended ID0 to extended ID3 These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-40 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) s CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) s CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) s CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) s CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) s CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) s CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) s CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) s CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) s CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) s CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) s CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) s CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) s CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) s CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) s CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) D8 EID4 9 EID5 10 EID6 11 EID7 12 EID8 13 EID9 14 EID10 D15 EID11 D 8-15 Bit Name EID4-EID11 (Extended ID4 to extended ID11) Function Extended ID4 to extended ID11 R W These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-41 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) s CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) s CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) s CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) s CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) s CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) s CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) s CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) s CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) s CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) s CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) s CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) s CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) s CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) s CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) s CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) D0 1 2 EID12 3 EID13 4 EID14 5 EID15 6 EID16 D7 EID17 D 0,1 2-7 Bit Name Function R 0 W – No functions assigned. (Always set these bits to 0) EID12-EID17 (Extended ID12 to extended ID17) Extended ID12 to extended ID17 These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. 13-42 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) s CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) s CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) s CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) s CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) s CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) s CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) s CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) D8 9 10 11 12 DLC0 13 DLC1 14 DLC2 D15 DLC3 D 8-11 12-15 Bit Name Function R 0 W – No functions assigned. (Always set these bits to 0) DLC0-DLC3 (Sets data length) 0 0 0 0 : 0 byte 0 0 0 1 : 1 byte 0 0 1 0 : 2 byte 0 0 1 1 : 3 byte 0 1 0 0 : 4 byte 0 1 0 1 : 5 byte 0 1 1 0 : 6 byte 0 1 1 1 : 7 byte 1 X X X : 8 byte These registers are the transmit frame/receive frame memory space. When transmitting, the register sets the length of transmit data. When receiving, the register stores the received DLC. 13-43 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 0 (C0MSL0DT0) s CAN0 Message Slot 1 Data 0 (C0MSL1DT0) s CAN0 Message Slot 2 Data 0 (C0MSL2DT0) s CAN0 Message Slot 3 Data 0 (C0MSL3DT0) s CAN0 Message Slot 4 Data 0 (C0MSL4DT0) s CAN0 Message Slot 5 Data 0 (C0MSL5DT0) s CAN0 Message Slot 6 Data 0 (C0MSL6DT0) s CAN0 Message Slot 7 Data 0 (C0MSL7DT0) s CAN0 Message Slot 8 Data 0 (C0MSL8DT0) s CAN0 Message Slot 9 Data 0 (C0MSL9DT0) s CAN0 Message Slot 10 Data 0 (C0MSL10DT0) s CAN0 Message Slot 11 Data 0 (C0MSL11DT0) s CAN0 Message Slot 12 Data 0 (C0MSL12DT0) s CAN0 Message Slot 13 Data 0 (C0MSL13DT0) s CAN0 Message Slot 14 Data 0 (C0MSL14DT0) s CAN0 Message Slot 15 Data 0 (C0MSL15DT0) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT0 D 0-7 Bit Name C0MSLnDT0 Function Message slot n data 0 R W These registers are the transmit frame/receive frame memory space. Note 1: If the data length (DLC value) of the data frame being stored by any receive slot is 0, an indeterminate value is written into the slot. Note 2: The first byte of a CAN frame’s data field corresponds to the data 0 of message slot n. The data is transmitted/received beginning with the register’s MSB side. 13-44 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 1 (C0MSL0DT1) s CAN0 Message Slot 1 Data 1 (C0MSL1DT1) s CAN0 Message Slot 2 Data 1 (C0MSL2DT1) s CAN0 Message Slot 3 Data 1 (C0MSL3DT1) s CAN0 Message Slot 4 Data 1 (C0MSL4DT1) s CAN0 Message Slot 5 Data 1 (C0MSL5DT1) s CAN0 Message Slot 6 Data 1 (C0MSL6DT1) s CAN0 Message Slot 7 Data 1 (C0MSL7DT1) s CAN0 Message Slot 8 Data 1 (C0MSL8DT1) s CAN0 Message Slot 9 Data 1 (C0MSL9DT1) s CAN0 Message Slot 10 Data 1 (C0MSL10DT1) s CAN0 Message Slot 11 Data 1 (C0MSL11DT1) s CAN0 Message Slot 12 Data 1 (C0MSL12DT1) s CAN0 Message Slot 13 Data 1 (C0MSL13DT1) s CAN0 Message Slot 14 Data 1 (C0MSL14DT1) s CAN0 Message Slot 15 Data 1 (C0MSL15DT1) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT1 D 8-15 Bit Name C0MSLnDT1 Function Message slot n data 1 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 1, an indeterminate value is written to this register. 13-45 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 2 (C0MSL0DT2) s CAN0 Message Slot 1 Data 2 (C0MSL1DT2) s CAN0 Message Slot 2 Data 2 (C0MSL2DT2) s CAN0 Message Slot 3 Data 2 (C0MSL3DT2) s CAN0 Message Slot 4 Data 2 (C0MSL4DT2) s CAN0 Message Slot 5 Data 2 (C0MSL5DT2) s CAN0 Message Slot 6 Data 2 (C0MSL6DT2) s CAN0 Message Slot 7 Data 2 (C0MSL7DT2) s CAN0 Message Slot 8 Data 2 (C0MSL8DT2) s CAN0 Message Slot 9 Data 2 (C0MSL9DT2) s CAN0 Message Slot 10 Data 2 (C0MSL10DT2) s CAN0 Message Slot 11 Data 2 (C0MSL11DT2) s CAN0 Message Slot 12 Data 2 (C0MSL12DT2) s CAN0 Message Slot 13 Data 2 (C0MSL13DT2) s CAN0 Message Slot 14 Data 2 (C0MSL14DT2) s CAN0 Message Slot 15 Data 2 (C0MSL15DT2) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT2 D 0-7 Bit Name C0MSLnDT2 Function Message slot n data 2 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 2, an indeterminate value is written to this register. 13-46 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 3 (C0MSL0DT3) s CAN0 Message Slot 1 Data 3 (C0MSL1DT3) s CAN0 Message Slot 2 Data 3 (C0MSL2DT3) s CAN0 Message Slot 3 Data 3 (C0MSL3DT3) s CAN0 Message Slot 4 Data 3 (C0MSL4DT3) s CAN0 Message Slot 5 Data 3 (C0MSL5DT3) s CAN0 Message Slot 6 Data 3 (C0MSL6DT3) s CAN0 Message Slot 7 Data 3 (C0MSL7DT3) s CAN0 Message Slot 8 Data 3 (C0MSL8DT3) s CAN0 Message Slot 9 Data 3 (C0MSL9DT3) s CAN0 Message Slot 10 Data 3 (C0MSL10DT3) s CAN0 Message Slot 11 Data 3 (C0MSL11DT3) s CAN0 Message Slot 12 Data 3 (C0MSL12DT3) s CAN0 Message Slot 13 Data 3 (C0MSL13DT3) s CAN0 Message Slot 14 Data 3 (C0MSL14DT3) s CAN0 Message Slot 15 Data 3 (C0MSL15DT3) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT3 D 8-15 Bit Name COMSLnDT3 Function Message slot n data 3 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 3, an indeterminate value is written to this register. 13-47 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 4 (C0MSL0DT4) s CAN0 Message Slot 1 Data 4 (C0MSL1DT4) s CAN0 Message Slot 2 Data 4 (C0MSL2DT4) s CAN0 Message Slot 3 Data 4 (C0MSL3DT4) s CAN0 Message Slot 4 Data 4 (C0MSL4DT4) s CAN0 Message Slot 5 Data 4 (C0MSL5DT4) s CAN0 Message Slot 6 Data 4 (C0MSL6DT4) s CAN0 Message Slot 7 Data 4 (C0MSL7DT4) s CAN0 Message Slot 8 Data 4 (C0MSL8DT4) s CAN0 Message Slot 9 Data 4 (C0MSL9DT4) s CAN0 Message Slot 10 Data 4 (C0MSL10DT4) s CAN0 Message Slot 11 Data 4 (C0MSL11DT4) s CAN0 Message Slot 12 Data 4 (C0MSL12DT4) s CAN0 Message Slot 13 Data 4 (C0MSL13DT4) s CAN0 Message Slot 14 Data 4 (C0MSL14DT4) s CAN0 Message Slot 15 Data 4 (C0MSL15DT4) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT4 D 0-7 Bit Name C0MSLnDT4 Function Message slot n data 4 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 4, an indeterminate value is written to this register. 13-48 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 5 (C0MSL0DT5) s CAN0 Message Slot 1 Data 5 (C0MSL1DT5) s CAN0 Message Slot 2 Data 5 (C0MSL2DT5) s CAN0 Message Slot 3 Data 5 (C0MSL3DT5) s CAN0 Message Slot 4 Data 5 (C0MSL4DT5) s CAN0 Message Slot 5 Data 5 (C0MSL5DT5) s CAN0 Message Slot 6 Data 5 (C0MSL6DT5) s CAN0 Message Slot 7 Data 5 (C0MSL7DT5) s CAN0 Message Slot 8 Data 5 (C0MSL8DT5) s CAN0 Message Slot 9 Data 5 (C0MSL9DT5) s CAN0 Message Slot 10 Data 5 (C0MSL10DT5) s CAN0 Message Slot 11 Data 5 (C0MSL11DT5) s CAN0 Message Slot 12 Data 5 (C0MSL12DT5) s CAN0 Message Slot 13 Data 5 (C0MSL13DT5) s CAN0 Message Slot 14 Data 5 (C0MSL14DT5) s CAN0 Message Slot 15 Data 5 (C0MSL15DT5) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT5 D 8-15 Bit Name C0MSLnDT5 Function Message slot n data 5 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 5, an indeterminate value is written to this register. 13-49 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 6 (C0MSL0DT6) s CAN0 Message Slot 1 Data 6 (C0MSL1DT6) s CAN0 Message Slot 2 Data 6 (C0MSL2DT6) s CAN0 Message Slot 3 Data 6 (C0MSL3DT6) s CAN0 Message Slot 4 Data 6 (C0MSL4DT6) s CAN0 Message Slot 5 Data 6 (C0MSL5DT6) s CAN0 Message Slot 6 Data 6 (C0MSL6DT6) s CAN0 Message Slot 7 Data 6 (C0MSL7DT6) s CAN0 Message Slot 8 Data 6 (C0MSL8DT6) s CAN0 Message Slot 9 Data 6 (C0MSL9DT6) s CAN0 Message Slot 10 Data 6 (C0MSL10DT6) s CAN0 Message Slot 11 Data 6 (C0MSL11DT6) s CAN0 Message Slot 12 Data 6 (C0MSL12DT6) s CAN0 Message Slot 13 Data 6 (C0MSL13DT6) s CAN0 Message Slot 14 Data 6 (C0MSL14DT6) s CAN0 Message Slot 15 Data 6 (C0MSL15DT6) D0 1 2 3 4 CAN MODULE 13.2 CAN Module Related Registers 5 6 D7 C0MSLnDT6 D 0-7 Bit Name C0MSLnDT6 Function Message slot n data 6 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 6, an indeterminate value is written to this register. 13-50 32170/32174 Group User's Manual (Rev. 2.1) 13 s CAN0 Message Slot 0 Data 7 (C0MSL0DT7) s CAN0 Message Slot 1 Data 7 (C0MSL1DT7) s CAN0 Message Slot 2 Data 7 (C0MSL2DT7) s CAN0 Message Slot 3 Data 7 (C0MSL3DT7) s CAN0 Message Slot 4 Data 7 (C0MSL4DT7) s CAN0 Message Slot 5 Data 7 (C0MSL5DT7) s CAN0 Message Slot 6 Data 7 (C0MSL6DT7) s CAN0 Message Slot 7 Data 7 (C0MSL7DT7) s CAN0 Message Slot 8 Data 7 (C0MSL8DT7) s CAN0 Message Slot 9 Data 7 (C0MSL9DT7) s CAN0 Message Slot 10 Data 7 (C0MSL10DT7) s CAN0 Message Slot 11 Data 7 (C0MSL11DT7) s CAN0 Message Slot 12 Data 7 (C0MSL12DT7) s CAN0 Message Slot 13 Data 7 (C0MSL13DT7) s CAN0 Message Slot 14 Data 7 (C0MSL14DT7) s CAN0 Message Slot 15 Data 7 (C0MSL15DT7) D8 9 10 11 12 CAN MODULE 13.2 CAN Module Related Registers 13 14 D15 C0MSLnDT7 D 0-7 Bit Name C0MSLnDT7 Function Message slot n data 7 R W These registers are the transmit frame/receive frame memory space. Note: F or receive slots, if when storing a data frame the data length (DLC value) = 7, an indeterminate value is written to this register. 13-51 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.2 CAN Module Related Registers s CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) s CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) s CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) s CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) s CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) s CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) s CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) s CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) s CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) s CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) s CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) s CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) s CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) s CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) s CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) s CAN0 Message Slot 15 Time Stamp (C0MSL15TSP) D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 C0MSLnTSP D 0-15 Bit Name C0MSLnTSP Function Message slot n time stamp R W These registers are the transmit frame/receive frame memory space. When the CAN module finishes transmitting or receiving, the CAN0 Time Stamp Count Register value is set in this register. 13-52 32170/32174 Group User's Manual (Rev. 2.1) 13 13.3 CAN Protocol 13.3.1 CAN Protocol Frame There are four types of frames which are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each another by an interframe space. CAN MODULE 13.3 CAN Protocol Data frame Standard format 1 11 1 6 0-64 16 2 7 Extended format 1 SOF 11 1 1 18 1 6 0-64 16 2 7 EOF Arbitration field CRC field Data field Control field ACK field Remote frame Standard format 1 11 1 6 16 2 7 Extended format 1 SOF 11 1 1 18 1 6 16 2 7 EOF Arbitration field ACK field CRC field Control field Numbers in each field denote the number of bits. Figure 13.3.1 CAN Protocol Frames (1) 13-53 32170/32174 Group User's Manual (Rev. 2.1) 13 Error frame 6-12 Error flag 8 Error delimiter CAN MODULE 13.3 CAN Protocol Interframe space or overload flag Overload frame 6-12 Overload flag Overload delimiter 8 Interframe space or overload flag Interframe space In an error-active state 3 0SOF SOF of next frame Bus idle Intermission In an error-passive state 3 8 0SOF SOF of next frame Bus idle Suspend transmission Intermission Numbers in each field denote the number of bits. Figure 13.3.2 CAN Protocol Frames (2) 13-54 32170/32174 Group User's Manual (Rev. 2.1) 13 Initial settings CAN MODULE 13.3 CAN Protocol Error-active state Transmit error counter ≥ 128 or Receive error counter ≥ 128 Transmit error counter < 128 and Receive error counter < 128 11 consecutive recessive bits detected on CAN bus 128 times or reset by software Error-passive state Transmit error counter > 255 Bus-off state Figure 13.3.3 CAN Control Error States The CAN controller assumes one of the following three error states depending on the transmit error and receive error counter values. (1) Error-active state • This is a state where almost no errors have occurred. • When an error is detected, an active error flag is transmitted. • Immediately after being initialized, the CAN controller is in this state. (2) Error-passive state • This is a state where many errors have occurred. • When an error is detected, a passive error flag is transmitted. (3) Bus-off state • This is a state where a large number of errors have occurred. • CAN communication with other nodes cannot be performed until the CAN module returns to an error-active state. Error status of the unit Error-active state Error-passive state Bus-off state Transmit error counter 0-127 128-255 256and or Receive error counter 0-127 128- 13-55 32170/32174 Group User's Manual (Rev. 2.1) 13 13.4 Initializing the CAN Module 13.4.1 Initialization of the CAN Module CAN MODULE 13.4 Initializing the CAN Module Before you perform communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output ports, so be sure to select the functions of these pins. (Refer to Chapter 8, "Input/ Output Ports and Pin Functions." (2) Setting the interrupt controller (ICU) When you use CAN module interrupts, set the interrupt priority. (3) Setting CAN Error Interrupt Mask and CAN Slot Interrupt Mask Registers When you use CAN bus error interrupts, CAN error passive interrupts, CAN error bus-off interrupts, or CAN slot interrupts, set each corresponding bit to 1 to enable interrupt requests. (4) Setting bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of times the CAN bus is sampled. (a) Setting the bit timing Determine the period Tq that is the base of bit timing, the configuration of Propagation Segment, Phase Segment1, and Phase Segment2, and reSynchronization Jump Width. The equation to calculate Tq is shown below. Tq = (CANBRP+1) /CPU clock The baud rate is determined by the number of Tq's that comprise one bit. The equation to calculate the baud rate is shown below. Baud rate (bps) = 1 Tq period × number of Tq's for 1 bit Number of Tq's for 1 bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 13-56 32170/32174 Group User's Manual (Rev. 2.1) 13 1 Bit Rate Synchronization Segment CAN MODULE 13.4 Initializing the CAN Module Propagation Segment Phase Segment1 Phase Segment2 1Tq (3) (2) (1) Sampling Point • • • Shown in this diagram is the bit timing for cases where one bit consists of 8 Tq's. When one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit. When three-time sampling is selected, the value of the bit is determined by majority from CAN bus values sampled at Sampling Points (1), (2), and (3). Figure 13.4.1 Example of Bit Timing (b) Setting the number of times sampled Select the number of times the CAN bus is sampled from "one time" and "three times." • When you select one-time sampling, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. • When you select three-time sampling, the value of the bit is determined by majority from values sampled at three points, i.e., the value sampled at the first point and those sampled one Tq before and two Tq's before that. (5) Setting ID Mask Registers Set the values of ID Mask Registers (Global Mask Register, Local Mask Register A, and Local Mask Register B) which are used in acceptance filtering of received messages. (6) Settings when running in BasicCAN mode • Set the CAN Extended ID Register IDE14 and IDE15 bits. (We recommend setting the same value in these bits.) • Set IDs for message slots 14 and 15. • Set the Message Control Registers 14 and 15 for data frame reception (H'40). (7) Setting CAN module operation mode Using the CAN Control Register (CAN0CNT), select the CAN module's operation mode (BasicCAN or loopback mode) and the clock source for the time stamp counter. (8) Releasing the CAN module from reset After you finished settings (1) through (7) above, clear the CAN Control Register (CAN0CNT)'s forcible reset bit (FRST) and reset bit (RST) to 0. Then, after detecting 11 consecutive "recessive" bits on the CAN bus, the CAN module becomes ready to communicate. 13-57 32170/32174 Group User's Manual (Rev. 2.1) 13 Initialize CAN module CAN MODULE 13.4 Initializing the CAN Module Set Input/output Port Operation Mode Register Set Interrupt Controller Set interrupt priority Set CAN Error Interrupt Mask Register Enable/disable CAN bus error interrupt Set CAN Slot Interrupt Mask Register Enable/disable interrupt to be generated at completion of transmission or reception in the slot Set CAN Related Interrupt Mask Register Enable/disable CAN error passive interrupt Enable/disable CAN bus off interrupt Set CAN Configuration Register Set bit timing (baud rate) Set the number of times sampled Set ID Mask Register Set ID mask bit Set loopback mode Set CAN operation mode Set BasicCAN mode Set CAN Extended IDRegister Set IDs for message slots 14 and 15 Set Message Slot Control Register Negate CAN reset Release CAN module from reset CAN module initialization completed Figure 13.4.2 Initializing the CAN Module 13-58 32170/32174 Group User's Manual (Rev. 2.1) 13 13.4.2 CAN Timing CAN MODULE 13.4 Initializing the CAN Module In the M32R/ECU CAN, CRX asynchronous input signals are sampled with Tq clock cycles (= base clock). The sampled signal is assumed to be the CAN bus value, with which CAN operation is controlled. Operation timing is shown below. 1Tq Internal Tq signal CRX pin Drift of up to 1 Tq Internal CRX signal Figure 13.4.3 Operation Timing 13-59 32170/32174 Group User's Manual (Rev. 2.1) 13 13.5 Transmitting Data Frames 13.5.1 Data Frame Transmit Procedure CAN MODULE 13.5 Transmitting Data Frames The following describes the procedure for transmitting data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit data Set the transmit ID and transmit data in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the data as a standard frame or 1 when you want to transmit the data as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'80 (note) to the CAN Message Slot Control Register to set the TR (Transmit Request) bit to 1. Note: When you are transmitting a data frame, always write H'80 to this register. 13-60 32170/32174 Group User's Manual (Rev. 2.1) 13 Data frame transmit procedure CAN MODULE 13.5 Transmitting Data Frames Initialize CAN Message Slot Control Register Write H’00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that transmission is idle YES Set ID and data in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H’80 (transmit request) Settings completed Figure 13.5.1 Data Frame Transmit Procedure 13-61 32170/32174 Group User's Manual (Rev. 2.1) 13 13.5.2 Data Frame Transmit Operation CAN MODULE 13.5 Transmitting Data Frames The following describes data frame transmit operation. The operations described below are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (2) Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (3) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (4) Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 13-62 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.5 Transmitting Data Frames B’0000 0000 (Note) Write H’80 d Transmit aborted n rre io u d at cc te tr bi r o ep Waiting for cc ar ro ta s er B’1000 0000 transmission es bu us qu ted t e os N b it r bor LA sm it a C an Tr ansm Transmit request Lost bus arbitration Tr accepted CAN bus error occurred B’0000 0010 Transmit aborted B’1000 0010 d rte ed bo let it a omp m ns it c Tra ansm Tr B’0000 0001 (Note) Transmit completed B’1000 0001 Note: When in this state, data can be written to the message slot. Figure 13.5.2 Operation of the CAN Message Slot Control Register when Transmitting Data Frames 13.5.3 Transmit Abort Function The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by writing H'0F to the CAN Message Slot Control Register for the slot concerned. When transmit abort is accepted, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0, allowing for data to be written to the message slot. The following shows conditions under which transmit abort is accepted: [Conditions] • When the target message is waiting for transmission • When a CAN bus error occurs during transmission • When the CAN module lost bus arbitration 13-63 32170/32174 Group User's Manual (Rev. 2.1) 13 13.6 Receiving Data Frames 13.6.1 Data Frame Receive Procedure The following describes the procedure for receiving data frames. (1) Initializing the CAN Message Slot Control Register CAN MODULE 13.6 Receiving Data Frames Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register Write H'40 to the CAN Message Slot Control Register to set the RR (Receive Request) bit to 1. 13-64 32170/32174 Group User's Manual (Rev. 2.1) 13 Data frame receive procedure CAN MODULE 13.6 Receiving Data Frames Initialize CAN Message Slot Control Register Write H’00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that reception is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H’40 (receive request) Settings completed Figure 13.6.1 Data Frame Receive Procedure 13-65 32170/32174 Group User's Manual (Rev. 2.1) 13 13.6.2 Data Frame Receive Operation CAN MODULE 13.6 Receiving Data Frames The following describes data frame receive operation. The operations described below are automatically performed in hardware. (1) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions] • The receive frame is a data frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bits." • The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 while being set for data frame reception can also receive remote frames. (2) When receive conditions are met When receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. (3) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. 13-66 32170/32174 Group User's Manual (Rev. 2.1) 13 B’0000 0000 CAN MODULE 13.6 Receiving Data Frames Receive request set Clear receive request Wait for receive data a t a st d d ue ive req e ec ive e r ce tor r re S ea Cl B’0100 0000 Store received data CPU read CPU read Clear receive request B’0000 0011 e eiv ec g r st rin eque sto r ed ive ish ece Fin ear r Clear receive Cl a dd ta B’0100 0011 Finished storing received data Finished storing received data B’0000 0001 request ata st dd e ve requ ei ec ve e r cei tor r re S ea Cl Clear receive request ata dd ive ce t e g r s Finished rin que sto re received ed eive ish ec Fin ear r l Clear receive C B’0100 0001 Store received data B’0000 0111 B’0100 0111 Finished storing received data storing data B’0000 0101 request Store received data Wait for receive data B’0100 0101 Figure 13.6.2 Operation of the CAN Message Slot Control Register when Receiving Data Frames 13-67 32170/32174 Group User's Manual (Rev. 2.1) 13 13.6.3 Reading Out Received Data Frames CAN MODULE 13.6 Receiving Data Frames The following describes the procedure for reading out received data frames from the slot. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'4E, H'40 or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to C0MSLnCNT H'4E H'40 H'00 Slot operation after write Operates as a data frame receive slot. Overwrite can be verified by ML bit. Operates as a data frame receive slot. Overwrite cannot be verified by ML bit. The slot stops transmit/receive operation. Note 1: If message-lost check by the ML bit is needed, write H'4E to the C0MSLnCNT register as you clear the TRFIN bit. Note 2: If you clear the TRFIN bit by writing H'4E, H'40 or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. (a) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). (b) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. 13-68 32170/32174 Group User's Manual (Rev. 2.1) 13 Reading out received data CAN MODULE 13.6 Receiving Data Frames Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register NO TRFIN bit = 0 YES Finished reading out received data Figure 13.6.3 Procedure for Reading Out Received Data 13-69 32170/32174 Group User's Manual (Rev. 2.1) 13 13.7 Transmitting Remote Frames 13.7.1 Remote Frame Transmit Procedure CAN MODULE 13.7 Transmitting Remote Frames The following describes the procedure for transmitting remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit ID Set the ID to be transmitted in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the frame as a standard frame or 1 when you want to transmit the frame as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'A0 to the CAN Message Slot Control Register to set the TR (Transmit Request) and RM (Remote) bits to 1. 13-70 32170/32174 Group User's Manual (Rev. 2.1) 13 Remote frame transmit procedure CAN MODULE 13.7 Transmitting Remote Frames Initialize CAN Message Slot Control Register Write H’00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that transmission is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H’A0 (transmit request, remote) Settings completed Figure 13.7.1 Remote Frame Transmit Procedure 13-71 32170/32174 Group User's Manual (Rev. 2.1) 13 13.7.2 Remote Frame Transmit Operation CAN MODULE 13.7 Transmitting Remote Frames The following describes remote frame transmit operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit At the same time H'A0 (Transmit Request, Remote) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Selecting a transmit frame The CAN module checks slots which have transmit requests (including data frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (3) Transmitting a remote frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (4) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (5) Completion of remote frame transmission When remote frame transmission is completed, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP) and the CAN Message Slot Control Register's RA (Remote Active) bit is cleared to 0. Also, the CAN Slot Interrupt Status bit is set to 1 by completion of transmission, but the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit is not set to 1. If the CAN slot interrupt has been enabled, an interrupt request is generated upon completion of transmission. (6) Receiving a data frame When remote frame transmission is completed, the slot automatically starts functioning as a data frame receive slot. (7) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). 13-72 32170/32174 Group User's Manual (Rev. 2.1) 13 [Conditions] CAN MODULE 13.7 Transmitting Remote Frames The following shows receive conditions for slots that have been set for data frame reception. • The receive frame is a data frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit." • The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 cannot be used as transmit slots. (8) When receive conditions are met When receive conditions in (7) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. Note: If the CAN module received a data frame before transmitting a remote frame, it stores the data frame in the slot and does not transmit the data frame. (9) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. 13-73 32170/32174 Group User's Manual (Rev. 2.1) 13 B’0000 0000 CAN MODULE 13.7 Transmitting Remote Frames B’0000 1000 CAN bus error occurs B’0000 1010 Finished transmitting remote frame B’0000 0000 B’1010 1000 Store received data B’1010 1011 Finished storing received data Clear transmit request B’0000 1011 Finished storing received data B’0000 0001 Clear transmit request B’1010 1010 n tio tra rbi sa bu st us s Lo N b ccur mit CA or o rans err ear t t Cl ues req Finished transmitting remote frame Wait for receive data B’1010 0000 Store received data Store received data Clear receive request B’0000 0011 B’1010 0011 g rin st sto ue ed ata eq sh ed d ive r i Fin eiv ece rec ear r Cl Finished storing received data B’0000 0001 B’1010 0001 Store received data Store received data Clear receive request B’0000 0111 Finished storing received data B’0000 0101 g rin sto ed ata ish ed d ive Fin eiv ece rec ear r t Cl ues req B’1010 0111 Finished storing received data Store received data Wait for receive data CPU read B’1010 0101 Figure 13.7.2 Operation of the CAN Message Slot Control Register when Transmitting Remote Frames 13-74 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.7 Transmitting Remote Frames 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission The following describes the procedure for reading out received data frames from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'AE or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to C0MSLnCNT H'AE H'00 Slot operation after write Operates as a data frame receive slot. Overwrite can be verified by ML bit. The slot stops transmit/receive operation. Note 1: If message-lost check by the ML bit is needed, write H'AE to the C0MSLnCNT register as you clear the TRFIN bit. Note 2: If you clear the TRFIN bit by writing H'AE or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. Note 3: The received data frame cannot be read out by writing H'A0 to the register. If you clear the TRFIN bit by writing H'A0, the slot performs remote frame transmit operation. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. (a) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). (b) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. 13-75 32170/32174 Group User's Manual (Rev. 2.1) 13 CAN MODULE 13.7 Transmitting Remote Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register NO TRFIN bit = 0 YES Finished reading out received data Figure 13.7.3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission 13-76 32170/32174 Group User's Manual (Rev. 2.1) 13 13.8 Receiving Remote Frames 13.8.1 Remote Frame Receive Procedure CAN MODULE 13.8 Receiving Remote Frames The following describes the procedure for receiving remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register (a) When automatic response (data frame transmission) for remote frame reception is desired Write H'60 to the CAN Message Slot Control Register to set the RR (Receive Request) and RM (Remote) bits to 1. (b) When automatic response (data frame transmission) for remote frame reception is not needed Write H'70 to the CAN Message Slot Control Register to set the RR (Receive Request), RM (Remote), and RL (Automatic Response Enable) bits to 1. Note: In BasicCAN mode, slots 14 and 15, although capable of receiving remote frames, cannot automatically respond to remote frame reception. 13-77 32170/32174 Group User's Manual (Rev. 2.1) 13 Remote frame reception procedure CAN MODULE 13.8 Receiving Remote Frames Initialize CAN Message Slot Control Register Write H’00 Read CAN Message Slot Control Register NO TRSTAT bit = 0 Verify that reception is idle YES Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Slot Control Register Write H’60 (receive request, remote, automatic response enable) Write H’70 (receive request, remote, automatic response disable) Settings completed Figure 13.8.1 Remote Frame Receive Procedure 13-78 32170/32174 Group User's Manual (Rev. 2.1) 13 13.8.2 Remote Frame Receive Operation CAN MODULE 13.8 Receiving Remote Frames The following describes remote frame receive operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit When H'60 (Transmit Request, Remote) or H'70 (Transmit Request, Remote, Automatic Response Disable) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions] • The receive frame is a remote frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit." • The standard and extended frame types are the same. (3) When receive conditions are met When receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated. Note 1: The ID field and DLC value are written to the message slot. Note 2: When receiving standard format frames, an indeterminate value is written to the extended ID area. Note 3: The data field is not accessed for write. Note 4: The RA and TRFIN bits are cleared to 0 after writing the remote frame received data. (4) When receive conditions are not met The received frame is discarded, and the CAN module waits for the next receive frame. No data is written to the message slot. 13-79 32170/32174 Group User's Manual (Rev. 2.1) 13 (5) Operation after receiving a remote frame CAN MODULE 13.8 Receiving Remote Frames The operation performed after receiving a remote frame differs depending on how automatic response is set. (a) When automatic response is disabled The slot which finished receiving goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. (b) When automatic response is enabled After receiving a remote frame, the slot automatically changes to a data frame transmit slot and performs the transmit operation described below. In this case, the transmitted data conforms to the ID and DLC of the received remote frame. • Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. • Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. • If the CAN module failed to gain control of the bus or a CAN bus error occurs If the CAN module failed to gain control of the bus or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. • Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 13-80 32170/32174 Group User's Manual (Rev. 2.1) 13 B’0000 0000 Write H’60 (automatic response enable) Wait for receive data B’0110 1000 Clear receive request CAN MODULE 13.8 Receiving Remote Frames Write H’70 (automatic response enable) B’0111 1000 Store received data Clear receive request Store Store received data received data B’0111 1011 B’0000 1010 Finished storing received data B’0000 0000 Finished storing received data Clear receive request B’0000 0010 Finished transmitting data frame B’0000 0001 B’0110 1011 Finished Finished storing received storing data received data B’0110 0000 Transmit data frame B’0111 0000 Store received data Clear receive request B’0000 Fi da nishe ds Cle ta tor ar ing rec rec eiv eiv er ed eq ue st 1010 B’0000 0000 Transmit data frame Clear receive request B’0110 0010 Finished transmitting data frame B’0110 0001 Figure 13.8.2 Operation of the CAN Message Slot Control Register when Receiving Remote Frames 13-81 32170/32174 Group User's Manual (Rev. 2.1) 13 13.9 Precautions about CAN Module CAN MODULE 13.9 Precautions about CAN Module • Note for cancelation of transmit and receive CAN remote frame When aborting remote frame transmission or canceling remote frame receiving, make sure that the RA (Remote Active) bit is cleared to 0 after writing "H'00" or "H'0F" to the CAN Message Slot Control Register. (1) When aborting remote frame transmission Start transmission abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register No RA (Remote Active) bit = "0" Yes Complete transmission abort Note 1: H'00 or H'0F can be used. Figure 13.9.1 Opertion Flow when Aborting Remote Frame Transmission (1) When canceling remote frame receiving Start receiving abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register No RA (Remote Active) bit = "0" Yes Complete receiving abort Note 1: H'00 or H'0F can be used. Figure 13.9.2 Opertion Flow when Canceling Remote Frame Receiving 13-82 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.2 Pin Function of the RTD 14.3 Functional Description of the RTD 14.4 Typical Connection with the Host 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.1 Outline of the Real-Time Debugger (RTD) The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU. Table 14.1.1 Outline of the Real-Time Debugger (RTD) Item Transfer method Generation of transfer clock RAM access area Transmit/receive data length Bit transfer sequence Maximum transfer rate Input/output pins Number of commands Content Clock-synchronized serial I/O Generated by external host Entire area of internal RAM (controlled by A16-A29) 32 bits (fixed) LSB first 2 Mbits/second 4 lines (RTDTXD, RTDRXD, RTDACK, RTDCLK) Following five functions • Monitors continuously • Outputs real-time RAM contents • Forcibly rewrites RAM contents (with verify) • Recovers from runaway • Requests RTD interrupt RTD control circuit Entire RAM area CPU Control circuit RTDCLK Address Data Address Data Address Data Command RTDACK RTDTXD Data RTDRXD Bus switching circuit Figure 14.1.1 Block Diagram of the Real-Time Debugger (RTD) 14-2 32170/32174 Group User's Manual (Rev. 2.1) 14 14.2 Pin Function of the RTD Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name RTDTXD RTDRXD RTDACK Type Output Input Output Function RTD serial data output RTD serial data input REAL-TIME DEBUGGER (RTD) 14.2 Pin Function of the RTD Outputs a low-level pulse synchronously with the beginning clock edge of the output data word. The width of the low-level pulse thus output indicates the type of instruction/data that the RTD received. 1 clock period 1 clock period 2 clock periods 3 clock periods : VER (continuous monitor) command : VEI (RTD interrupt request) command : RDR (real-time RAM content output) command : WRR (RAM content forcible rewrite) command or the data to rewrite 4 clock periods or more : RCV (recover from runaway) command RTDCLK Input RTD transfer clock input 14-3 32170/32174 Group User's Manual (Rev. 2.1) 14 14.3 Functional Description of the RTD 14.3.1 Outline of RTD Operation REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19(note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data b19 b18 b17 b16 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 VEI (VErify Interrupt request) RDR (ReaD RAM) WRR (WRite RAM) RCV (ReCoVer) System reserved (use inhibited) RTD interrupt request Real-time RAM content output RAM content forcibly rewrite (with verify) Recover from runaway (Note 2, Note 3) VER (VERify) Continuous monitor Command Mnemonic RTD Function ↑ (Note 1) Note 1 : Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command, is handled as "Don't Care" bit. (Bits 16-18 are effective for the command specified.) Note 2 : The RCV command must always be transmitted twice in succession. Note 3 : For the RCV command, all bits, not just bits 16-19, (i.e., bits 0-15 and bits 20-31) must be set to 1. 14-4 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.2 Operation of RDR (Real-time RAM Content Output) When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop. Because the RTD reads data from the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device. (LSB side) 31 RTDRXD X 20 19 18 17 16 15 14 13 12 X 0 0 1 0 X X A29 A28 (MSB side) 1 0 A17 A16 Command (RDR) Specified address Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.1 RDR Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) RDR (A2) RDR (A3) RTDTXD D (A1) D (A2) RTDACK 2 clock periods Note: (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.2 Operation of the RDR Command 14-5 32170/32174 Group User's Manual (Rev. 2.1) 14 (LSB side) 31 30 D31 D30 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD (MSB side) 1 0 RTDTXD D1 D0 Read data (Note) Note: The read data is transferred LSB-first. Figure 14.3.3 Read Data Transfer Format 14-6 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are written to the internal RAM in units of 32 bits. The external host should transmit the command and address in the first frame and then the write data in the second frame. The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data. a) First frame (LSB side) 31 RTDRXD X 20 19 18 17 16 15 14 13 12 X 0 0 1 1 X X A29 A28 (MSB side) 1 0 A17 A16 Command (WRR) Specified address b) Second frame (LSB side) 31 30 RTDRXD D31 D30 (MSB side) 1 0 D1 D0 Write data (Note) Note 1: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 2: The specified address and write data are transferred LSB-first. Figure 14.3.4 WRR Command Data Format 14-7 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD WRR (A1) (A1) Write data WRR (A2) (A2) Write data RTDTXD RTDACK 3 clock periods D (A1) Read value before write D (A1) Verify value after write Note: (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.5 Operation of the WRR Command 14-8 32170/32174 Group User's Manual (Rev. 2.1) 14 14.3.4 Operation of VER (Continuous Monitor) REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command. (LSB side) 31 RTDRXD X 20 19 18 17 16 15 X 0 0 0 0 X (MSB side) 0 X Command (VER) Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.6 VER (Continuous Monitor) Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) (Note 1) VER VER RTDTXD RTDACK 2 clock periods D (A1) Read value (Note 2) D (A1) Latest read value Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.7 Operation of the VER (Continuous Monitor) Command 14-9 32170/32174 Group User's Manual (Rev. 2.1) 14 14.3.5 Operation of VEI (Interrupt Request) REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command. (LSB side) 31 RTDRXD X (Note) (MSB side) 20 19 18 17 16 15 X 0 1 1 0 X (Note) 0 X VEI (interrupt request generation) command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Figure 14.3.8 VEI (Interrupt Request) Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR (A1) (Note 1) VEI RTDTXD RTDACK 2 clock periods D (A1) Read value (Note 2) RTD interrupt request D (A1) Read value (Note 2) RTD interrupt Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.9 Operation of the VEI (Interrupt Request) Command 14-10 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.6 Operation of RCV (Recover from Runaway) When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession. Also, any command issued subsequently after the RCV command must have its bits 20-31 all set to 1. (LSB side) 31 RTDRXD 1 (Note) (MSB side) 20 19 18 17 16 15 1 1 1 1 1 1 (Note) 0 1 Command (RCV) Note: All of 32 data bits are 1's. The RCV command must always be issued twice in succession. Figure 14.3.10 RCV Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods Bits 20-31 RTDRXD RCV RCV 1 1 RDR (A1) Next command following the RCV command RTDTXD Indeterminate data during runway condition D (A1) RTDACK Indeterminate value during runway condition 2 clock periods 2 clock periods RCV command stored here Note: The next command following the RCV command must have its bits 20-31 all set to 1. Figure 14.3.11 Operation of the RCV Command 14-11 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.7 Method to Set a Specified Address when Using the RTD When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses of that area. However, access to any locations other than the area where the RAM resides is inhibited. Note also that two least significant address bits, A31 and A30, are always 0's because data are read and written to the internal RAM in a fixed length of 32 bits. Memory map X X A29 - A16 H’0080 0000 SFR 16KB H’0080 4000 H’0080 4000~H’0080 FFFF only can be specified RAM area H’0080 FFFF Figure 14.3.12 Method for Setting Addresses in Real-Time Debugger 14-12 32170/32174 Group User's Manual (Rev. 2.1) 14 14.3.8 Resetting the RTD REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after System Reset Pin Name RTDACK RTDTXD State High-level output High-level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK. 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RESET System reset RTDRXD Don’t Care RDR (A1) RDR (A2) RTDTXD "H" 0000 0000 0000 0000 D (A1) D (A2) RTDACK "H" Note: (An) = Specified address D (An) = Data at specified address (An) Figure 14.3.13 Command Transfer to the RTD after System Reset 14-13 32170/32174 Group User's Manual (Rev. 2.1) 14 14.4 Typical Connection with the Host REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. M32R/ECU Host microprocessor RTDCLK RTDRXD RTDTXD RTDACK (Note) SCLK RXD TXD PORT Note: In this example, the RTDACK level is checked between transfer frames. Figure 14.4.1 Connecting the RTD and Host 14-14 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally. After transmitting a command, the RTDACK signal is pulled low, making it possible to verify the communication status. When issuing the VER command, the RTDACK signal goes low for only one clock period. Therefore, after sending 32 bits in one frame, turn off RTDCLK output and check whether RTDACK is low. If RTDACK is low, you know that the RTD is communicating normally. If you want to identify the type of transmitted command by the width of RTDACK, use the 32170's internal measurement timer (to count RTDCLK pulses while RTDACK is low) or create a dedicated circuit. Transfer of next frame Transfer of 1 frame (32 bits) 1 RTDCLK 2 RTDRXD (8 bits) (8 bits) (8 bits) RTDTXD RTDACK Check the RTDACK signal L level. Figure 14.4.2 Typical Operation for Communication with the Host (when Issuing VER Command) 14-15 32170/32174 Group User's Manual (Rev. 2.1) 14 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host * This is a blank page.* 14-16 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.2 Read/Write Operations 15.3 Bus Arbitration 15.4 Typical Connection of External Extension Memory 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.1 External Bus Interface Related Signals The 32170 comes with external bus interface related signals shown below. These signals can be used in external extension mode or processor mode. (1) Address The 32170 outputs a 20-bit address (A11-A30) for addressing any location in 2 Mbytes ___ of space. The least significant A31 is not output, and in external write cycles, the 32170 outputs BHW and ___ BLW signals to indicate the valid byte position at which to write on the 16-bit data bus. In read cycles, the 32170 reads data always in 16 bits, transferring only the data read from the valid byte position of the bus. ___ ___ (2) Chip select (CS0, CS1) ___ ___ These signals are output in external extension mode or processor mode, with CS0 and CS1 ___ specifying an extended external area of 2 Mbytes each. The CS0 signal points to a 2-Mbyte area in processor mode or a 1-Mbyte area in external extension mode. (For details, refer to Chapter 3, "Address Space.") __ (3) Read strobe (RD) Output during external read cycle, this signal indicates the timing at which to read data from the bus. This signal is driven high when writing to the bus or accessing the internal function. ___ ___ (4) Byte High Write/Byte High Enable (BHW / BHE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte High Write (BHW), during external write access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. During external read and when accessing the internal function it outputs a high. ___ When BUSMOD = 1 and this signal is Byte High Enable (BHE), during external access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high. ___ ___ (5) Byte Low Write/Byte Low Enable (BLW / BLE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte Low Write (BLW), during external write access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. During external read cycle, it outputs a high. ___ When BUSMOD = 1 and this signal is Byte Low Enable (BLE), during external access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high. 15-2 32170/32174 Group User's Manual (Rev. 2.1) 15 (6) Data bus (DB0 - DB15) EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals This is the 16-bit data bus used to access external devices. __ (7) System clock/write (BCLK / WR) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = 0 and this signal is System Clock (BCLK), it outputs the system clock necessary to synchronize operations in an external system. When the CPU clock = 40 MHz, a 20 MHz clock is output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by setting the P7 Operation Mode Register P70MOD bit to 0. __ When BUSMOD = 1 and this signal is Write (WR), during external write access it indicates the valid data on the data bus to transfer. During external read cycle and when accessing the internal function, it outputs a high. ____ (8) Wait (WAIT) ____ When the 32170 started an external bus cycle, it automatically inserts wait cycles while the WAIT signal is asserted. For details, refer to Chapter 16, "Wait Controller." When not using the WAIT function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. Note that the 32170 always inserts one or more wait cycles for external access. Therefore, the shortest time in which an external device can be accessed is one wait cycle (2 BCLK periods). ____ ____ (9) Hold control (HREQ, HACK) The hold state refers to a state in which the 32170 has stopped bus access and bus interface related pins are tristated (high impedance). While the 32170 is in a hold state, any bus master external to the chip can use the system bus to transfer data. ____ The 32170 is placed in a hold state by pulling the HREQ pin input low. While the 32170 remains in ____ a hold state after accepting the hold request and during a transition to the hold state, the HACK pin outputs a low-level signal. To exit from the hold state and return to normal operating state, release ____ the HREQ signal back high. When not using the HREQ and HACK functions, these pins can be used as P72 and P7 by setting the P73 Operation Mode Register P72MOD and P73MOD bits to 0. The status of each 32170 pin during hold are shown below. Table 15.1.1 Pin State during Hold Period Pin Name ___ ___ __ ___ ___ ___ ___ __ A11-A30, DB0-DB15, CS0, CS1, RD, BHW, BLW, BHE, BLE, WR ____ HACK Other pins (e.g., ports and timer output) Pin State or Operation High impedance Outputs a low Normal operation 15-3 32170/32174 Group User's Manual (Rev. 2.1) 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (10) Port P7 Operation Mode Register (P7MOD) ____ ____ ____ The WAIT, HREQ, and HACK pins are shared with P71, P72, and P73, respectively. The Port P7 Operation Mode Register is used to select the function of port P7. Configuration of this register is shown below. s P7 Operation Mode Register D8 9 10 11 12 13 D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 __ 1 : BCLK / WR 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK R W 15-4 32170/32174 Group User's Manual (Rev. 2.1) 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (11) Bus Mode Control Register (BUSMODC) The 32170 contains a function to switch between two external bus modes. s Bus Mode Control Register (BUSMODC) D8 9 10 11 12 13 D 8 - 15 15 Bit Name No functions assigned BUSMOD (Bus mode control) 0: WR signal separate mode 1: Byte enable separate mode Function R 0 W — This register is used to facilitate memory connection in processor mode and external extension mode. When Bus Mode Control Register (BUSMOD) = 0, the WR signal is output separately for each byte __ ___ ___ ____ ____ area. Signals RD, BHW, BLW, BCLK, and WAIT can be used. For memory connection in boot mode, the Bus Mode Control Register has no effect and the interface operates under conditions where Bus Mode Control Register (BUSMOD) = 0. When Bus Mode Control __ ___(BUSMOD) = 1, the byte enable signal is output separately for Register ___ __ ____ each byte area. Signals RD, BHW, BLE, WR, and WAIT can be used. For WAIT control circuit configuration, because BCLK is not output, external timing control is required. BUSMOD = 0 A11 - A30 CS0, CS1 BCLK RD BHW BLW DB0 - DB15 WAIT BUSMOD = 1 A11 - A30 CS0, CS1 RD WR BHE BLE DB0 - DB15 WAIT Figure 15.1.1 Pin Function when Bus Modes are Changed 15-5 32170/32174 Group User's Manual (Rev. 2.1) 15 15.2 Read/Write Operations (1) When Bus Mode Control Register = 0 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. In external read cycle, the RD signal is low while BHW and BLW both are high, reading data from only the valid byte position of the bus. In external write cycle, BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low. ____ Unless the WAIT signal is needed, leave it held high. During external bus cycles, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 "H" Hi-z WAIT "H" Note: THi-Z denotes a high-impedance state. Figure 15.2.1 Internal Bus Access during Bus Free State 15-6 32170/32174 Group User's Manual (Rev. 2.1) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" Note: Circles above indicate points at which signals are sampled. Figure 15.2.2 Read/Write Timing (for Shortest-case External Access) 15-7 32170/32174 Group User's Manual (Rev. 2.1) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (4 cycles) 2 internal wait cycles BCLK 1 external wait cycle A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" Write Write (4 cycles) 2 internal wait cycles BCLK 1 external wait cycle A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" Note: Circles above indicate points at which signals are sampled. Figure 15.2.3 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) 15-8 32170/32174 Group User's Manual (Rev. 2.1) 15 (2) When Bus Mode Control Register = 1 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations ___ External ___ ___ ____ ___ __read/write operations are performed using the address bus, data bus, and signals CS0, __ __ ___ CS1, ___ RD, BHE, BLE, WAIT, and WR. In external read cycle, the RD signal goes low and BHE or BLE output for the byte position from which to __ is pulled low, reading data ___ only the byte read ___ from position of the bus. In external write cycle, the WR signal goes low and BHE or BLE output for the byte position to which to write is pulled low, writing data to the necessary byte position. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low. ____ Unless the WAIT signal is needed, leave it held high. During external bus cycle, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) When not using the WAIT function, the pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 RD "H" WR "H" BHE, BLE DB0 - DB15 "H" Hi-z WAIT "H" Note 1: Hi-Z denotes a high-impedance state. Note 2: BCLK is not output. Figure 15.2.4 Internal Bus Access during Bus Free State 15-9 32170/32174 Group User's Manual (Rev. 2.1) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 15.2.5 Read/Write Timing (for Shortest-case External Access) 15-10 32170/32174 Group User's Manual (Rev. 2.1) 15 Read EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read (4 cycles) 2 internal wait cycles BCLK 1 external wait cycle A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" "L" Write Write (4 cycles) 2 internal wait cycles BCLK 1 external wait cycle A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) "L" Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 15.2.6 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) 15-11 32170/32174 Group User's Manual (Rev. 2.1) 15 15.3 Bus Arbitration (1) When Bus Mode Control Register = 0 EXTERNAL BUS INTERFACE 15.3 Bus Arbitration ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the highimpedance state, allowing data to be transferred on the system bus. To exit the hold state and ____ return to normal operating state, release the HREQ signal back high. Bus cycle Idle Go to hold Hold state Return Next bus cycle BCLK HREQ HACK A11 - A30 CS0 , CS1 Hi-Z RD BHW , BLW DB0 - DB15 Hi-Z Hi-Z Hi-Z WAIT Note 1: Circles above indicate points at which signals are sampled. Note 2: Hi-z indicate the high-impedance state. Note 3: Idle cycles are inserted only when the hold state is assumed after external lead access. Figure 15.3.1 Bus Arbitration Timing 15-12 32170/32174 Group User's Manual (Rev. 2.1) 15 (2) When Bus Mode Control Register = 1 EXTERNAL BUS INTERFACE 15.3 Bus Arbitration ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the highimpedance state, allowing data to be transferred on the system bus. To exit the hold state and ____ return to normal operating state, release the HREQ signal back high. Bus cycle Idle Go to hold Hold state Return Next bus cycle BCLK HREQ HACK A11 - A30 CS0 , CS1 RD WR BHW , BLW DB0 - DB15 Hi-Z WAIT Hi-Z Hi-Z Hi-Z Hi-Z Note 1: Circles above indicate points at which signals are sampled. Note 2: Hi-z indicate the high-impedance state. Note 3: Idle cycles are inserted only when the hold state is assumed after external lead access. Figure 15.3.2 Bus Arbitration Timing 15-13 32170/32174 Group User's Manual (Rev. 2.1) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory 15.4 Typical Connection of External Extension Memory (1) When Bus Mode Control Register = 0 A typical connection when using external extension memory is shown in Figure 15.4.1. (External extension memory can only be used in external extension mode and processor mode.) 32170F6 A11 Flash memory H’0000 0000 A18 A0 D15 D0 RD CS max1MB H’0010 0000 H’000C 0000 Memory mapping Internal flash memory (768KB) Unused A30 D0 D15 RD CS0 External memory area (1MB) SRAM H’0020 0000 1M-CS0 area A18 A0 D15 D0 BHW BLW CS1 WAIT Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. WR (D0-D7) WR (D8-D15) RD (D0-D15) CS max1MB * 2 (total2MB) External memory area (2MB) 2M-CS1 area H’0040 0000 Figure 15.4.1 Typical Connection of External Extension Memory (When BUSMOD = 0) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-14 32170/32174 Group User's Manual (Rev. 2.1) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (2) When Bus Mode Control Register = 1 A typical connection when using external extension memory is shown in Figure 15.4.2. (External extension memory can only be used in external extension mode and processor mode.) M32170F6 A11 Flash memory H’0000 0000 A18 A0 D15 D0 RD CS max1MB H’0010 0000 H’000C 0000 Memory mapping Internal flash memory (768KB) Unused A30 D0 D15 RD CS0 External memory area (1MB) SRAM H’0020 0000 1M-CS0 area A19 A0 D15 D0 BHE BLE CS1 WR WAIT Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. BHE (D0-D7) BLE (D8-D15) RD (D0-D15) CS WR (D0-D15) max2MB External memory area (2MB) 2M-CS1 area H’0040 0000 Figure 15.4.2 Typical Connection of External Extension Memory (When BUSMOD = 1) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-15 32170/32174 Group User's Manual (Rev. 2.1) 15 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (3) Using 8/16-bit data bus memories in combination when Bus Mode Control Register = 1 The diagram below shows a typical connection of external extension memory, with 8-bit data bus memory located in the CS0 area, and 16-bit data bus memory located in the CS1 area. (External extension memory can only be used in external extension mode and processor mode.) When CL = 50 pF, memory can be connected with only 2 ns data delay M32170F6VFP A11 8-bit memory H’0000 0000 A18 A0 D7 AB AB OE D0 H’0010 0000 RD CS A0 max1MB H’000C 0000 Memory mapping Internal flash memory (768KB) Unused External memory area (1MB) 8-bit bus area A30 D0 D7 D8 D15 RD CS0 QS32X2245 1M-CS0 area SRAM A19 A0 D15 max2MB D0 WR BHE BLE CS1 WAIT WR (D0-D15) RD (D0-D15) BHE BLE CS H’0020 0000 External memory area (2MB) 16-bit bus area 2M-CS1 area H’0040 0000 Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. Note: The QS32X2245 is a product made by IDT Company. Figure 15.4.3 Typical Connection of External Extension Memory (Using 8/16-bit Mixed Memories when BUSMOD = 1) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. 15-16 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.2 Wait Controller Related Registers 16.3 Typical Operation of the Wait Controller 16 16.1 Outline of the Wait Controller WAIT CONTROLLER 16.1 Outline of the Wait Controller The wait controller controls the number of wait cycles inserted in bus cycles during access to an extended external area. The following outlines the wait controller. Table 16.1.1 Outline of the Wait Controller Item Target space Specification Wait cycles in following memory spaces are controlled depending on operation mode Single-chip mode : No target space (Wait controller settings have no effect) External extension mode : CS0 area (1 Mbytes), CS1 area (2 Mbytes) Processor mode Number of wait cycles that can be inserted : CS0 area (2 Mbytes), CS1 area (2 Mbytes) 1 to 4 wait cycles inserted by software + any number of wait cycles inserted from ____ WAIT pin (Bus cycles with 1 wait cycle are the shortest bus cycle for external access.) ___ ___ In external extension mode and processor mode, two chip select signals (CS0, CS1) are output to ___ ___ an extended external area. Two areas in it corresponding to CS0 and CS1 signals are called the CS0 and the CS1 areas, respectively. Non-CS0 area (Internal ROM access area) H’0000 0000 Internal ROM area CS0 area (1 Mbytes) H’001F FFFF H’0020 0000 Extended external area CS1 area (2 Mbytes) Extended external area H’000F FFFF H’0010 0000 Reserved area CS0 area (2 Mbytes) CS1 area (2 Mbytes) H’003F FFFF Figure 16.1.1 CS0 and CS1 Area Address Map 16-2 32170/32174 Group User's Manual (Rev. 2.1) 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller When accessing an extended external area, the wait controller controls the number of wait cycles to be inserted in bus cycles based on the number of wait cycles set by software and those entered ____ from the WAIT pin. The number of wait cycles that can controlled in software is 1 to 4. (For external access, bus cycles with 1 wait cycle are the shortest bus cycle.) ____ When the WAIT pin input is sampled low in the last cycle of internal wait cycles set by software, the ____ ____ wait cycle is extended as long as the WAIT signal is held low. Then when the WAIT signal is released back high, the wait cycle is terminated and the next new bus cycle is entered into. Table 16.1.2 Number of Wait Cycles that Can be Set by the Wait Controller Extended External Area CS0 area Address H'0010 0000 - H'001F FFFF (External extension mode) H'0000 0000 - H'001F FFFF (Processor mode) CS1 area H'0020 0000 - H'003F FFFF (External extension mode and processor mode) One to 4 wait cycles set by software + any number of ____ wait cycles entered from WAIT pin (However, wait cycles set by software have priority.) Number of Wait Cycles Inserted One to 4 wait cycles set by software + any number of ____ wait cycles entered from WAIT pin (However, wait cycles set by software have priority.) 16-3 32170/32174 Group User's Manual (Rev. 2.1) 16 16.2 Wait Controller Related Registers WAIT CONTROLLER 16.2 Wait Controller Related Registers The following shows a wait controller related register map. Address D0 +0 Address D7 D8 +1 Address D15 H’0080 0180 Wait Cycles Control Register (WTCCR) Blank addresses are a reserved area. Figure 16.2.1 Wait Controller Related Register Map 16-4 32170/32174 Group User's Manual (Rev. 2.1) 16 16.2.1 Wait Cycles Control Register s Wait Cycles Control Register (WTCCR) D0 1 2 CS0WTC 3 4 WAIT CONTROLLER 16.2 Wait Controller Related Registers D 0,1 2,3 Bit Name No functions assigned CS0WTC (CS0 wait cycles control) 00 : 4 wait cycles (when reset) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle 4,5 6,7 No functions assigned CS1WTC (CS1 wait cycles control) 00 : 4 wait cycles (when reset) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle 0 — Function R 0 W — 16-5 32170/32174 Group User's Manual (Rev. 2.1) 16 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller 16.3 Typical Operation of the Wait Controller The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller. (1) When Bus Mode Control Register = 0 ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 "H" Hi-z WAIT "H" Note: THi-Z denotes a high-impedance state. Figure 16.3.1 Internal Bus Access during Bus Free State 16-6 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" Note: Circles above indicate points at which signals are sampled. Figure 16.3.2 Read/Write Timing (for Access with 1 Internal Wait Cycle) 16-7 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Write Write (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Note: Circles above indicate points at which signals are sampled. Figure 16.3.3 Read/Write Timing (for Access with 2 Internal Wait Cycles) 16-8 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Write Write (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Note: Circles above indicate points at which signals are sampled. Figure 16.3.4 Read/Write Timing (for Access with 3 Internal Wait Cycles) 16-9 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Write Write (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) Note: Circles above indicate points at which signals are sampled. Figure 16.3.5 Read/Write Timing (for Access with 4 Internal Wait Cycles) 16-10 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (6 cycles) 4 internal wait cycles 1 external wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" Write Write (6 cycles) 4 internal wait cycles 1 external wait cycle BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" Note: Circles above indicate points at which signals are sampled. Figure 16.3.6 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) 16-11 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3+n cycles) 2 internal wait cycles n external wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" "L" "L" Write Write (3+n cycles) 2 internal wait cycles n external wait cycles BCLK A11 - A30 CS0, CS1 RD "H" BHW, BLW DB0 - DB15 WAIT "H" (Don’t Care) "L" "L" "L" Note: Circles above indicate points at which signals are sampled. Figure 16.3.7 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) 16-12 32170/32174 Group User's Manual (Rev. 2.1) 16 (2) When Bus Mode Control Register = 1 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller ___ External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ___ ____ __ CS1, RD, BHE, BLE, WAIT, and WR. Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 RD WR "H" "H" BHW, BLW DB0 - DB15 "H" Hi-z WAIT "H" Note 1: Hi-Z denotes a high-impedance state. Note 2: BCLK is not output. Figure 16.3.8 Internal Bus Access during Bus Free State 16-13 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (2 cycles) 1 internal wait cycle BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) 1 internal wait cycle BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.9 Read/Write Timing (for Access with 1 Internal Wait Cycle) 16-14 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" Write Write (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.10 Read/Write Timing (for Access with 2 Internal Wait Cycles) 16-15 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" Write Write (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.11 Read/Write Timing (for Access with 3 Internal Wait Cycles) 16-16 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" Write Write (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.12 Read/Write Timing (for Access with 4 Internal Wait Cycles) 16-17 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (6 cycles) 1 external wait cycle 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" "L" Write Write (6 cycles) 1 external wait cycle 4 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) "L" Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.13 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) 16-18 32170/32174 Group User's Manual (Rev. 2.1) 16 Read WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3+n cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD n external wait cycles WR "H" BHE, BLE DB0 - DB15 WAIT (Don’t Care) "H" "L" "L" "L" Write Write (3+n cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 RD "H" n external wait cycles WR BHE, BLE DB0 - DB15 WAIT "H" (Don’t Care) "L" "L" "L" Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. Figure 16.3.14 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) 16-19 32170/32174 Group User's Manual (Rev. 2.1) 16 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller * This is a blank page.* 16-20 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 17 RAM BACKUP MODE 17.1 Outline 17.2 Example of RAM Backup when Power is Down 17.3 Example of RAM Backup for Saving Power Consumption 17.4 Exiting RAM Backup Mode (Wakeup) 17 17.1 Outline RAM BACKUP MODE 17.1 Outline In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes: • Back up the internal RAM data when the power is down • Turn off the power to the CPU whenever necessary to save on the system's power consumption The M32R/ECU CPU is placed in RAM backup mode by applying a voltage of 2.0-3.3 V to the VDD pin (provided for RAM backup) and 0 V to all other pins. During RAM backup mode, the contents of the internal RAM are retained, while the CPU and internal peripheral I/O remain idle. Also, because all pins except VDD are held low during RAM backup mode, power consumption in the system can effectively reduced. 17.2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 17.2.1. The following explains how the RAM can be backed up by using this circuit as an example. DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C Power supply monitor IC VCC VDD Backup power supply for power outage (Note 1) Reference voltage for power outage detection VREF VBB Backup battery VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 3) Power outage detection signal SBI (Note 2) OUT ADnINi M32R/ECU Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. Figure 17.2.1 Typical Circuit for RAM Backup at Power Outage 17-2 32170/32174 Group User's Manual (Rev. 2.1) 17 17.2.1 Normal Operating State RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down Figure 17.2.2 shows the normal operating state of the M32R/ECU. During normal operation, input ___ on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C Power supply monitor IC VCC VDD Backup power supply for power outage (Note 4) 3.3V 3.3V 3.3V (Note 1) Reference voltage for power outage detection 5V 5V 5V VREF VBB Backup battery (Note 3) Power outage detection signal SBI OUT ADnINi "H" VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 2) M32R/ECU Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. Note 4: Backup power supply = 2.0 to 3.3 V Figure 17.2.2 Normal Operating State 17-3 32170/32174 Group User's Manual (Rev. 2.1) 17 17.2.2 RAM Backup State RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down Shown in Figure 17.2.3 is the power outage RAM backup state of the M32R/ECU. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/ECU. Also, the power supply monitor IC's power outage detection pin outputs a low, ___ causing the SBI pin or ADnINi pin input to go low, which generates a RAM backup signal ((a) in Figure 17.2.3). Whether the power is down or not must be determined with respect to the DC IN (regulator input) voltage in order to allow for a software processing time at power outage. To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.2.3). When the power supply to VCC goes down after settings in (1), the voltage applied to the VDD pin becomes 2.0-3.3 V and voltages applied to all other pins drop to 0 V, and the M32R/ECU thereby enters RAM backup mode ((c) in Figure 17.2.3). DC IN Input Regulator Output (5V system) Regulator Output (3.3V system) C (Note 5) (Note 1) Reference voltage for power outage detection Power supply monitor IC VCC VDD Backup power supply for power outage 2.0V - 3.3V 3.3V 0V 0V 0V 0V 0V VREF (Note 4) Backup battery VBB (Note 3) Power outage detection signal SBI OUT ADnINi "L" VDD VCCI OSC-VCC VCCE VREFn AVCCn (Note 2) M32R/ECU Example of RAM backup processing (a) (b) Power goes down (Note 4) Create check data for backup RAM (c) RAM backup mode Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. ___ Note 4: Determined by the input voltage level on SBI pin or ADnINi pin. Note 5: Adjust this capacitance to provid the necessary processing time in (b) . Figure 17.2.3 RAM Backup State at Power Outage 17-4 32170/32174 Group User's Manual (Rev. 2.1) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3 Example of RAM Backup for Saving Power Consumption Figure 17.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example. DC IN Input Regulator Output (3.3V system) Regulator Output (5V system) Regulator Output (3.3V system) RAM backup power supply IB External circuit RAM backup signal (Note 1) Port X (Note 2) SBI ADnINi (Note 3) VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. Figure 17.3.1 Typical Circuit for RAM Backup to Save on Power Consumption 17-5 32170/32174 Group User's Manual (Rev. 2.1) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.1 Normal Operating State Figure 17.3.2 shows the normal operating state of the M32R/ECU. During normal operation, the ___ RAM backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 015) pin used for RAM backup signal detection remains high. Port X, which is the transistor's base connecting pin, should output a high. This causes the transistor's base voltage, IB, to go high, so that current is fed from the power supply to the VCC pin via the transistor. DC IN Input Regulator Output (3.3V system) Regulator Output (5V system) Regulator Output (3.3V system) "H" RAM backup power supply IB External circuit RAM backup signal (Note 1) "H" Port X (Note 2) "H" SBI ADnINi (Note 3) 3.3V 3.3V 5V 5V 5V 3.3V VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. Figure 17.3.2 Normal Operating State 17-6 32170/32174 Group User's Manual (Rev. 2.1) 17 RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.2 RAM Backup State Figure 17.3.3 shows the RAM backup state of the M32R/ECU. Figure 17.3.4 shows a RAM backup ___ sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and (a) in Figure 17.3.3). To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.3.3). (2) To materialize low-power operation, set all programmable input/output pins except port X for input mode (or for output mode, with pins outputting a low) ((c) in Figure 17.3.3). (3) Set port X for input mode (B and (d) in Figure 17.3.3). This causes the transistor's base voltage, IB, to go low, so that no current flows from the power supply to the VCC pin via the transistor (C in Figure 17.3.3). Consequently, the power to the VCC pin is shut off (D in Figure 17.3.3). Due to settings in (1) to (3), the voltage applied to the VDD pin becomes 3.3 V ± 10% and voltages applied to all other pins drop to 0 V, thus placing the M32R/ECU in RAM backup mode ((d) in Figure 17.2.3). DC IN Input C IB "L" Regulator Output (5V system) Regulator Output (3.3V system) "L" B "L" Port X (Note 2) A "L" SBI ADnINi (Note 3) 0V 0V 0V 0V 0V 3.3V Regulator Output (3.3V system) D Power supply for RAM External circuit RAM backup signal (Note 1) "L" VCCI OSC-VCC VCCE VREFn AVCCn VDD M32R/ECU Example of RAM backup processing (a) (b) Generate RAM backup signal (Note 4) Create check data for backup RAM Set transistor’s base connecting pin (port X) for input mode (Note 5) (c) (d) RAM backup mode Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. ___ Note 4: Determined by the input voltage level on SBI pin or ADnINi pin. Note 5: Base voltage IB = 0 causes the current fed to the VCC pin to stop. Explained in A to D above. Figure 17.3.3 RAM Backup State for Low-Power Operation 17-7 32170/32174 Group User's Manual (Rev. 2.1) 17 Power on VCCE, VREFn, AVCCn VCCI, OSC-VCC RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 5.0V RAM backup period 0V 3.3V 0V VDD Port output setting (High level) Port input mode Port output setting (High level) Port X External input signal goes low External input signal goes high SBI ADnINi f (XIN) Oscillation stabilization time Oscillation stabilization time RESET Figure 17.3.4 Example of RAM Backup Sequence for Low-Power Operation 17.3.3 Precautions to Be Observed at Power-on When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port's initial output level is indeterminate. Therefore, be sure to set the output high level in the Port X Data Register before you set port X for output mode. Unless this method is followed, port output may go low at the same time port output is set after the clock oscillation has stabilized, causing the device to enter RAM backup mode. 17-8 32170/32174 Group User's Manual (Rev. 2.1) 17 RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) 17.4 Exiting RAM Backup Mode (Wakeup) Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input. The following shows how to execute wakeup processing. (1) Reset the device ((a) in Figure 17.4.1). For details about reset, refer to Chapter 7, "Reset." (2) Set port X for output mode and output a high from the port ((b) in Figure 17.4.1).(Note) (3) Check the RAM contents against the check data created before entering RAM backup mode ((c) in Figure 17.4.1). (4) If the RAM contents and check data did not match when checked in (3), initialize the RAM ((d) in Figure 17.4.1). If the RAM contents and check data matched, use the retained data in the program. (5) After initializing each internal circuit ((e) in Figure 17.4.1), return the main routine ((f) in Figure 17.4.1). Note : For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Example of wakeup processing (a) (b) Reset Set transistor’s base connecting pin (port X) for high-level output mode (Note) (c) Check RAM contents against backup RAM check data Error OK (d) Initialize RAM (e) Initial each internal circuit (f) To main routine Note: For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Figure 17.4.1 Wakeup Processing 17-9 32170/32174 Group User's Manual (Rev. 2.1) 17 RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) * This is a blank page.* 17-10 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.2 Clock Generator Circuit 18 18.1 Oscillator Circuit OSCILLATION CIRCUIT 18.1 Oscillator Circuit The M32R/ECU contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory. The frequency of this clock is divided by 2 in the subsequent circuit to produce the internal peripheral clock, which is the operating clock for the internal peripheral I/O. 18.1.1 Example of an Oscillator Circuit A clock generating circuit can be configured by connecting a ceramic (or crystal) resonator between the XIN and XOUT pins external to the chip. Figure 18.1.1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin (VCNT). For constants Rf, CIN, COUT, and Rd, consult your resonator manufacturer to determine the appropriate values. When you use an externally sourced clock signal without using the internal oscillator circuit, connect the external clock signal to the XIN pin and leave the XOUT pin open. M32R/ECU Oscillator module Oscillator circuit PLL circuit 1/2 To CPU clock To internal peripheral clock OSCVSS OSCVCC XIN Rf XOUT Rd VCNT BCLK / P70 220pF (Note) C CIN COUT 1KΩ (Note) 0.1µF (Note) OSCVCC : 3.3 V power supply Note: allowable error ±10% Figure 18.1.1 Example of a System Clock Generating Circuit 18-2 32170/32174 Group User's Manual (Rev. 2.1) 18 18.1.2 System Clock Output Function OSCILLATION CIRCUIT 18.1 Oscillator Circuit A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1. Configuration of the P7 Operation Mode Register is shown below. s P7 Operation Mode Register (P7MOD) D 8 Bit Name P70MOD (Port P70 operation mode) 9 P71MOD (Port P71 operation mode) 10 P72MOD (Port P72 operation mode) 11 P73MOD (Port P73 operation mode) 12 P74MOD (Port P74 operation mode) 13 P75MOD (Port P75 operation mode) 14 P76MOD (Port P76 operation mode) 15 P77MOD (Port P77 operation mode) Function 0 : P70 1 : BCLK 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK R W 18-3 32170/32174 Group User's Manual (Rev. 2.1) 18 18.1.3 Oscillation Stabilization Time at Power-on OSCILLATION CIRCUIT 18.1 Oscillator Circuit The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used. Figure 18.1.2 shows an oscillation stabilization time at poweron. Oscillation stabilization time OSC-VCC RESET XIN Figure 18.1.2 Oscillation Stabilization Time at Power-on 18-4 32170/32174 Group User's Manual (Rev. 2.1) 18 18.2 Clock Generator Circuit OSCILLATION CIRCUIT 18.2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits. XIN (8MHz - 10MHz) X4 CPU clock (32MHz - 40MHz) 1/2 BCLK (16MHz - 20MHz) 1/2 internal peripheral clock (8MHz - 10MHz) 1/4 Figure 18.2.1 Configuration of the Clock Generator Circuit 18-5 32170/32174 Group User's Manual (Rev. 2.1) 18 OSCILLATION CIRCUIT 18.2 Clock Generator Circuit * This is a blank page.* 18-6 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 19 JTAG 19.1 Outline of JTAG 19.2 Configuration of the JTAG Circuit 19.3 JTAG Registers 19.4 Basic Operation of JTAG 19.5 Boundary Scan Description Language 19.6 Precautions on Board Design when Using JTAG 19.7 Processing Pins when Not Using JTAG 19 19.1 Outline of JTAG JTAG 19.1 Outline of JTAG The 32170/32174 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std. 1149.1a-1993 documentation. The functions of JTAG interface related pins mounted on the 32170/32174 are shown below. Table 19.1.1 JTAG Pin Functions Type TAP (Note) Symbol Pin Name JTCK JTDI Test clock Test data input I/O Input input Function Clock input to the test circuit. Synchronous serial data input pin used to enter test instruction code and test data. This input is sampled on rising edges of JTCK. JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data. This signal changes state on falling edges of JTCK, and is output only in Shift-IR or ShiftDR state. JTMS Test mode select Input Test mode select input to control the test circuit's state transitions. This input is sampled on rising edges of JTCK. JTRST Test reset Input Active-low test reset input to initialize the test circuit asynchronously. To ensure that the test circuit is reset without fail, JTMS signal input must be held high while this signal changes state from low to high. Note: TAP = Test Access Port, a JTAG interface stipulated in IEEE 1149.1. 19-2 32170/32174 Group User's Manual (Rev. 2.1) 19 19.2 Configuration of the JTAG Circuit JTAG 19.2 Configuration of the JTAG Circuit The 32170/32174's JTAG circuit consists of the following blocks: • Instruction register to hold instruction codes which are fetched through the boundary-scan path • A set of data registers which are accessed through the boundary-scan path • Test access port (abbreviated TAP) controller to control the JTAG unit's state transitions • Control logic to select input, output, etc. A configuration of the JTAG circuit is shown below. M32R/ECU Data register set JTDI Boundary-scan register (JTAGBSR) Bypass register (JTAGBPR) ID code register (JTAGIDR) Output selection Decoder Output selection Instruction register (6 bits) (JTAGIR) JTMS JTCK JTRST TAP controller Figure 19.2.1 Configuration of the JTAG Circuit 19-3 32170/32174 Group User's Manual (Rev. 2.1) Buffer JTDO 19 19.3 JTAG Registers 19.3.1 Instruction Register (JTAGIR) JTAG 19.3 JTAG Registers The Instruction Register (JTAGIR) is a 6-bit register to hold instruction code. This register is set in IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. When test is reset (to initialize the test circuit), the initial value of this register is b'000010 (IDCODE instruction). After a test reset, the IDCODE Register is selected as the data register until an instruction code is set by an external device. In "Capture-IR" state, this register always has b'110001 (fixed value) loaded into it. Therefore, when in "Shift-IR" state, no matter what value was set in this register, b'110001 is always output from the JTDO pin (sequentially beginning with LSB). However, this value normally is not handled as instruction code. Shown below is outside the scope of guaranteed operations. Note that if this operation is performed, the device may inadvertently handle b'110001 as instruction code, which makes it unable to operate normally. [Capture-IR] → [Exit1-IR] → [Update-IR] The 32170/32174's JTAG interface supports the following instructions: • Three instructions stipulated as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS) • Device ID register access instruction (IDCODE) Table 19.3.1 JTAG Instruction List Instruction Code Abbreviation b'000000 b'000001 EXTEST SAMPLE/PRELOAD Operation Tests circuit/board-level connections outside the chip. Samples operating circuit status and outputs the sampled status from JTDO pin, while at the same time entering the data used for boundary-scan test from the JTDI pin and presets it in Boundary Scan Register. b'000010 IDCODE Selects ID Code Register and outputs device and manufacturer identification data from JTDO pin. b'111111 BYPASS Selects Bypass Register and inspects or sets data. Note 1: Do not set any other instruction code. Note 2: For details about "IR path sequence," "DR path sequence," "Test reset," "Capture-IR" state, "Shift-IR" state, "Exit1-IR" state, and "Update-IR" state, refer to Section 19.4. 19-4 32170/32174 Group User's Manual (Rev. 2.1) 19 19.3.2 Data Registers (1) Boundary Scan Register (JTAGBSR) JTAG 19.3 JTAG Registers The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this register are assigned to each pin on the 32170/32174. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/PRELOAD instruction. In "Capture-DR" state, this register captures the status of input pins or internal logic output values. In "Shift-DR" state, while outputting the sampled value, it is used to set pin functions (input/output pin and tristate output pin direction) and output values by entering data for boundary-scan test. (2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32170/ 32174 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction. This register when in "Capture-DR" state has b'0 (fixed value) loaded into it. (3) ID Code Register (JTAGIDR) The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds the following information: • Version information (4 bits) • Part number (16 bits) • Manufacturer ID (11 bits) : b'0000 : b'0011 0010 0010 0000 : b'000 0001 1100 This register is connected between the JTDI and JTDO pins, and is selected when issuing IDCODE instruction. When in "Capture-DR" state, this register has the said IDCODE data loaded into it, which is output from the JTDO pin in "Shift_DR" state. This register is a read-only register, so that the data written from the JTDI pin during DR pass sequence is ignored. Therefore, make sure JTDI input = low during "Shift-DR" state. 0 34 Version 4 bits Part number 16 bits 19 20 Manufacturer ID 11 bits 30 31 1 Note : For details about "Capture-DR" and "Shift-DR" states, refer to Section 19.4. 19-5 32170/32174 Group User's Manual (Rev. 2.1) 19 19.4 Basic Operation of JTAG 19.4.1 Outline of JTAG Operation JTAG 19.4 Basic Operation of JTAG The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state. • Capture operation The result of boundary-scan test or the fixed data defined for each register is sampled. As register operation, the input data is loaded into the shift register stage. • Shift operation The register is accessed from outside through the boundary-scan path. The sampled value is output to an external device at the same time data is set from outside. As register operation, bits are shifted right between each shift register stage. • Update operation The data set from outside during shift is driven. As register operation, the value set in the shift register stage is transferred to the parallel output stage. The JTAG interface undergoes transitions of internal state depending on JTMS input as it performs the following two operations. In either case, the operation basically is performed in order of Capture → Shift → Update. • IR path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subsequent DR path sequence. • DR path sequence The selected data register is operated on to inspect or set data. 19-6 32170/32174 Group User's Manual (Rev. 2.1) 19 related registers are shown below. JTAG 19.4 Basic Operation of JTAG The state transitions of the TAP controller and the basic configuration of the 32170/32174's JTAG 1 Test-Logic-Reset 0 1 1 1 0 Run-Test/Idle Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 Select-IR-Scan 0 1 0 Capture-IR 0 Shift-IR 1 0 1 0 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 1 0 Note: Values (0 and 1) in this diagram denote the state of JTMS input signal. Figure 19.4.1 TAP Controller State Transition Input multiplexer Shift register stage To next cell Data input 0 1 G DQ T DQ T R Data output "Shift-DR" or "Shift-IR" "Clock-DR" or "Clock-IR" "Update-DR" or "Update-IR" Test reset From preceding cell Parallel output stage Note: Shown here is the basic configuration, and the configuration of DR and IR does not all have to be like this. Figure 19.4.2 Basic Configuration of JTAG Related Registers 19-7 32170/32174 Group User's Manual (Rev. 2.1) 19 19.4.2 IR Path Sequence JTAG 19.4 Basic Operation of JTAG Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of two JTCK cycles from "Run-Test/Idle" state to go to "Select-IR-Scan" state. (2) Set JTMS = low to go to "Capture-IR" state. At this time, b'110001 (fixed value) is set in the instruction register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-IR" state. In "Shift-IR" state, the value of the shift register stage is shifted right one bit every cycle, and the data b'110001 (fixed value) that was set in (2) is serially output from the JTDO pin. At the same time, the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit. Because instruction code is set in the instruction register which is comprised of 6 bits, the "Shift-IR" state continues for a period of 6 JTCK cycles. To stop the shift operation in the middle, go to "Pause-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). Also, to return from "Pause-IR" state, go to "Shift-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). (4) By setting JTMS = high, go from "Shift-IR" state to "Exit1-IR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-IR" state. In "Update-IR" state, the instruction code that was set in the instruction register's shift register stage is transferred to the instruction register's parallel output stage and, thus, JTAG instruction decoding begins. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state. 19-8 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise of JTCK in "Shift-IR" state. Instruction code is set in the parallel output stage at fall of JTCK in "Update-IR" state. JTCK JTMS Select-DR-Scan Select-IR-Scan Run-Test/Idle Run-Test/Idle Capture-IR Update-IR Exit1-IR Shift-IR TAP state JTDI Don’t Care Instruction code (6 bits) LSB value MSB value Don’t Care High impedance JTDO 1 0 0 0 1 1 High impedance JTDO is output at fall of JTCK in "Shift-IR" state. Shift output from the instruction register is fixed to b’110001. Finished storing instruction code in the instruction register’s shift register stage. Figure 19.4.3 IR Path Sequence 19-9 32170/32174 Group User's Manual (Rev. 2.1) 19 19.4.3 DR Path Sequence JTAG 19.4 Basic Operation of JTAG The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of one JTCK cycle from "Run-Test/Idle" state to go to "SelectDR-Scan" state. Which data register will be selected at this time depends on the instruction that was set during the IR path sequence performed prior to the DR path sequence. (2) Set JTMS = low to go to "Capture-DR" state. At this time, the result of boundary-scan test or the fixed data defined for each register is set in the data register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-DR" state. In "Shift-DR" state, the DR value is shifted right one bit every cycle, and the data that was set in (2) is serially output from the JTDO in. At the same time, the setup data serially entered from the JTDI pin is set in the data register's shift register stage bit by bit. By continuing the "Shift-DR" state as long as the number of bits of the selected data register (by entering JTMS = low), all bits of data can be set in and read out from the shift register stage. To stop the shift operation in the middle, go to "Pause-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). Also, to return from "Pause-DR" state, go to "Shift-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). (4) Set JTMS = high to go from "Shift-DR" state to "Exit2-DR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-DR" state. In "Update-DR" state, the data that was set in the data register's shift register stage is transferred to the parallel output stage and, thus, the setup data becomes ready for use. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state. 19-10 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise of JTCK in "Shift-DR" state. Setup data is set in the parallel output stage at fall of JTCK in "Update-DR" state. JTCK JTMS Select-DR-Scan Run-Test/Idle Run-Test/Idle Capture-DR Update-DR Exit1-DR Shift-DR TAP state JTDI Don’t Care Don’t Care LSB value High impedance JTDO MSB value High impedance JTDO is output at fall of JTCK in "Shift-DR" state. Finished storing setup data in the shift register stage of the selected data register. Note: The shift operation of the data register for the shift register stage is right-shifted, therefore, the output from JTDO is from the LSB side. Input to JTDI starts from the value to be set in LSB side. Figure 19.4.4 DR Path Sequence 19-11 32170/32174 Group User's Manual (Rev. 2.1) 19 19.4.4 Examining and Setting Data Registers JTAG 19.4 Basic Operation of JTAG To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit). Test reset can be entered by one of the following two methods: • Pull JTRST pin input low • Drive JTMS pin input high and enter JTCK for 5 cycles or more (2) Set JTMS = low to go to "Run-Test/Idle" state. To continue the idle state, hold JTMS input low. (3) Set JTMS = high to exit "Run-Test/Idle" state and perform IR path sequence. In IR path sequence, specify the data register you want to inspect or set. (4) Subsequently, perform DR path sequence. For the data register specified in IR path sequence, enter setup data from the JTDI pin and read out reference data from the JTDO pin. (5) If after DR path sequence is completed you want to proceed and perform IR path sequence or DR path sequence, enter JTMS = high to return to "Select-DR-Scan" state. If after a series of IR and DR path sequence processing is completed you want to wait for the next processing, enter JTMS = low to go to "Run-Test/Idle" state and retain the state. 19-12 32170/32174 Group User's Manual (Rev. 2.1) 19 TAP states Test-Logic- Run-Test Reset state /Idle state IR path sequence DR path sequence JTAG 19.4 Basic Operation of JTAG Run-Test /Idle state IR path sequence DR path sequence JTDI (Note 1) Instruction Setup data code #0 #0 Fixed value b’110001 Specify the data register you want to inspect or set. Instruction Setup data code #1 #1 Fixed value b’110001 JTDO (Note 2) (Note 3) (Note 3) Setup data is entered serially from JTDI. Reference data is serially output from JTDO. (1) Basic access TAP states Test-Logic- Run-Test Reset state /Idle state IR path sequence DR path sequence Run-Test /Idle state IR path sequence DR path sequence JTDI (Note 1) Instruction Setup data code #0 #0 Fixed value b’110001 Specify the data register you want to inspect or set. Setup data Setup data #1 #2 JTDO (Note 2) (Note 3) (Note 3) (Note 3) Same data register can be operated on to inspect or set data continuously. (2) Continuous access to the same data register Note 1: The setup value for each register must be entered from the JTDI pin beginning with the LSB. Note 2: The value of each register is output from the JTDO pin beginning with the LSB. The JTDO pin outputs valid data in only "Shift-IR" state of IR path sequence and "Shift-DR" state of DR path sequence. In all other states, the JTDO pin is tristated (high impedance). Note 3: Data can only be read out from the data register which is selected by the instruction that was set in the immediately preceding IR path sequence. Output in the selected data register's shift register stage is the value that was sampled during "Capture-DR" state. Figure 19.4.5 Continuous JTAG Access 19-13 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.5 Boundary Scan Description Language 19.5 Boundary Scan Description Language The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to "Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL). BSDL helps to precisely describe the functions of standard-compliant components to be tested. For package connection test, this language is used by Automated Test Pattern Generation tools, and for synthesized test logic and verification, it is used by Electronic Design Automation tools. BSDL provides powerful extended functions usable in internal test generation and necessary to write hardware debug and diagnostics software. The primary section of BSDL contains statements of logical port description, physical pin map, instruction set, and boundary register description. • Logical port description The logical port description assigns meaningful symbol names to each pin on the chip. This determines the logic type of input, output, input/output, buffer, or link of each pin that defines the logical direction of signal flow. • Physical pin map The physical pin map correlates the chip's logical ports to the physical pins on each package. Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description. • Instruction set statement The instruction set statement writes bit patterns to be shifted in into the chip's instruction register. This bit pattern is necessary to place the chip into each test mode defined in standards. It is also possible to write instructions exclusive to the chip. • Boundary register description The boundary register description is a list of boundary register cells or shift stages. Each cell is assigned a separate number. The cell with number 0 is located closest to the test data output (JTDO) pin, and the cell with the largest number is located closest to the test data input (JTDI) pin. Cells also contain related other information which includes cell type, logical port corresponding to cell, logical function of cell, safety value, control cell number, disable value, and result value. Note: Information on the Boundary Scan Description Language (BSDL) can be downloaded from the M32R family application engineering data in “Mitsubishi Microcomputer Technology Home Page.” The URL address of this home page is shown below. • http://www.infomicom.maec.co.jp/ 19-14 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.6 Precautions on Board Design when Using JTAG 19.6 Precautions on Board Design when Using JTAG The JTAG pins require that wiring lengths be matched during board design in order to accomplish fast, highly reliable communication with JTAG tools. An example of how to process pins when using JTAG tools is shown below. VCCE(5V) M32R/ECU 10KΩ JTDO 10KΩ SDI connector (JTAG connector) Power 33Ω 33Ω JTAG tool TDO JTDI 10KΩ JTMS 10KΩ 33Ω JTCK 33Ω JTRST 2KΩ 0.1 F 33Ω TDI TMS TCK TRST GND User board Make sure wiring lengths are the equal, and avoid bending wiring as much as possible. Also, do not use through holes with in this wiring. Note 1: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Note 2: Even when not using JTAG tools, always be sure to process each pin. The same pulldown/pullup resistance values as when using JTAG tools may be used without causing any problem. Figure 19.6.1 Example for Processing Pins when Using JTAG Tools (for the 240QFP) 19-15 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.6 Precautions on Board Design when Using JTAG VCCE(5V) M32R/ECU 10KΩ SDI connector (JTAG connector) Power 33Ω When connecting JTAG tool JTDO TDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω TDI TMS JTCK 33Ω JTRST 2KΩ 10KΩ DBI 33Ω TRCLK 33Ω TRSYNC 33Ω TRDATA[0:7] 33Ω EVENT[0:1] 0.1 F User board TCK TRST GND 33Ω DBI TRCLK TRSYNC TRDATA[0:7] 8 EVENT[0:1] 2 When connecting emulator Make sure wiring lengths are the same, and avoid bending wires as much as possible. Also, do not use through-holes within wiring. Note 1: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Note 2: Even when not using JTAG tools, always be sure to process each pin. The same pulldown/pullup resistance values as when using JTAG tools may be used without causing any problem. Figure 19.6.2 Precautions to Be Observed when Connecting JTAG Tool (when Using the 255FBGA) 19-16 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.7 Processing Pins when Not Using JTAG 19.7 Processing Pins when Not Using JTAG The diagram below shows how to process JTAG pins when not using these pins (i.e. for boards that do not have pins/connectors connecting to JTAG tools). VCCE(5V) M32R/ECU 0—100KΩ JTDO JTDI 0—100KΩ 0—100KΩ JTMS 0—100KΩ JTCK JTRST 0—100KΩ User board Note: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Figure 19.7.1 Processing Pins when Not Using JTAG (for 240QFP) 19-17 32170/32174 Group User's Manual (Rev. 2.1) 19 JTAG 19.7 Processing Pins when Not Using JTAG VCCE(5V) M32R/ECU 0—100KΩ JTDO 0—100KΩ JTDI 0—100KΩ JTMS 0—100KΩ JTCK JTRST 0—100K 0—100KΩ DBI TRCLK ( OPEN ) TRSYNC ( OPEN ) TRDATA[0:7] ( OPEN ) EVENT[0:1] ( OPEN ) User board Note: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Figure 19.7.2 Processing Pins when Not Using JTAG (for 255FBGA) 19-18 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 20 POWER-ON/POWERSHUTDOWN SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.2 Power-On Sequence 20.3 Power-Shutdown Sequence 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.1 Configuration of the Power Supply Circuit To accomplish fast operation and low power consumption, the M32R/ECU is designed in such a way that its external interface circuits operate with a 5 V or 3.3 V power supply, and that all other circuits operate with 3.3 V. Therefore, control timings of 5 V and 3.3 V power supplies must be taken into consideration when designing the application circuit. Table 20.1.1 Power Supply Functions Type of Power Supply 5.0 V Pin name VCCE AVCC0, AVCC1 VREF0, VREF1 3.3 V VCCI FVCC VDD OSC-VCC Function Power supply fed to external I/O ports Power supply for the A-D converter Reference voltage for the A-D converter Power supply fed to the internal logic Power supply for internal flash memory Power supply for internal RAM backup Power supply for the oscillator and PLL circuits M32R/ECU VCCE 5 V power supply AVCC A-D converter circuit I/O control circuit VCCI 3.3 V power supply CPU Peripheral circuit VDD RAM FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.1.1 Configuration of the Power Supply Circuit (when VCC=5V) 20-2 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.1 Configuration of the Power Supply Circuit M32R/ECU VCCE I/O control circuit AVCC A-D converter circuit 3.3V power supply VCCI CPU Peripheral circuit VDD RAM FVCC OSC-VCC Flash Oscillator and PLL circuits Figure 20.1.2 Configuration of the Power Supply Circuit (when VCC=3.3V) 20-3 32170/32174 Group User's Manual (Rev. 2.1) 20 20.2 Power-On Sequence POWER-ON/POWER-SHUTDOWN SEQUENCE 20.2 Power-On Sequence 20.2.1 Power-On Sequence When Not Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/ECU when not using RAM backup. 5V VCCE AVCC0, AVCC1 VREF0, VREF1 RESET 0V 5V 0V 5V 0V 0V 3.3V VDD 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (a) (b) 5V (a): Turn on the 3.3 V power supply after turning on the 5 V power supply. ____________ (b): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.1 Power-On Sequence When Not Using RAM Backup (when VCC=5V) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit. 20-4 32170/32174 Group User's Manual (Rev. 2.1) 20 3.3V VCCE AVCC0, AVCC1 VREF0, VREF1 RESET 0V 3.3V 0V 3.3V 0V 0V 3.3V VDD 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V POWER-ON/POWER-SHUTDOWN SEQUENCE 20.2 Power-On Sequence (a) 3.3V ____________ (a): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.2 Power-On Sequence When Not Using RAM Backup (when VCC=3.3V) 20-5 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.2 Power-On Sequence 20.2.2 Power-On Sequence When Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/ECU when using RAM backup. 5V VCCE AVCC0, AVCC1 VREF0, VREF1 RESET 0V 5V 0V 5V 0V 0V 3.3V VDD 2.0V 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (a) (b) 5V (a): Turn on the 3.3 V power supply after turning on the 5 V power supply. ____________ (b): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations • VDD OSC-VCC VCCI FVCC • VCCE VCCI, FVCC, OSC-VCC Figure 20.2.3 Power-On Sequence When Using RAM Backup (when VCC=5V) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit. 20-6 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.2 Power-On Sequence 3.3V VCCE AVCC0, AVCC1 VREF0, VREF1 RESET 0V 3.3V 0V 3.3V 0V 0V 3.3V VDD 2.0V 0V 3.3V VCCI 0V 3.3V FVCC 0V 3.3V OSC-VCC 0V (a) 3.3V ____________ (a): After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations • VDD OSC-VCC • VCCE VCCI FVCC VCCI, FVCC, OSC-VCC Figure 20.2.4 Power-On Sequence When Using RAM Backup (when VCC=3.3V) 20-7 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence 20.3 Power-Shutdown Sequence 20.3.1 Power-Shutdown Sequence When Not Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ ECU when not using RAM backup. 5V VCCE 0V AVCC0, AVCC1 VREF0, VREF1 RESET 0V (b) 5V 0V 5V (a) 0V 5V VDD 3.3V 3.3V 0V 0V 3.3V VCCI FVCC 0V 3.3V OSC-VCC 0V ____________ (a): Pull the RESET pin input low. ____________ (b): Turn off the 5 V and the 3 V power supply after the RESET pin goes low. Note: Power-shutdown requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.1 Power-Shutdown Sequence When Not Using RAM Backup (when VCC=5V) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit. 20-8 32170/32174 Group User's Manual (Rev. 2.1) 20 3.3V VCCE 3.3V AVCC0, AVCC1 3.3V VREF0, VREF1 RESET 3.3V VDD 3.3V VCCI 3.3V FVCC 3.3V OSC-VCC POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence 0V 0V 3.3V (a) 0V 0V 0V 0V 0V 0V ____________ (a): Turn off the power supply after the RESET pin goes low. Note: Power-shutdown requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.2 Power-Shutdown Sequence When Not Using RAM Backup (when VCC=3.3V) 20-9 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence 20.3.2 Power-Shutdown Sequence When Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ ECU when using RAM backup. VCCE AVCC0, AVCC1 VREF0, VREF1 5V P72 / HREQ 5V 0V 5V 0V 5V (a) (b) 0V 0V 5V RESET (c) 0V VDD VCCI (c) 3.3V 3.3V (d) 2.0V 0V 3.3V FVCC 0V OSC-VCC 3.3V 0V __________ (a): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. ____________ (b): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull ____________ the RESET pin input low. ____________ (c): Turn off the 5 V and the 3.3 V power supply after the RESET pin goes low. (d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: Power-shutdown requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.3 Power-Shutdown Sequence When Using RAM Backup(when VCC=5V) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit. 20-10 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence 3.3V VCCE 3.3V AVCC0, AVCC1 3.3V VREF0, VREF1 3.3V P72 / HREQ 3.3V RESET 3.3V VDD 3.3V VCCI 3.3V FVCC 3.3V OSC-VCC 0V 0V 0V 0V (a) (b) 0V 0V (c) 0V (d) 2.0V (c) 0V __________ (a): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. ____________ (b): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull ____________ the RESET pin input low. ____________ (c): Turn off the power supply after the RESET pin goes low. (d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: Power-shutdown requirements • VDD VCCI FVCC • OSC-VCC VCCI Figure 20.3.4 Power-Shutdown Sequence When Using RAM Backup(when VCC=3.3V) 20-11 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/ECU VCCE 5V power supply AVCC A-D converter circuit I/O control circuit 5V 3.3V VCCI 3.3V power supply CPU Peripheral circuits VDD RAM FVCC OSC-VCC Flash Oscillator and PLL circuits Figure 20.3.5 Microcomputer Ready to Run State 1 M32R/ECU VCCE I/O control circuit AVCC A-D converter circuit 3.3V 3.3V power supply VCCI CPU Peripheral circuit VDD FVCC OSC-VCC RAM Flash Oscillator and PLL circuit Figure 20.3.6 Microcomputer Ready to Run State 2 20-12 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/ECU VCCE 0V 5V power supply AVCC A-D converter circuit I/O control circuit VCCI 3.3V 3.3V power supply CPU Peripheral circuits VDD RAM FVCC OSC-VCC Flash Oscillator and PLL circuits Figure 20.3.7 CPU Reset State 1 M32R/ECU VCCE I/O control circuit AVCC A-D converter circuit 3.3V 3.3V power supply VCCI CPU Peripheral circuit VDD FVCC OSC-VCC RAM Flash Oscillator and PLL circuit Figure 20.3.8 CPU Reset State 2 20-13 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/ECU VCCE 5V power supply AVCC A-D converter circuit I/O control circuit 5V 0V VCCI 3.3V power supply CPU Peripheral circuits VDD RAM FVCC OSC-VCC Flash Oscillator and PLL circuits Figure 20.3.9 CPU Halt State 1 M32R/ECU VCCE 3.3V 5V power supply AVCC I/O control circuit A-D converter circuit 0V 3.3V power supply VCCI CPU Peripheral circuit VDD FVCC OSC-VCC RAM Flash Oscillator and PLL circuit Figure 20.3.10 CPU Halt State 2 20-14 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/ECU VCCE 5V power supply AVCC A-D converter circuit I/O control circuit 0V 0V VCCI 3.3V power supply CPU Peripheral circuits VDD 3.3V-2.0V FVCC RAM Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.11 SRAM Data Backup State 1 M32R/ECU VCCE I/O control circuit AVCC A-D converter circuit 0V 3.3V power supply VCCI CPU Peripheral circuit 3.3V-2.0V VDD FVCC OSC-VCC RAM Flash Oscillator and PLL circuit Figure 20.3.12 SRAM Data Backup State 2 20-15 32170/32174 Group User's Manual (Rev. 2.1) 20 POWER-ON/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence * This is a blank page.* 20-16 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.2 Electrical Characteristics (VCCE = 3.3V) 21.3 AC Characteristics 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1 Electrical Characteristics (VCCE = 5V) 21.1.1 Absolute Maximum Ratings Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Symbol VCCI VDD OSC-VCC FVCC VCCE AVCC VREF Parameter Internal Logic Power Supply Voltage RAM Power Supply Voltage PLL Power Supply Voltage Flash Power Supply Voltage External I/O Buffer Voltage Analog Power Supply Voltage Analog Reference Voltage Xin, VCNT Condition VDD VDD VDD VDD VCCE VCCE VCCE VCCI VCCI VCCI VCCI FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC VREF VREF VREF Rated Value -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 -0.3 to 6.5 -0.3 to OSC-VCC+0.3 Unit V V V V V V V V AVCC AVCC AVCC VI Other Xout -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 V -0.3 to VCCE+0.3 Ta=-40 to 85oC 600 500 -40 to 125 -65 to 150 mW mW o VO Other Pd Power Dissipation Ta=-40 to 125 C TOPR Tstg Operating Ambient Temperature (Note) Storage Temperature o C C o Note: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Mitsubishi. 21-2 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Min. VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note1) Internal Logic Power Supply Voltage (Note2) RAM Power Supply Voltage (Note2) Flash Power Supply Voltage (Note2) Analog Power Supply Voltage (Note1) PLL Power Supply Voltage (Note2) Analog Reference Voltage (Note1) Rated Value Typ. 5.0 3.3 3.3 3.3 5.0 3.3 5.0 Max. 5.5 3.6 3.6 3.6 5.5 3.6 5.5 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 10 Unit 4.5 3.0 3.0 3.0 4.5 3.0 4.5 0.8VCCE 0.43VCCE 0 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0—P22 (Note 3) High State Average Output Current P0—P22 (Note4) Low State Peak Output Current P0—P22 (Note 3) Low State Average Output Current P0—P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF. Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | | ports P2 + P3 | 80 mA 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | 80 mA | ports P18 + P19 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. 21-3 32170/32174 Group User's Manual (Rev. 2.1) 21 Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Rated Value Min. Typ. 5.0 3.3 3.3 3.3 5.0 3.3 5.0 Max. 5.5 3.6 3.6 3.6 5.5 3.6 5.5 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 8 Unit VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note 1) Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2) Flash Power Supply Voltage (Note 2) Analog Power Supply Voltage (Note 1) PLL Power Supply Voltage (Note 2) Analog Reference Voltage (Note 1) 4.5 3.0 3.0 3.0 4.5 3.0 4.5 0.8VCCE 0.43VCCE 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT 0 IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0—P22 (Note 3) High State Average Output Current P0—P22 (Note 4) Low State Peak Output Current P0—P22 (Note 3) Low State Average Output Current P0—P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF. 80 mA Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | | ports P2 + P3 | 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | | ports P18 + P19 | Note 4: The average output current is a value averaged during a 100 ms period. 80 mA 80 mA 21-4 32170/32174 Group User's Manual (Rev. 2.1) 21 21.1.3 DC Characteristics 21.1.3.1 Electrical Characteristics ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition Min. VOH VOL VDD Output High Voltage Output Low Voltage RAM Retention Power Supply Voltage High State Input Current Low State Input Current IOH IOL -5mA 5mA VCCE+0.2 ×IOH(mA) Rated Value Typ. Max. VCCE 0.09×IOL (mA) Unit V V V 0 3.0 2.0 -5 -5 When operating When back-up VCCI 3.6 5 5 1 mA 1 10 75 mA 75 See RAM retention power supply current characteristic graph IIH IIL VI=VCCE VI=0V f(XIN)=10.0MHz, When reset µA µA ICC-5V 5 V power supply (Note 1) f(XIN)=10.0MHz, When operating f(XIN)=10.0MHz, When reset f(XIN)=10.0MHz, When operating ICCI-3V 3.3 V power supply (Note 2) 125 100 2000 µA IDDhold Ta=25oC RAM Retention Power Supply Current Ta=85 C VT+ —VTHysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,2,3, RXD0, 1,2,3,4,5, TCLK3—0, JTMS,JTRST, JTDI, TIN0—33, RESET, FP, MOD0, 1 Hysteresis (Note 4) SBI, HREQ o VCCE=5V 1.0 V VT+ —VT- VCCE=5V 0.3 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-5 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition Min. ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value Typ. Max. 10 Unit f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ mA 120 20 50 35 3 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21-6 32170/32174 Group User's Manual (Rev. 2.1) 21 (3) Electrical characteristics when f(XIN) = 8 MHz ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (Referenced to VCCE = 5 V ± 10%, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition Min. VOH VOL VDD Output High Voltage Output Low Voltage RAM Retention Power Supply Voltage High State Input Current Low State Input Current IOH IOL -5mA 5mA VCCE+0.2 ×IOH(mA) Rated Value Typ. Max. VCCE 0.09×IOL (mA) Unit V V V 0 3.0 2.0 -5 -5 When operating When back-up VCCI 3.6 5 5 1 mA 1 10 70 mA 60 See RAM retention power supply current characteristic graph IIH IIL VI=VCCE VI=0V f(XIN)=8.0MHz, When reset µA µA ICC-5V 5 V power supply (Note 1) f(XIN)=8.0MHz, When operating f(XIN)=8.0MHz, When reset f(XIN)=8.0MHz, When operating ICCI-3V 3.3 V power supply (Note 2) 110 100 7500 µA IDDhold Ta=25oC RAM Retention Power Supply Current Ta=125 C VT+ —VTHysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,2,3, RXD0, 1,2,3,4,5, TCLK3—0, JTMS,JTRST, JTDI, TIN0—33, RESET, FP, MOD0,1 Hysteresis (Note 4) SBI, HREQ o VCCE=5V 1.0 V VT+ —VT- VCCE=5V 0.3 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-7 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) (4) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition Min. ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSCVCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value Typ. Max. 10 Unit f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ mA 105 16 50 30 3 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. RAM retention power supply current in a standard sample (reference value) 1000 Ta=125oC 100 Ta=85oC IDD [µA] 10 Ta=25oC 1 1 1.5 2 VDD [V] 3 3.6 4 21-8 32170/32174 Group User's Manual (Rev. 2.1) 21 90 80 70 60 50 40 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) Standard sample’s ICCI-3V temperature characteristics (when operating: f = 8 MHz, 10 MHz) ICCI(mA) 8MHz:25°C 30 20 10 0 2.4 90°C 110°C 130°C 10MHz:25°C 90°C 110°C 130°C 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 VCCI(V) Note: VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V Standard sample’s ICCI-3V temperature characteristics (when reset: f = 8 MHz, 10 MHz) 35 30 25 ICCI(mA) 20 15 8MHz:25°C 90°C 10 110°C 130°C 5 10MHz:25°C 90°C 110°C 0 2.4 130°C 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 VCCI(V) Note: VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V 21-9 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) 21.1.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Condition Min. Rated Value Typ. Max. 50 40 0 70 100 Unit Ifvcc1 lfvcc2 Topr cycle tPRG tBERS FVCC Power Supply Current (when Programming) FVCC Power Supply Current (when Erasing) Flash Rewrite Ambient Temperature mA mA o C Rewrite Durabillity Program Time Block Erase Time times ms ms 1 Page 1 Block 8 50 120 600 21-10 32170/32174 Group User's Manual (Rev. 2.1) 21 21.1.4 A-D Conversion Characteristics ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5V) A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX 10 ±2 14950 Unit — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current VREF=VCC Bits LSB ns 8650 (Note 2) -5 5 µA IIAN Note 1: The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 125°C, f(XIN) = 8.0 MHz Unless Otherwise Noted) Symbol Parameter Condition MIN Rated Value TYP MAX 10 ±2 18687.5 Unit — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current VREF=VCC Bits LSB ns 10812.5 (Note 2) -5 5 µA IIAN Note 1: The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 125°C. 21-11 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) 21.2 ELECTRICAL CHARACTERISTICS (VCCE = 3.3V) 21.2.1 Absolute Maximum Ratings Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Symbol VCCI VDD OSC-VCC FVCC VCCE AVCC VREF Parameter Internal Logic Power Supply Voltage RAM Power Supply Voltage PLL Power Supply Voltage Flash Power Supply Voltage External I/O Buffer Voltage Analog Power Supply Voltage Analog Reference Voltage Xin, VCNT Condition VDD VDD VDD VDD VCCE VCCE VCCE VCCI VCCI VCCI VCCI FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC FVCC=OSC-VCC VREF VREF VREF Rated Value -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 -0.3 to 6.5 -0.3 to OSC-VCC+0.3 Unit V V V V V V V V AVCC AVCC AVCC VI Other Xout -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 V -0.3 to VCCE+0.3 Ta=-40 to 85oC 600 500 -40 to 125 -65 to 150 mW mW o VO Other Pd Power Dissipation Ta=-40 to 125oC TOPR Tstg Operating Ambient Temperature (Note) Storage Temperature C C o Note: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Mitsubishi. 21-12 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) 21.2.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Min. VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note1) Internal Logic Power Supply Voltage (Note2) RAM Power Supply Voltage (Note2) Flash Power Supply Voltage (Note2) Analog Power Supply Voltage (Note1) PLL Power Supply Voltage (Note2) Analog Reference Voltage (Note1) Rated Value Typ. 3.3 3.3 VCCI VCCI VCCE VCCI VCCE Max. 3.6 3.6 VCCI+0.3 VCCI+0.3 VCCE+0.3 VCCI+0.3 VCCE+0.3 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 10 3.6 3.6 3.6 3.6 3.6 Unit 3.0 3.0 3.0 3.0 3.0 3.0 3.0 VCCI-0.3 VCCI-0.3 VCCE-0.3 VCCI-0.3 VCCE-0.3 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT 0.8VCCE 0.43VCCE 0 0 VIL Input Low Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0—P22 (Note 3) High State Average Output Current P0—P22 (Note4) Low State Peak Output Current P0—P22 (Note 3) Low State Average Output Current P0—P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | | ports P2 + P3 | 80 mA 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | 80 mA | ports P18 + P19 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. 21-13 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) Recommended Operating Conditions (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Min. VCCE VCCI VDD FVCC AVCC OSC-VCC VREF External I/O Buffer Power Supply Voltage (Note 1) Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2) Flash Power Supply Voltage (Note 2) Analog Power Supply Voltage (Note 1) PLL Power Supply Voltage (Note 2) Analog Reference Voltage (Note 1) Rated Value Typ. 3.3 3.3 VCCI VCCI VCCE VCCI VCCE Max. 3.6 3.6 VCCI+0.3 VCCI+0.3 VCCE+0.3 VCCI+0.3 VCCE+0.3 VCCE VCCE 0.2VCCE 0.16VCCE -10 -5 10 5 80 15 5 50 8 3.6 3.6 3.6 3.6 3.6 Unit 3.0 3.0 3.0 3.0 3.0 3.0 3.0 VCCI-0.3 VCCI-0.3 VCCE-0.3 VCCI-0.3 VCCE-0.3 0.8VCCE 0.43VCCE 0 V V V V V V V V V V V mA mA mA mA PF PF MHz VIH Input High Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT VIL Input Low Voltage Ports P0—P22, RESET , MOD0, MOD1, FP Ports P0, P1 (external extension/ processor mode only), WAIT 0 IOH(peak) IOH(avg) IOL(peak) IOL(avg) High State Peak Output Current P0—P22 (Note 3) High State Average Output Current P0—P22 (Note 4) Low State Peak Output Current P0—P22 (Note 3) Low State Average Output Current P0—P22 (Note 4) CL Output Load Capacitance JTCK,JTDI,JTMS, JTDO,JTRST Other than above f(XIN) External Clock Input Frequency Note 1: Subject to conditions VCCE AVCC VREF 80 mA Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | | ports P2 + P3 | 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | | ports P18 + P19 | Note 4: The average output current is a value averaged during a 100 ms period. 80 mA 80 mA 21-14 32170/32174 Group User's Manual (Rev. 2.1) 21 21.2.3 DC Characteristics 21.2.3.1 Electrical Characteristics ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition Min. VOH Output High Voltage IOH -2mA VCCE+0.5 ×IOH(mA) Rated Value Typ. Max. VCCE 0.225× IOL (mA) VCCI V 2.0 -5 -5 3.6 5 5 76 mA 76 See RAM retention power supply current characteristic graph Unit V VOL Output Low Voltage IOL 2mA 0 3.0 V VDD RAM Retention Power Supply Voltage High State Input Current Low State Input Current Power supply current when reset (Note 1) When operating When back-up VI=VCCE VI=0V f(XIN)=10.0MHz, When reset IIH IIL ICCres ICC µA µA Power supply current when operating f(XIN)=10.0MHz, (Note 2) When operating RAM Retention Power Supply Current Hysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,4,5, RXD0,1,2,3,4,5, TCLK3—0, JTMS, JTRST, JTDI, TIN0—33, RESET, FP, MOD0,1 Hysteresis (Note 4) SBI, HREQ Ta=25oC Ta=85oC 132 100 2000 µA IDDhold VT+ —VT- VCCE=3.3V 0.65 V VT+ —VT- VCCE=3.3V 0.2 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-15 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Condition Min. ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value Typ. Max. 7 Unit f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ mA 120 20 50 35 2 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21-16 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (3) Electrical characteristics when f(XIN) = 8 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition Min. VOH Output High Voltage IOH -2mA VCCE+0.5 ×IOH(mA) Rated Value Typ. Max. VCCE 0.225× IOL (mA) VCCI V 2.0 -5 -5 3.6 5 5 71 mA 61 See RAM retention power supply current characteristic graph Unit V VOL Output Low Voltage IOL 2mA 0 3.0 V VDD RAM Retention Power Supply Voltage High State Input Current Low State Input Current Power supply current when reset (Note 1) When operating When back-up VI=VCCE VI=0V f(XIN)=8.0MHz, When reset IIH IIL ICCres ICC µA µA Power supply current when operating f(XIN)=8.0MHz, (Note 2) When operating RAM Retention Power Supply Current Hysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,4,5, RXD0,1,2,3,4,5, TCLK3—0, JTMS, JTRST, JTDI, TIN0—33, RESET, FP, MOD0,1 Hysteresis (Note 4) SBI, HREQ Ta=25oC Ta=125 C o 117 100 7500 µA IDDhold VT+ —VT- VCCE=3.3V 0.65 V VT+ —VT- VCCE=3.3V 0.2 V Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. ____________ Note 3: All these pins except RESET serve dual-functions. __________ Note 4: The HREQ pin serves dual-functions. 21-17 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) (2) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition Min. ICCE ICCI OSC-ICC FICC IDD IAVCC IVREF VCCE power supply current when operating VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Rated Value Typ. Max. 7 Unit f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz f(XIN)=8.0MHz mA 105 16 50 30 2 1 mA mA mA mA mA Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. 21.2.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Condition Min. Ifvcc1 lfvcc2 Topr cycle tPRG tBERS FVCC Power Supply Current (when Programming) FVCC Power Supply Current (when Erasing) Flash Rewrite Ambient Temperature Rated Value Typ. Max. 50 40 0 70 100 Unit mA mA o C Rewrite Durabillity Program Time Block Erase Time times ms ms 1 Page 1 Block 8 50 120 600 21-18 32170/32174 Group User's Manual (Rev. 2.1) 21 21.2.4 A-D Conversion Characteristics ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics (VCCE = 3.3V) A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 3.3 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Symbol Parameter Condition Min. Rated Value Typ. Max. 10 ±4 14950 Unit — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current VREF=VCC Bits LSB ns 8650 (Note 2) -5 5 µA IIAN Note 1: The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = 25°C, f(XIN) = 8.0 MHz Unless Otherwise Noted) Symbol Parameter Condition Min. Rated Value Typ. Max. 10 ±4 18687.5 Unit — — TCONV Resolution Absolute Accuracy (Note 1) During nomal mode Conversion During doubleTime speed mode Analog Input Leakage Current VREF=VCC Bits LSB ns 10812.5 (Note 2) -5 5 µA IIAN Note 1: The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2: This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 125°C. 21-19 32170/32174 Group User's Manual (Rev. 2.1) 21 21.3 AC Characteristics 21.3.1 Timing Requirements • • ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Unless otherwise noted, timing conditions are VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF (however, 80 pF for JTAG-related). In cases where the output load capacitance varies, they may deviate from the rated switching characteristics. (1) Input/output ports Symbol Parameter Condition Rated Value Min. tsu(P-E) th(E-P) Port Input Setup Time Port Input Hold Time 100 0 Max. Unit See Figure 21.3.1 ns ns 1 2 (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Condition Rated Value Min. tsu(D-CLK) th(CLK-D) Max. Unit See Figure 21.3.2 ns ns RxD Input Setup Time RxD Input Hold Time 150 50 4 5 b) CSIO mode, with external clock selected Symbol Parameter Condition Rated Value Min. tc(CLK) tw(CLKH) tw(CLKL) tsu(D-CLK) th(CLK-D) Max. Unit See Figure 21.3.2 ns ns ns ns ns CLK Input Cycle Time CLK Input High Pulse Width CLK Input Low Pulse Width RxD Input Setup Tim RxD Input Hold Time 640 300 300 60 100 7 8 9 10 11 (3) SBI Symbol Parameter Condition Rated Value Min. tw(SBIL) Max. Unit See Figure 21.3.3 ns SBI Input Pulse Width 5 tc(BCLK) 2 13 21-20 32170/32174 Group User's Manual (Rev. 2.1) 21 (4) TINi (i=0-33), TCLKi (i=0-3) Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value Min. Max. Unit See Figure 21.3.5 ns tw(TINi) TINi, TCLKi Input Pulse Width 7 tc(BCLK) 2 14 (5) Read and write timing Symbol Parameter Condition Rated Value Min. tsu(D-BCLKH) th(BCLKH-D) Data Input Setup Time before BCLK Data Input Hold Time after BCLK 26 0 26 0 26 0 3 tc(BCLK) -23 2 Unit Figure 21.3.6 21.3.7 21.3.8 See Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 32 33 34 78 79 43 44 45 51 56 57 68 80 81 tsu(WAITL-BCLKH) WAIT Input Setup Time before BCLK th(BCLKH-WAITL) WAIT Input Hold Time after BCLK tsu(WAITH-BCLKH) WAIT Input Setup Time before BCLK th(BCLKH-WAITH) tw(RDL) tsu(D-RDH) th(RDH-D) tw(BLWL) tw(BHWL) td(RDH-BLWL) td(RDH-BHWL) td(BLWH-RDL) td(BHWH-RDL) tw(WRL) td(RDH-BLEL) td(RDH-BHEL) td(BLEH-RDL) td(BHEH-RDL) WAIT Input Hold Time after BCLK Read Low Pulse Width Data Input Setup Time before Read Data Input Hold Time after Read Write Low Pulse Width (Byte write mode) Write Delay Time after Read Read Delay Time after Write Write Low Pulse Width (Byte enable mode) Write Delay Time after Read (Byte enable mode) Read Delay Time after Write (Byte enable mode) 30 0 tc(BCLK) -25 tc(BCLK) 2 tc(BCLK) -10 -10 2 tc(BCLK) -25 tc(BCLK) 2 tc(BCLK) -10 -10 2 21-21 32170/32174 Group User's Manual (Rev. 2.1) 21 (6) Bus arbitration timing Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value Min. Max. Unit See Figure 21.3.9 ns ns tsu(HREQL-BCLKH) HREQ Input Setup Time before BCLK th(BCLKH-HREQL) HREQ Input Hold Time after BCLK 27 0 35 36 (7) Input transition time on JTAG pin Rated Value Symbol Condition Min. Other than JTRST pin Max. See Unit Figure 21.3.10 tr Input Rising Transition Time (JTCK,JTDI,JTMS,JTDO) When using TAP When not using TAP 10 ns 10 2 ns ms ns 58 JTRST pin Other than JTRST pin (JTCK,JTDI,JTMS,JTDO) 10 tf Input Falling Transition Time JTRST pin When using TAP When not using TAP 59 10 2 ns ms Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF. (8) JTAG interface timing Rated Value Symbol tc(JTCK) tw(JTCKH) tw(JTCKL) tsu(JTDI-JTCK) th(JTCK-JTDI) td(JTCK-JTDOV) td(JTCK-JTDOX) tW(JTRST) Condition Min. JTCK Input Cycle Time JTCK Input High Pulse Width JTCK Input Low Pulse Width JTDI, JTMS Input Setup Time JTDI, JTMS Input Hold Time JTDO Output Delay Time after JTCK Fall JTDO Output Hi-Z Delay Time after JTCK Fall TRST Input Low Pulse Width tc(JTCK) 100 40 40 15 20 40 40 Max. See Unit Figure 21.3.11 ns ns ns ns ns ns ns ns 60 61 62 63 64 65 66 67 Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF. 21-22 32170/32174 Group User's Manual (Rev. 2.1) 21 (9) RTD timing ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Rated Value Symbol Parameter Min. tc(RTDCLK) tw(RTDCLKH) tw(RTDCLKL) td(RTDCLKH-RTDACK) tv(RTDCLKL-RTDACK) td(RTDCLKH-RTDTXD) th(RTDCLKH-RTDRXD) tv(RTDRXD-RTDCLKL) Max. See Unit Figure 21.3.12 ns ns ns RTDCLK Input Cycle Time RTDCLK Input High Pulse Width RTDCLK Input Low Pulse Width RTDACK Delay Time after RTDCLK Input Valid RTDACK Time after RTDCLK input RTDTXD Delay Time after RTDCLK Input RTDRXD Input Hold Time RTDRXD Input Setup Time 500 230 230 160 160 1 2 90 83 84 85 86 87 88 89 ns ns ns ns ns tc(RTDCLK)+160 50 60 21-23 32170/32174 Group User's Manual (Rev. 2.1) 21 21.3.2 Switching Characteristics (1) Input/output ports Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value Min. Max. 100 Unit See Figure 21.3.1 ns td(E-P) Port Data Output Delay Time 3 (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Condition Rated Value Min. td(CLK-D) th(CLK-D) TxD Output Delay Time TxD Hold Time 0 Max. 60 Unit See Figure 21.3.2 ns ns 6 90 b) CSIO mode, with external clock selected Symbol Parameter Condition Rated Value Min. td(CLK-D) TxD Output Delay Time Max. 160 Unit See Figure 21.3.2 ns 12 (3) TOi (i=0-44) Symbol Parameter Condition Rated Value Min. td(BCLK-TOi) TOi Output Delay Time Max. 100 Unit See Figure 21.3.4 ns 15 21-24 32170/32174 Group User's Manual (Rev. 2.1) 21 (4) Read and write timing Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Condition Rated Value Min. Max. tc(Xin) 2 tc(BCLK) -5 2 tc(BCLK) -5 2 Unit See Figure 21.3.6 21.3.7 21.3.8 tc(BCLK) tw(BCLKH) tw(BCLKL) td(BCLKH-A) td(BCLKH-CS) tv(BCLKH-A) tv(BCLKH-CS) td(BCLKL-RDL) tv(BCLKH-RDL) td(BCLKL-BLWL) td(BCLKL-BHWL) tv(BCLKL-BLWL) td(BCLKL-D) tv(BCLKL-BHWL) tv(BCLKH-D) tpzx(BCLKL-DZ) tpxz(BCLKH-DZ) td(A-RDL) td(CS-RDL) tv(RDH-A) tv(RDH-CS) tpzx(RDH-DZ) td(A-BLWL) td(A-BHWL) td(CS-BLWL) td(CS-BHWL) tv(BLWH-A) tv(BHWH-A) tv(BLWH-CS) tv(BHWH-CS) BCLK Output Cycle Time BCLK Output High Pulse Width BCLK Output Low Pulse Width Address Delay Time after BCLK Chip Select Delay Time after BCLK Valid Address Time after BCLK Valid Chip Select Time after BCLK Read Delay Time after BCLK Valid Read Time after BCLK Write Delay Time after BCLK Valid Write Time after BCLK Data Output Delay Time after BCLK Valid Data Output Time after BCLK Data Output Enable Time after BCLK Data Output Disable Time after BCLK Address Delay Time before Read Chip Select Delay Time before Read Valid Address Time after Read Valid Chip Select Time after Read Data Output Enable Time after Read Address Delay Time before Write (Byte write mode) Chip Select Delay Time before Write (Byte write mode) Valid Address Time after Write (Byte write mode) Valid Chip Select Time after Write (Byte write mode) tc(BCLK) -15 2 tc(BCLK) -15 2 ns ns ns 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 39 40 41 42 46 47 48 49 50 24 24 -11 -11 10 -12 11 -12 18 -16 -19 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0 tc(BCLK) 2 tc(BCLK) -15 2 tc(BCLK) -15 2 tc(BCLK) -15 2 tc(BCLK) -15 2 ns ns ns 21-25 32170/32174 Group User's Manual (Rev. 2.1) 21 Symbol Parameter ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics Read and write timing (continued from the preceding page) Condition Rated Value Min. td(BLWL-D) td(BHWL-D) tv(BLWH-D) tv(BHWH-D) tpxz(BLWH-DZ) tpxz(BHWH-DZ) td(A-WRL) td(CS-WRL) tv(WRH-A) tv(WRH-CS) td(BLE-WRL) td(BHE-WRL) tv(WRH-BLE) tv(WRH-BHE) td(WRL-D) Data Output Delay Time after Write (Byte write mode) Valid Data Output Time after Write (Byte write mode) Data Output Disable Time after Write (Byte write mode) Address Delay Time before Write (Byte enable mode) Chip Select Delay Time before Write (Byte enable mode) Valid Address Time after Write (Byte enable mode) Valid Chip Select Time after Write (Byte enable mode) Byte enable delay time before write (Byte enable mode) Byte enable delay time after write (Byte enable mode) Data Output Delay Time after Write (Byte enable mode) Valid Data Output Time after Write (Byte enable mode) Data output disable time after write (Byte enable mode) Read high-level pulse width tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 tc(BCLK) 2 Unit Figure 21.3.6 21.3.7 21.3.8 See Max. 15 -13 tc(BCLK) 2 ns ns +5 ns ns ns ns ns ns ns 52 53 54 69 70 71 72 73 74 75 76 77 55 -15 -15 -15 -15 -15 -15 15 -13 tc(BCLK) 2 ns ns +5 ns tv(WRH-D) tpxz(WRH-DZ) tw(RDH) -3 ns (5) Bus arbitration Symbol Parameter Condition Rated Value Min. td(BCLKL-HACKL) tv(BCLKL-HACKL) HACK Delay Time after BCLK Valid HACK Time after BCLK -11 Max. 29 Unit See Figure 21.3.9 ns ns 37 38 21-26 32170/32174 Group User's Manual (Rev. 2.1) 21 21.3.3 AC Characteristics ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 0.8VCCE BCLK 1 Port input tsu(P-E) 0.2VCCE 2 th(E-P) 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE 3 td(E-P) 0.8VCCE 0.2VCCE Port output Figure 21.3.1 Input/Output Port Timing a) CSIO mode, with internal clock selected CLKOUT 6 td(CLK-D) TxD 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE 90 4 tsu(D-CLK) RxD 0.8VCCE 0.2VCCE 5 th(CLK-D) 0.8VCCE 0.2VCCE b) CSIO mode, with external clock selected 7 tc(CLK) CLKIN 12 td(CLK-D) 9 tw(CLKL) TxD 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE 8 tw(CLKH) 10 tsu(D-CLK) RxD 0.8VCCE 0.2VCCE 11 th(CLK-D) 0.8VCCE 0.2VCCE Figure 21.3.2 Serial I/O Timing 21-27 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics SBI 0.2VCCE 0.2VCCE 13 tw(SBIL) Figure 21.3.3 SBI Timing BCLK 0.2VCCE 15 td(BCLK-TOi) 0.8VCCE 0.2VCCE TOi Figure 21.3.4 TOi Timing 14 tw(TINi) 0.8VCCE 0.2VCCE TINi, TCLKi 0.8VCCE 0.2VCCE Figure 21.3.5 TINi, TCLKi Timing 21-28 32170/32174 Group User's Manual (Rev. 2.1) 21 16 tc(BCLK) 17 tw(BCLKH) ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 18 tw(BCLKL) BCLK 0.43VCCE 0.16VCCE 20 td(BCLKH-CS) 19 Address (A11—A30) CS0, CS1 40 td(CS-RDL) 39 td(A-RDL) 43 tw(RDL) td(BCLKH-A) 22 tv(BCLKH-CS) 23 td(BCLKL-RDL) 21 tv(BCLKH-A) 0.43VCCE 0.16VCCE 41 tv(RDH-A) 42 tv(RDH-CS) RD 24 tv(BCLKH-RDL) 0.43VCCE 55 tw(RDH) td(BLWH-RDL) 0.16VCCE 57 td(BHWH-RDL) Data input (D0—D15) 44 tsu(D-RDH) 45 th(RDH-D) 0.43VCCE 0.16VCCE 31 tsu(D-BCLKH) 32 th(BCLKH-D) td(RDH-BLWL) 56 td(RDH-BHWL) BLW BHW 0.43VCCE 0.16VCCE 29 tpzx(BCLKL-DZ) 30 tpxz(BCLKH-DZ) 46 tpzx(RDH-DZ) 0.43VCCE 0.16VCCE Data output (D0—D15) 78 tsu(WAITH-BCLKH) 33 tsu(WAITL-BCLKH) 34 th(BCLKH-WAITL) 0.16VCCE 0.43VCCE 0.43VCCE 79 th(BCLKH-WAITH) WAIT 0.16VCCE Note 1: Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. Note 2: Input and output signals are determined high or low with respect to TTL level. Figure 21.3.6 Read Timing 21-29 32170/32174 Group User's Manual (Rev. 2.1) 21 16 tc(BCLK) 17 tw(BCLKH) ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 18 tw(BCLKL) BCLK 0.43VCCE 0.16VCCE 0.16VCCE 20 td(BCLKH-CS) 19 td(BCLKH-A) Address (A11-A30) CS0, CS1 56 td(RDH-BHWL) td(RDH-BLWL) 22 tv(BCLKH-CS) 21 tv(BCLKH-A) 0.43VCCE 0.16VCCE 23 td(BCLKL-RDL) RD 0.43VCCE 0.16VCCE 48 td(CS-BHWL) 47 td(A-BHWL) td(A-BLWL) td(CS-BLWL) 51 tw(BHWL) 0.43VCCE 0.16VCCE tw(BLWL) 57 td(BHWH-RDL) td(BLWH-RDL) BLW BHW 0.16VCCE 25 td(BCLKL-BLWL) td(BCLKL-BHWL) 26 tv(BCLKL-BHWL) tv(BCLKL-BLWL) 50 tv(BHWH-CS) 49 tv(BLWH-A) tv(BHWH-A) tpxz(BLWH-DZ) tv(BLWH-CS) 54 tpxz(BHWH-DZ) 53 tv(BHWH-D) 28 tv(BCLKH-D) tv(BLWH-D) td(BLWL-D) 52 td(BHWL-D) Data output (D0-D15) 29 tpzx(BCLKL-DZ) 27 td(BCLKL-D) 0.43VCCE 0.16VCCE 30 tpxz(BCLKH-DZ) 78 tsu(WAITH-BCLKH) 79 th(BCLKH-WAITH) 0.43VCCE WAIT 0.16VCCE 0.16VCCE 0.43VCCE 33 tsu(WAITL-BCLKH) 34 th(BCLKH-WAITL) Note 1: Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. Note 2: Input and output signals are determined high or low with respect to TTL level. Figure 21.3.7 Write Timing 21-30 32170/32174 Group User's Manual (Rev. 2.1) 21 Address (A11-A30) CS0, CS1 0.43VCCE 0.16VCCE ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 0.43VCCE 0.16VCCE 80 td(RDH-BHEL) 0.43VCCE td(RDH-BLEL) 81 td(BHEH-RDL) td(BLEH-RDL) RD 0.16VCCE 70 td(CS-WRL) 69 td(A-WRL) 68 tw(WRL) 72 tv(WRH-CS) 71 tv(WRH-A) WR 0.16VCCE 0.16VCCE 0.43VCCE 73 td(BHEL-WRL) td(BLEL-WRL) tv(WRH-BLEL) 74 tv(WRH-BHEL) 0.43VCCE BLE , BHE 0.16VCCE 0.16VCCE 75 td(WRL-D) 77 tpxz(WRH-DZ) 76 tv(WRH-D) Data output (D0-D15) 0.43VCCE 0.16VCCE Note 1: Stipulated values are guaranteed values when the test pin load capacitance CL = 15 to 50 pF. Note 2: Input and output signals are determined high or low with respect to TTL level. Figure 21.3.8 Write Timing (Byte enable mode) BCLK 0.43VCCE 0.16VCCE 35 tsu(HREQL-BCLKH) HREQ 0.16VCCE 0.16VCCE 36 th(BCLKH-HREQL) 38 tv(BCLKL-HACKL) HACK 0.16VCCE 0.16VCCE 37 td(BCLKL-HACKL) Figure 21.3.9 Bus Arbitration Timing 21-31 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 58 tr JTCK,JTDI JTMS,JRST 0.8VCCE 0.2VCCE 59 tf 0.8VCCE 0.2VCCE Note: Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 21.3.10 Input Transition Time on JTAG pins 60 tc(JTCK) 61 tw(JTCKH) 62 tw(JTCKL) JTCK 0.5VCCE 63 tsu(JTDI-JTCK) 64 th(JTCK-JTDI) 0.8VCCE 0.2VCCE Data input, (JTDI) JTMS 0.8VCCE 0.2VCCE 65 td(JTCK-JTDOV) 66 td(JTCK-JTDOX) 0.8VCCE 0.2VCCE Data output, (JTDO) 0.8VCCE 0.2VCCE 67 tw(JTRST) JTRST 0.2VCCE 0.2VCCE Note: Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 21.3.11 JTAG Interface Timing 21-32 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics 90 83 tc(RTDCLK) 84 tw(RTDCLKL) 0.5VCCE 0.5VCCE 0.5VCCE tw(RTDCLKH) RTDCLK 0.5VCCE 85 RTDACK td(RTDCLKH-RTDACK) 86 tv(RTDCLKH-RTDACK) 0.8VCCE 0.2VCCE 87 td(RTDCLKH-RTDTXD) RTDTXD 0.8VCCE 0.2VCCE 88 RTDRXD th(RTDCLKH-RTDRXD) 89 tsu(RTDRXD-RTDCLKL) 0.8VCCE 0.2VCCE 0.8VCCE 0.2VCCE Figure 21.3.12 RTD Timing 21-33 32170/32174 Group User's Manual (Rev. 2.1) 21 ELECTRICAL CHARACTERISTICS 21.3 AC Characteristics ❊ This is a blank page. ❊ 21-34 32170/32174 Group User's Manual (Rev. 2.1) CHAPTER C HAPTER 22 TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics 22 22.1 A-D Conversion Characteristics (1) Test conditions • Ta = -40°C, 27°C, 125°C • Test voltage (VCC) = 5.12 V • Double-speed mode TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics (2) Measured value (Reference value) Ta = -40°C Ta = 27°C Ta = 125°C Vertical axis : Conversion error Horizontal axis : Analog input voltage ( 5.12 × N/1024 [V] ) 22-2 32170/32174 Group User's Manual (Rev. 2.1) APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing Appendix 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing Appendix 1.1 Dimensional Outline Drawing (1) 240-pin QFP 240P6Y-A MMP JEDEC Code – HD D Weight(g) Lead Material Cu Alloy Plastic 240pin 32✕32mm body QFP MD EIAJ Package Code QFP240-P-3232-0.50 e 240 1 181 180 b2 I2 Recommended Mount Pad HE Symbol A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME 60 61 120 121 e F A L1 y b L x M Detail F Dimension in Millimeters Min Nom Max – – 4.1 0.35 0.45 0.25 – – 3.6 0.15 0.2 0.3 0.13 0.15 0.2 31.9 32.0 32.1 31.9 32.0 32.1 0.5 – – 34.4 34.6 34.8 34.4 34.6 34.8 0.3 0.5 0.7 1.3 – – – – 0.08 0.1 – – 0° 10° – 0.225 – – 1.2 – – 32.6 – – – – 32.6 E A2 Appendix 1-2 A1 32170/32174 Group User's Manual (Rev. 2.1) c ME Appendix 1 (2) 255-pin FBGA MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing 255F7F EIAJ Package Code — JEDEC Code — Weight(g) 255pin 17×17mm body FBGA Under Development 17TYP (16.6) 0.20 C A 0.35–0.05 0.8TYP 0.8×19=15.2 A Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.8×19=15.2 17TYP (16.6) B 0.20 C B ✕4 0.2 C 255-φ0.45–0.05 1.2MAX φ0.08 M C AB Ni/Au plating Metal wiring (Cu pattern) 0.32mm via [Package side] Solder resist [P.C.B.side] 0.3mm Cu pattern Recommended Mount Pad 255FBGA Note: 255FBGA is currently under development. Appendix 1-3 0.8TYP 0.1 C 32170/32174 Group User's Manual (Rev. 2.1) Appendix 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing ❊ This is a blank page. ❊ Appendix 1-4 32170/32174 Group User's Manual (Rev. 2.1) APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32170/32174 Instruction Processing Time Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32170/32174 Instruction Processing Time Appendix 2.1 32170/32174 Instruction Processing Time For the M32R, the number of instruction execution cycles in E stage normally represents its instruction processing time. However, depending on pipeline operation, other stages may affect the instruction processing time. Especially when a branch instruction is executed, the processing time in IF (instruction fetch) and D (decode) stages, not just E (execution) stage, must also be taken into account. The table below shows the instruction processing time in each pipelined stage of the M32R. Table 2.1.1 Instruction Processing Time of Each Pipeline Stage Number of execution cycles in each stage (Note 1) Instruction Load instructions (LD, LDB, LDUB, LDH, LDUH, LOCK) Store instructions (ST,STB,STH,UNLOCK) Multiply instruction (MUL) Divide/remainder instructions (DIV, DIVU,REM,REMU) Other instructions (including those for DSP function) IF R R R R R D 1 1 1 1 1 E 1 1 3 37 1 MEM R W WB 1 1 1 1 Note: For R and W, refer to the calculation methods described in the next page. Appendix 2-2 32170/32174 Group User's Manual (Rev. 2.1) Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32170/32174 Instruction Processing Time The following shows the number of memory access cycles in IF and MEM stages. Shown here are the minimum number of cycles required for memory access. Therefore, these values do not always reflect the number of cycles required for actual memory or bus access. In write access, for example, although the CPU finishes the MEM stage by only writing to the write buffer, this operation actually is followed by a write to memory. Depending on the memory or bus state before or after the CPU requested a memory access, the instruction processing may take more time than the calculated value. s R (read cycle) Cycles When existing in instruction queue ............................................................................. 1 When reading internal resource (ROM, RAM) ........................................................... 1 When reading internal resource (SFR)(byte, halfword) .............................................. 2 When reading internal resource (SFR)(word) ............................................................ 4 When reading external memory (byte, halfword) ....................................................... 5 (Note) When reading external memory (word) ...................................................................... 9 (Note) When successively fetching instructions from external memory ................................ 8 (Note) s W (write cycle) Cycles When writing to internal resource (RAM) ................................................................... 1 When writing to internal resource (SFR)(byte, halfword) ........................................... 2 When writing to internal resource (SFR)(word) .......................................................... 4 When writing to external memory (byte, halfword) ..................................................... 4 (Note) When writing to external memory (word) .................................................................... 8 (Note) Note: This applies for external access with one wait cycle. (When the 32170/32174 accesses external circuits, it requires at least one wait cycle inserted.) Appendix 2-3 32170/32174 Group User's Manual (Rev. 2.1) Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32170/32174 Instruction Processing Time ❊ This is a blank page. ❊ Appendix 2-4 32170/32174 Group User's Manual (Rev. 2.1) APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Appendix 3 Appendix 3.1 Precautions about Noise PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system with these measures incorporated be fully evaluated before it can actually be put to use. Appendix 3.1.1 Reduction of Wiring Length Wiring on the board may serve as an antenna to draws noise into the microcomputer. Shorter the total wiring length, the smaller the possibility of drawing noise into the microcomputer. ____________ (1) Wiring of the RESET pin _____________ Reduce the length of wiring connecting to the RESET pin. Especially when connecting a _____________ capacitor between the RESET and VSS pins, make sure it is wired to each pin in the shortest distance possible (within 20 mm). Reset is a function to initialize the internal logic of the microcomputer. The pulse width applied _____________ to the RESET pin is important and is therefore stipulated as part of timing requirements. If a _____________ pulse in width shorter than the stipulated duration (i.e., noise) is applied to the RESET pin, the microcomputer will not be reset for a sufficient duration of time and come out of reset before its internal logic is fully initialized, causing the program to malfunction. Noise Reset circuit VSS Reset circuit VSS RESET# VSS RESET# VSS Long wiring Short wiring ____________ Figure 3.1.1 Example Wiring of the RESET Pin Appendix 3-2 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 (2) Wiring of clock input/output pins PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Use as much thick and short wiring as possible for connections to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its grounding lead wire and the OSCVSS pin on the microcomputer are connected in the shortest distance possible (within 20 mm). Also, make sure the VSS pattern used for clock oscillation is a large ground plane and is connected to GND. The microcomputer operates synchronously with the clock generated by an oscillator circuit. Inclusion of noise on the clock input/output pins causes the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. Furthermore, if a noise-induced potential difference exists between the microcomputer's VSS level and that of the oscillator, the clock fed into the microcomputer may not be an exact clock. Noise OSC-VSS XIN XOUT VSS OSC-VSS XIN XOUT VSS Thin and long wiring Thick and short wiring Figure 3.1.2 Example Wiring of Clock Input/Output Pins Appendix 3-3 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 (3) Wiring of the VCNT pin PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Use as much thick and short wiring as possible for connections to the VCNT pin. When connecting a capacitor to VCNT, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible. Also, make sure the VSS pattern used for VCNT is a large ground plane and is connected to GND. The external circuit inserted for the VCNT pin plays the role of a low-pass filter that stabilizes the PLLís internal voltage and eliminates noise. If noise exceeding the limit of the low-pass filter penetrates into the wiring, the internal circuit may be disturbed by that noise and become unable to produce a precise clock, causing the microcomputer to operate erratically or get out of control. Noise OSC-VSS VCNT VSS OSC-VSS VCNT VSS Thin and long wiring Thick and short wiring Figure 3.1.3 Example Wiring of the VCNT Pin (4) Wiring of the operation mode setup pins When connecting operation mode setup pins and the VCC or VSS pin, make sure they are wired in the shortest distance possible. The levels of operation mode setup pins affect the microcomputer's operation mode. When connecting operation mode setup pins and the VCC or VSS pin, be careful that no noiseinduced potential difference will exist between operation mode setup pins and the VCC or VSS pin. This is because the presence of such a potential difference makes operation mode instable, which may result in the microcomputer operating erratically or getting out of control. Noise Operation mode setup pins Operation mode setup pins VSS VSS Long wiring Short wiring Figure 3.1.4 Example Wiring of the MOD0 and MOD1 Pins Appendix 3-4 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Appendix 3.1.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between the VSS and VCC lines. At this time, make sure the requirements described below are met. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the same. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the shortest distance possible. • The VSS and VCC lines have a greater wiring width than that of all other signal lines. VCC Chip VCC VSS Chip VSS VCC VSS Figure 3.1.5 Example of a Bypass Capacitor Inserted between VSS and VCC Lines Appendix 3-5 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Appendix 3.1.3 Processing Analog Input Pin Wiring Insert a resistor of about 100 to 500Ω in series to the analog signal line connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible. The signal fed into the analog input pin (e.g., A-D converter input pin) normally is an output signal from a sensor. In many cases, a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted, so that wiring to the analog input pin is inevitably long. Because a long wiring serves as an antenna which draws noise into the microcomputer, the signal fed into the analog input pin tends to be noise-ridden. Furthermore, if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin, noise ridding on the ground line may penetrate into the microcomputer via the capacitor. Noise Sensor Microcomputer Analog input pin AVSS Figure 3.1.6 Example of a Resistor and Capacitor Inserted for the Analog Signal Line Appendix 3-6 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Appendix 3.1.4 Consideration about the Oscillator and VCNT Pin The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it unsusceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines that conduct a large current exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator and VCNT pin) as possible. Also, make sure the circuit is protected with a GND pattern. Systems using a microcomputer have signal lines to control a motor, LED or thermal head, for example. When a large current flows in these signal lines, it generates noise due to mutual inductance (M). Noise is generated by mutual inductance between the microcomputer and an adjacent signal line M OSC-VSS XIN Large current XOUT VCNT GND A signal line that conducts a large current exists near the microcomputer. M OSC-VSS XIN XOUT Large current VCNT GND Locate a signal line that conducts a large current apart from the microcomputer. Figure 3.1.7 Example Wiring of a Large-current Signal Line Appendix 3-7 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure rapidly level-changing signal lines will not intersect clock-related signal lines and other noise-sensitive signal lines. Rapidly level-changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls. Especially if they intersect clock-related signal lines, they will cause the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. High-speed serial I/O High-speed timer input/output, etc. XIN XOUT VCNT Signal line intersecting the clock-related and other signal lines High-speed serial I/O High-speed timer input/output, etc. XIN XOUT VCNT Locate the signal line away from the clock-related and other signal lines Figure 3.1.8 Example Wiring of a Rapidly Level-Changing Signal Line Appendix 3-8 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise (3) Protection against signal lines that are the source of strong noise Do not use any pin that will probably be subject to strong noise for an adjacent port near the oscillator and VCNT pins. If the pin can be left unused, set it for input and connect to GND via a resistor, or fix it to output and leave open. If the pin needs to be used, it is recommended that it be used for input-only. For protection against a still stronger noise source, set the adjacent port for input and connect to GND via a resistor, and use those that belong to the same port group as much for input-only as possible. If greater stability is required, do not use those that belong to the same port group and set them for input and connect to GND via a resistor. If they need to be used, insert a limiting resistor for protection against noise. If the ports or pins adjacent to the oscillator and VCNT pins operate at high speed or are exposed to strong noise from an external source, noise may affect the oscillator circuit, causing its oscillation to become instable. XIN XOUT Oscillator External noise or switching noise Noise VCNT Adjacent pin/peripheral pin (set for output) Fast switching Switching noise from an output pin applied directly to the port Adjacent pin/peripheral pin (set for input) Noise External noise from an input pin applied directly to the port Figure 3.1.9 Example Processing of a Noise-Laden Pin Appendix 3-9 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for output) Method for limiting the effect of noise in output mode Adjacent pin/peripheral pin (set for input) Noise Method for limiting noise with a resistor Noise Adjacent pin/peripheral pin (set for output) Fast switching Method for limiting switching noise with a resistor Figure 3.1.10 Example Processing of Pins Adjacent to the Oscillator and VCNT Pins Appendix 3-10 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 Appendix 3.1.5 Processing Input/Output Ports PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100 Ω (or more) in series to input/output ports. Software measures • For input ports, read out data in a program two or more times to verify that levels coincide. • For output ports, rewrite the data register at certain intervals, because there is a possibility of the output data being inverted by noise. • Rewrite the direction register at certain intervals. Noise Data bus Direction register Noise Data register Input/output port Figure 3.1.11 Example Processing of Input/Output Ports Appendix 3-11 32170/32174 Group User's Manual (Rev. 2.1) Appendix 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise ❊ This is a blank page. ❊ Appendix 3-12 32170/32174 Group User's Manual (Rev. 2.1) APPENDIX 4 PROCESSING OF UNUSED PINS Appendix 4.1 Example for Processing Unused Pins Appendix 4 PROCESSING OF UNUSED PINS Appendix 4.1 Example for Processing Unused Pins Appendix 4.1 Example for Processing Unused Pins An example for processing unused pins is shown below. (1) When operating in single-chip mode Table A4.1.1 Example for Processing Unused Pins when Operating in Single-chip Mode Pin name Input/output ports (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, P61-P67 (Note 2), P70-P77, P82-P87, P93-P97, P100-P107, P110-P117, P124-P127, P130-P137, P140-P147, P150-P157, P160-P167, P172-P177, P180-P187, P190-P197, P200-P203, P210-P217, P220-P225 (Note 3) XOUT (Note 4) A-D converter AD0IN0-AD0IN15, AD1IN0-AD1IN15, AVREF0, AVREF1, AVSS0, AVSS1 AVCC0, AVCC1 JTAG JTOD, JTMS, JTDI JTRST DBI (Note 5) TRCLK, TRSYNC, TRDATA [0:7], EVENT [0:1] (Note 5) Processing Set these pins for input mode and connect them to VSS via 1 kΩ to 10 kΩ resistors (pulldown). Leave these pins open. Connect these pins to VSS. Connect these pins to VCCE. Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Connect this pin to VSS (pulldown) via a 0 to 100 kW resistor. Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Leave these pins open. Note 1: After reset, the input/output ports are set for input by default. ___ Note 2: P64 is used exclusively for SBI input. Note 3: P221 is used exclusively for CAN input. Note 4: This applies when an external clock is fed to XIN. Note 5: This applies when using 255FBGA (not available when using 240QFP). Appendix 4-2 32170/32174 Group User's Manual (Rev. 2.1) Appendix 4 PROCESSING OF UNUSED PINS Appendix 4.1 Example for Processing Unused Pins (2) When operating in external extension mode or processor mode Table A4.1.2 Example for Processing Unused Pins when Operating in External Extension or Processor Mode Pin name Input/output ports (Note 1) P61-P67 (Note 2), P70-P77, P82-P87, P93-P97, P100-P107, P110-P117, P124-P127, P130-P137, P140-P147, P150-P157, P160-P167, P172-P177, P180-P187, P190-P197, P200-P203, P210-P217, P220-P225 (Note 3) BLW/BLE, BHW/BHE, CS1 XOUT (Note 4) A-D converter AD0IN0-AD0IN15, AD1IN0-AD1IN15, AVREF0, AVREF1, AVSS0, AVSS1 AVCC0, AVCC1 JTAG JTOD, JTMS, JTDI JTRST DBI (Note 5) TRCLK, TRSYNC, TRDATA [0:7], EVENT [0:1] (Note 5) Processing Set these pins for input mode and connect them to VSS via 1 kΩ to 10 kΩ resistors (pulldown). Leave these pins open. Leave these pins open. Connect these pins to VSS. Connect these pins to VCCE. Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Connect this pin to VSS (pulldown) via a 0 to 100 kΩ resistor. Connect these pins to VCCE (pullup) or VSS (pulldown) via 0 to 100 kΩ resistors. Leave these pins open. Note 1: After reset, the input/output ports are set for input by default. ___ Note 2: P64 is used exclusively for SBI input. Note 3: P221 is used exclusively for CAN input. Note 4: This applies when an external clock is fed to XIN. Note 5: This applies when using 255FBGA (not available when using 240QFP). Appendix 4-3 32170/32174 Group User's Manual (Rev. 2.1) Appendix 4 PROCESSING OF UNUSED PINS Appendix 4.1 Example for Processing Unused Pins ❊ This is a blank page. ❊ Appendix 4-4 32170/32174 Group User's Manual (Rev. 2.1) Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/E Series 32170/32174 Group User's MANUAL Rev.2.1 Jan. 16, 2003 Editioned by Committee of editing of Mitsubishi Semiconductor User’s Manual Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2003 MITSUBISHI ELECTRIC CORPORATION M32R Family M32R/ECU Series 32170/32174 Group User’s Manual © 2003 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Jan. 2003. Specifications subject to change without notice.