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32185

32185

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

  • 描述:

    32185 - MCU - Renesas Technology Corp

  • 数据手册
  • 价格&库存
32185 数据手册
REJ09B0235-0110 32 32185/32186 Group Hardware Manual RENESAS MCU M32R FAMILY / M32R/ECU SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 1.10 Revision date: May 15, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. REVISION HISTORY Rev. Date Page 1.00 Dec 26, 2005 1.10 May 15, 2007 – – 5-6 First edition issued Add the 32185 Group 32185/32186 Group Hardware Manual Description Summary Correct notes of IMASK register Incorrect) the Interrupt Request Mask Register (IMASK) in the EIT handler → Correct) the Interrupt Request Mask Register (IMASK) 6-15 6-16 6-17 6-19, 20 6-34 8-39 8-40 8-41 8-42 8-44 Add a description for FAENS Add descriptions for ERASE bit and WRERR bit Add a description for FENTRY bit Correct descriptions of FCNT3 Register Add Figure 6.6.7 Replace Figure 8.7.1 Replace Figure 8.7.2 Replace Figure 8.7.3 Replace Figure 8.7.4 Add a note about the peripheral function input when it is set to the general-purpose port. 10-114, 176 Add descriptions to Reload register updates timing of PWM period 12-22, 23 Add descriptions to OVR bit, PTY bit, and FLM bit 12-45, 62 Add a note about switching from general-purpose port to serial interface pin 13-27 13-31 20-2 20-3 Chap.23 Add a description to RBO bit Add a description to CRS bit Correct Figure 20.1.1 Correct the description of XIN Oscillation Stoppage Detection Circuit Add electrical characteristics of the 32185 Appendix 4 Add correction of notes (REVISION HISTORY-1) Before Use • Guide to Understanding the Register Table (1) Bit number: Indicates a register’s bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is “0” after reset. 1: This bit is “1” after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always “0.” 1: The value read from this bit is always “1.” (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write “0.” 1: To write to this bit, always write “1.” –: Writing to this bit has no effect. (It does not matter whether this bit is set to “0” or “1” by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. (1) XXXRegister(XXX) (5) b0 AAA 0 1 BBB 0 2 CCC 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 (2) (4) (3) b 0 1 2 3–15 Bit name AAA ••• ••• ••• R W W W Function bit bit bit 0: 1: 0: 1: 0: 1: ••• ••• ••• ••• ••• ••• bit bit bit bit bit bit R R BBB ••• ••• ••• ••• ••• ••• ••• ••• ••• CCC ••• ••• ••• ••• ••• ••• ••• ••• ••• R (Note 1) 0 0 No function assigned. Fix to “0.” Note 1: Only writing “0” is effective. Writing “1” has no effect, in which case the bit retains the value it had before the write. (6) (7) • Notation of “L” (signals) The symbol “#” suffixed to the pin (or signal) names means that the pins (or signals) are “L.” Table of Contents CHAPTER 1 OVERVIEW 1.1 Outline of 32185/32186 Group ........................................................................................................... 1-2 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) ............................................................ 1-2 1.1.2 Built-in Multiplier/Accumulator .................................................................................................... 1-3 1.1.3 Built-in Single-precision FPU ...................................................................................................... 1-3 1.1.4 Built-in Flash Memory and RAM ................................................................................................. 1-3 1.1.5 Built-in Clock Frequency Multiplier ............................................................................................. 1-4 1.1.6 Powerful Peripheral Functions Built-in ....................................................................................... 1-4 1.2 Block Diagram .................................................................................................................................... 1-5 1.3 Pin Functions ..................................................................................................................................... 1-9 1.4 Pin Assignments ................................................................................................................................. 1-13 CHAPTER 2 CPU 2.1 CPU Registers ................................................................................................................................... 2-2 2.2 General-purpose Registers ................................................................................................................ 2-2 2.3 Control Registers ............................................................................................................................... 2-2 2.3.1 Processor Status Word Register: PSW (CR0) ............................................................................ 2-3 2.3.2 Condition Bit Register: CBR (CR1) ............................................................................................ 2-4 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) .................................... 2-4 2.3.4 Backup PC: BPC (CR6) ............................................................................................................. 2-4 2.3.5 Floating-point Status Register: FPSR (CR7) .............................................................................. 2-5 2.4 Accumulator ....................................................................................................................................... 2-7 2.5 Program Counter ................................................................................................................................ 2-7 2.6 Data Formats ...................................................................................................................................... 2-8 2.6.1 Data Types ................................................................................................................................. 2-8 2.6.2 Data Formats ............................................................................................................................. 2-9 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution ................ 2-14 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space ................................................................................................................... 3-2 3.2 Operation Modes ................................................................................................................................ 3-3 3.3 Internal ROM and External Extension Areas ...................................................................................... 3-6 3.3.1 Internal ROM Area ..................................................................................................................... 3-6 3.3.2 External Extension Area ............................................................................................................. 3-6 3.4 Internal RAM and SFR Areas ............................................................................................................. 3-7 3.4.1 Internal RAM Area ...................................................................................................................... 3-7 3.4.2 SFR (Special Function Register) Area ........................................................................................ 3-7 3.5 EIT Vector Entry ................................................................................................................................. 3-47 3.6 ICU Vector Table ................................................................................................................................ 3-48 3.7 Notes on Address Space .................................................................................................................... 3-51 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-1 CHAPTER 4 EIT 4.1 Outline of EIT ..................................................................................................................................... 4-2 4.2 EIT Events .......................................................................................................................................... 4-3 4.2.1 Exception ................................................................................................................................... 4-3 4.2.2 Interrupt ...................................................................................................................................... 4-5 4.2.3 Trap ............................................................................................................................................ 4-6 4.3 EIT Processing Procedure ................................................................................................................. 4-6 4.4 EIT Processing Mechanism ................................................................................................................ 4-7 4.5 Acceptance of EIT Events .................................................................................................................. 4-8 4.6 Saving and Restoring PC and PSW ................................................................................................... 4-8 4.7 EIT Vector Entry ................................................................................................................................. 4-10 4.8 Exception Processing ......................................................................................................................... 4-11 4.8.1 Reserved Instruction Exception (RIE) ........................................................................................ 4-11 4.8.2 Address Exception (AE) ............................................................................................................. 4-12 4.8.3 Floating-Point Exception (FPE) .................................................................................................. 4-13 4.9 Interrupt Processing ........................................................................................................................... 4-15 4.9.1 Reset Interrupt (RI) .................................................................................................................... 4-15 4.9.2 System Break Interrupt (SBI) ..................................................................................................... 4-15 4.9.3 External Interrupt (EI) ................................................................................................................. 4-17 4.10 Trap Processing ............................................................................................................................... 4-18 4.10.1 Trap .......................................................................................................................................... 4-18 4.11 EIT Priority Levels ............................................................................................................................ 4-19 4.12 Example of EIT Processing .............................................................................................................. 4-20 4.13 Notes on EIT .................................................................................................................................... 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of Interrupt Controller ............................................................................................................. 5-2 5.2 ICU Related Registers ....................................................................................................................... 5-4 5.2.1 Interrupt Vector Register ............................................................................................................ 5-5 5.2.2 Interrupt Request Mask Register ............................................................................................... 5-6 5.2.3 SBI (System Break Interrupt) Control Register .......................................................................... 5-7 5.2.4 Interrupt Control Registers ......................................................................................................... 5-8 5.3 Interrupt Request Sources in Internal Peripheral I/O .......................................................................... 5-11 5.4 ICU Vector Table ................................................................................................................................ 5-12 5.5 Description of Interrupt Operation ...................................................................................................... 5-13 5.5.1 Acceptance of Internal Peripheral I/O Interrupts ......................................................................... 5-13 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers ........................................................... 5-14 5.6 Description of System Break Interrupt (SBI) Operation ...................................................................... 5-17 5.6.1 Acceptance of SBI ...................................................................................................................... 5-17 5.6.2 SBI Processing by Handler ........................................................................................................ 5-17 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-2 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of Internal Memory ................................................................................................................. 6-2 6.2 Internal RAM ...................................................................................................................................... 6-2 6.3 Internal RAM Protect Function ........................................................................................................... 6-2 6.4 Internal Flash Memory ........................................................................................................................ 6-11 6.5 Registers Associated with Internal Flash Memory .............................................................................. 6-14 6.5.1 Flash Mode Register .................................................................................................................. 6-15 6.5.2 Flash Status Register ................................................................................................................. 6-16 6.5.3 Flash Control Registers .............................................................................................................. 6-17 6.5.4 Virtual Flash L Bank Registers ................................................................................................... 6-24 6.6 Programming Internal Flash Memory ................................................................................................. 6-25 6.6.1 Outline of Internal Flash Memory Programming ......................................................................... 6-25 6.6.2 Controlling Operation Modes during Flash Programming .......................................................... 6-31 6.6.3 Procedure for Programming/Erasing Internal Flash Memory ..................................................... 6-35 6.6.4 Flash Programming Time (Reference) ....................................................................................... 6-43 6.7 Virtual Flash Emulation Function ........................................................................................................ 6-44 6.7.1 Virtual Flash Emulation Area ...................................................................................................... 6-46 6.7.2 Entering Virtual Flash Emulation Mode ...................................................................................... 6-49 6.8 Connecting to Serial Programmer (CSIO Mode) ................................................................................ 6-50 6.9 Connecting to Serial Programmer (UART Mode) ............................................................................... 6-52 6.10 Internal Flash Memory Protect Function .......................................................................................... 6-54 6.11 Notes on Internal RAM ..................................................................................................................... 6-55 6.12 Notes on Internal Flash Memory ...................................................................................................... 6-55 CHAPTER 7 RESET 7.1 Outline of Reset ................................................................................................................................. 7-2 7.2 Reset Operation ................................................................................................................................. 7-2 7.2.1 Reset at Power-on ..................................................................................................................... 7-3 7.2.2 Reset during Operation .............................................................................................................. 7-3 7.2.3 Reset Vector Relocation during Flash Programming ................................................................. 7-3 7.3 Internal State upon Exiting Reset ....................................................................................................... 7-4 7.4 Things to Be Considered upon Exiting Reset ..................................................................................... 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports .............................................................................................................. 8-2 8.2 Selecting Pin Functions ...................................................................................................................... 8-3 8.3 Input/Output Port Related Registers .................................................................................................. 8-9 8.3.1 Port Data Registers .................................................................................................................... 8-12 8.3.2 Port Direction Registers ............................................................................................................. 8-13 8.3.3 Port Operation Mode and Port Peripheral Function Select Registers ........................................ 8-14 8.3.4 Port Input Special Function Control Register ............................................................................. 8-29 8.4 Port Input Level Switching Function ................................................................................................... 8-32 8.5 Port Output Drive Capability Setting Function .................................................................................... 8-34 8.6 Noise Canceller Control Function ....................................................................................................... 8-37 8.7 Port Peripheral Circuits ...................................................................................................................... 8-39 8.8 Notes on Input/Output Ports ............................................................................................................... 8-44 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-3 CHAPTER 9 DMAC 9.1 Outline of DMAC ................................................................................................................................ 9-2 9.2 DMAC Related Registers ................................................................................................................... 9-4 9.2.1 DMA Channel Control Registers ................................................................................................ 9-6 9.2.2 DMA Software Request Generation Registers ........................................................................... 9-29 9.2.3 DMA Source Address Registers ................................................................................................. 9-30 9.2.4 DMA Destination Address Registers .......................................................................................... 9-31 9.2.5 DMA Transfer Count Registers .................................................................................................. 9-32 9.2.6 DMA Interrupt Related Registers ................................................................................................ 9-33 9.3 Functional Description of DMAC ........................................................................................................ 9-38 9.3.1 DMA Transfer Request Sources ................................................................................................. 9-38 9.3.2 DMA Transfer Processing Procedure ......................................................................................... 9-44 9.3.3 Starting DMA .............................................................................................................................. 9-45 9.3.4 DMA Channel Priority ................................................................................................................. 9-45 9.3.5 Gaining and Releasing Control of Internal Bus .......................................................................... 9-45 9.3.6 Transfer Units ............................................................................................................................. 9-46 9.3.7 Transfer Counts .......................................................................................................................... 9-46 9.3.8 Address Space ........................................................................................................................... 9-46 9.3.9 Transfer Operation ..................................................................................................................... 9-46 9.3.10 End of DMA and Interrupt ......................................................................................................... 9-48 9.3.11 Each Register Status after Completion of DMA Transfer .......................................................... 9-48 9.4 Notes on DMAC ................................................................................................................................. 9-49 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers ......................................................................................................... 10-2 10.2 Common Units of Multijunction Timers ............................................................................................. 10-9 10.2.1 MJT Common Unit Register Map ............................................................................................. 10-10 10.2.2 Common Count Clock Select Function .................................................................................... 10-12 10.2.3 Prescaler Unit ........................................................................................................................... 10-13 10.2.4 Clock Bus and Input/Output Event Bus Control Unit ................................................................ 10-14 10.2.5 Input Processing Control Unit .................................................................................................. 10-18 10.2.6 Output Flip-flop Control Unit ..................................................................................................... 10-26 10.2.7 Interrupt Control Unit ................................................................................................................ 10-34 10.3 TOP (Output-Related 16-Bit Timer) .................................................................................................. 10-60 10.3.1 Outline of TOP .......................................................................................................................... 10-60 10.3.2 Outline of Each Mode of TOP ................................................................................................... 10-62 10.3.3 TOP Related Register Map ...................................................................................................... 10-64 10.3.4 TOP Control Registers ............................................................................................................. 10-66 10.3.5 TOP Counters (TOP0CT–TOP10CT) ....................................................................................... 10-71 10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) .......................................................................... 10-72 10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) ..................................................................... 10-73 10.3.8 TOP Enable Control Registers ................................................................................................. 10-74 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) ................................... 10-76 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) ................... 10-82 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) ............................ 10-87 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-4 10.4 TIO (Input/Output-Related 16-Bit Timer) .......................................................................................... 10-90 10.4.1 Outline of TIO ........................................................................................................................... 10-90 10.4.2 Outline of Each Mode of TIO .................................................................................................... 10-92 10.4.3 TIO Related Register Map ........................................................................................................ 10-95 10.4.4 TIO Control Registers ............................................................................................................... 10-97 10.4.5 TIO Counters (TIO0CT–TIO9CT) ............................................................................................. 10-105 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) ......................................................... 10-106 10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ......................................................................... 10-107 10.4.8 TIO Enable Control Registers .................................................................................................. 10-108 10.4.9 Operation in TIO Measure Free-Run/Clear Input Modes ......................................................... 10-110 10.4.10 Operation in TIO Noise Processing Input Mode ..................................................................... 10-112 10.4.11 Operation in TIO PWM Output Mode ...................................................................................... 10-113 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ............................. 10-117 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ............... 10-119 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ............................. 10-121 10.5 TMS (Input-Related 16-Bit Timer) ..................................................................................................... 10-123 10.5.1 Outline of TMS ......................................................................................................................... 10-123 10.5.2 Outline of TMS Operation ......................................................................................................... 10-123 10.5.3 TMS Related Register Map ...................................................................................................... 10-125 10.5.4 TMS Control Registers ............................................................................................................. 10-126 10.5.5 TMS Counters (TMS0CT, TMS1CT) ......................................................................................... 10-127 10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ........................................................... 10-127 10.5.7 Operation of TMS Measure Input ............................................................................................. 10-128 10.6 TML (Input-Related 32-Bit Timer) ..................................................................................................... 10-129 10.6.1 Outline of TML .......................................................................................................................... 10-129 10.6.2 Outline of TML Operation ......................................................................................................... 10-130 10.6.3 TML Related Register Map ...................................................................................................... 10-130 10.6.4 TML Control Registers ............................................................................................................. 10-131 10.6.5 TML Counters ........................................................................................................................... 10-132 10.6.6 TML Measure Registers ........................................................................................................... 10-132 10.6.7 Operation of TML Measure Input .............................................................................................. 10-133 10.7 TID (Input-Related 16-Bit Timer) ...................................................................................................... 10-135 10.7.1 Outline of TID ........................................................................................................................... 10-135 10.7.2 TID Related Register Map ........................................................................................................ 10-137 10.7.3 TID Control & Prescaler Enable Registers ............................................................................... 10-138 10.7.4 TID Counters (TID0CT and TID1CT) ........................................................................................ 10-140 10.7.5 TID Reload Registers (TID0RL and TID1RL) ........................................................................... 10-140 10.7.6 Outline of Each Mode of TID .................................................................................................... 10-141 10.8 TOU (Output-Related 24-Bit Timer) .................................................................................................. 10-146 10.8.1 Outline of TOU ......................................................................................................................... 10-146 10.8.2 Outline of Each Mode of TOU .................................................................................................. 10-148 10.8.3 TOU Related Register Map ...................................................................................................... 10-150 10.8.4 TOU Control Registers ............................................................................................................. 10-153 10.8.5 Shorting Prevention Function Registers ................................................................................... 10-155 10.8.6 TOU Counters .......................................................................................................................... 10-157 10.8.7 TOU Reload Registers ............................................................................................................. 10-160 10.8.8 TOU Enable Protect Registers ................................................................................................. 10-163 10.8.9 TOU Count Enable Registers ................................................................................................... 10-164 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-5 10.8.10 PWMOFF Input Processing Control Registers ....................................................................... 10-166 10.8.11 PWM Output Disable Control Registers ................................................................................. 10-168 10.8.12 PWM Output Disable Level Control Registers ....................................................................... 10-171 10.8.13 PWMOFF Function Enable Registers .................................................................................... 10-173 10.8.14 Operation in TOU PWM Output Mode (without Correction Function) ..................................... 10-174 10.8.15 Operation in TOU Single-shot PWM Output Mode (without Correction Function) .................. 10-180 10.8.16 Operation in TOU Delayed Single-shot Output Mode (without Correction Function) ............. 10-182 10.8.17 Operation in TOU Single-shot Output Mode (without Correction Function) ............................ 10-184 10.8.18 Operation in TOU Continuous Output Mode (without Correction Function) ........................... 10-186 10.8.19 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes 10-188 10.8.20 PWM Output Disable Function ............................................................................................... 10-193 10.8.21 Shorting Prevention Function ................................................................................................. 10-198 10.8.22 Example Application for Using 32185/32186 in Motor Control ............................................... 10-202 CHAPTER 11 A/D CONVERTER 11.1 Outline of A/D Converter ................................................................................................................... 11-2 11.1.1 Conversion Modes ................................................................................................................... 11-6 11.1.2 Operation Modes ...................................................................................................................... 11-6 11.1.3 Special Operation Modes ......................................................................................................... 11-9 11.1.4 A/D Converter Interrupt and DMA Transfer Requests ............................................................... 11-12 11.1.5 Sample-and-Hold Function ....................................................................................................... 11-12 11.1.6 Simultaneous Sampling Function ............................................................................................. 11-13 11.2 A/D Converter Related Registers ..................................................................................................... 11-15 11.2.1 A/D Single Mode Register 0 ..................................................................................................... 11-17 11.2.2 A/D Single Mode Register 1 ..................................................................................................... 11-19 11.2.3 A/D Single Mode Register 2 ..................................................................................................... 11-21 11.2.4 A/D Scan Mode Register 0 ....................................................................................................... 11-22 11.2.5 A/D Scan Mode Register 1 ....................................................................................................... 11-24 11.2.6 A/D Conversion Speed Control Register ................................................................................... 11-26 11.2.7 A/D Disconnection Detection Assist Function Control Register ................................................ 11-27 11.2.8 A/D Disconnection Detection Assist Method Select Register ................................................... 11-28 11.2.9 A/D Successive Approximation Register .................................................................................. 11-31 11.2.10 A/D Comparate Data Register ................................................................................................ 11-32 11.2.11 10-bit A/D Data Registers ....................................................................................................... 11-33 11.2.12 8-bit A/D Data Registers ......................................................................................................... 11-34 11.3 Functional Description of A/D Converter ........................................................................................... 11-35 11.3.1 How to Find Analog Input Voltages ........................................................................................... 11-35 11.3.2 A/D Conversion by Successive Approximation Method ............................................................ 11-36 11.3.3 Comparator Operation .............................................................................................................. 11-37 11.3.4 Calculating A/D Conversion Time ............................................................................................. 11-38 11.3.5 Accuracy of A/D Conversion ..................................................................................................... 11-43 11.4 Inflow Current Bypass Circuit ........................................................................................................... 11-45 11.5 Notes on Using A/D Converter ......................................................................................................... 11-47 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-6 CHAPTER 12 SERIAL INTERFACE 12.1 Outline of Serial Interface ................................................................................................................. 12-2 12.2 Serial Interface Related Registers .................................................................................................... 12-5 12.2.1 SIO Interrupt Related Registers ............................................................................................... 12-6 12.2.2 SIO Transmit Control Registers ................................................................................................ 12-14 12.2.3 SIO Transmit/Receive Mode Registers .................................................................................... 12-15 12.2.4 SIO Transmit Buffer Registers .................................................................................................. 12-19 12.2.5 SIO Receive Buffer Registers .................................................................................................. 12-20 12.2.6 SIO Receive Control Registers ................................................................................................ 12-21 12.2.7 SIO Baud Rate Registers ......................................................................................................... 12-24 12.2.8 SIO Special Mode Registers .................................................................................................... 12-27 12.3 Transmit Operation in CSIO Mode ................................................................................................... 12-29 12.3.1 Setting CSIO Baud Rate .......................................................................................................... 12-29 12.3.2 Initializing CSIO Transmission .................................................................................................. 12-30 12.3.3 Starting CSIO Transmission ..................................................................................................... 12-32 12.3.4 Successive CSIO Transmission ............................................................................................... 12-32 12.3.5 Processing at End of CSIO Transmission ................................................................................ 12-33 12.3.6 Transmit Interrupts ................................................................................................................... 12-33 12.3.7 Transmit DMA Transfer Request .............................................................................................. 12-33 12.3.8 Example of CSIO Transmit Operation ...................................................................................... 12-35 12.4 Receive Operation in CSIO Mode .................................................................................................... 12-37 12.4.1 Initialization for CSIO Reception .............................................................................................. 12-37 12.4.2 Starting CSIO Reception .......................................................................................................... 12-39 12.4.3 Processing at End of CSIO Reception ..................................................................................... 12-39 12.4.4 About Successive Reception .................................................................................................... 12-40 12.4.5 Flags Showing Status of CSIO Receive Operation .................................................................. 12-41 12.4.6 Example of CSIO Receive Operation ....................................................................................... 12-42 12.5 Notes on Using CSIO Mode ............................................................................................................. 12-44 12.6 Transmit Operation in UART Mode .................................................................................................. 12-46 12.6.1 Setting UART Baud Rate ......................................................................................................... 12-46 12.6.2 UART Transmit/Receive Data Formats .................................................................................... 12-46 12.6.3 Initializing UART Transmission ................................................................................................. 12-48 12.6.4 Starting UART Transmission .................................................................................................... 12-50 12.6.5 Successive UART Transmission .............................................................................................. 12-50 12.6.6 Processing at End of UART Transmission ............................................................................... 12-50 12.6.7 Transmit Interrupts ................................................................................................................... 12-50 12.6.8 Transmit DMA Transfer Request .............................................................................................. 12-51 12.6.9 Example of UART Transmit Operation ..................................................................................... 12-52 12.7 Receive Operation in UART Mode ................................................................................................... 12-54 12.7.1 Initialization for UART Reception .............................................................................................. 12-54 12.7.2 Starting UART Reception ......................................................................................................... 12-56 12.7.3 Processing at End of UART Reception .................................................................................... 12-56 12.7.4 Example of UART Receive Operation ...................................................................................... 12-58 12.7.5 Start Bit Detection and Data Sampling Timing during UART Reception ................................... 12-60 12.8 Fixed Period Clock Output Function ................................................................................................. 12-61 12.9 Notes on Using UART Mode ............................................................................................................ 12-62 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-7 CHAPTER 13 CAN MODULE 13.1 Outline of CAN Module ..................................................................................................................... 13-2 13.2 CAN Module Related Registers ....................................................................................................... 13-4 13.2.1 CAN Bus Mode Control Register .............................................................................................. 13-23 13.2.2 CAN Control Registers ............................................................................................................. 13-26 13.2.3 CAN Status Registers .............................................................................................................. 13-29 13.2.4 CAN Configuration Registers ................................................................................................... 13-32 13.2.5 CAN Timestamp Count Registers ............................................................................................ 13-34 13.2.6 CAN Error Count Registers ...................................................................................................... 13-35 13.2.7 CAN Baud Rate Prescalers ...................................................................................................... 13-36 13.2.8 CAN Interrupt Related Registers .............................................................................................. 13-37 13.2.9 CAN Cause of Error Registers ................................................................................................. 13-66 13.2.10 CAN Mode Registers ............................................................................................................. 13-68 13.2.11 CAN DMA Transfer Request Select Registers ....................................................................... 13-69 13.2.12 CAN Message Slot Number Registers ................................................................................... 13-70 13.2.13 CAN Clock Select Registers .................................................................................................. 13-71 13.2.14 CAN Frame Format Select Registers ..................................................................................... 13-73 13.2.15 CAN Mask Registers .............................................................................................................. 13-75 13.2.16 CAN Single-Shot Mode Control Registers ............................................................................. 13-79 13.2.17 CAN Message Slot Control Registers .................................................................................... 13-81 13.2.18 CAN Message Slots ............................................................................................................... 13-85 13.3 CAN Protocol ................................................................................................................................... 13-115 13.3.1 CAN Protocol Frames .............................................................................................................. 13-115 13.3.2 Data Formats during CAN Transmission/Reception ................................................................. 13-116 13.3.3 CAN Controller Error States ..................................................................................................... 13-117 13.4 Initializing CAN Module .................................................................................................................... 13-118 13.4.1 Initializing CAN Module ............................................................................................................ 13-118 13.5 Transmitting Data Frames ................................................................................................................ 13-121 13.5.1 Data Frame Transmit Procedure .............................................................................................. 13-121 13.5.2 Data Frame Transmit Operation ............................................................................................... 13-122 13.5.3 Transmit Abort Function ........................................................................................................... 13-123 13.6 Receiving Data Frames .................................................................................................................... 13-124 13.6.1 Data Frame Receive Procedure ............................................................................................... 13-124 13.6.2 Data Frame Receive Operation ................................................................................................ 13-125 13.6.3 Reading Out Received Data Frames ....................................................................................... 13-127 13.7 Transmitting Remote Frames ........................................................................................................... 13-129 13.7.1 Remote Frame Transmit Procedure ......................................................................................... 13-129 13.7.2 Remote Frame Transmit Operation .......................................................................................... 13-130 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ................... 13-132 13.8 Receiving Remote Frames ............................................................................................................... 13-134 13.8.1 Remote Frame Receive Procedure .......................................................................................... 13-134 13.8.2 Remote Frame Receive Operation ........................................................................................... 13-135 13.9 Notes on CAN Module ..................................................................................................................... 13-138 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-8 CHAPTER 14 DIRECT RAM INTERFACE (DRI) 14.1 Outline of Direct RAM Interface (DRI) .............................................................................................. 14-2 14.2 DRI Related Registers ...................................................................................................................... 14-4 14.2.1 DD Input Pin Select Register .................................................................................................... 14-6 14.2.2 DRI Interrupt Related Registers ............................................................................................... 14-7 14.2.3 DRI Transfer Control Register .................................................................................................. 14-13 14.2.4 DRI Special Mode Control Register .......................................................................................... 14-15 14.2.5 DRI Data Capture Control Register .......................................................................................... 14-18 14.2.6 DRI Data Interleave Control Register ....................................................................................... 14-22 14.2.7 DIN Input Event Select Register ............................................................................................... 14-22 14.2.8 DD Input Enable Registers ....................................................................................................... 14-23 14.2.9 DRI Data Capture Event Count Setting Register ...................................................................... 14-25 14.2.10 DRI Capture Event Counter ................................................................................................... 14-26 14.2.11 DRI Transfer Counter ............................................................................................................. 14-27 14.2.12 DRI Address Counters ........................................................................................................... 14-28 14.2.13 DRI Address Reload Registers .............................................................................................. 14-29 14.2.14 DIN Input Processing Control Register .................................................................................. 14-30 14.2.15 DRI Event Counter (DEC) Control Registers ......................................................................... 14-31 14.2.16 DRI Event Counters (DEC Counters) ..................................................................................... 14-36 14.2.17 DRI Event Counter (DEC) Reload Registers .......................................................................... 14-36 14.3 Notes on DRI .................................................................................................................................... 14-37 CHAPTER 15 REAL TIME DEBUGGER (RTD) 15.1 Outline of Real-Time Debugger (RTD) ............................................................................................. 15-2 15.2 Pin Functions of RTD ....................................................................................................................... 15-3 15.3 RTD Related Register ...................................................................................................................... 15-3 15.3.1 RTD Write Function Disable Register ....................................................................................... 15-3 15.4 Functional Description of RTD ......................................................................................................... 15-4 15.4.1 Outline of RTD Operation ......................................................................................................... 15-4 15.4.2 Operation of RDR (Real-time RAM Content Output) ................................................................ 15-4 15.4.3 Operation of WRR (RAM Content Forcible Rewrite) ................................................................ 15-6 15.4.4 Operation of VER (Continuous Monitor) ................................................................................... 15-7 15.4.5 Operation of VEI (Interrupt Request) ........................................................................................ 15-7 15.4.6 Operation of RCV (Recover from Runaway) ............................................................................ 15-8 15.4.7 Method for Setting Specified Address when Using the RTD .................................................... 15-9 15.4.8 Resetting RTD .......................................................................................................................... 15-10 15.5 Typical Connection with Host ........................................................................................................... 15-11 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-9 CHAPTER 16 NON-BREAK DEBUG (NBD) 16.1 Outline of Non-Break Debug (NBD) ................................................................................................. 16-2 16.2 Pin Functions of NBD ....................................................................................................................... 16-4 16.2.1 NBD Pin Control Register ......................................................................................................... 16-4 16.3 NBD Related Registers .................................................................................................................... 16-6 16.3.1 NBD Enable Register ............................................................................................................... 16-6 16.4 Communication Protocol .................................................................................................................. 16-7 16.5 RAM Monitor Function ...................................................................................................................... 16-8 16.5.1 Description of NBD Operation .................................................................................................. 16-8 16.5.2 NBDD Data Format .................................................................................................................. 16-9 16.6 Event Detection Function ................................................................................................................. 16-11 16.6.1 Event Address Setting Register ................................................................................................ 16-11 16.6.2 Event Condition Setting Register ............................................................................................. 16-12 16.6.3 Event Generation Register ....................................................................................................... 16-12 CHAPTER 17 EXTERNAL BUS INTERFACE 17.1 Outline of External Bus Interface ...................................................................................................... 17-2 17.1.1 External Bus Interface Related Signals .................................................................................... 17-2 17.2 External Bus Interface Related Registers ........................................................................................ 17-5 17.2.1 Port Operation Mode and Port Peripheral Function Select Registers ...................................... 17-5 17.2.2 Bus Mode Control Register ...................................................................................................... 17-15 17.2.3 CLKOUT Select Register ......................................................................................................... 17-16 17.3 Read/Write Operations ..................................................................................................................... 17-19 17.4 Bus Arbitration .................................................................................................................................. 17-25 17.5 Typical Connection of External Extension Memory .......................................................................... 17-27 17.6 Example of Bus Voltage Settings Using VCC-BUS .......................................................................... 17-30 CHAPTER 18 WAIT CONTROLLER 18.1 Outline of Wait Controller ................................................................................................................. 18-2 18.2 Wait Controller Related Registers .................................................................................................... 18-4 18.2.1 CS Area Wait Control Registers ............................................................................................... 18-4 18.2.2 Flash E/W Wait Select Register ............................................................................................... 18-6 18.3 Typical Operation of Wait Controller ................................................................................................. 18-7 CHAPTER 19 RAM BACKUP MODE 19.1 Outline of RAM Backup Mode .......................................................................................................... 19-2 19.2 Example of RAM Backup when Power is Off ................................................................................... 19-3 19.2.1 Normal Operating State ............................................................................................................ 19-3 19.2.2 RAM Backup State ................................................................................................................... 19-4 19.3 Example of RAM Backup for Saving Power Consumption ............................................................... 19-5 19.3.1 Normal Operating State ............................................................................................................ 19-6 19.3.2 RAM Backup State ................................................................................................................... 19-7 19.3.3 Precautions to Be Observed at Power-On ............................................................................... 19-8 19.3.4 Power-On Limitation ................................................................................................................. 19-8 19.4 Exiting RAM Backup Mode (Wakeup) .............................................................................................. 19-9 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-10 CHAPTER 20 OSCILLATOR CIRCUIT 20.1 Oscillator Circuit ............................................................................................................................... 20-2 20.1.1 Example of Oscillator Circuit .................................................................................................... 20-2 20.1.2 XIN Oscillation Stoppage Detection Circuit .............................................................................. 20-3 20.1.3 Oscillation Drive Capability Select Function ............................................................................. 20-5 20.1.4 System Clock Output Function ................................................................................................. 20-7 20.1.5 Oscillation Stabilization Time at Power-On ............................................................................... 20-11 20.2 Clock Generator Circuit .................................................................................................................... 20-12 CHAPTER 21 JTAG 21.1 Outline of JTAG ................................................................................................................................ 21-2 21.2 Configuration of JTAG Circuit ........................................................................................................... 21-3 21.3 JTAG Registers ................................................................................................................................ 21-4 21.3.1 Instruction Register (JTAGIR) .................................................................................................. 21-4 21.3.2 Data Register ........................................................................................................................... 21-5 21.4 Basic Operation of JTAG .................................................................................................................. 21-6 21.4.1 Outline of JTAG Operation ....................................................................................................... 21-6 21.4.2 IR Path Sequence .................................................................................................................... 21-8 21.4.3 DR Path Sequence .................................................................................................................. 21-9 21.4.4 Inspecting and Setting Data Registers ..................................................................................... 21-10 21.5 Boundary Scan Description Language ............................................................................................. 21-11 21.6 Notes on Board Design when Connecting JTAG ............................................................................. 21-12 21.7 Processing Pins when Not Using JTAG ........................................................................................... 21-13 CHAPTER 22 POWER SUPPLY CIRCUIT 22.1 Configuration of Power Supply Circuit .............................................................................................. 22-2 22.2 Power-On Sequence ........................................................................................................................ 22-3 22.2.1 Power-On Sequence when Not Using RAM Backup ................................................................ 22-3 22.2.2 Power-On Sequence when Using RAM Backup ...................................................................... 22-4 22.3 Power-Off Sequence ........................................................................................................................ 22-5 22.3.1 Power-Off Sequence when Not Using RAM Backup ................................................................ 22-5 22.3.2 Power-Off Sequence when Using RAM Backup ...................................................................... 22-6 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-11 CHAPTER 23 ELECTRICAL CHARACTERISTICS 23.1 Adapted Table .................................................................................................................................. 23-2 23.2 Absolute Maximum Ratings .............................................................................................................. 23-2 23.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ......................................................... 23-3 23.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) .......................... 23-3 23.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ...................................................... 23-5 23.3.3 A/D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) .................................... 23-6 23.4 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ........................................................... 23-7 23.4.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) ............................ 23-7 23.4.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ........................................................ 23-9 23.4.3 A/D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ...................................... 23-10 23.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz ...................................................... 23-11 23.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ±0.3 V, f(XIN) = 10 MHz) ............ 23-11 23.5.2 D.C. Characteristics (when VCCE = 3.3 V ±0.3 V, f(XIN) = 10 MHz) ....................................... 23-13 23.5.3 A/D Conversion Characteristics (when VCCE = 3.3 V ±0.3 V, f(XIN) = 10 MHz) ...................... 23-14 23.6 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ........................................................ 23-15 23.6.1 Recommended Operating Conditions (when VCCE = 3.3 V ±0.3 V, f(XIN) = 8 MHz) .............. 23-15 23.6.2 D.C. Characteristics (when VCCE = 3.3 V ±0.3 V, f(XIN) = 8 MHz) ......................................... 23-17 23.6.3 A/D Conversion Characteristics (when VCCE = 3.3 V ±0.3 V, f(XIN) = 8 MHz) ........................ 23-18 23.7 Flash Memory Related Characteristics ............................................................................................ 23-19 23.8 External Capacitance for Power Supply ........................................................................................... 23-19 23.9 A.C. Characteristics (when VCCE = 5 V) ......................................................................................... 23-20 23.10 A.C. Characteristics (when VCCE = 3.3 V) .................................................................................... 23-42 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing ..................................................................................... Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32185/32186 Instruction Processing Time ................................................................. Appendix 2-2 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins ........................................................................ Appendix 3-2 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Appendix 4.2 Appendix 4.3 Appendix 4.4 Appendix 4.5 Appendix 4.6 Appendix 4.7 Appendix 4.8 Notes on CPU -------------------------------------------------------------------------------------Notes on Address Space -----------------------------------------------------------------------Notes on EIT ---------------------------------------------------------------------------------------Notes on Internal RAM --------------------------------------------------------------------------Notes on Internal Flash Memory --------------------------------------------------------------Things to Be Considered upon Exiting Reset ---------------------------------------------Notes on Input/Output Ports -------------------------------------------------------------------Notes on DMAC -----------------------------------------------------------------------------------Appendix 4-2 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-4 Appendix 4-4 Appendix 4-5 Appendix 4-6 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-12 Appendix 4.9 Notes on Multijunction Timers -----------------------------------------------------------------Appendix 4.9.1 Notes on using TOP single-shot output mode --------------------------------------Appendix 4.9.2 Notes on using TOP delayed single-shot output mode --------------------------Appendix 4.9.3 Notes on using TOP continuous output mode --------------------------------------Appendix 4.9.4 Notes on using TIO measure free-run/ clear input modes ----------------------Appendix 4.9.5 Notes on using TIO PWM output mode ----------------------------------------------Appendix 4.9.6 Notes on using TIO single-shot output mode ---------------------------------------Appendix 4.9.7 Notes on using TIO delayed single-shot output mode ---------------------------Appendix 4.9.8 Notes on using TIO continuous output mode ---------------------------------------Appendix 4.9.9 Notes on using TMS measure input --------------------------------------------------Appendix 4.9.10 Notes on using TML measure input -------------------------------------------------Appendix 4.9.11 Notes on using TOU PWM output mode -------------------------------------------Appendix 4.9.12 Notes on using TOU single-shot PWM output mode ---------------------------Appendix 4.9.13 Notes on using TOU delayed single-shot output mode ------------------------Appendix 4.9.14 Notes on using TOU single-shot output mode ------------------------------------Appendix 4.9.15 Notes on using TOU continuous output mode ------------------------------------Appendix 4.9.16 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes ------------------------------------------------------Appendix 4.10 Notes on A/D Converter -----------------------------------------------------------------------Appendix 4.11 Notes on Serial Interface ----------------------------------------------------------------------Appendix 4.11.1 Notes on Using CSIO Mode -----------------------------------------------------------Appendix 4.11.2 Notes on Using UART Mode ----------------------------------------------------------Appendix 4.12 Notes on CAN Module -------------------------------------------------------------------------Appendix 4.13 Notes on DRI -------------------------------------------------------------------------------------Appendix 4.14 Notes on RAM Backup Mode ----------------------------------------------------------------Appendix 4.14.1 Precautions to Be Observed at Power-On -----------------------------------------Appendix 4.14.2 Power-On Limitation ---------------------------------------------------------------------Appendix 4.15 Notes on JTAG ----------------------------------------------------------------------------------Appendix 4.15.1 Notes on Board Design when Connecting JTAG --------------------------------Appendix 4.15.2 Processing Pins when Not Using JTAG --------------------------------------------Appendix 4.16 Notes on Noise ----------------------------------------------------------------------------------Appendix 4.16.1 Reduction of Wiring Length ------------------------------------------------------------Appendix 4.16.2 Inserting a Bypass Capacitor between VSS and VCC Lines -----------------Appendix 4.16.3 Processing Analog Input Pin Wiring -------------------------------------------------Appendix 4.16.4 Consideration about the Oscillator --------------------------------------------------Appendix 4.16.5 Processing Input/Output Ports --------------------------------------------------------- Appendix 4-7 Appendix 4-7 Appendix 4-9 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-11 Appendix 4-11 Appendix 4-11 Appendix 4-12 Appendix 4-13 Appendix 4-16 Appendix 4-16 Appendix 4-16 Appendix 4-17 Appendix 4-17 Appendix 4-22 Appendix 4-25 Appendix 4-25 Appendix 4-26 Appendix 4-28 Appendix 4-29 Appendix 4-29 Appendix 4-29 Appendix 4-29 Appendix 4-30 Appendix 4-30 Appendix 4-31 Appendix 4-32 Appendix 4-32 Appendix 4-34 Appendix 4-34 Appendix 4-35 Appendix 4-39 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Contents-13 CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Outline of the 32185/32186 Group Block Diagram Pin Functions Pin Assignments 1 1.1 Outline of 32185/32186 Group OVERVIEW 1.1 Outline of 32185/32186 Group The 32185/32186 group (hereafter simply the 32185/32186) belongs to the M32R/ECU series in the M32R family of Renesas microcomputers. For details about the current development status of the 32185/32186, please contact your nearest office of Renesas or its distributor. Table 1.1.1 Product List Type Name M32185F4VFP M32186F8VFP ROM capacity 512 Kbytes 1 Mbyte RAM capacity 32 Kbytes 64 Kbytes 80MHz 80MHz Frequency Power supply voltage at single-supply 5V or 3.3V 5V or 3.3V at double-supply 5V, 3.3V 5V, 3.3V Temperature Range (Note 1) –40°C to 125°C –40°C to 125°C Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile). 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) (1) Based on a RISC architecture • The 32185/32186 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32185/32186 products listed in the above table are built around the M32R-FPU and incorporate flash memory, RAM and various peripheral functions, all integrated into a single chip. • The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic/logic operations are executed using register-to-register operation instructions. • The M32R-FPU internally contains sixteen 32-bit general-purpose registers. The instruction set consists of 100 discrete instructions in total (83 instructions common to the M32R Family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long. • In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Six-stage pipelined processing • The M32R-FPU supports six-stage pipelined instruction processing. Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5 ns when f(CPUCLK) = 80 MHz). • Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R-FPU is able to control instruction execution without wasting clock cycles. (3) Compact instruction code • The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program. • Moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward from the currently executed address in one instruction, making programming easy. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-2 1 1.1.2 Built-in Multiplier/Accumulator (1) Built-in high-speed multiplier OVERVIEW 1.1 Outline of 32185/32186 Group • The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable multiply-accumulate instructions • The M32R-FPU supports the following four types of multiply-accumulate instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) (2) (3) (4) 16 16 All All high-order bits of register × 16 high-order bits of register low-order bits of register × 16 low-order bits of register 32 bits of register × 16 high-order bits of register 32 bits of register × 16 low-order bits of register • The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions too are executed in one CPUCLK period, when used in combination with highspeed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP. 1.1.3 Built-in Single-precision FPU • The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward – Infinity) are supported. What’s more, because general-purpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced. 1.1.4 Built-in Flash Memory and RAM • The 32185/32186 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system. • The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. • The internal flash memory can be rewritten as many as 100 times. • The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal RealTime Debugger (RTD) and the M32R Family’s common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy. • The internal RAM can be accessed for reading or rewriting data from an external device independently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger’s exclusive clock-synchronous serial interface. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-3 1 1.1.5 Built-in Clock Frequency Multiplier OVERVIEW 1.1 Outline of 32185/32186 Group • The 32185/32186 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. XIN pin (10MHz) X8 PLL 1/4 CPUCLK (CPU clock) (80MHz) BCLK (peripheral clock) (20MHz) 1/2 CLKO SEL CLKOUT(external bus clock) (20MHz or 10MHz) Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block CPUCLK BCLK Clock output Features • CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU core, internal flash memory and internal RAM. • Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. • BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin. • CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin. 1.1.6 Powerful Peripheral Functions Built-in (1) 8-level interrupt controller (ICU) (2) 10-channel DMAC (3) 55-channel multijunction timer (MJT) (4) 16-channel A/D converter (ADC) (5) 6-channel serial interface (SIO) (6) 2-channel Full-CAN (7) Direct RAM interface (DRI) (8) Real-time debugger (RTD) (9) Non-break debug (NBD) (10) Wait controller (11) M32R Family’s common debug function (Scalable Debug Interface or SDI) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-4 1 1.2 Block Diagram OVERVIEW 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32185/32186. The features of each block are described in Table 1.2.1. M32R-FPU Core (Max. 80MHz) Multiplier/Accumulator (32 bits x 16 bits + 56 bits) Single-precision FPU (fully IEEE 754 compliant) Internal Bus Interface DMAC (10 channels) Internal 32-bit bus Multijunction Timer (MJT: 55 channels) Internal 32-bit bus Internal Flash Memory (M32185F4: 512 Kbytes) (M32186F8: 1 Mbyte) A/D Converter (A/D0 : 10-bit converter, 16 channels) Internal 16-bit bus Non-Break Debug (NBD) Internal RAM (M32185F4: 32 Kbytes) (M32186F8: 64 Kbytes) Serial Interface (6 channels) Interrupt Controller (8 levels) Wait Controller Real-Time Debugger (RTD) Direct RAM Interface (DRI) Full CAN (2 channels) PLL Clock Generator External Bus Interface Data Address Internal Power Supply Generator (VDC) Input/output ports, 97 lines Figure 1.2.1 Block Diagram of the 32185/32186 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-5 1 Table 1.2.1 Features of the 32185/32186 (1/3) Functional Block M32R-FPU CPU core Features • Implementation: Six-stage pipelined instruction processing • Internal 32-bit structure of the core • Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 6 registers • Instruction set 16 and 32-bit instruction formats 100 discrete instructions and six addressing modes • Internal multiplier/accumulator (32 bits × 16 bits + 56 bits) • Internal single-precision floating-point arithmetic unit (FPU) • Capacity: M32185F4: 512 Kbytes M32186F8: 1 Mbyte • One wait access • Durability: Rewritable 100 times OVERVIEW 1.2 Block Diagram Internal Flash memory Internal RAM • Capacity: M32185F4: 32 Kbytes M32186F8: 64 Kbytes • Accessible with zero wait state • The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease. • A part of internal RAM can be backed up by using RAM back up mode when turn off the power supply. • Fundamental bus cycle :12.5 ns (when f(CPUCLK) = 80 MHz) • Logical address space : 4 Gbytes linear • Internal bus specification : Internal 32-bit data bus (for CPU internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access) • External extension area : During processor mode: maximum 32 Mbytes During external extension mode: maximum 31 Mbytes (7 Mbytes + 8 Mbytes × 3 blocks) • External data address: 22-bit address • External data bus: 16-bit data bus • Shortest external bus access: 1 CLKOUT during read, 1 CLKOUT during write • 55-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels, 16-bit input related up/down timer × 2 channels, and 24-bit output related timer × 16 channels • Flexible timer configuration is possible by interconnecting these timer channels. • Interrupt request: Counter underflow or overflow and rising or falling or both edges or “H” or “L” level from the TIN pin (TIN pin can be used as external interrupt inputs irrespective of timer operation.) • DMA transfer request: Counter underflow or overflow and rising or falling or both edges or “H” or “L” level from the TIN pin (TIN pin can be used as DMA transfer request inputs irrespective of timer operation.) • Number of channels: 10 • Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O and internal RAM are supported. • Capable of advanced DMA transfers when used in combination with internal peripheral I/O • Transfer request: Software or internal peripheral I/O (A/D converter, MJT, serial interface or CAN) • DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.) • Interrupt request: DMA transfer counter register underflow Bus specification Multijunction timer (MJT) DMAC 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-6 1 Table 1.2.1 Features of the 32185/32186 (2/3) Functional Block A/D Converter (ADC) Features OVERVIEW 1.2 Block Diagram • 16 channels: 10-bit resolution A/D converter × 1 block • Conversion modes: In addition to ordinary A/D conversion modes, the ADC incorporates comparator mode and 2-channel simultaneous sampling mode. • Operation modes: Single conversion mode and n-channel scan mode (n = 1–16) • A/D conversion with the analog input voltages sampled at start of A/D conversion is performable byusing sample-and-hold function. • Effects of the analog input voltage leakage from the preceding channel during A/D conversion is deterrable by using A/D disconnection detection assist function. • An inflow current bypass circuit is built-in. • Can generate an interrupt or start DMA transfer upon completion of A/D conversion. • Either 8 or 10-bit conversion results can be read out. • Interrupt request: Completion of A/D conversion • DMA transfer request: Completion of A/D conversion Serial Interface (SIO) • 6-channel serial interface • Can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface. • Data can be transferred at high speed (2.5 Mbits per second during clock-synchronous mode or 1.25 Mbits per second during clock-asynchronous mode when f(BCLK) = 20 MHz). • Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed • DMA transfer request: Reception completed or transmit buffer empty • 32 message slots × 2 blocks • Compliant with CAN specification 2.0B active. • Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot • DMA transfer request: Failed to send, transmission completed or reception completed • Internal RAM can be rewritten or monitored independently of the CPU by entering a command from the outside. • Comes with exclusive clock-synchronous serial ports. • Interrupt request: RTD interrupt command input • Can access to all resources on the address map from the outside • Clock-synchronous parallel interface (4-bit) • Event output function • RAM monitor function • Can control capture of clock-synchronous parallel data to the internal RAM independently of the CPU • Clock-synchronous parallel input (8, 16 or 32-bit) • Maximum transfer rate: 20 Mbytes/s (when f(CPUCLK)=80 MHz) • Controls interrupt requests from the internal peripheral I/O. • Supports 8-level interrupt priority including an interrupt disabled state. • External interrupt: 27 sources (SBI#, TIN0, TIN3–TIN11, TIN16–TIN27, TIN30–TIN33) • TIN pin input sensing: Rising, falling or both edges or “H” or “L” level • Controls wait states for access to the external extension area. • Insertion of 0–15 wait states by setting up in software + wait state extension by entering WAIT# signal • A multiply-by-8 clock generating circuit • The Maximum external input clock frequency (XIN) is 10.0 MHz. • CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM The Maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz). • BCLK: Operating clock for the peripheral I/O and external data bus The Maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz). • BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin. • CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin. • Boundary scan function CAN Real-Time Debugger (RTD) Non-Break Debug (NBD) Direct RAM Interface (DRI) Interrupt Controller (ICU) Wait Controller PLL Clock JTAG 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-7 1 Table 1.2.1 Features of the 32185/32186 (3/3) Functional Block VDC Ports Features OVERVIEW 1.2 Block Diagram • Internal power supply generating circuit: Generates the internal power supply from an external power supply (5 or 3.3 V). • Input/output pins: 97 pins • The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-8 1 1.3 Pin Functions OVERVIEW 1.3 Pin Functions Figure 1.3.1 shows pin function diagram of the 32185/32186. Pin functions are described in Table 1.3.1. XIN Clock Reset VCC-BUS P93/TO16/SCLKI5/SCLKO5 P94/TO17/TXD5/DD15 P95/TO18/RXD5/DD14 P96/TO19/DD13 Port 9 DRI Serial Interface XOUT RESET# MOD0 Mode MOD1 MOD2 (Note 1) VCCE P97/TO20/DD12 P100/TO8 P101/TO9/CRX0 P102/TO10/CTX0 CAN Flash Interrupt controller FP SBI# AD0IN0-AD0IN15 AVCC0 16 P103/TO11/TIN24 P104/TO12/TIN25/DD3 P105/TO13/SCLKI4/SCLKO4/DD2 Port 10 A/D converter AVSS0 VREF0 P106/TO14/TXD4/DD1 Serial Interface DRI Data bus DRI Address bus Multijunction timer Port 0 Port 1 Port 2 VCC-BUS Multijunction timer Port 3 P00/DB0/TO21/DD0P07/DB7/TO28/DD7 P10/DB8/TO29/DD8P17/DB15/TO36/DD15 P20/A23/DD24P27/A30/DD31 P30/A15/TIN4/DD16P33/A18/TIN7/DD19 P34/A19/TIN30/DD20P37/A22/TIN33/DD23 P41/BLW#/BLE# P42/BHW#/BHE# VCCE 8 8 8 4 4 P107/TO15/RXD4/DD0 8 P110/TO0/TO29/DD11P117/TO7/TO36/DD4 P124/TCLK0/A9/DD3 P125/TCLK1/A10/DD2 P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 P130/TIN16/PWMOFF0/DIN0 Port 12 Bus control DRI Port 11 Multijunction timer Address bus 32185/32186 Group P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P136/TIN22/CRX1 VCC-BUS Port 13 Serial Interface CAN Bus control Port 4 Multijunction timer P43/RD# P44/CS0#/TIN8, P45/CS1#/TIN9 P46/A13/TIN10, P47/A14/TIN11 2 2 3 Address bus Port 6 P61-P63 P70/CLKOUT/WR#/BCLK P137/TIN23/CTX1 P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# Port 15 Bus control/ Clock Serial Interface CAN/ Bus control Port 22 Address bus/ Bus control Bus control/ Clock P71/WAIT# Multijunction timer Port 7 Serial Interface VCCE P72/HREQ#/TIN27 P73/HACK#/TIN26 P74/RTDTXD/TXD3/NBDD0 P174/TXD2/TO28 P175/RXD2/TO27 Port 17 NBD VCCE Real time debugger P75/RTDRXD/RXD3/NBDD1 P76/RTDACK/CTX1/NBDD2 P77/RTDCLK/CRX1/NBDD3 VCC-BUS P220/CTX0/HACK# P221/CRX0/HREQ# P224/A11/CS2# P225/A12/CS3# JTRST CAN P82/TXD0/TO26 P83/RXD0/TO25 Serial Interface Port 8 VCCE Multijunction timer P84/SCLKI0/SCLKO0/TO24 P85/TXD1/TO23 P86/RXD1/TO22 P87/SCLKI1/SCLKO1/TO21 VCCE VCCER EXCVCC JTMS JTCK/NBDCLK JTDO/NBDEVNT# JTDI/NBDSYNC# JTAG NBD 2 2 2 Power supply VCC-BUS VDDE EXCVDD VSS 6 Note 1: MOD2 must be connected to the ground (GND). Notes: . The symbol "#" suffixed to the pin (or signal) names means that the pins (or signal) are "L." . VCCE : operates with VCCE power supply . VCC-BUS : operates with VCC-BUS power supply Figure 1.3.1 Pin Function Diagram 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-9 1 Table 1.3.1 Description of Pin Functions (1/3) Type Power supply Pin Name VCCER VCCE Signal Name Internal power supply input Port/internal peripheral I/O pin power supply input VCC-BUS Port/bus interface pin power supply input VDDE VSS EXCVCC EXCVDD Clock XIN, XOUT CLKOUT, BCLK RAM power supply input Ground VCCER control VDDE control Clock input Clock output System clock – – – Input Output Output – – – Input/Output Description – (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). OVERVIEW 1.3 Pin Functions Power supply input for the internal voltage generator circuit Power supply input for the port and internal peripheral I/O pins (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). Apply same voltage to the all VCCE pins. Power supply input for the port and bus interface pins (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). Apply same voltage to the all VCC-BUS pins. Backup power supply input for the internal RAM (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). Connect all VSS pins to ground (GND). This pin connects an external capacitor for the internal voltage generator circuit. This pin connects an external capacitor for the internal power supply of the internal RAM. These are clock input/output pins. Including a PLL-based ×8 frequency multiplier, they input 1/8 of the CPU clock frequency. (XIN input is 10 MHz when f(CPUCLK) = 80 MHz.) The CLKOUT pin outputs a clock that is equal to the external input clock frequency, XIN (i.e., CLKOUT output is 10 MHz when f(CPUCLK) = 80 MHz), or two times of XIN (i.e., CLKOUT output is 20 MHz when f(CPUCLK) = 8 MHz). This clock is used when operations are synchronous external to the chip. The BCLK pin outputs a clock that is two times the external input clock frequency, XIN (i.e. BCLK output is 20 MHz when f(CPUCLK) = 80 MHz). Reset Mode RESET# MOD0− MOD2 Reset Mode Input Input Reset input pin for the internal circuit. Set the microcomputer’s operation mode. MOD0 L L H H X X: Don’t care MOD1 L H L H X MOD2 L L L L H Mode Single-chip mode External extension mode Processor mode (boot mode) (Note 1) (Settings inhibited) (Settings inhibited) Flash protect Address bus FP A9–A30 Flash protect Address bus Input Output This special pin protects the flash memory against rewrites in hardware. Twenty-two address lines (A9–A30) are included, allowing four blocks each up to 8 Mbyte memory space to be connected external to the chip. A31 is not output. Note 1: Boot mode requires that the FP pin should be at the “H” level. For details about boot mode, see Chapter 6, “Internal Memory.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-10 1 Table 1.3.1 Description of Pin Functions (2/3) Type Data bus Pin Name DB0–DB15 Signal Name Data bus Input/Output Description Input/output OVERVIEW 1.3 Pin Functions This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit. These are chip select signals for external devices. This signal is output when reading an external device. This signal is output when writing to an external device. When writing to an external device, this signal indicates the valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0–7 are valid) and the lower address side (bits 8–15 are valid), respectively. During an external device access, this signal indicates that the high-order data (bits 0–7) is valid. During an external device access, this signal indicates that the low-order data (bits 8–15) is valid. When accessing an external device, a “L” level input on WAIT# pin extends the wait cycle. This input pin is used by an external device to request control of the external bus. A ”L” level input on HREQ# pin places the CPU in a hold state. This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Input pins for the multijunction timer. Bus control CS0#–CS3# Chip select RD# WR# Read Write Output Output Output Output BHW#/BLW# Byte high/low write BHE# BLE# WAIT# HREQ# Byte high enable Byte low enable Wait Hold request Output Output Input Input HACK# Multijunction timer Hold acknowledge Output Input TIN0, Timer input TIN3–TIN11, TIN16–TIN27, TIN30–TIN33 TO0–TO36 TCLK0 –TCLK3 Timer output Timer clock Analog power supply input Analog ground Analog input Reference voltage input System break interrupt Output Input – – Input Input Input Output pins for the multijunction timer. Clock input pins for the multijunction timer. AVCC0 is the power supply input for the A/D0 converter. Connect AVCC0 to the power supply rail. AVSS0 is the analog ground for the A/D0 converter. Connect AVSS0 to ground. 16-channel analog input pins for the A/D0 converter. VREF0 is the reference voltage input pin for the A/D0 converter. This is the system break interrupt (SBI) input pin for the interrupt controller. When channel is in UART mode: This pin outputs a clock derived from BRG output by dividing it by 2. When channel is in CSIO mode: This pin inputs a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. A/D converter AVCC0 AVSS0 AD0IN0 –AD0IN15 VREF0 Interrupt controller SBI# Serial interface SCLKI0/ SCLKO0, SCLKI1/ SCLKO1, SCLKI4/ SCLKO4, SCLKI5/ SCLKO5 UART transmit/ Input/output receive clock output or CSIO transmit/ receive clock input/output 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-11 1 Table 1.3.1 Description of Pin Functions (3/3) Type Pin Name Signal Name Input/Output Description Output Input Output Input Input Output Serial interface TXD0–TXD5 Transmit data RXD0–RXD5 Received data Real-time debugger (RTD) RTDTXD RTDRXD RTDCLK RTDACK RTD transmit data RTD received data RTD clock input RTD acknowledge OVERVIEW 1.3 Pin Functions Transmit data output pin for serial interface. Received data input pin for serial interface. Serial data output pin for the real-time debugger. Serial data input pin for the real-time debugger. Serial data transmit/receive clock input pin for the real-time debugger. A “L” level pulse is output from this pin synchronously with the start clock for the real-time debugger’s serial data output word. The “L” level pulse width indicates the type of command/ data received by the real-time debugger. This pin outputs data from the CAN module. This pin inputs the data for the CAN module. Test mode select input to control the state transition of the test circuit. Clock input for the debug module and test circuit. Test reset input to initialize the test circuit asynchronously with device operation. This pin inputs the test instruction code or test data that is serially received. This pin outputs the test instruction code or test data serially. NBD command, address, and data input/output pins. NBD synchronous clock input pin. Input pin to control the start position of NBD data. Output pin used for event output when an NBD event occurs. DRI data input pin. DRI event input pin. Programmable input/output port. CAN JTAG CTX0, CTX1 Transmit data CRX0, CRX1 Received data JTMS JTCK JTRST JTDI JTDO Test mode select Test clock Test reset Test data input Test data output Command/ Address/Data Synchronous clock input Event output DD input DIN input Input/output port 0 Input/output port 1 Input/output port 2 Input/output port 3 Input/output port 4 Input/output port 6 Input/output port 7 Input/output port 8 Input/output port 9 Output Input Input Input Input Input Output Input/output Input Input Output Input Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output NBD NBDD0 –NBDD3 NBDCLK NBDSYNC# Top of data input NBDEVNT# DRI Input/output ports (Note 1) DD0–DD31 DIN0–DIN4 P00–P07 P10–P17 P20–P27 P30–P37 P41–P47 P61–P63 P70–P77 P82–P87 P93–P97 P100–P107 P110–P117 P124–P127 P130–P137 P150, P153 P174, P175 Input/output port 10 Input/output Input/output port 11 Input/output Input/output port 12 Input/output Input/output port 13 Input/output Input/output port 15 Input/output Input/output port 17 Input/output P220, Input/output port 22 Input/output P221 (Note 2), P224, P225 Note 1: Input/output ports 5, 14, 16 and 18−21 are nonexistent. Note 2: P221 is input-only port. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-12 1 1.4 Pin Assignments OVERVIEW 1.4 Pin Assignments Figure 1.4.1 shows the 32185/32186 pin assignment diagram. A pin assignment table is shown in Table 1.4.1. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDDE P102/TO10/CTX0 P101/TO9/CRX0 P100/TO8 P117/TO7/TO36/DD4 P116/TO6/TO35/DD5 P115/TO5/TO34/DD6 P114/TO4/TO33/DD7 P113/TO3/TO32/DD8 P112/TO2/TO31/DD9 P111/TO1/TO30/DD10 P110/TO0/TO29/DD11 VSS VCCE FP MOD1 MOD0 RESET# P97/TO20/DD12 P96/TO19/DD13 P95/TO18/RXD5/DD14 P94/TO17/TXD5/DD15 P93/TO16/SCLKI5/SCLKO5 P77/RTDCLK/CRX1/NBDD3 P76/RTDACK/CTX1/NBDD2 P75/RTDRXD/RXD3/NBDD1 P74/RTDTXD/TXD3/NBDD0 P73/HACK#/TIN26 P72/HREQ#/TIN27 P71/WAIT# P70/CLKOUT/WR#/BCLK SBI# P63 P62 P61 EXCVDD JTMS JTCK/NBDCLK JTRST JTDO/NBDEVNT# JTDI/NBDSYNC# P103/TO11/TIN24 P104/TO12/TIN25/DD3 P105/TO13/SCLKI4/SCLKO4/DD2 P106/TO14/TXD4/DD1 P107/TO15/RXD4/DD0 P124/TCLK0/A9/DD3 P125/TCLK1/A10/DD2 P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 MOD2(Note 1) P130/TIN16/PWMOFF0/DIN0 P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23/CTX1 VCCE P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# P41/BLW#/BLE# P42/BHW#/BHE# EXCVCC VSS P43/RD# P44/CS0#/TIN8 P45/CS1#/TIN9 P46/A13/TIN10 P47/A14/TIN11 P220/CTX0/HACK# 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 32185/32186 Group 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS P87/SCLKI1/SCLKO1/TO21 P86/RXD1/TO22 P85/TXD1/TO23 P84/SCLKI0/SCLKO0/TO24 P83/RXD0/TO25 P82/TXD0/TO26 VCCER P175/RXD2/TO27 P174/TXD2/TO28 VSS EXCVCC AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 P17/DB15/TO36/DD15 P16/DB14/TO35/DD14 P15/DB13/TO34/DD13 P14/DB12/TO33/DD12 P13/DB11/TO32/DD11 Note 1: MOD2 must be connected to the ground (GND). Notes: • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are "L." • Dimensional Outline Drawing is refer to "Appendix 1.1 Dimensional Outline Drawing." Figure 1.4.1 Pin Assignment Diagram (Top View) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 P221/CRX0/HREQ# P225/A12/CS3# VSS XIN XOUT VCC-BUS P224/A11/CS2# P30/A15/TIN4/DD16 P31/A16/TIN5/DD17 P32/A17/TIN6/DD18 P33/A18/TIN7/DD19 P34/A19/TIN30/DD20 P35/A20/TIN31/DD21 P36/A21/TIN32/DD22 P37/A22/TIN33/DD23 P20/A23/DD24 P21/A24/DD25 P22/A25/DD26 P23/A26/DD27 VCC-BUS VSS P24/A27/DD28 P25/A28/DD29 P26/A29/DD30 P27/A30/DD31 P00/DB0/TO21/DD0 P01/DB1/TO22/DD1 P02/DB2/TO23/DD2 P03/DB3/TO24/DD3 P04/DB4/TO25/DD4 P05/DB5/TO26/DD5 P06/DB6/TO27/DD6 P07/DB7/TO28/DD7 P10/DB8/TO29/DD8 P11/DB9/TO30/DD9 P12/DB10/TO31/DD10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Package: 144pin LQFP(PLQP0144KA-A) 1-13 1 OVERVIEW 1.4 Pin Assignments The pins directed for input go to a high-impedance state (Hi-Z) when reset. The term “when reset” means that input on RESET# pin is held “L” (the device remains reset), and that the RESET# pin is released back “H” (the device comes out of reset). Table 1.4.1 Pin Assignments of the 32185/32186 Group (1/4) Pin No. 1 2 3 4 5 6 7 Function Symbol Port P221/CRX0/HREQ# P225/A12/CS3# VSS XIN XOUT VCC-BUS P224/A11/CS2# P221 P225 P224 Function 1 Function 2 CRX0(Note1) HREQ#(Note1) A12 VSS XIN XOUT VCC-BUS A11 CS3#(Note1) CS2#(Note1) DRI function NBD function Type Input Input/ output Input Output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Power supply Pin state when reset Condition Function P221 During single-chip and external extension modes During processor mode Type Input Input State upon State during reset exitingreset Hi-Z Hi-Z Hi-Z XOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Undefined XOUT Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Undefined Hi-Z Hi-Z - VCC-BUS P225 VCC-BUS During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode A12 Output VSS XIN Input XOUT Output VCC-BUS P224 A11 P30 A15 P31 A16 P32 A17 P33 A18 P34 A19 P35 A20 P36 A21 P37 A22 P20 A23 P21 A24 P22 A25 P23 Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input 8 P30/A15/TIN4/DD16 P30 A15 TIN4 DD16 9 P31/A16/TIN5/DD17 P31 A16 TIN5 DD17 10 P32/A17/TIN6/DD18 P32 A17 TIN6 DD18 11 P33/A18/TIN7/DD19 P33 A18 TIN7 DD19 12 P34/A19/TIN30/DD20 P34 A19 TIN30 DD20 13 P35/A20/TIN31/DD21 P35 A20 TIN31 DD21 14 P36/A21/TIN32/DD22 P36 A21 TIN32 DD22 15 P37/A22/TIN33/DD23 P37 A22 TIN33 DD23 16 P20/A23/DD24 P20 A23 - DD24 VCC-BUS 17 P21/A24/DD25 P21 A24 - DD25 18 P22/A25/DD26 P22 A25 - DD26 19 P23/A26/DD27 20 VCC-BUS 21 VSS 22 P24/A27/DD28 P23 P24 A26 VCC-BUS VSS A27 - DD27 DD28 During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode Output A26 VCC-BUS VSS P24 A27 P25 A28 P26 A29 P27 A30 P00 DB0 Input Output Input Output Input Output Input Output Input Input/output 23 P25/A28/DD29 P25 A28 - DD29 24 P26/A29/DD30 P26 A29 - DD30 VCC-BUS 25 P27/A30/DD31 P27 A30 - DD31 26 P00/DB0/TO21/DD0 P00 DB0 TO21(Note1) DD0(Note1) Note1: The pins are outputted at two places. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-14 1 Table 1.4.1 Pin Assignments of the 32185/32186 Group (2/4) Pin No. 27 Function Symbol P01/DB1/ TO22/DD1 P02/DB2/ TO23/DD2 P03/DB3/ TO24/DD3 P04/DB4/ TO25/DD4 P05/DB5/ TO26/DD5 P06/DB6/ TO27/DD6 P07/DB7/ TO28/DD7 P10/DB8/ TO29/DD8 P11/DB9/ TO30/DD9 P12/DB10/ TO31/DD10 P13/DB11/ TO32/DD11 P14/DB12/ TO33/DD12 P15/DB13/ TO34/DD13 P16/DB14/ TO35/DD14 P17/DB15/ TO36/DD15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Port P01 Function 1 DB1 Function 2 TO22(Note1) DRI function NBD function OVERVIEW 1.4 Pin Assignments Type Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Power supply Pin state when reset Condition Function P01 DB1 P02 DB2 P03 DB3 P04 DB4 P05 DB5 P06 DB6 P07 DB7 P10 DB8 P11 DB9 P12 DB10 P13 DB11 P14 DB12 P15 DB13 P16 DB14 P17 Type Input Input/output State upon State during reset exiting Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DD1(Note1) 28 P02 DB2 TO23(Note1) DD2(Note1) 29 P03 DB3 TO24(Note1) DD3(Note1) 30 P04 DB4 TO25(Note1) DD4(Note1) 31 P05 DB5 TO26(Note1) DD5(Note1) 32 P06 DB6 TO27(Note1) DD6(Note1) 33 P07 DB7 TO28(Note1) DD7(Note1) 34 P10 DB8 TO29(Note1) DD8(Note1) 35 P11 DB9 TO30(Note1) DD9(Note1) 36 P12 DB10 TO31(Note1) DD10(Note1) 37 P13 DB11 TO32(Note1) DD11(Note1) 38 P14 DB12 TO33(Note1) DD12(Note1) 39 P15 DB13 TO34(Note1) DD13(Note1) 40 P16 DB14 TO35(Note1) DD14(Note1) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 P17 - DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 TO36(Note1) - DD15(Note1) - During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and VCC-BUS external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode AVCC0 - Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input AVCC0 Input/output DB15 VREF0 AVCC0 Input AD0IN0 Input AD0IN1 Input AD0IN2 Input AD0IN3 Input AD0IN4 Input AD0IN5 Input AD0IN6 Input AD0IN7 Input AD0IN8 Input AD0IN9 Input AD0IN10 Input AD0IN11 Input AD0IN12 Input AD0IN13 Input AD0IN14 Input AD0IN15 Note1: The pins are outputted at two places. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-15 1 Table 1.4.1 Pin Assignments of the 32185/32186 Group (3/4) Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Function Symbol AVSS0 EXCVCC VSS P174/TXD2/TO28 P175/RXD2/TO27 VCCER P82/TXD0/TO26 P83/RXD0/TO25 P84/SCLKI0/ SCLKO0/TO24 P85/TXD1/TO23 P86/RXD1/TO22 P87/SCLKI1/ SCLKO1/TO21 VSS EXCVDD P61 P62 P63 SBI# P70/CLKOUT/WR# /BCLK P71/WAIT# P72/HREQ#/TIN27 P73/HACK#/TIN26 P74/RTDTXD/ TXD3/NBDD0 P75/RTDRXD/ RXD3/NBDD1 P76/RTDACK/ CTX1/NBDD2 P77/RTDCLK/ CRX1/NBDD3 P93/TO16/ SCLKI5/SCLKO5 P94/TO17/ TXD5/DD15 P95/TO18/ RXD5/DD14 P96/TO19/DD13 P97/TO20/DD12 RESET# MOD0 MOD1 FP VCCE VSS P110/TO0/TO29/DD11 P111/TO1/TO30/DD10 P112/TO2/TO31/DD9 P113/TO3/TO32/DD8 P114/TO4/TO33/DD7 P115/TO5/TO34/DD6 P116/TO6/TO35/DD5 P117/TO7/TO36/DD4 P100/TO8 P101/TO9/CRX0 P102/TO10/CTX0 VDDE JTMS (Note2) JTCK/NBDCLK (Note2) JTRST (Note2) Port P174 P175 P82 P83 P84 P85 P86 P87 P61 P62 P63 P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 Function 1 AVSS0 EXCVCC VSS TXD2 RXD2 VCCER TXD0 RXD0 SCLKI0/ SCLKO0 TXD1 RXD1 SCLKI1/ SCLKO1 VSS EXCVDD SBI# CLKOUT/ WR# WAIT# HREQ# HACK# Function 2 TO28(Note1) TO27(Note1) TO26(Note1) TO25(Note1) TO24(Note1) TO23(Note1) TO22(Note1) TO21(Note1) BCLK TIN27 TIN26 DRI function NBD function OVERVIEW 1.4 Pin Assignments Type Input/output Input/output Input/output Input/output Input/output Power Condition supply VCCE - Function AVSS0 EXCVCC VSS P174 P175 VCCER P82 P83 P84 NBDD0 Pin state when reset State State upon during reset exiting Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Input/ output Input/output Input/output VCCE P85 P86 P87 Input/ output Input/output Input/output Input/output - Input Input/ output Input/output Input/output Input/output VSS EXCVDD P61 P62 P63 SBI# P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 RESET# MOD0 MOD1 FP VCCE VSS P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 VDDE JTMS JTCK JTRST JTDO JTDI P103 P104 P105 P106 RTDTXD TXD3(Note1) RTDRXD RXD3(Note1) RTDACK CTX1(Note1) RTDCLK CRX1(Note1) TO16 TO17 TO18 TO19 TO20 RESET# MOD0 MOD1 FP VCCE VSS TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO8 TO9 TO10 VDDE JTMS JTCK JTRST JTDO JTDI TO11 TO12 TO13 TO14 SCLKI5/ SCLKO5 TXD5 RXD5 TO29(Note1) TO30(Note1) TO31(Note1) TO32(Note1) TO33(Note1) TO34(Note1) TO35(Note1) TO36(Note1) CRX0(Note1) CTX0(Note1) TIN24 TIN25 SCLKI4/ SCLKO4 TXD4 P96 P97 P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 JTDO/NBDEVNT# (Note2) JTDI/NBDSYNC# (Note2) P103 P103/TO11/TIN24 P104 P104/TO12/TIN25/DD3 P105/TO13/ 116 P105 SCLKI4/SCLKO4/DD2 117 P106/TO14/TXD4/DD1 P106 Input/ output Input/ NBDD1 output Input/ NBDD2 output VCCE Input/ NBDD3 output Input/ output Input/ DD15(Note1) output Input/ DD14(Note1) output DD13(Note1) Input/output DD12(Note1) Input/output Input Input Input Input DD11(Note1) Input/output DD10(Note1) Input/output DD9(Note1) Input/output DD8(Note1) Input/output DD7(Note1) Input/output DD6(Note1) Input/output VCCE DD5(Note1) Input/output DD4(Note1) Input/output Input/output Input/output Input/output Input NBDCLK Input Input NBDEVNT# Output NBDSYNC# Input VCCE Input/output DD3(Note1) Input/output Input/ DD2(Note1) output DD1(Note1) Input/output Note 1: The pins are outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, not reset from the RESET# pin. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-16 1 Table 1.4.1 Pin Assignments of the 32185/32186 Group (4/4) Pin No. Function Symbol Port Function 1 TO15 TCLK0 Function 2 RXD4 A9 Power DRI function Type supply NBD function DD0(Note1) Input/output DD3(Note1) Input/ output DD2(Note1) Input/ output Condition 118 P107/TO15/RXD4/DD0 P107 119 P124/TCLK0/A9/DD3 P124 During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode OVERVIEW 1.4 Pin Assignments Pin state when reset Function P107 P124 A9 P125 A10 P126 P127 MOD2 P130 P131 P132 P133 P134 P135 P136 P137 VCCE P150 During single-chip mode During external extension and processor modes During single-chip mode During external extension and processor modes P153 P41 BLW#/ BLE# P42 BHW#/ BHE# EXCVCC VSS P43 RD# P44 CS0# P45 CS1# P46 A13 P47 A14 P220 Type Input Input Output Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input State State upon during reset exiting reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z "H" level Hi-Z "H" level Hi-Z "H" level Hi-Z "H" level Hi-Z "H" level Hi-Z Undefined Hi-Z Undefined Hi-Z 120 P125/TCLK1/A10/DD2 P126/TCLK2/ 121 CS2#/DD1 122 P127/TCLK3/ CS3#/DD0 MOD2 123 P130/TIN16/ 124 PWMOFF0/DIN0 125 P131/TIN17/ PWMOFF1/DIN1 126 P132/TIN18/DIN2 127 P133/TIN19/DIN3 P134/TIN20/ 128 TXD3/DIN4 129 P135/TIN21/RXD3 130 P136/TIN22/CRX1 131 P137/TIN23/CTX1 VCCE 132 P150/TIN0/ 133 CLKOUT/WR# 134 P153/TIN3/WAIT# 135 P41/BLW#/BLE# P125 P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P150 P153 P41 TCLK1 TCLK2 A10 CS2#(Note1) Input/ DD1(Note1) output DD0(Note1) Input/ CS3#(Note1) TCLK3 output MOD2 VCCE TIN16/ Input/ DIN0 output PWMOFF0 TIN17/ Input/ DIN1 output PWMOFF1 Input/output DIN2 TIN18 Input/output DIN3 TIN19 Input/ DIN4 TXD3(Note1) TIN20 output Input/output RXD3(Note1) TIN21 Input/output CRX1(Note1) TIN22 Input/output CTX1(Note1) TIN23 VCCE CLKOUT(Note1) Input/ TIN0 output / WR#(Note1) WAIT#(Note1) TIN3 Input/output BLW#/ BLE# BHW#/ BHE# EXCVCC VSS RD# Input/ output VCC-BUS 136 P42/BHW#/BHE# 137 138 139 EXCVCC VSS P43/RD# P42 P43 - - Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/output During single-chip mode During external extension and processor modes During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 140 P44/CS0#/TIN8 P44 CS0# TIN8 - VCC-BUS 141 P45/CS1#/TIN9 P45 CS1# TIN9 - 142 P46/A13/TIN10 P46 A13 TIN10 - 143 P47/A14/TIN11 144 P220/CTX0/HACK# P47 P220 A14 TIN11 - CTX0(Note1) HACK#(Note1) Note1: The pins are outputted at two places. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-17 1 OVERVIEW 1.4 Pin Assignments This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1-18 CHAPTER 2 CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 CPU Registers General-purpose Registers Control Registers Accumulator Program Counter Data Formats Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution 2 2.1 CPU Registers CPU 2.1 CPU Registers The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration. 2.2 General-purpose Registers The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). Upon exiting the reset state, the value of the general-purpose registers is undefined. b0 b31 b0 b31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1) Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW. Figure 2.2.1 General-purpose Registers 2.3 Control Registers There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating-point Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. CRn b0 CR0 CR1 CR2 CR3 CR6 CR7 b31 PSW CBR SPI SPU BPC FPSR Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer Backup PC Floating-point Status Register Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number. • The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. • The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. Figure 2.3.1 Control Registers 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-2 2 2.3.1 Processor Status Word Register: PSW (CR0) b0 0 CPU 2.3 Control Registers 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 b16 BSM ? 17 BIE ? 18 0 19 0 20 0 21 0 22 0 23 BC ? 24 SM 0 25 IE 0 26 0 27 0 28 0 29 0 30 0 b31 C 0 BPSW field PSW field b 0–15 16 17 18–22 23 24 25 26–30 31 Bit Name No function assigned. Fix to "0." BSM Backup SM Bit BIE Backup IE Bit No function assigned. Fix to "0." BC Backup C Bit SM Stack Mode Bit IE Interrupt Enable Bit (Note 1) No function assigned. Fix to "0." C Condition Bit Function R 0 W 0 W W 0 W W W 0 W Saves value of SM bit when EIT occurs Saves value of IE bit when EIT occurs R R 0 Saves value of C bit when EIT occurs 0: Uses R15 as the interrupt stack pointer 1: Uses R15 as the user stack pointer 0: Does not accept interrupt 1: Accepts interrupt R R R 0 Indicates carry, borrow or overflow resulting from operations (instruction dependent) R Note 1: Interrupt which is controllable is External Interrupt (EI). Reserved Instruction Exception (RIE), Address Except (AE), FP Floating-point Except (FPE), Reset Interrupt (RI), System Break Interrupt (SBI) and Trap are not controled. The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. Upon exiting the reset state, BSM, BIE and BC are undefined. All other bits are "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-3 2 2.3.2 Condition Bit Register: CBR (CR1) CPU 2.3 Control Registers The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) Upon exiting the reset state, the value of CBR is H’0000 0000. b0 b31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C CBR 0 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. Upon exiting the reset state, the values of the SPI and SPU are undefined. b0 b31 SPI SPI b0 b31 SPU SPU 2.3.4 Backup PC: BPC (CR6) The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0." When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) Upon exiting the reset state, the value of the BPC is undefined. b0 b31 BPC BPC 0 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-4 2 2.3.5 Floating-point Status Register: FPSR (CR7) b0 FS 0 CPU 2.3 Control Registers 1 FX 0 2 FU 0 3 FZ 0 4 FO 0 5 FV 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 b16 0 17 EX 0 18 EU 0 19 EZ 0 20 EO 0 21 EV 0 22 0 23 DN 1 24 CE 0 25 CX 0 26 CU 0 27 CZ 0 28 CO 0 29 CV 0 30 0 b31 RM 0 b 0 1 Bit Name Function R R R W – W FS Reflects the logical sum of FU, FZ, FO and FV. Floating-point Exception Summary Bit FX Inexact Exception Flag Set to "1" when an inexact exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an underflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when a zero divide exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an overflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. 2 FU Underflow Exception Flag FZ Zero Divide Exception Flag R W 3 R W 4 FO Overflow Exception Flag R W 5 FV Invalid Operation Exception Flag Set to "1" when an invalid operation exception occurs (if EIT processing R is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. 0 0: Mask EIT processing to be executed when an inexact exception occurs. 1: Execute EIT processing when an inexact exception occurs. 0: Mask EIT processing to be executed when an underflow exception occurs. 1: Execute EIT processing when an underflow exception occurs. 0: Mask EIT processing to be executed when a zero divide exception occurs. 1: Execute EIT processing when a zero divide exception occurs. 0: Mask EIT processing to be executed when an overflow exception occurs. 1: Execute EIT processing when an overflow exception occurs. 0: Mask EIT processing to be executed when an invalid operation exception occurs. 1: Execute EIT processing when an invalid operation exception occurs. 0 0: Handle the denormalized number as a denormalized number. 1: Handle the denormalized number as zero. 0: No unimplemented operation exception occurred. 1: An unimplemented operation exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." 0: No inexact exception occurred. 1: An inexact exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." R R R R R R W 6–16 17 18 No function assigned. Fix to "0." EX Inexact Exception Enable Bit EU Underflow Exception Enable Bit 0 W W 19 EZ Zero Divide Exception Enable Bit W 20 EO Overflow Exception Enable Bit W 21 EV Invalid Operation Exception Enable Bit W 22 23 No function assigned. Fix to "0." DN Denormalized Number Zero Flush Bit (Note 2) 0 W 24 CE Unimplemented Operation Exception Cause Bit R (Note 3) 25 CX Inexact Exception Cause Bit R (Note 3) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-5 2 26 CU Underflow Exception Cause Bit 27 CZ Zero Divide Exception Cause Bit 28 CO Overflow Exception Cause Bit 29 CV Invalid Operation Exception Cause Bit RM Rounding Mode Selection Bit 0: No underflow exception occurred 0: No zero divide exception occurred. CPU 2.3 Control Registers R (Note 3) 1: An underflow exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." R (Note 3) 1: A zero divide exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." 0: No overflow exception occurred. 1: An overflow exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." 0: No invalid operation exception occurred. R (Note 3) 1: An invalid operation exception occurred. When the bit is set to "1," the execution of an FPU operation instruction will clear it to "0." 00: Round to nearest 01: Round toward Zero 10: Round toward + Infinity 11: Round toward – Infinity R W R (Note 3) 30, 31 Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bits settings. Note 2: If a denormalized number is given to the operand when DN = "0," an unimplemented exception occurs. Note 3: This bit is cleared by writing "0." Writing "1" has no effect (the bit retains the value it had before the write). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-6 2 2.4 Accumulator CPU 2.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the loworder 32 bits (bits 32–63) and the middle 32 bits (bits 16–47), respectively. Upon exiting the reset state, the value of accumulator is undefined. (Note 1) b0 78 15 16 Read range of MVFACMI instruction 31 32 47 48 b63 ACC Write and read ranges of MVTACHI and MVFACHI instructions Write and read ranges of MVTACLO and MVFACLO instructions Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored. 2.5 Program Counter The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0." Upon exiting the reset state, the value of PC is H’0000 0000. b0 b31 PC PC 0 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-7 2 2.6 Data Formats 2.6.1 Data Types CPU 2.6 Data Formats The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements. b0 b7 Signed byte (8-bit) integer S b0 b7 Unsigned byte (8-bit) integer b0 b15 Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer S b0 b15 b0 b31 Signed word (32-bit) integer S b0 b31 Unsigned word (32-bit) integer b0 b1 b8 b9 b31 Single-precision floating-point number S E F S: Sign bit; E: Exponent field; F: Fraction field Figure 2.6.1 Data Types 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-8 2 2.6.2 Data Formats (1) Data formats in registers CPU 2.6 Data Formats The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is signextended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8-bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively. b0 Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) 24 b31 Rn Sign-extended (LDH instruction) or Byte From memory (LDH, LDUH instructions) b31 b0 zero-extended (LDUH instruction) 16 Rn Halfword From memory (LD instruction) b0 b31 Rn Word b0 24 b31 Rn Byte To memory (STB instruction) b0 16 b31 Rn Halfword To memory (STH instruction) b0 b31 Rn Word To memory (ST instruction) Figure 2.6.2 Data Formats in Registers 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-9 2 (2) Data formats in memory CPU 2.6 Data Formats The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs. Address +0 address b0 +1 address 78 +2 address +3 address b31 15 16 23 24 Byte Byte Byte Byte Byte b0 15 b31 Halfword Halfword Halfword b0 b31 Word Word Figure 2.6.3 Data Formats in Memory (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R Family microcomputers. Bit endian (H'01) Byte endian (H'01234567) Big endian B'0000001 b0 b7 H'01 HH H'23 HL H'45 LH H'67 LL Little endian B'0000001 b7 b0 H'67 LL H'45 LH H'23 HL H'01 HH Note: • Even when bits are arranged in big endian, H'01 is not B'10000000. Figure 2.6.4 General Endian System 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-10 2 Microcomputer family name Endian (bit/byte) Address Data arrangement Bit number Example: 0x01234567 +0 CPU 2.6 Data Formats 7700 and M16C Families M32R Family Little/little +1 +2 +3 +0 Little/big +1 +2 +3 +0 Big/big +1 +2 +3 LL LH HL HH HH HL LH LL HH HL LH LL 7–0 15–8 23–16 31–24 31–24 23–16 15–8 7–0 0–7 8–15 16–23 24–31 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: • The M32R family uses the big endian for both bits and bytes. Figure 2.6.5 Endian Adopted for the M32R Family (4) Transfer instructions • Constant transfer LD24 LDI LDI Rdest, #imm24 Rdest, #imm16 Rdest, #imm8 LD24 Rdest, #imm24 imm24 b0 b23 Rdest 00 b0 8 b31 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 b0 b15 Rdest b0 15 00 00 b31 • Register to register transfer MV MV Rdest, Rsrc Rsrc b0 b31 Rdest, Rsrc Rdest b0 b31 • Control register transfer MVTC Rsrc, CRdest MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc b0 b31 CRdest b0 b31 Note: • The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction. Figure 2.6.6 Transfer Instructions 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-11 2 (5) Transfer from memory (signed) to registers CPU 2.6 Data Formats • Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc label Memory Rdest +0 +1 +2 +3 Register b0 b31 • Signed 16 bits label LD24 Rsrc, #label LDH Rdest, @Rsrc Rdest +0 +1 +2 +3 Determined by MSB 0: Positive number 1: Negative number 00 FF b0 00 FF b31 • Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest +0 +1 +2 +3 Determined by MSB 0: Positive number 1: Negative number 00 FF b0 00 FF 00 FF b31 Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers Memory • Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc label Rdest Register +0 +1 +2 +3 b0 b31 • Unsigned 16 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc label Rdest 00 +0 +1 +2 +3 b0 00 b31 • Unsigned 8 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc label Rdest 00 +0 +1 +2 +3 b0 00 00 b31 Figure 2.6.8 Transfer from Memory (Unsigned) to Registers 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-12 2 (7) Notes on data transfer CPU 2.6 Data Formats When transferring data, be aware that data arrangements in registers and memory are different. Data in registers Data in memory • Word data (32 bits) (R0–R15) HH HL LH LL +0 HH +1 HL +2 LH +3 LL b0 b31 b0 b31 • Halfword data (16 bits) (R0–R15) H L +0 H +1 L +2 +3 b0 b31 b0 b15 (R0–R15) H L +0 b31 +1 +2 H +3 L b0 b16 b31 • Byte data (8 bits) (R0–R15) b0 b31 b0 +0 b7 +1 +2 +3 (R0–R15) b0 b31 +0 b8 +1 b15 +2 +3 (R0–R15) b0 b31 +0 +1 +2 b16 b23 +3 (R0–R15) b0 b31 +0 +1 +2 +3 b24 b31 Figure 2.6.9 Difference in Data Arrangements 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-13 2 CPU 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes. The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU. • When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted • When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied Control of the bus may be requested by devices other than the CPU in the following two cases: • When DMA transfer is requested by the internal DMAC • When HREQ# input is pulled "L" to request that the CPU be placed in a hold state 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 2-14 CHAPTER 3 ADDRESS SPACE 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Outline of Address Space Operation Modes Internal ROM and External Extension Areas Internal RAM and SFR Areas EIT Vector Entry ICU Vector Table Notes on Address Space 3 3.1 Outline of Address Space ADDRESS SPACE 3.1 Outline of Address Space The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space • Internal ROM area • External extension area • Internal RAM area • SFR (Special Function Register) area The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an external extension area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and external extension areas are located differently depending on mode settings as will be described later. (2) System space(not open to the user) The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space. This space (except for SFR area for NBD control) is reserved for use by development tools such as an incircuit emulator and debug monitor. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-2 3 3.2 Operation Modes ADDRESS SPACE 3.2 Operation Modes The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.6, “Programming the Internal Flash Memory.” Table 3.2.1 Operation Mode Settings MOD0 VSS VSS VCCE VCCE – MOD1 VSS VCCE VSS VCCE – MOD2 (Note 1) VSS VSS VSS VSS VCCE Operation mode (Note 2) Single-chip mode External extension mode Processor mode (FP = VSS) (Settings inhibited) (Settings inhibited) Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.6, “Programming the Internal Flash Memory.” The internal ROM and external extension areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The following diagram shows how the internal ROM and external extension areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.6, “Programming the Internal Flash Memory.”) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-3 3 Logical address H'0000 0000 ADDRESS SPACE 3.2 Operation Modes (64 Mbytes) External extension mode Internal ROM H'0000 0000 Internal ROM area (512 Kbytes) H'0007 FFFF area (512 Kbytes) H'0008 0000 Reserved H'000F FFFF area (512 Kbytes) Single chip mode H'0010 0000 Processor mode CS0 area (8 Mbytes) (64 Mbytes) SFR area (16 Kbytes) Internal RAM area (32 Kbytes) CS0 area (7 Mbytes) H'007F FFFF H'0080 0000 SFR area H'0080 3FFF (16 Kbytes) H'0080 4000 Internal RAM H'0080 BFFF H'0080 C000 H'00FF FFFF H'0100 0000 2 Gbytes User space Ghost area in 64-Mbyte units area (32 Kbytes) SFR area (16 Kbytes) Internal RAM area (32 Kbytes) CS1 area (8 Mbytes) H'017F FFFF H'0180 0000 CS1 area (8 Mbytes) (64 Mbytes) H'7FFF FFFF H'8000 0000 H'01FF FFFF H'0200 0000 CS2 area (8 Mbytes) H'027F FFFF H'0280 0000 CS2 area (8 Mbytes) 2 Gbytes System space H'02FF FFFF H'0300 0000 CS3 area (8 Mbytes) H'E000 0000 NBD control H'037F FFFF H'0380 0000 CS3 area (8 Mbytes) H'FFFF FFFF H'03FF FFFF Notes: • CS0–CS3 areas: External extension areas of up to 32 Mbytes • : Indicate Ghost area. This area must not be used during programing intentionally. Figure 3.2.1 Address Space of the M32185F4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-4 3 Logical address H'0000 0000 ADDRESS SPACE 3.2 Operation Modes Single chip mode H'0000 0000 External extension mode Internal ROM area (1 Mbyte) H'000F FFFF H'0010 0000 Processor mode (64 Mbytes) Internal ROM area (1 Mbyte) CS0 area (8 Mbytes) CS0 area (7 Mbytes) (64 Mbytes) SFR area (16 Kbytes) Internal RAM area (64 Kbytes) 2 Gbytes User space H'007F FFFF H'0080 0000 SFR area H'0080 3FFF (16 Kbytes) H'0080 4000 Internal RAM H'0081 3FFF H'0081 4000 H'00FF FFFF H'0100 0000 Ghost area in 64-Mbyte units area (64 Kbytes) SFR area (16 Kbytes) Internal RAM area (64 Kbytes) CS1 area (8 Mbytes) H'017F FFFF H'0180 0000 CS1 area (8 Mbytes) (64 Mbytes) H'7FFF FFFF H'8000 0000 H'01FF FFFF H'0200 0000 CS2 area (8 Mbytes) H'027F FFFF H'0280 0000 CS2 area (8 Mbytes) 2 Gbytes System space H'02FF FFFF H'0300 0000 CS3 area (8 Mbytes) H'E000 0000 NBD control H'037F FFFF H'0380 0000 CS3 area (8 Mbytes) H'FFFF FFFF H'03FF FFFF Notes: • CS0–CS3 areas: External extension areas of up to 32 Mbytes • : Indicate Ghost area. This area must not be used during programing intentionally. Figure 3.2.2 Address Space of the M32186F8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-5 3 ADDRESS SPACE 3.3 Internal ROM and External Extension Areas 3.3 Internal ROM and External Extension Areas The 64-Mbyte area in the user space from the address H’0000 0000 to the address H’03FF FFFF comprise the internal ROM and external extension areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, “Operation Modes.” 3.3.1 Internal ROM Area The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address Type Name M32185F4 M32186F8 Size 512 Kbytes 1 Mbyte Allocation Address H’0000 0000 to H’0007 FFFF H’0000 0000 to H’000F FFFF 3.3.2 External Extension Area The external extension area is only available when external extension or processor mode is selected by operation mode settings. When accessing the external extension area, the control signals necessary to access external devices are output. The CS0# through CS3# signals are output corresponding to the address mapping of the external extension area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively. Table 3.3.2 Address Mapping of the External Extension Area in Each Operation Mode Operation Mode Single-chip mode External extension mode Address Mapping of External Extension Area None Addresses H’0010 0000 to H’007F FFFF (CS0 area: 7 Mbytes) Addresses H’0100 0000 to H’017F FFFF (CS1 area: 8 Mbytes) Addresses H’0200 0000 to H’027F FFFF (CS2 area: 8 Mbytes) Addresses H’0300 0000 to H’037F FFFF (CS3 area: 8 Mbytes) Processor mode Addresses H’0000 0000 to H’007F FFFF (CS0 area: 8 Mbytes) Addresses H’0100 0000 to H’017F FFFF (CS1 area: 8 Mbytes) Addresses H’0200 0000 to H’027F FFFF (CS2 area: 8 Mbytes) Addresses H’0300 0000 to H’037F FFFF (CS3 area: 8 Mbytes) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-6 3 3.4 Internal RAM and SFR Areas ADDRESS SPACE 3.4 Internal RAM and SFR Areas The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 256-Kbyte area from the address H’0080 0000 to the address H’0083 FFFF. The other areas here are ghosts in 256-Kbyte units. (Do not use the ghost area intentionally during programming.) 3.4.1 Internal RAM Area The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address Type Name M32185F4 M32186F8 Size 32 Kbytes 64 Kbytes Allocation Address H’0080 4000 to H’0080 BFFF H’0080 4000 to H’0081 3FFF 3.4.2 SFR (Special Function Register) Area The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. H'0080 0000 H'0080 3FFF H'0080 4000 SFR area (16 Kbytes) Internal RAM (32 Kbytes) Virtual flash emulation areas separated in 8-Kbyte units can be allocated here. For details, see Section 6.7. H'0080 BFFF Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32185F4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-7 3 H'0080 0000 H'0080 3FFF H'0080 4000 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR area (16 Kbytes) Internal RAM (64 Kbytes) Virtual flash emulation areas separated in 8-Kbyte units can be allocated here. For details, see Section 6.7. H'0081 3FFF Figure 3.4.2 Internal RAM and SFR (Special Function Register) Areas of the M32186F8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-8 3 SFR Area Register Map (1/37) Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 5-5 (Use inhibited area) (Use inhibited area) 5-6 5-7 | H'0080 0056 RAM Write Monitor Interrupt Control Register CAN1 Error Interrupt Control Register (IRAMWRCR) (ICAN1ERCR) H'0080 0058 CAN1 Single-Shot Interrupt Control Register CAN1 Transmit/Receive Interrupt Control Register (ICAN1SSCR) (ICAN1TRCR) H'0080 005A CAN0 Error Interrupt Control Register CAN0 Single-Shot Interrupt Control Register (ICAN0ERCR) (ICAN0SSCR) H'0080 005C CAN0 Transmit/Receive Interrupt Control Register DRI Event Detection Interrupt Control Register (ICAN0TRCR) (IDRIEVCR) H'0080 005E DRI Counter Interrupt Control Register DRI Transfer Interrupt Control Register (IDRICNTCR) (IDRITRCR) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register TML1 Input Interrupt Control Register (ICAN0CR) (ITML1CR) H'0080 0062 (Use inhibited area) H'0080 0064 H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E H'0080 0080 H'0080 0082 H'0080 0084 H'0080 0086 H'0080 0088 H'0080 008A H'0080 008C H'0080 008E SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TID1 Output Interrupt Control Register ( ITID1CR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) TOU0 Output Interrupt Control Register (ITOU0CR) A/D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 6 (IMJTOCR6) MJT Input Interrupt Control Register 0 (IMJTICR0) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 4 (IMJTICR4) A/D0 Single Mode Register 0 (AD0SIM0) (Use inhibited area) TOU1 Output Interrupt Control Register (ITOU1CR) RTD Interrupt Control Register (IRTDCR) DMA5–9 Interrupt Control Register (IDMA59CR) TID0 Output Interrupt Control Register (ITID0CR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0–4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 3 (IMJTICR3) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) A/D0 Single Mode Register 1 (AD0SIM1) A/D0 Single Mode Register 2 (AD0SIM2) A/D0 Scan Mode Register 0 A/D0 Scan Mode Register 1 (AD0SCM0) (AD0SCM1) A/D0 Disconnection Detection Assist A/D0 Conversion Speed Control Register Function Control Register (AD0DDACR) (AD0CVSCR) A/D0 Successive Approximation Register (AD0SAR) A/D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) A/D0 Comparate Data Register (AD0CMP) (Use inhibited area) 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 11-17 11-19 11-21 11-22 11-24 11-27 11-26 11-31 11-28 11-32 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-9 3 SFR Area Register Map (2/37) Address b0 H'0080 0090 H'0080 0092 H'0080 0094 H'0080 0096 H'0080 0098 H'0080 009A H'0080 009C H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 H'0080 00A8 H'0080 00AA H'0080 00AC H'0080 00AE +0 address b7 b8 10-bit A/D0 Data Register 0 (AD0DT0) 10-bit A/D0 Data Register 1 (AD0DT1) 10-bit A/D0 Data Register 2 (AD0DT2) 10-bit A/D0 Data Register 3 (AD0DT3) 10-bit A/D0 Data Register 4 (AD0DT4) 10-bit A/D0 Data Register 5 (AD0DT5) 10-bit A/D0 Data Register 6 (AD0DT6) 10-bit A/D0 Data Register 7 (AD0DT7) 10-bit A/D0 Data Register 8 (AD0DT8) 10-bit A/D0 Data Register 9 (AD0DT9) 10-bit A/D0 Data Register 10 (AD0DT10) 10-bit A/D0 Data Register 11 (AD0DT11) 10-bit A/D0 Data Register 12 (AD0DT12) 10-bit A/D0 Data Register 13 (AD0DT13) 10-bit A/D0 Data Register 14 (AD0DT14) 10-bit A/D0 Data Register 15 (AD0DT15) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 11-33 | H'0080 00D0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE 8-bit A/D0 Data Register 0 (AD08DT0) 8-bit A/D0 Data Register 1 (AD08DT1) 8-bit A/D0 Data Register 2 (AD08DT2) 8-bit A/D0 Data Register 3 (AD08DT3) 8-bit A/D0 Data Register 4 (AD08DT4) 8-bit A/D0 Data Register 5 (AD08DT5) 8-bit A/D0 Data Register 6 (AD08DT6) 8-bit A/D0 Data Register 7 (AD08DT7) 8-bit A/D0 Data Register 8 (AD08DT8) 8-bit A/D0 Data Register 9 (AD08DT9) 8-bit A/D0 Data Register 10 (AD08DT10) 8-bit A/D0 Data Register 11 (AD08DT11) 8-bit A/D0 Data Register 12 (AD08DT12) 8-bit A/D0 Data Register 13 (AD08DT13) 8-bit A/D0 Data Register 14 (AD08DT14) 8-bit A/D0 Data Register 15 (AD08DT15) 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 11-34 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-10 3 SFR Area Register Map (3/37) Address b0 H'0080 0100 H'0080 0102 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 12-9 12-10 12-11 | H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 H'0080 0118 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Mask Register (SI23STAT) (SI03MASK) SIO03 Interrupt Request Source Select Register (Use inhibited area) (SI03SEL) (Use inhibited area) SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register (S0TCNT) (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register SIO0 Baud Rate Register (S0RCNT) (S0BAUR) SIO0 Special Mode Register (Use inhibited area) (S0SMOD) (Use inhibited area) SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register (S1TCNT) (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register SIO1 Baud Rate Register (S1RCNT) (S1BAUR) SIO1 Special Mode Register (Use inhibited area) (S1SMOD) (Use inhibited area) SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register (S2TCNT) (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register SIO2 Baud Rate Register (S2RCNT) (S2BAUR) SIO2 Special Mode Register (Use inhibited area) (S2SMOD) (Use inhibited area) SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register (S3TCNT) (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SSIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register SIO3 Baud Rate Register (S3RCNT) (S3BAUR) SIO3 Special Mode Register (Use inhibited area) (S3SMOD) (Use inhibited area) CS0 Area Wait Control Register CS1 Area Wait Control Register (CS0WTCR) (CS1WTCR) CS2 Area Wait Control Register CS3 Area Wait Control Register (CS2WTCR) (CS3WTCR) (Use inhibited area) CLKOUT Select Register (CLKOUTSEL) Flash E/W Wait Select Register (FWAIT) (Use inhibited area) Flash Mode Register (FMOD) Flash Status Register (FSTAT) (Use inhibited area) (Use inhibited area) 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 H'0080 0128 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136 H'0080 0138 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146 H'0080 0148 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0180 H'0080 0182 18-4 18-4 | H'0080 01A0 H'0080 01A2 17-16 20-8 18-6 | H'0080 01E0 6-15 6-16 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-11 3 SFR Area Register Map (4/37) Address b0 H'0080 01E2 H'0080 01E4 Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) (Use inhibited area) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) See pages 6-17 6-18 6-19 6-22 | H'0080 0200 H'0080 0202 H'0080 0204 | H'0080 0210 H'0080 0212 H'0080 0214 H'0080 0216 H'0080 0218 H'0080 021A Common Count Clock Select Register Clock Bus & Input Event Bus Control Register (CNTCKSEL) (CKIEBCR) Prescaler Register 0 Prescaler Register 1 (PRS0) (PRS1) Prescaler Register 2 Output Event Bus Control Register (PRS2) (OEBCR) (Use inhibited area) TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 1 (TINCR1) TIN Input Processing Control Register 2 (TINCR2) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) (Use inhibited area) F/F Source Select Register 0 (FFS0) (Use inhibited area) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) (Use inhibited area) F/F Protect Register 1 (FFP1) (Use inhibited area) F/F Data Register 1 (FFD1) (Use inhibited area) TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 2 (TINIR2) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 3 (TINIR3) TIN Interrupt Control Register 5 (TINIR5) TIN Interrupt Control Register 7 (TINIR7) 10-12 10-17 10-13 10-13 10-18 10-21 10-22 10-23 10-24 10-25 10-25 | H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A 10-28 10-29 10-30 10-32 10-30 10-32 | H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E H'0080 0240 H'0080 0242 H'0080 0244 H'0080 0246 10-38 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-50 10-52 10-55 10-71 10-72 TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) (Use inhibited area) TOP0 Correction Register (TOP0CC) (Use inhibited area) 10-73 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-12 3 SFR Area Register Map (5/37) Address b0 H'0080 0250 H'0080 0252 H'0080 0254 H'0080 0256 +0 address b7 b8 TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) (Use inhibited area) TOP1 Correction Register (TOP1CC) (Use inhibited area) TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) (Use inhibited area) TOP2 Correction Register (TOP2CC) (Use inhibited area) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) (Use inhibited area) TOP3 Correction Register (TOP3CC) (Use inhibited area) TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) (Use inhibited area) TOP4 Correction Register (TOP4CC) (Use inhibited area) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) (Use inhibited area) TOP5 Correction Register (TOP5CC) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-71 10-72 10-73 | H'0080 0260 H'0080 0262 H'0080 0264 H'0080 0266 10-71 10-72 10-73 | H'0080 0270 H'0080 0272 H'0080 0274 H'0080 0276 10-71 10-72 10-73 | H'0080 0280 H'0080 0282 H'0080 0284 H'0080 0286 10-71 10-72 10-73 | H'0080 0290 H'0080 0292 H'0080 0294 H'0080 0296 H'0080 0298 H'0080 029A H'0080 029C (Use inhibited area) 10-71 10-72 10-73 | H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA TOP0–5 Control Register 0 (TOP05CR0) TOP0–5 Control Register 1 (TOP05CR1) (Use inhibited area) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) (Use inhibited area) TOP6 Correction Register (TOP6CC) (Use inhibited area) TOP6,7 Control Register (TOP67CR) 10-67 10-67 10-71 10-72 10-73 10-69 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-13 3 SFR Area Register Map (6/37) Address b0 +0 address b7 b8 (Use inhibited area) TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) (Use inhibited area) TOP7 Correction Register (TOP7CC) (Use inhibited area) TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) (Use inhibited area) TOP8 Correction Register (TOP8CC) (Use inhibited area) TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) (Use inhibited area) TOP9 Correction Register (TOP9CC) (Use inhibited area) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) (Use inhibited area) TOP10 Correction Register (TOP10CC) (Use inhibited area) TOP8–10 Control Register (TOP810CR) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages | H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6 10-71 10-72 10-73 | H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 02C6 10-71 10-72 10-73 | H'0080 02D0 H'0080 02D2 H'0080 02D4 H'0080 02D6 10-71 10-72 10-73 | H'0080 02E0 H'0080 02E2 H'0080 02E4 H'0080 02E6 H'0080 02E8 H'0080 02EA 10-71 10-72 10-73 10-70 | H'0080 02FA H'0080 02FC H'0080 02FE H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306 TOP0-10 External Enable Permit Register (TOPEEN) TOP0-10 Enable Protect Register (TOPPRO) TOP0-10 Count Enable Register (TOPCEN) TIO0 Counter (TIO0CT) (Use inhibited area) TIO0 Reload 1 Register (TIO0RL1) TIO0 Reload 0/ Measure Register (TIO0RL0) (Use inhibited area) TIO1 Counter (TIO1CT) (Use inhibited area) TIO1 Reload 1 Register (TIO1RL1) 10-74 10-74 10-75 10-105 10-107 10-106 | H'0080 0310 H'0080 0312 H'0080 0314 10-105 10-107 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-14 3 SFR Area Register Map (7/37) Address b0 H'0080 0316 H'0080 0318 H'0080 031A H'0080 031C (Use inhibited area) +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b7 b8 TIO1 Reload 0/ Measure Register (TIO1RL0) (Use inhibited area) TIO0–3 Control Register 0 (TIO03CR0) TIO0–3 Control Register 1 (TIO03CR1) (Use inhibited area) TIO2 Counter (TIO2CT) (Use inhibited area) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) (Use inhibited area) TIO3 Counter (TIO3CT) (Use inhibited area) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) (Use inhibited area) TIO4 Counter (TIO4CT) (Use inhibited area) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) (Use inhibited area) b15 See pages 10-106 10-98 10-99 | H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 10-105 10-107 10-106 | H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 10-105 10-107 10-106 | H'0080 0340 H'0080 0342 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A 10-105 10-107 10-106 TIO4 Control Register (TIO4CR) (Use inhibited area) TIO5 Counter (TIO5CT) (Use inhibited area) TIO5 Control Register (TIO5CR) 10-100 10-102 | H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356 10-105 | H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) (Use inhibited area) TIO6 Counter (TIO6CT) (Use inhibited area) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) (Use inhibited area) TIO6 Control Register (TIO6CR) (Use inhibited area) TIO7 Control Register (TIO7CR) 10-107 10-106 10-105 10-107 10-106 10-103 10-104 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-15 3 SFR Area Register Map (8/37) Address b0 H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376 +0 address b7 b8 TIO7 Counter (TIO7CT) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-105 | H'0080 0380 H'0080 0382 H'0080 0384 H'0080 0386 H'0080 0388 H'0080 038A TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) (Use inhibited area) TIO8 Counter (TIO8CT) (Use inhibited area) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/ Measure Register (TIO8RL0) (Use inhibited area) TIO8 Control Register (TIO8CR) (Use inhibited area) TIO9 Counter (TIO9CT) (Use inhibited area) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) (Use inhibited area) TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register TMS1 Control Register (TMS0CR) (TMS1CR) (Use inhibited area) TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) (Use inhibited area) TML0 Counter (TML0CT) (Upper) (TML0CTH) (Lower) (TML0CTL) TIO9 Control Register (TIO9CR) 10-107 10-106 10-105 10-107 10-106 10-104 10-105 | H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396 10-105 10-107 10-106 | H'0080 03BC H'0080 03BE H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA 10-108 10-109 10-127 10-127 10-127 10-127 10-127 10-126 | H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 10-127 10-127 10-127 10-127 10-127 | H'0080 03E0 H'0080 03E2 10-132 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-16 3 SFR Area Register Map (9/37) Address b0 +0 address b7 b8 (Use inhibited area) (Use inhibited area) (Use inhibited area) TML0 Measure 3 Register (TML0MR3) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages | H'0080 03EA TML0 Control Register (TML0CR) 10-131 | H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA H'0080 03FC H'0080 03FE H'0080 0400 TML0 Measure 2 Register (TML0MR2) TML0 Measure 1 Register (TML0MR1) TML0 Measure 0 Register (TML0MR0) | H'0080 0408 DMA0–4 Interrupt Request Status Register DMA0–4 (DM04ITST) (Use inhibited area) (Upper) (TML0MR3H) (Lower) (TML0MR3L) (Upper) (TML0MR2H) (Lower) (TML0MR2L) (Upper) (TML0MR1H) (Lower) (TML0MR1L) (Upper) (TML0MR0H) (Lower) (TML0MR0L) Interrupt Request Mask Register (DM04ITMK) 10-132 10-132 10-132 10-132 9-35 9-36 | H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) DMA1 Channel Control Register 0 DMA1 Channel Control (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) DMA6 Channel Control Register 0 DMA6 Channel Control (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) DMA2 Channel Control Register 0 DMA2 Channel Control (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) Register 1 9-35 9-36 9-6 9-7 9-30 9-31 9-32 Register 1 9-16 9-17 9-30 9-31 9-32 Register 1 9-8 9-9 9-30 9-31 9-32 Register 1 9-18 9-19 9-30 9-31 9-32 Register 1 9-10 9-11 9-30 9-31 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-17 3 SFR Area Register Map (10/37) Address b0 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA9 DMA4 DMA8 DMA3 DMA7 +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas | H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 +1 address b7 b8 DMA2 Transfer Count Register (DM2TCT) Channel Control Register 0 DMA7 Channel Control (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) Channel Control Register 0 DMA3 Channel Control (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) Channel Control Register 0 DMA8 Channel Control (DM8CNT0) (DM8CNT1) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) Channel Control Register 0 DMA4 Channel Control (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) Channel Control Register 0 DMA9 Channel Control (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) (Use inhibited area) DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) (Use inhibited area) (Use inhibited area) Register Register Register Register Register See pages b15 9-32 Register 1 9-20 9-21 9-30 9-31 9-32 Register 1 9-12 9-13 9-30 9-31 9-32 Register 1 9-22 9-23 9-30 9-31 9-32 Register 1 9-14 9-15 9-30 9-31 9-32 Register 1 9-24 9-25 9-30 9-31 9-32 9-29 9-29 9-29 9-29 9-29 9-29 9-29 9-29 9-29 9-29 | H'0080 0480 DMA0 Channel Control Register 2 (DM0CNT2) 9-26 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-18 3 SFR Area Register Map (11/37) Address b0 H'0080 0482 H'0080 0484 H'0080 0486 H'0080 0488 (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 Register 2 Register 2 Register 2 Register 2 DMA1 Channel Control (DM1CNT2) DMA2 Channel Control (DM2CNT2) DMA3 Channel Control (DM3CNT2) DMA4 Channel Control (DM4CNT2) (Use inhibited area) DMA5 Channel Control (DM5CNT2) DMA6 Channel Control (DM6CNT2) DMA7 Channel Control (DM7CNT2) DMA8 Channel Control (DM8CNT2) DMA9 Channel Control (DM9CNT2) (Use inhibited area) See pages 9-26 9-26 9-26 9-26 | H'0080 0490 H'0080 0492 H'0080 0494 H'0080 0496 H'0080 0498 (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) Register 2 Register 2 Register 2 Register 2 Register 2 9-26 9-26 9-26 9-26 9-26 | H'0080 0500 H'0080 0502 H'0080 0504 H'0080 0506 H'0080 0508 H'0080 050A H'0080 050C H'0080 050E H'0080 0510 Port Group 0,1 Input Level Setting Register Port Group 3 Input Level Setting Register (PG01LEV) (PG3LEV) Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) Port Group 0,1 Output Drive Capability Setting Register Port Group 3 Output Drive Capability Setting Register (PG01DRV) (PG3DRV) Port Group 4,5 Output Drive Capability Setting Register Port Group 6,7 Output Drive Capability Setting Register (PG45DRV) (PG67DRV) Port Group 8 Output Drive Capability Setting Register P70 Output Drive Capability Setting Register (PG8DRV) (P70DRV) (Use inhibited area) Noise Canceller Control Register (NZCNSLCR) (Use inhibited area) PWM Output 0 Disable Control Register GA PWM Output 0 Disable Level Control Register GA (PO0DISGACR) (PO0LVGACR) PWM Output 1 Disable Control Register GA PWM Output 1 Disable Level Control Register GA (PO1DISGACR) (PO1LVGACR) (Use inhibited area) PWMOFF 0 Function Enable Register PWMOFF 1 Function Enable Register (PWMOFF0EN) (PWMOFF1EN) (Use inhibited area) CAN Bus Mode Control Register DD Input Pin Select Register (CANBUSCR) (DDSEL) (Use inhibited area) RAM Write Monitor Interrupt Status Register (RAMWRIST) (Use inhibited area) RAM Write Source Status Register (RAMWRFST) (Use inhibited area) RAM Write Disable Control Register (RAMWRCNT) (Use inhibited area) 8-33 8-33 8-33 8-35 8-35 8-35 8-36 8-38 | H'0080 0520 H'0080 0522 H'0080 0524 H'0080 0526 H'0080 0528 H'0080 052A 10-168 10-171 10-168 10-171 10-173 13-23 14-6 | H'0080 0530 H'0080 0532 H'0080 0534 H'0080 0536 H'0080 0538 H'0080 053A 6-4 6-5 6-6 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-19 3 SFR Area Register Map (12/37) Address b0 H'0080 053C (Use inhibited area) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 RAM Write Disable Protect Register (RAMWRPROT) (Use inhibited area) Dummy Access area (Note1) 3-43 Dummy Access area (Note1) 3-43 (Use inhibited area) See pages 6-7 | H'0080 0600 H'0080 0602 Dummy Access area (Note1) Dummy Access area (Note1) H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) (Use inhibited area) (Use inhibited area) (Use inhibited area) P22 Data Register (P22DATA) (Use inhibited area) P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) (Use inhibited area) (Use inhibited area) (Use inhibited area) P22 Direction Register (P22DIR) (Use inhibited area) P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) (Use inhibited area) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) 8-12 8-12 8-12 8-12 6-32 8-12 8-12 8-12 8-12 8-12 | H'0080 0716 (Use inhibited area) 8-12 | H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) 8-13 8-13 8-13 8-13 8-13 8-13 8-13 8-13 8-13 | H'0080 0736 (Use inhibited area) 8-13 | H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) 8-14.17-5 8-15,17-7 8-16,17-8 8-17,17-9 8-18,17-10 8-29,20-3 8-19,17-11 20-9 8-20 8-21 8-22 8-23 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-20 3 SFR Area Register Map (13/37) Address b0 H'0080 074C H'0080 074E H'0080 0750 P12 Operation Mode Register (P12MOD) (Use inhibited area) (Use inhibited area) (Use inhibited area) P22 Operation Mode Register (P22MOD) (Use inhibited area) P0 Peripheral Function Select Register (P0SMOD) (Use inhibited area) P4 Peripheral Function Select Register (P4SMOD) (Use inhibited area) P8 Peripheral Function Select Register (P8SMOD) P10 Peripheral Function Select Register (P10SMOD) P12 Peripheral Function Select Register (P12SMOD) (Use inhibited area) (Use inhibited area) (Use +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) See pages 8-24,17-12 8-25 8-26,17-13 20-10 8-27 | H'0080 0756 (Use inhibited area) 8-28 17-14 | H'0080 0760 H'0080 0762 H'0080 0764 H'0080 0766 H'0080 0768 H'0080 076A H'0080 076C H'0080 076E H'0080 0770 P1 Peripheral Function Select Register (P1SMOD) P3 Peripheral Function Select Register (P3SMOD) (Use inhibited area) P7 Peripheral Function Select Register (P7SMOD) P9 Peripheral Function Select Register (P9SMOD) P11 Peripheral Function Select Register (P11SMOD) P13 Peripheral Function Select Register (P13SMOD) P15 Peripheral Function Select Register (P15SMOD) P17 Peripheral Function Select Register (P17SMOD) inhibited area) (Use inhibited area) 8-14,17-6 8-15,17-7 8-17 17-9 8-18 17-10 8-19,17-11 20-9 8-20 8-21 8-22 8-23 8-24,17-12 8-25 8-26,17-13 20-10 8-27 | H'0080 0776 H'0080 0778 H'0080 077A H'0080 077C H'0080 077E H'0080 0780 H'0080 0782 H'0080 0784 H'0080 0786 (Use inhibited area) PWM Output 0 Disable Control (PO0DISGBCR) PWM Output 1 Disable Control (PO1DISGBCR) P22 Peripheral Function Select Register (P22SMOD) (Use inhibited area) (Use inhibited area) 8-28 17-14 RTD Write Function Disable Control Register (WRRDIS) (Use inhibited area) 15-3 Bus Mode Control Register (BUSMODC) Register GB PWM Output 0 Disable Level Control Register GB (PO0LVGBCR) Register GB PWM Output 1 Disable Level Control Register GB (PO1LVGBCR) (Use inhibited area) (Use inhibited area) (Use inhibited area) TID0 Counter (TID0CT) TID0 Reload Register (TID0RL) TOU0_0 Counter (TOU00CTW) 17-15 10-168 10-171 10-169 10-171 Clock Control Register (CLKCR) 20-5 | H'0080 078C H'0080 078E H'0080 0790 H'0080 0792 H'0080 0794 H'0080 0796 H'0080 0798 H'0080 079A 10-140 10-140 (Upper) (TOU00CTH) (Lower) (TOU00CT) TOU0_0 Reload 1 Register (TOU00RL1) TOU0_0 Reload 0 Register (TOU00RL0) (Upper) (TOU01CTH) (Lower) (TOU01CT) 10-157 10-159 10-160 10-162 10-161 10-157 10-159 TOU0_0 Reload Register (TOU00RLW) TOU0_1 Counter (TOU01CTW) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-21 3 SFR Area Register Map (14/37) Address b0 H'0080 079C H'0080 079E H'0080 07A0 H'0080 07A2 H'0080 07A4 H'0080 07A6 H'0080 07A8 H'0080 07AA H'0080 07AC H'0080 07AE H'0080 07B0 H'0080 07B2 H'0080 07B4 H'0080 07B6 H'0080 07B8 H'0080 07BA H'0080 07BC H'0080 07BE H'0080 07C0 H'0080 07C2 H'0080 07C4 H'0080 07C6 H'0080 07C8 H'0080 07CA H'0080 07CC H'0080 07CE H'0080 07D0 H'0080 07D2 H'0080 07D4 H'0080 07D6 H'0080 07D8 H'0080 07DA H'0080 07DC H'0080 07DE +0 address b7 b8 TOU0_1 Reload Register (TOU01RLW) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-13 10-138 10-56 10-155 10-31 10-156 10-33 10-153 10-153 10-163 10-164 TOU0_1 Reload 1 Register (TOU01RL1) TOU0_1 Reload 0 Register (TOU01RL0) TOU0_2 Counter (Upper) (TOU02CTW) (TOU02CTH) (Lower) (TOU02CT) TOU0_2 Reload Register TOU0_2 Reload 1 Register (TOU02RLW) (TOU02RL1) TOU0_2 Reload 0 Register (TOU02RL0) TOU0_3 Counter (Upper) (TOU03CTW) (TOU03CTH) (Lower) (TOU03CT) TOU0_3 Reload Register TOU0_3 Reload 1 Register (TOU03RLW) (TOU03RL1) TOU0_3 Reload 0 Register (TOU03RL0) TOU0_4 Counter (Upper) (TOU04CTW) (TOU04CTH) (Lower) (TOU04CT) TOU0_4 Reload Register TOU0_4 Reload 1 Register (TOU04RLW) (TOU04RL1) TOU0_4 Reload 0 Register (TOU04RL0) TOU0_5 Counter (Upper) (TOU05CTW) (TOU05CTH) (Lower) (TOU05CT) TOU0_5 Reload Register TOU0_5 Reload 1 Register (TOU05RLW) (TOU05RL1) TOU0_5 Reload 0 Register (TOU05RL0) TOU0_6 Counter (Upper) (TOU06CTW) (TOU06CTH) (Lower) (TOU06CT) TOU0_6 Reload Register TOU0_6 Reload 1 Register (TOU06RLW) (TOU06RL1) TOU0_6 Reload 0 Register (TOU06RL0) TOU0_7 Counter (Upper) (TOU07CTW) (TOU07CTH) (Lower) (TOU07CT) TOU0_7 Reload Register TOU0_7 Reload 1 Register (TOU07RLW) (TOU07RL1) TOU0_7 Reload 0 Register (TOU07RL0) Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register (PRS3) (TID0PRS3EN) TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register (TOU0IMA) (TOU0IST) Shorting Prevention Function F/F21-26 Protect Register F/F21-28 Protect Register (SHFF2126P) (FF2128P) Shorting Prevention Function F/F21-26 Data Register F/F21-28 Data Register (SHFF2126D) (FF2128D) TOU0 Control Register 1 (TOU0CR1) TOU0 Control Register 0 (TOU0CR0) (Use inhibited area) TOU0 Enable Protect Register (TOU0PRO) (Use inhibited area) TOU0 Count Enable Register (TOU0CEN) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-22 3 SFR Area Register Map (15/37) Address b0 H'0080 07E0 H'0080 07E2 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address See pages 10-166 10-26 10-52 | H'0080 07E8 H'0080 07EA H'0080 07EC H'0080 07EE H'0080 07F0 H'0080 07F2 H'0080 07F4 H'0080 07F6 b15 PWMOFF0 Input Processing Control Register TIN24,25 Input Processing Control Register (PWMOFF0CR) (TIN2425CR) TIN24,25 Interrupt Request Mask Register TIN24,25 Interrupt Request Status Register (TIN2425IMA) (TIN2425IST) (Use inhibited area) Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash L Bank Register 1 (FELBANK1) Virtual Flash L Bank Register 2 (FELBANK2) Virtual Flash L Bank Register 3 (FELBANK3) Virtual Flash L Bank Register 4 (Note (FELBANK4) Virtual Flash L Bank Register 5 (Note (FELBANK5) Virtual Flash L Bank Register 6 (Note (FELBANK6) Virtual Flash L Bank Register 7 (Note (FELBANK7) (Use inhibited area) 6-24 6-24 6-24 6-24 2) 2) 2) 2) 6-24 6-24 6-24 6-24 | H'0080 0A00 H'0080 0A02 | H'0080 0A10 H'0080 0A12 H'0080 0A14 H'0080 0A16 H'0080 0A18 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Mask Register (SI45STAT) (SI45MASK) SIO45 Interrupt Request Source Select Register (Use inhibited area) (SI45SEL) (Use inhibited area) SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register (S4TCNT) (S4MOD) SIO4 Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register SIO4 Baud Rate Register (S4RCNT) (S4BAUR) SIO4 Special Mode Register (Use inhibited area) (S4SMOD) (Use inhibited area) SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register (S5TCNT) (S5MOD) SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) SIO5 Receive Control Register SIO5 Baud Rate Register (S5RCNT) (S5BAUR) SIO5 Special Mode Register (Use inhibited area) (S5SMOD) (Use inhibited area) TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) TOU1_0 Counter (TOU10CTW) 12-9 12-10 12-11 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0A20 H'0080 0A22 H'0080 0A24 H'0080 0A26 H'0080 0A28 12-14 12-15 12-19 12-20 12-21 12-24 12-27 | H'0080 0B8C H'0080 0B8E H'0080 0B90 H'0080 0B92 H'0080 0B94 H'0080 0B96 H'0080 0B98 H'0080 0B9A 10-140 10-140 (Upper) (TOU10CTH) (Lower) (TOU10CT) TOU1_0 Reload 1 Register (TOU10RL1) TOU1_0 Reload 0 Register (TOU10RL0) (Upper) (TOU11CTH) (Lower) (TOU11CT) 10-157 10-159 10-160 10-162 10-161 10-157 10-159 TOU1_0 Reload Register ( TOU10RLW) TOU1_1 Counter (TOU11CTW) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-23 3 SFR Area Register Map (16/37) Address b0 H'0080 0B9C H'0080 0B9E H'0080 0BA0 H'0080 0BA2 H'0080 0BA4 H'0080 0BA6 H'0080 0BA8 H'0080 0BAA H'0080 0BAC H'0080 0BAE H'0080 0BB0 H'0080 0BB2 H'0080 0BB4 H'0080 0BB6 H'0080 0BB8 H'0080 0BBA H'0080 0BBC H'0080 0BBE H'0080 0BC0 H'0080 0BC2 H'0080 0BC4 H'0080 0BC6 H'0080 0BC8 H'0080 0BCA H'0080 0BCC H'0080 0BCE H'0080 0BD0 H'0080 0BD2 H'0080 0BD4 H'0080 0BD6 H'0080 0BD8 H'0080 0BDA H'0080 0BDC H'0080 0BDE (TOU15RL0) TOU1_6 Counter (TOU16CTW) TOU1_5 Reload Register (TOU15RLW) TOU1_5 Counter (TOU15CTW) TOU1_4 Reload Register (TOU14RLW) TOU1_4 Counter (TOU14CTW) TOU1_3 Reload Register (TOU13RLW) TOU1_3 Counter (TOU13CTW) TOU1_2 Reload Register (TOU12RLW) TOU1_2 Counter (TOU12CTW) +0 address b7 b8 TOU1_1 Reload Register (TOU11RLW) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 TOU1_1 Reload 1 Register (TOU11RL1) TOU1_1 Reload 0 Register (TOU11RL0) (Upper) (TOU12CTH) (Lower) (TOU12CT) TOU1_2 Reload 1 Register (TOU12RL1) TOU1_2 Reload 0 Register (TOU12RL0) (Upper) (TOU13CTH) (Lower) (TOU13CT) TOU1_3 Reload 1 Register (TOU13RL1) TOU1_3 Reload 0 Register (TOU13RL0) (Upper) (TOU14CTH) (Lower) (TOU14CT) TOU1_4 Reload 1 Register (TOU14RL1) TOU1_4 Reload 0 Register (TOU14RL0) (Upper) (TOU15CTH) (Lower) (TOU15CT) TOU1_5 Reload 1 Register (TOU15RL1) TOU1_5 Reload 0 Register See pages 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-13 10-139 10-58 10-155 10-31 10-156 10-33 10-154 10-154 10-163 10-164 (Upper) (TOU16CTH) (Lower) (TOU16CT) TOU1_6 Reload Register TOU1_6 Reload 1 Register (TOU16RLW) (TOU16RL1) TOU1_6 Reload 0 Register (TOU16RL0) TOU1_7 Counter (Upper) (TOU17CTW) (TOU17CTH) (Lower) (TOU17CT) TOU1_7 Reload Register TOU1_7 Reload 1 Register ( TOU17RLW) (TOU17RL1) TOU1_7 Reload 0 Register (TOU17RL0) Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register (PRS4) (TID1PRS4EN) TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register (TOU1IMA) (TOU1IST) Shorting Prevention Function F/F29-34 Protect Register F/F29-36 Protect Register (SHFF2934P) (FF2936P) Shorting Prevention Function F/F29-34 Data Register F/F29-36 Data Register (SHFF2934D) (FF2936D) TOU1 Control Register 1 (TOU1CR1) TOU1 Control Register 0 (TOU1CR0) (Use inhibited area) TOU1 Enable Protect Register (TOU1PRO) (Use inhibited area) TOU1 Count Enable Register (TOU1CEN) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-24 3 SFR Area Register Map (17/37) Address b0 H'0080 0BE0 H'0080 0BE2 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-166 10-26 10-53 | H'0080 0FE0 H'0080 0FE2 PWMOFF1 Input Processing Control Register TIN26,27 Input Processing Control Register (PWMOFF1CR) (TIN2627CR) TIN26,27 Interrupt Request Mask Register TIN26,27 Interrupt Request Status Register (TIN2627IMA) (TIN2627IST) (Use inhibited area) TML1 Counter (TML1CT) (Upper) (TML1CTH) (Lower) (TML1CTL) 10-132 | H'0080 0FEA (Use inhibited area) (Use inhibited area) TML1 Control Register (TML1CR) (Use inhibited area) TML1 Measure 3 Register (TML1MR3) (Upper) (TML1MR3H) (Lower) (TML1MR3L) (Upper) (TML1MR2H) (Lower) (TML1MR2L) (Upper) (TML1MR1H) (Lower) (TML1MR1L) (Upper) (TML1MR0H) (Lower) (TML1MR0L) 10-132 10-131 | H'0080 0FF0 H'0080 0FF2 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA H'0080 0FFC H'0080 0FFE TML1 Measure 2 Register (TML1MR2) 10-132 TML1 Measure 1 Register (TML1MR1) 10-132 TML1 Measure 0 Register (TML1MR0) 10-132 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-25 3 SFR Area Register Map (18/37) Address b0 H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1006 H'0080 1008 H'0080 100A H'0080 100C H'0080 100E H'0080 1010 H'0080 1012 H'0080 1014 H'0080 1016 H'0080 1018 H'0080 101A H'0080 101C H'0080 101E H'0080 1020 H'0080 1022 H'0080 1024 H'0080 1026 H'0080 1028 H'0080 102A H'0080 102C H'0080 102E H'0080 1030 H'0080 1032 H'0080 1034 H'0080 1036 H'0080 1038 H'0080 103A H'0080 103C H'0080 103E H'0080 1040 H'0080 1042 +0 address b7 b8 CAN0 Control Register (CAN0CNT) CAN0 Status Register (CAN0STAT) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-26 13-29 CAN0 Configuration Register (CAN0CONF) CAN0 Timestamp Count Register (CAN0TSTMP) CAN0 Receive Error Count Register CAN0 Transmit Error Count Register (CAN0REC) (CAN0TEC) CAN0 Slot Interrupt Request Status Register(Upper) (CAN0SLISTW) (CAN0SLIST) (Lower) (CAN0SLISTL) CAN0 Slot Interrupt Request Mask Register(Upper) (CAN0SLIMKW) (CAN0SLIMK) (Lower) (CAN0SLIMKL) CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Mask Register (CAN0ERIST) (CAN0ERIMK) CAN0 Baud Rate Prescaler CAN0 Cause of Error Register (CAN0BRP) (CAN0EF) CAN0 Mode Register CAN0 DMA Transfer Request Select Register (CAN0MOD) (CAN0DMARQ) CAN0 Message Slot Number Register CAN0 Clock Select Register (CAN0MSN) (CAN0CKSEL) CAN0 Frame Format Select Register (Upper) (CAN0FFSW) (CAN0FFS) (Lower) (CAN0FFSL) CAN0 Global Mask Register A Standard ID0 CAN0 Global Mask Register A Standard ID1 (C0GMSKAS0) (C0GMSKAS1) CAN0 Global Mask Register A Extended ID0 CAN0 Global Mask Register A Extended ID1 (C0GMSKAE0) (C0GMSKAE1) CAN0 Global Mask Register A Extended ID2 (Use inhibited area) (C0GMSKAE2) (Use inhibited area) CAN0 Global Mask Register B Standard ID0 CAN0 Global Mask Register B Standard ID1 (C0GMSKBS0) (C0GMSKBS1) CAN0 Global Mask Register B Extended ID0 CAN0 Global Mask Register B Extended ID1 (C0GMSKBE0) (C0GMSKBE1) CAN0 Global Mask Register B Extended ID2 (Use inhibited area) (C0GMSKBE2) (Use inhibited area) CAN0 Local Mask Register A Standard ID0 CAN0 Local Mask Register A Standard ID1 (C0LMSKAS0) (C0LMSKAS1) CAN0 Local Mask Register A Extended ID0 CAN0 Local Mask Register A Extended ID1 (C0LMSKAE0) (C0LMSKAE1) CAN0 Local Mask Register A Extended ID2 (Use inhibited area) (C0LMSKAE2) (Use inhibited area) CAN0 Local Mask Register B Standard ID0 CAN0 Local Mask Register B Standard ID1 (C0LMSKBS0) (C0LMSKBS1) CAN0 Local Mask Register B Extended ID0 CAN0 Local Mask Register B Extended ID1 (C0LMSKBE0) (C0LMSKBE1) CAN0 Local Mask Register B Extended ID2 (Use inhibited area) (C0LMSKBE2) (Use inhibited area) CAN0 Single-Shot Mode Control Register (Upper) (CAN0SSMODEW) (CAN0SSMODE) (Lower) (CAN0SSMODEL) 13-32 13-34 13-35 13-39 13-41 13-42 13-43 13-36 13-66 13-68 13-69 13-70 13-71 10-73 13-75 13-76 13-77 13-75 13-76 13-77 13-75 13-76 13-77 13-75 13-76 13-77 13-79 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-26 3 SFR Area Register Map (19/37) Address b0 H'0080 1044 H'0080 1046 H'0080 1048 H'0080 104A +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas | H'0080 1050 H'0080 1052 H'0080 1054 H'0080 1056 H'0080 1058 H'0080 105A H'0080 105C H'0080 105E H'0080 1060 H'0080 1062 H'0080 1064 H'0080 1066 H'0080 1068 H'0080 106A H'0080 106C H'0080 106E +1 address b7 b8 CAN0 Single-Shot Interrupt Request Status Register (Upper) (CAN0SSISTW) (CAN0SSIST) (Lower) (CAN0SSISTL) CAN0 Single-Shot Interrupt Request Mask Register (Upper) (CAN0SSIMKW) (CAN0SSIMK) (Lower) (CAN0SSIMKL) (Use inhibited area) See pages b15 13-44 13-46 | H'0080 1100 H'0080 1102 H'0080 1104 H'0080 1106 H'0080 1108 H'0080 110A H'0080 110C H'0080 110E H'0080 1110 H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1118 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register (C0MSL0CNT) (C0MSL1CNT) CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register (C0MSL2CNT) (C0MSL3CNT) CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register (C0MSL4CNT) (C0MSL5CNT) CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register (C0MSL6CNT) (C0MSL7CNT) CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register (C0MSL8CNT) (C0MSL9CNT) CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register (C0MSL10CNT) (C0MSL11CNT) CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register (C0MSL12CNT) (C0MSL13CNT) CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register (C0MSL14CNT) (C0MSL15CNT) CAN0 Message Slot 16 Control Register CAN0 Message Slot 17 Control Register (C0MSL16CNT) (C0MSL17CNT) CAN0 Message Slot 18 Control Register CAN0 Message Slot 19 Control Register (C0MSL18CNT) (C0MSL19CNT) CAN0 Message Slot 20 Control Register CAN0 Message Slot 21 Control Register (C0MSL20CNT) (C0MSL21CNT) CAN0 Message Slot 22 Control Register CAN0 Message Slot 23 Control Register (C0MSL22CNT) (C0MSL23CNT) CAN0 Message Slot 24 Control Register CAN0 Message Slot 25 Control Register (C0MSL24CNT) (C0MSL25CNT) CAN0 Message Slot 26 Control Register CAN0 Message Slot 27 Control Register (C0MSL26CNT) (C0MSL27CNT) CAN0 Message Slot 28 Control Register CAN0 Message Slot 29 Control Register (C0MSL28CNT) (C0MSL29CNT) CAN0 Message Slot 30 Control Register CAN0 Message Slot 31 Control Register (C0MSL30CNT) (C0MSL31CNT) (Use inhibited area) CAN0 Message Slot 0 Standard ID0 CAN0 Message Slot 0 Standard ID1 (C0MSL0SID0) (C0MSL0SID1) CAN0 Message Slot 0 Extended ID0 CAN0 Message Slot 0 Extended ID1 (C0MSL0EID0) (C0MSL0EID1) CAN0 Message Slot 0 Extended ID2 CAN0 Message Slot 0 Data Length Register (C0MSL0EID2) (C0MSL0DLC) CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 (C0MSL0DT0) (C0MSL0DT1) CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 (C0MSL0DT2) (C0MSL0DT3) CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 (C0MSL0DT4) (C0MSL0DT5) CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 (C0MSL0DT6) (C0MSL0DT7) CAN0 Message Slot 0 Timestamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID0 CAN0 Message Slot 1 Standard ID1 (C0MSL1SID0) (C0MSL1SID1) CAN0 Message Slot 1 Extended ID0 CAN0 Message Slot 1 Extended ID1 (C0MSL1EID0) (C0MSL1EID1) CAN0 Message Slot 1 Extended ID2 CAN0 Message Slot 1 Data Length Register (C0MSL1EID2) (C0MSL1DLC) CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 (C0MSL1DT0) (C0MSL1DT1) CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 (C0MSL1DT2) (C0MSL1DT3) 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-27 3 SFR Area Register Map (20/37) Address b0 H'0080 111A H'0080 111C H'0080 111E H'0080 1120 H'0080 1122 H'0080 1124 H'0080 1126 H'0080 1128 H'0080 112A H'0080 112C H'0080 112E H'0080 1130 H'0080 1132 H'0080 1134 H'0080 1136 H'0080 1138 H'0080 113A H'0080 113C H'0080 113E H'0080 1140 H'0080 1142 H'0080 1144 H'0080 1146 H'0080 1148 H'0080 114A H'0080 114C H'0080 114E H'0080 1150 H'0080 1152 H'0080 1154 H'0080 1156 H'0080 1158 H'0080 115A H'0080 115C H'0080 115E +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 (C0MSL1DT4) (C0MSL1DT5) CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 (C0MSL1DT6) (C0MSL1DT7) CAN0 Message Slot 1 Timestamp (C0MSL1TSP) CAN0 Message Slot 2 Standard ID0 CAN0 Message Slot 2 Standard ID1 (C0MSL2SID0) (C0MSL2SID1) CAN0 Message Slot 2 Extended ID0 CAN0 Message Slot 2 Extended ID1 (C0MSL2EID0) (C0MSL2EID1) CAN0 Message Slot 2 Extended ID2 CAN0 Message Slot 2 Data Length Register (C0MSL2EID2) (C0MSL2DLC) CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 (C0MSL2DT0) (C0MSL2DT1) CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 (C0MSL2DT2) (C0MSL2DT3) CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 (C0MSL2DT4) (C0MSL2DT5) CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 (C0MSL2DT6) (C0MSL2DT7) CAN0 Message Slot 2 Timestamp (C0MSL2TSP) CAN0 Message Slot 3 Standard ID0 CAN0 Message Slot 3 Standard ID1 (C0MSL3SID0) (C0MSL3SID1) CAN0 Message Slot 3 Extended ID0 CAN0 Message Slot 3 Extended ID1 (C0MSL3EID0) (C0MSL3EID1) CAN0 Message Slot 3 Extended ID2 CAN0 Message Slot 3 Data Length Register (C0MSL3EID2) (C0MSL3DLC) CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 (C0MSL3DT0) (C0MSL3DT1) CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 (C0MSL3DT2) (C0MSL3DT3) CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 (C0MSL3DT4) (C0MSL3DT5) CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 (C0MSL3DT6) (C0MSL3DT7) CAN0 Message Slot 3 Timestamp (C0MSL3TSP) CAN0 Message Slot 4 Standard ID0 CAN0 Message Slot 4 Standard ID1 (C0MSL4SID0) (C0MSL4SID1) CAN0 Message Slot 4 Extended ID0 CAN0 Message Slot 4 Extended ID1 (C0MSL4EID0) (C0MSL4EID1) CAN0 Message Slot 4 Extended ID2 CAN0 Message Slot 4 Data Length Register (C0MSL4EID2) (C0MSL4DLC) CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 (C0MSL4DT0) (C0MSL4DT1) CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 (C0MSL4DT2) (C0MSL4DT3) CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 (C0MSL4DT4) (C0MSL4DT5) CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 (C0MSL4DT6) (C0MSL4DT7) CAN0 Message Slot 4 Timestamp (C0MSL4TSP) CAN0 Message Slot 5 Standard ID0 CAN0 Message Slot 5 Standard ID1 (C0MSL5SID0) (C0MSL5SID1) CAN0 Message Slot 5 Extended ID0 CAN0 Message Slot 5 Extended ID1 (C0MSL5EID0) (C0MSL5EID1) CAN0 Message Slot 5 Extended ID2 CAN0 Message Slot 5 Data Length Register (C0MSL5EID2) (C0MSL5DLC) CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 (C0MSL5DT0) (C0MSL5DT1) CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 (C0MSL5DT2) (C0MSL5DT3) CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 (C0MSL5DT4) (C0MSL5DT5) CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 (C0MSL5DT6) (C0MSL5DT7) CAN0 Message Slot 5 Timestamp (C0MSL5TSP) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-28 3 SFR Area Register Map (21/37) Address b0 H'0080 1160 H'0080 1162 H'0080 1164 H'0080 1166 H'0080 1168 H'0080 116A H'0080 116C H'0080 116E H'0080 1170 H'0080 1172 H'0080 1174 H'0080 1176 H'0080 1178 H'0080 117A H'0080 117C H'0080 117E H'0080 1180 H'0080 1182 H'0080 1184 H'0080 1186 H'0080 1188 H'0080 118A H'0080 118C H'0080 118E H'0080 1190 H'0080 1192 H'0080 1194 H'0080 1196 H'0080 1198 H'0080 119A H'0080 119C H'0080 119E H'0080 11A0 H'0080 11A2 H'0080 11A4 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 CAN0 Message Slot 6 Standard ID0 CAN0 Message Slot 6 Standard ID1 (C0MSL6SID0) (C0MSL6SID1) CAN0 Message Slot 6 Extended ID0 CAN0 Message Slot 6 Extended ID1 (C0MSL6EID0) (C0MSL6EID1) CAN0 Message Slot 6 Extended ID2 CAN0 Message Slot 6 Data Length Register (C0MSL6EID2) (C0MSL6DLC) CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 (C0MSL6DT0) (C0MSL6DT1) CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 (C0MSL6DT2) (C0MSL6DT3) CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 (C0MSL6DT4) (C0MSL6DT5) CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 (C0MSL6DT6) (C0MSL6DT7) CAN0 Message Slot 6 Timestamp (C0MSL6TSP) CAN0 Message Slot 7 Standard ID0 CAN0 Message Slot 7 Standard ID1 (C0MSL7SID0) (C0MSL7SID1) CAN0 Message Slot 7 Extended ID0 CAN0 Message Slot 7 Extended ID1 (C0MSL7EID0) (C0MSL7EID1) CAN0 Message Slot 7 Extended ID2 CAN0 Message Slot 7 Data Length Register (C0MSL7EID2) (C0MSL7DLC) CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 (C0MSL7DT0) (C0MSL7DT1) CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 (C0MSL7DT2) (C0MSL7DT3) CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 (C0MSL7DT4) (C0MSL7DT5) CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 (C0MSL7DT6) (C0MSL7DT7) CAN0 Message Slot 7 Timestamp (C0MSL7TSP) CAN0 Message Slot 8 Standard ID0 CAN0 Message Slot 8 Standard ID1 (C0MSL8SID0) (C0MSL8SID1) CAN0 Message Slot 8 Extended ID0 CAN0 Message Slot 8 Extended ID1 (C0MSL8EID0) (C0MSL8EID1) CAN0 Message Slot 8 Extended ID2 CAN0 Message Slot 8 Data Length Register (C0MSL8EID2) (C0MSL8DLC) CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 (C0MSL8DT0) (C0MSL8DT1) CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 (C0MSL8DT2) (C0MSL8DT3) CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 (C0MSL8DT4) (C0MSL8DT5) CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 (C0MSL8DT6) (C0MSL8DT7) CAN0 Message Slot 8 Timestamp (C0MSL8TSP) CAN0 Message Slot 9 Standard ID0 CAN0 Message Slot 9 Standard ID1 (C0MSL9SID0) (C0MSL9SID1) CAN0 Message Slot 9 Extended ID0 CAN0 Message Slot 9 Extended ID1 (C0MSL9EID0) (C0MSL9EID1) CAN0 Message Slot 9 Extended ID2 CAN0 Message Slot 9 Data Length Register (C0MSL9EID2) (C0MSL9DLC) CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 (C0MSL9DT0) (C0MSL9DT1) CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 (C0MSL9DT2) (C0MSL9DT3) CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 (C0MSL9DT4) (C0MSL9DT5) CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 (C0MSL9DT6) (C0MSL9DT7) CAN0 Message Slot 9 Timestamp (C0MSL9TSP) CAN0 Message Slot 10 Standard ID0 CAN0 Message Slot 10 Standard ID1 (C0MSL10SID0) (C0MSL10SID1) CAN0 Message Slot 10 Extended ID0 CAN0 Message Slot 10 Extended ID1 (C0MSL10EID0) (C0MSL10EID1) CAN0 Message Slot 10 Extended ID2 CAN0 Message Slot 10 Data Length Register (C0MSL10EID2) (C0MSL10DLC) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-29 3 SFR Area Register Map (22/37) Address b0 H'0080 11A6 H'0080 11A8 H'0080 11AA H'0080 11AC H'0080 11AE H'0080 11B0 H'0080 11B2 H'0080 11B4 H'0080 11B6 H'0080 11B8 H'0080 11BA H'0080 11BC H'0080 11BE H'0080 11C0 H'0080 11C2 H'0080 11C4 H'0080 11C6 H'0080 11C8 H'0080 11CA H'0080 11CC H'0080 11CE H'0080 11D0 H'0080 11D2 H'0080 11D4 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DC H'0080 11DE H'0080 11E0 H'0080 11E2 H'0080 11E4 H'0080 11E6 H'0080 11E8 H'0080 11EA +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 (C0MSL10DT0) (C0MSL10DT1) CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 (C0MSL10DT2) (C0MSL10DT3) CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 (C0MSL10DT4) (C0MSL10DT5) CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 (C0MSL10DT6) (C0MSL10DT7) CAN0 Message Slot 10 Timestamp (C0MSL10TSP) CAN0 Message Slot 11 Standard ID0 CAN0 Message Slot 11 Standard ID1 (C0MSL11SID0) (C0MSL11SID1) CAN0 Message Slot 11 Extended ID0 CAN0 Message Slot 11 Extended ID1 (C0MSL11EID0) (C0MSL11EID1) CAN0 Message Slot 11 Extended ID2 CAN0 Message Slot 11 Data Length Register (C0MSL11EID2) (C0MSL11DLC) CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 (C0MSL11DT0) (C0MSL11DT1) CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 (C0MSL11DT2) (C0MSL11DT3) CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 (C0MSL11DT4) (C0MSL11DT5) CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 (C0MSL11DT6) (C0MSL11DT7) CAN0 Message Slot 11 Timestamp (C0MSL11TSP) CAN0 Message Slot 12 Standard ID0 CAN0 Message Slot 12 Standard ID1 (C0MSL12SID0) (C0MSL12SID1) CAN0 Message Slot 12 Extended ID0 CAN0 Message Slot 12 Extended ID1 (C0MSL12EID0) (C0MSL12EID1) CAN0 Message Slot 12 Extended ID2 CAN0 Message Slot 12 Data Length Register (C0MSL12EID2) (C0MSL12DLC) CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 (C0MSL12DT0) (C0MSL12DT1) CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 (C0MSL12DT2) (C0MSL12DT3) CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 (C0MSL12DT4) (C0MSL12DT5) CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 (C0MSL12DT6) (C0MSL12DT7) CAN0 Message Slot 12 Timestamp (C0MSL12TSP) CAN0 Message Slot 13 Standard ID0 CAN0 Message Slot 13 Standard ID1 (C0MSL13SID0) (C0MSL13SID1) CAN0 Message Slot 13 Extended ID0 CAN0 Message Slot 13 Extended ID1 (C0MSL13EID0) (C0MSL13EID1) CAN0 Message Slot 13 Extended ID2 CAN0 Message Slot 13 Data Length Register (C0MSL13EID2) (C0MSL13DLC) CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 (C0MSL13DT0) (C0MSL13DT1) CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 (C0MSL13DT2) (C0MSL13DT3) CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 (C0MSL13DT4) (C0MSL13DT5) CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 (C0MSL13DT6) (C0MSL13DT7) CAN0 Message Slot 13 Timestamp (C0MSL13TSP) CAN0 Message Slot 14 Standard ID0 CAN0 Message Slot 14 Standard ID1 (C0MSL14SID0) (C0MSL14SID1) CAN0 Message Slot 14 Extended ID0 CAN0 Message Slot 14 Extended ID1 (C0MSL14EID0) (C0MSL14EID1) CAN0 Message Slot 14 Extended ID2 CAN0 Message Slot 14 Data Length Register (C0MSL14EID2) (C0MSL14DLC) CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 (C0MSL14DT0) (C0MSL14DT1) CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 (C0MSL14DT2) (C0MSL14DT3) CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 (C0MSL14DT4) (C0MSL14DT5) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-30 3 SFR Area Register Map (23/37) Address b0 H'0080 11EC H'0080 11EE H'0080 11F0 H'0080 11F2 H'0080 11F4 H'0080 11F6 H'0080 11F8 H'0080 11FA H'0080 11FC H'0080 11FE H'0080 1200 H'0080 1202 H'0080 1204 H'0080 1206 H'0080 1208 H'0080 120A H'0080 120C H'0080 120E H'0080 1210 H'0080 1212 H'0080 1214 H'0080 1216 H'0080 1218 H'0080 121A H'0080 121C H'0080 121E H'0080 1220 H'0080 1222 H'0080 1224 H'0080 1226 H'0080 1228 H'0080 122A H'0080 122C H'0080 122E H'0080 1230 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 (C0MSL14DT6) (C0MSL14DT7) CAN0 Message Slot 14 Timestamp (C0MSL14TSP) CAN0 Message Slot 15 Standard ID0 CAN0 Message Slot 15 Standard ID1 (C0MSL15SID0) (C0MSL15SID1) CAN0 Message Slot 15 Extended ID0 CAN0 Message Slot 15 Extended ID1 (C0MSL15EID0) (C0MSL15EID1) CAN0 Message Slot 15 Extended ID2 CAN0 Message Slot 15 Data Length Register (C0MSL15EID2) (C0MSL15DLC) CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 (C0MSL15DT0) (C0MSL15DT1) CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 (C0MSL15DT2) (C0MSL15DT3) CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 (C0MSL15DT4) (C0MSL15DT5) CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 (C0MSL15DT6) (C0MSL15DT7) CAN0 Message Slot 15 Timestamp (C0MSL15TSP) CAN0 Message Slot 16 Standard ID0 CAN0 Message Slot 16 Standard ID1 (C0MSL16SID0) (C0MSL16SID1) CAN0 Message Slot 16 Extended ID0 CAN0 Message Slot 16 Extended ID1 (C0MSL16EID0) (C0MSL16EID1) CAN0 Message Slot 16 Extended ID2 CAN0 Message Slot 16 Data Length Register (C0MSL16EID2) (C0MSL16DLC) CAN0 Message Slot 16 Data 0 CAN0 Message Slot 16 Data 1 (C0MSL16DT0) (C0MSL16DT1) CAN0 Message Slot 16 Data 2 CAN0 Message Slot 16 Data 3 (C0MSL16DT2) (C0MSL16DT3) CAN0 Message Slot 16 Data 4 CAN0 Message Slot 16 Data 5 (C0MSL16DT4) (C0MSL16DT5) CAN0 Message Slot 16 Data 6 CAN0 Message Slot 16 Data 7 (C0MSL16DT6) (C0MSL16DT7) CAN0 Message Slot 16 Timestamp (C0MSL16TSP) CAN0 Message Slot 17 Standard ID0 CAN0 Message Slot 17 Standard ID1 (C0MSL17SID0) (C0MSL17SID1) CAN0 Message Slot 17 Extended ID0 CAN0 Message Slot 17 Extended ID1 (C0MSL17EID0) (C0MSL17EID1) CAN0 Message Slot 17 Extended ID2 CAN0 Message Slot 17 Data Length Register (C0MSL17EID2) (C0MSL17DLC) CAN0 Message Slot 17 Data 0 CAN0 Message Slot 17 Data 1 (C0MSL17DT0) (C0MSL17DT1) CAN0 Message Slot 17 Data 2 CAN0 Message Slot 17 Data 3 (C0MSL17DT2) (C0MSL17DT3) CAN0 Message Slot 17 Data 4 CAN0 Message Slot 17 Data 5 (C0MSL17DT4) (C0MSL17DT5) CAN0 Message Slot 17 Data 6 CAN0 Message Slot 17 Data 7 (C0MSL17DT6) (C0MSL17DT7) CAN0 Message Slot 17 Timestamp (C0MSL17TSP) CAN0 Message Slot 18 Standard ID0 CAN0 Message Slot 18 Standard ID1 (C0MSL18SID0) (C0MSL18SID1) CAN0 Message Slot 18 Extended ID0 CAN0 Message Slot 18 Extended ID1 (C0MSL18EID0) (C0MSL18EID1) CAN0 Message Slot 18 Extended ID2 CAN0 Message Slot 18 Data Length Register (C0MSL18EID2) (C0MSL18DLC) CAN0 Message Slot 18 Data 0 CAN0 Message Slot 18 Data 1 (C0MSL18DT0) (C0MSL18DT1) CAN0 Message Slot 18 Data 2 CAN0 Message Slot 18 Data 3 (C0MSL18DT2) (C0MSL18DT3) CAN0 Message Slot 18 Data 4 CAN0 Message Slot 18 Data 5 (C0MSL18DT4) (C0MSL18DT5) CAN0 Message Slot 18 Data 6 CAN0 Message Slot 18 Data 7 (C0MSL18DT6) (C0MSL18DT7) CAN0 Message Slot 18 Timestamp (C0MSL18TSP) CAN0 Message Slot 19 Standard ID0 CAN0 Message Slot 19 Standard ID1 (C0MSL19SID0) (C0MSL19SID1) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-31 3 SFR Area Register Map (24/37) Address b0 H'0080 1232 H'0080 1234 H'0080 1236 H'0080 1238 H'0080 123A H'0080 123C H'0080 123E H'0080 1240 H'0080 1242 H'0080 1244 H'0080 1246 H'0080 1248 H'0080 124A H'0080 124C H'0080 124E H'0080 1250 H'0080 1252 H'0080 1254 H'0080 1256 H'0080 1258 H'0080 125A H'0080 125C H'0080 125E H'0080 1260 H'0080 1262 H'0080 1264 H'0080 1266 H'0080 1268 H'0080 126A H'0080 126C H'0080 126E H'0080 1270 H'0080 1272 H'0080 1274 H'0080 1276 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 CAN0 Message Slot 19 Extended ID0 CAN0 Message Slot 19 Extended ID1 (C0MSL19EID0) (C0MSL19EID1) CAN0 Message Slot 19 Extended ID2 CAN0 Message Slot 19 Data Length Register (C0MSL19EID2) (C0MSL19DLC) CAN0 Message Slot 19 Data 0 CAN0 Message Slot 19 Data 1 (C0MSL19DT0) (C0MSL19DT1) CAN0 Message Slot 19 Data 2 CAN0 Message Slot 19 Data 3 (C0MSL19DT2) (C0MSL19DT3) CAN0 Message Slot 19 Data 4 CAN0 Message Slot 19 Data 5 (C0MSL19DT4) (C0MSL19DT5) CAN0 Message Slot 19 Data 6 CAN0 Message Slot 19 Data 7 (C0MSL19DT6) (C0MSL19DT7) CAN0 Message Slot 19 Timestamp (C0MSL19TSP) CAN0 Message Slot 20 Standard ID0 CAN0 Message Slot 20 Standard ID1 (C0MSL20SID0) (C0MSL20SID1) CAN0 Message Slot 20 Extended ID0 CAN0 Message Slot 20 Extended ID1 (C0MSL20EID0) (C0MSL20EID1) CAN0 Message Slot 20 Extended ID2 CAN0 Message Slot 20 Data Length Register (C0MSL20EID2) (C0MSL20DLC) CAN0 Message Slot 20 Data 0 CAN0 Message Slot 20 Data 1 (C0MSL20DT0) (C0MSL20DT1) CAN0 Message Slot 20 Data 2 CAN0 Message Slot 20 Data 3 (C0MSL20DT2) (C0MSL20DT3) CAN0 Message Slot 20 Data 4 CAN0 Message Slot 20 Data 5 (C0MSL20DT4) (C0MSL20DT5) CAN0 Message Slot 20 Data 6 CAN0 Message Slot 20 Data 7 (C0MSL20DT6) (C0MSL20DT7) CAN0 Message Slot 20 Timestamp (C0MSL20TSP) CAN0 Message Slot 21 Standard ID0 CAN0 Message Slot 21 Standard ID1 (C0MSL21SID0) (C0MSL21SID1) CAN0 Message Slot 21 Extended ID0 CAN0 Message Slot 21 Extended ID1 (C0MSL21EID0) (C0MSL21EID1) CAN0 Message Slot 21 Extended ID2 CAN0 Message Slot 21 Data Length Register (C0MSL21EID2) (C0MSL21DLC) CAN0 Message Slot 21 Data 0 CAN0 Message Slot 21 Data 1 (C0MSL21DT0) (C0MSL21DT1) CAN0 Message Slot 21 Data 2 CAN0 Message Slot 21 Data 3 (C0MSL21DT2) (C0MSL21DT3) CAN0 Message Slot 21 Data 4 CAN0 Message Slot 21 Data 5 (C0MSL21DT4) (C0MSL21DT5) CAN0 Message Slot 21 Data 6 CAN0 Message Slot 21 Data 7 (C0MSL21DT6) (C0MSL21DT7) CAN0 Message Slot 21 Timestamp (C0MSL21TSP) CAN0 Message Slot 22 Standard ID0 CAN0 Message Slot 22 Standard ID1 (C0MSL22SID0) (C0MSL22SID1) CAN0 Message Slot 22 Extended ID0 CAN0 Message Slot 22 Extended ID1 (C0MSL22EID0) (C0MSL22EID1) CAN0 Message Slot 22 Extended ID2 CAN0 Message Slot 22 Data Length Register (C0MSL22EID2) (C0MSL22DLC) CAN0 Message Slot 22 Data 0 CAN0 Message Slot 22 Data 1 (C0MSL22DT0) (C0MSL22DT1) CAN0 Message Slot 22 Data 2 CAN0 Message Slot 22 Data 3 (C0MSL22DT2) (C0MSL22DT3) CAN0 Message Slot 22 Data 4 CAN0 Message Slot 22 Data 5 (C0MSL22DT4) (C0MSL22DT5) CAN0 Message Slot 22 Data 6 CAN0 Message Slot 22 Data 7 (C0MSL22DT6) (C0MSL22DT7) CAN0 Message Slot 22 Timestamp (C0MSL22TSP) CAN0 Message Slot 23 Standard ID0 CAN0 Message Slot 23 Standard ID1 (C0MSL23SID0) (C0MSL23SID1) CAN0 Message Slot 23 Extended ID0 CAN0 Message Slot 23 Extended ID1 (C0MSL23EID0) (C0MSL23EID1) CAN0 Message Slot 23 Extended ID2 CAN0 Message Slot 23 Data Length Register (C0MSL23EID2) (C0MSL23DLC) CAN0 Message Slot 23 Data 0 CAN0 Message Slot 23 Data 1 (C0MSL23DT0) (C0MSL23DT1) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-32 3 SFR Area Register Map (25/37) Address b0 H'0080 1278 H'0080 127A H'0080 127C H'0080 127E H'0080 1280 H'0080 1282 H'0080 1284 H'0080 1286 H'0080 1288 H'0080 128A H'0080 128C H'0080 128E H'0080 1290 H'0080 1292 H'0080 1294 H'0080 1296 H'0080 1298 H'0080 129A H'0080 129C H'0080 129E H'0080 12A0 H'0080 12A2 H'0080 12A4 H'0080 12A6 H'0080 12A8 H'0080 12AA H'0080 12AC H'0080 12AE H'0080 12B0 H'0080 12B2 H'0080 12B4 H'0080 12B6 H'0080 12B8 H'0080 12BA H'0080 12BC +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 CAN0 Message Slot 23 Data 2 CAN0 Message Slot 23 Data 3 (C0MSL23DT2) (C0MSL23DT3) CAN0 Message Slot 23 Data 4 CAN0 Message Slot 23 Data 5 (C0MSL23DT4) (C0MSL23DT5) CAN0 Message Slot 23 Data 6 CAN0 Message Slot 23 Data 7 (C0MSL23DT6) (C0MSL23DT7) CAN0 Message Slot 23 Timestamp (C0MSL23TSP) CAN0 Message Slot 24 Standard ID0 CAN0 Message Slot 24 Standard ID1 (C0MSL24SID0) (C0MSL24SID1) CAN0 Message Slot 24 Extended ID0 CAN0 Message Slot 24 Extended ID1 (C0MSL24EID0) (C0MSL24EID1) CAN0 Message Slot 24 Extended ID2 CAN0 Message Slot 24 Data Length Register (C0MSL24EID2) (C0MSL24DLC) CAN0 Message Slot 24 Data 0 CAN0 Message Slot 24 Data 1 (C0MSL24DT0) (C0MSL24DT1) CAN0 Message Slot 24 Data 2 CAN0 Message Slot 24 Data 3 (C0MSL24DT2) (C0MSL24DT3) CAN0 Message Slot 24 Data 4 CAN0 Message Slot 24 Data 5 (C0MSL24DT4) (C0MSL24DT5) CAN0 Message Slot 24 Data 6 CAN0 Message Slot 24 Data 7 (C0MSL24DT6) (C0MSL24DT7) CAN0 Message Slot 24 Timestamp (C0MSL24TSP) CAN0 Message Slot 25 Standard ID0 CAN0 Message Slot 25 Standard ID1 (C0MSL25SID0) (C0MSL25SID1) CAN0 Message Slot 25 Extended ID0 CAN0 Message Slot 25 Extended ID1 (C0MSL25EID0) (C0MSL25EID1) CAN0 Message Slot 25 Extended ID2 CAN0 Message Slot 25 Data Length Register (C0MSL25EID2) (C0MSL25DLC) CAN0 Message Slot 25 Data 0 CAN0 Message Slot 25 Data 1 (C0MSL25DT0) (C0MSL25DT1) CAN0 Message Slot 25 Data 2 CAN0 Message Slot 25 Data 3 (C0MSL25DT2) (C0MSL25DT3) CAN0 Message Slot 25 Data 4 CAN0 Message Slot 25 Data 5 (C0MSL25DT4) (C0MSL25DT5) CAN0 Message Slot 25 Data 6 CAN0 Message Slot 25 Data 7 (C0MSL25DT6) (C0MSL25DT7) CAN0 Message Slot 25 Timestamp (C0MSL25TSP) CAN0 Message Slot 26 Standard ID0 CAN0 Message Slot 26 Standard ID1 (C0MSL26SID0) (C0MSL26SID1) CAN0 Message Slot 26 Extended ID0 CAN0 Message Slot 26 Extended ID1 (C0MSL26EID0) (C0MSL26EID1) CAN0 Message Slot 26 Extended ID2 CAN0 Message Slot 26 Data Length Register (C0MSL26EID2) (C0MSL26DLC) CAN0 Message Slot 26 Data 0 CAN0 Message Slot 26 Data 1 (C0MSL26DT0) (C0MSL26DT1) CAN0 Message Slot 26 Data 2 CAN0 Message Slot 26 Data 3 (C0MSL26DT2) (C0MSL26DT3) CAN0 Message Slot 26 Data 4 CAN0 Message Slot 26 Data 5 (C0MSL26DT4) (C0MSL26DT5) CAN0 Message Slot 26 Data 6 CAN0 Message Slot 26 Data 7 (C0MSL26DT6) (C0MSL26DT7) CAN0 Message Slot 26 Timestamp (C0MSL26TSP) CAN0 Message Slot 27 Standard ID0 CAN0 Message Slot 27 Standard ID1 (C0MSL27SID0) (C0MSL27SID1) CAN0 Message Slot 27 Extended ID0 CAN0 Message Slot 27 Extended ID1 (C0MSL27EID0) (C0MSL27EID1) CAN0 Message Slot 27 Extended ID2 CAN0 Message Slot 27 Data Length Register (C0MSL27EID2) (C0MSL27DLC) CAN0 Message Slot 27 Data 0 CAN0 Message Slot 27 Data 1 (C0MSL27DT0) (C0MSL27DT1) CAN0 Message Slot 27 Data 2 CAN0 Message Slot 27 Data 3 (C0MSL27DT2) (C0MSL27DT3) CAN0 Message Slot 27 Data 4 CAN0 Message Slot 27 Data 5 (C0MSL27DT4) (C0MSL27DT5) CAN0 Message Slot 27 Data 6 CAN0 Message Slot 27 Data 7 (C0MSL27DT6) (C0MSL27DT7) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-33 3 SFR Area Register Map (26/37) Address b0 H'0080 12BE H'0080 12C0 H'0080 12C2 H'0080 12C4 H'0080 12C6 H'0080 12C8 H'0080 12CA H'0080 12CC H'0080 12CE H'0080 12D0 H'0080 12D2 H'0080 12D4 H'0080 12D6 H'0080 12D8 H'0080 12DA H'0080 12DC H'0080 12DE H'0080 12E0 H'0080 12E2 H'0080 12E4 H'0080 12E6 H'0080 12E8 H'0080 12EA H'0080 12EC H'0080 12EE H'0080 12F0 H'0080 12F2 H'0080 12F4 H'0080 12F6 H'0080 12F8 H'0080 12FA H'0080 12FC H'0080 12FE +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas | +1 address See pages b7 b8 b15 CAN0 Message Slot 27 Timestamp 13-113 (C0MSL27TSP) CAN0 Message Slot 28 Standard ID0 CAN0 Message Slot 28 Standard ID1 13-85 (C0MSL28SID0) (C0MSL28SID1) 13-87 CAN0 Message Slot 28 Extended ID0 CAN0 Message Slot 28 Extended ID1 13-89 (C0MSL28EID0) (C0MSL28EID1) 13-91 CAN0 Message Slot 28 Extended ID2 CAN0 Message Slot 28 Data Length Register 13-93 (C0MSL28EID2) (C0MSL28DLC) 13-95 CAN0 Message Slot 28 Data 0 CAN0 Message Slot 28 Data 1 13-97 (C0MSL28DT0) (C0MSL28DT1) 13-99 CAN0 Message Slot 28 Data 2 CAN0 Message Slot 28 Data 3 13-101 (C0MSL28DT2) (C0MSL28DT3) 13-103 CAN0 Message Slot 28 Data 4 CAN0 Message Slot 28 Data 5 13-105 (C0MSL28DT4) (C0MSL28DT5) 13-107 CAN0 Message Slot 28 Data 6 CAN0 Message Slot 28 Data 7 13-109 (C0MSL28DT6) (C0MSL28DT7) 13-111 CAN0 Message Slot 28 Timestamp 13-113 (C0MSL28TSP) CAN0 Message Slot 29 Standard ID0 CAN0 Message Slot 29 Standard ID1 13-85 (C0MSL29SID0) (C0MSL29SID1) 13-87 CAN0 Message Slot 29 Extended ID0 CAN0 Message Slot 29 Extended ID1 13-89 (C0MSL29EID0) (C0MSL29EID1) 13-91 CAN0 Message Slot 29 Extended ID2 CAN0 Message Slot 29 Data Length Register 13-93 (C0MSL29EID2) (C0MSL29DLC) 13-95 CAN0 Message Slot 29 Data 0 CAN0 Message Slot 29 Data 1 13-97 (C0MSL29DT0) (C0MSL29DT1) 13-99 CAN0 Message Slot 29 Data 2 CAN0 Message Slot 29 Data 3 13-101 (C0MSL29DT2) (C0MSL29DT3) 13-103 CAN0 Message Slot 29 Data 4 CAN0 Message Slot 29 Data 5 13-105 (C0MSL29DT4) (C0MSL29DT5) 13-107 CAN0 Message Slot 29 Data 6 CAN0 Message Slot 29 Data 7 13-109 (C0MSL29DT6) (C0MSL29DT7) 13-111 CAN0 Message Slot 29 Timestamp 13-113 (C0MSL29TSP) CAN0 Message Slot 30 Standard ID0 CAN0 Message Slot 30 Standard ID1 13-85 (C0MSL30SID0) (C0MSL30SID1) 13-87 CAN0 Message Slot 30 Extended ID0 CAN0 Message Slot 30 Extended ID1 13-89 (C0MSL30EID0) (C0MSL30EID1) 13-91 CAN0 Message Slot 30 Extended ID2 CAN0 Message Slot 30 Data Length Register 13-93 (C0MSL30EID2) (C0MSL30DLC) 13-95 CAN0 Message Slot 30 Data 0 CAN0 Message Slot 30 Data 1 13-97 (C0MSL30DT0) (C0MSL30DT1) 13-99 CAN0 Message Slot 30 Data 2 CAN0 Message Slot 30 Data 3 13-101 (C0MSL30DT2) (C0MSL30DT3) 13-103 CAN0 Message Slot 30 Data 4 CAN0 Message Slot 30 Data 5 13-105 (C0MSL30DT4) (C0MSL30DT5) 13-107 CAN0 Message Slot 30 Data 6 CAN0 Message Slot 30 Data 7 13-109 (C0MSL30DT6) (C0MSL30DT7) 13-111 CAN0 Message Slot 30 Timestamp 13-113 (C0MSL30TSP) CAN0 Message Slot 31 Standard ID0 CAN0 Message Slot 31 Standard ID1 13-85 (C0MSL31SID0) (C0MSL31SID1) 13-87 CAN0 Message Slot 31 Extended ID0 CAN0 Message Slot 31 Extended ID1 13-89 (C0MSL31EID0) (C0MSL31EID1) 13-91 CAN0 Message Slot 31 Extended ID2 CAN0 Message Slot 31 Data Length Register 13-93 (C0MSL31EID2) (C0MSL31DLC) 13-95 CAN0 Message Slot 31 Data 0 CAN0 Message Slot 31 Data 1 13-97 (C0MSL31DT0) (C0MSL31DT1) 13-99 CAN0 Message Slot 31 Data 2 CAN0 Message Slot 31 Data 3 13-101 (C0MSL31DT2) (C0MSL31DT3) 13-103 CAN0 Message Slot 31 Data 4 CAN0 Message Slot 31 Data 5 13-105 (C0MSL31DT4) (C0MSL31DT5) 13-107 CAN0 Message Slot 31 Data 6 CAN0 Message Slot 31 Data 7 13-109 (C0MSL31DT6) (C0MSL31DT7) 13-111 CAN0 Message Slot 31 Timestamp 13-113 (C0MSL31TSP) (Use inhibited area) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-34 3 SFR Area Register Map (27/37) Address b0 H'0080 1400 H'0080 1402 H'0080 1404 H'0080 1406 H'0080 1408 H'0080 140A H'0080 140C H'0080 140E H'0080 1410 H'0080 1412 H'0080 1414 H'0080 1416 H'0080 1418 H'0080 141A H'0080 141C H'0080 141E H'0080 1420 H'0080 1422 H'0080 1424 H'0080 1426 H'0080 1428 H'0080 142A H'0080 142C H'0080 142E H'0080 1430 H'0080 1432 H'0080 1434 H'0080 1436 H'0080 1438 H'0080 143A H'0080 143C H'0080 143E H'0080 1440 H'0080 1442 +0 address b7 b8 CAN1 Control Register (CAN1CNT) CAN1 Status Register (CAN1STAT) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-26 13-29 CAN1 Configuration Register (CAN1CONF) CAN1 Timestamp Count Register (CAN1TSTMP) CAN1 Receive Error Count Register CAN1 Transmit Error Count Register (CAN1REC) (CAN1TEC) CAN1 Slot Interrupt Request Status Register (Upper) (CAN1SLISTW) (CAN1SLIST) (Lower) (CAN1SLISTL) CAN1 Slot Interrupt Request Mask Register (Upper) (CAN1SLIMKW) (CAN1SLIMK) (Lower) (CAN1SLIMKL) CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Mask Register (CAN1ERIST) (CAN1ERIMK) CAN1 Baud Rate Prescaler CAN1 Cause of Error Register (CAN1BRP) (CAN1EF) CAN1 Mode Register CAN1 DMA Transfer Request Select Register (CAN1MOD) (CAN1DMARQ) CAN1 Message Slot Number Register CAN1 Clock Select Register (CAN1MSN) (CAN1CKSEL) CAN1 Frame Format Select Register (Upper) (CAN1FFSW) (CAN1FFS) (Lower) (CAN1FFSL) CAN1 Global Mask Register A Standard ID0 CAN1 Global Mask Register A Standard ID1 (C1GMSKAS0) (C1GMSKAS1) CAN1 Global Mask Register A Extended ID0 CAN1 Global Mask Register A Extended ID1 (C1GMSKAE0) (C1GMSKAE1) CAN1 Global Mask Register A Extended ID2 (Use inhibited area) (C1GMSKAE2) (Use inhibited area) CAN1 Global Mask Register B Standard ID0 CAN1 Global Mask Register B Standard ID1 (C1GMSKBS0) (C1GMSKBS1) CAN1 Global Mask Register B Extended ID0 CAN1 Global Mask Register B Extended ID1 (C1GMSKBE0) (C1GMSKBE1) CAN1 Global Mask Register B Extended ID2 (Use inhibited area) (C1GMSKBE2) (Use inhibited area) CAN1 Local Mask Register A Standard ID0 CAN1 Local Mask Register A Standard ID1 (C1LMSKAS0) (C1LMSKAS1) CAN1 Local Mask Register A Extended ID0 CAN1 Local Mask Register A Extended ID1 (C1LMSKAE0) (C1LMSKAE1) CAN1 Local Mask Register A Extended ID2 (Use inhibited area) (C1LMSKAE2) (Use inhibited area) CAN1 Local Mask Register B Standard ID0 CAN1 Local Mask Register B Standard ID1 (C1LMSKBS0) (C1LMSKBS1) CAN1 Local Mask Register B Extended ID0 CAN1 Local Mask Register B Extended ID1 (C1LMSKBE0) (C1LMSKBE1) CAN1 Local Mask Register B Extended ID2 (Use inhibited area) (C1LMSKBE2) (Use inhibited area) CAN1 Single-Shot Mode Control Register (CAN1SSMODEW) (Upper) (CAN1SSMODE) (Lower) (CAN1SSMODEL) 13-32 13-34 13-35 13-39 13-41 13-42 13-43 13-36 13-66 13-68 13-69 13-70 13-71 13-73 13-75 13-76 13-77 13-75 13-76 13-77 13-75 13-76 13-77 13-75 13-76 13-77 13-79 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-35 3 SFR Area Register Map (28/37) Address b0 H'0080 1444 H'0080 1446 H'0080 1448 H'0080 144A +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas | H'0080 1450 H'0080 1452 H'0080 1454 H'0080 1456 H'0080 1458 H'0080 145A H'0080 145C H'0080 145E H'0080 1460 H'0080 1462 H'0080 1464 H'0080 1466 H'0080 1468 H'0080 146A H'0080 146C H'0080 146E +1 address b7 b8 CAN1 Single-Shot Interrupt Request Status Register (Upper) (CAN1SSISTW) (CAN1SSIST) (Lower) (CAN1SSISTL) CAN1 Single-Shot Interrupt Request Mask Register (Upper) (CAN1SSIMKW) (CAN1SSIMK) (Lower) (CAN1SSIMKL) (Use inhibited area) See pages b15 13-44 13-46 | H'0080 1500 H'0080 1502 H'0080 1504 H'0080 1506 H'0080 1508 H'0080 150A H'0080 150C H'0080 150E H'0080 1510 H'0080 1512 H'0080 1514 H'0080 1516 H'0080 1518 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register (C1MSL0CNT) (C1MSL1CNT) CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register (C1MSL2CNT) (C1MSL3CNT) CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register (C1MSL4CNT) (C1MSL5CNT) CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register (C1MSL6CNT) (C1MSL7CNT) CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register (C1MSL8CNT) (C1MSL9CNT) CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register (C1MSL10CNT) (C1MSL11CNT) CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register (C1MSL12CNT) (C1MSL13CNT) CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register (C1MSL14CNT) (C1MSL15CNT) CAN1 Message Slot 16 Control Register CAN1 Message Slot 17 Control Register (C1MSL16CNT) (C1MSL17CNT) CAN1 Message Slot 18 Control Register CAN1 Message Slot 19 Control Register (C1MSL18CNT) (C1MSL19CNT) CAN1 Message Slot 20 Control Register CAN1 Message Slot 21 Control Register (C1MSL20CNT) (C1MSL21CNT) CAN1 Message Slot 22 Control Register CAN1 Message Slot 23 Control Register (C1MSL22CNT) (C1MSL23CNT) CAN1 Message Slot 24 Control Register CAN1 Message Slot 25 Control Register (C1MSL24CNT) (C1MSL25CNT) CAN1 Message Slot 26 Control Register CAN1 Message Slot 27 Control Register (C1MSL26CNT) (C1MSL27CNT) CAN1 Message Slot 28 Control Register CAN1 Message Slot 29 Control Register (C1MSL28CNT) (C1MSL29CNT) CAN1 Message Slot 30 Control Register CAN1 Message Slot 31 Control Register (C1MSL30CNT) (C1MSL31CNT) (Use inhibited area) CAN1 Message Slot 0 Standard ID0 CAN1 Message Slot 0 Standard ID1 (C1MSL0SID0) (C1MSL0SID1) CAN1 Message Slot 0 Extended ID0 CAN1 Message Slot 0 Extended ID1 (C1MSL0EID0) (C1MSL0EID1) CAN1 Message Slot 0 Extended ID2 CAN1 Message Slot 0 Data Length Register (C1MSL0EID2) (C1MSL0DLC) CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 (C1MSL0DT0) (C1MSL0DT1) CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 (C1MSL0DT2) (C1MSL0DT3) CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 (C1MSL0DT4) (C1MSL0DT5) CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 (C1MSL0DT6) (C1MSL0DT7) CAN1 Message Slot 0 Timestamp (C1MSL0TSP) CAN1 Message Slot 1 Standard ID0 CAN1 Message Slot 1 Standard ID1 (C1MSL1SID0) (C1MSL1SID1) CAN1 Message Slot 1 Extended ID0 CAN1 Message Slot 1 Extended ID1 (C1MSL1EID0) (C1MSL1EID1) CAN1 Message Slot 1 Extended ID2 CAN1 Message Slot 1 Data Length Register (C1MSL1EID2) (C1MSL1DLC) CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 (C1MSL1DT0) (C1MSL1DT1) CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 (C1MSL1DT2) (C1MSL1DT3) 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-81 13-82 13-82 13-82 13-82 13-82 13-82 13-82 13-82 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-36 3 SFR Area Register Map (29/37) Address b0 H'0080 151A H'0080 151C H'0080 151E H'0080 1520 H'0080 1522 H'0080 1524 H'0080 1526 H'0080 1528 H'0080 152A H'0080 152C H'0080 152E H'0080 1530 H'0080 1532 H'0080 1534 H'0080 1536 H'0080 1538 H'0080 153A H'0080 153C H'0080 153E H'0080 1540 H'0080 1542 H'0080 1544 H'0080 1546 H'0080 1548 H'0080 154A H'0080 154C H'0080 154E H'0080 1550 H'0080 1552 H'0080 1554 H'0080 1556 H'0080 1558 H'0080 155A H'0080 155C H'0080 155E +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 (C1MSL1DT4) (C1MSL1DT5) CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 (C1MSL1DT6) (C1MSL1DT7) CAN1 Message Slot 1 Timestamp (C1MSL1TSP) CAN1 Message Slot 2 Standard ID0 CAN1 Message Slot 2 Standard ID1 (C1MSL2SID0) (C1MSL2SID1) CAN1 Message Slot 2 Extended ID0 CAN1 Message Slot 2 Extended ID1 (C1MSL2EID0) (C1MSL2EID1) CAN1 Message Slot 2 Extended ID2 CAN1 Message Slot 2 Data Length Register (C1MSL2EID2) (C1MSL2DLC) CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 (C1MSL2DT0) (C1MSL2DT1) CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 (C1MSL2DT2) (C1MSL2DT3) CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 (C1MSL2DT4) (C1MSL2DT5) CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 (C1MSL2DT6) (C1MSL2DT7) CAN1 Message Slot 2 Timestamp (C1MSL2TSP) CAN1 Message Slot 3 Standard ID0 CAN1 Message Slot 3 Standard ID1 (C1MSL3SID0) (C1MSL3SID1) CAN1 Message Slot 3 Extended ID0 CAN1 Message Slot 3 Extended ID1 (C1MSL3EID0) (C1MSL3EID1) CAN1 Message Slot 3 Extended ID2 CAN1 Message Slot 3 Data Length Register (C1MSL3EID2) (C1MSL3DLC) CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 (C1MSL3DT0) (C1MSL3DT1) CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 (C1MSL3DT2) (C1MSL3DT3) CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 (C1MSL3DT4) (C1MSL3DT5) CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 (C1MSL3DT6) (C1MSL3DT7) CAN1 Message Slot 3 Timestamp (C1MSL3TSP) CAN1 Message Slot 4 Standard ID0 CAN1 Message Slot 4 Standard ID1 (C1MSL4SID0) (C1MSL4SID1) CAN1 Message Slot 4 Extended ID0 CAN1 Message Slot 4 Extended ID1 (C1MSL4EID0) (C1MSL4EID1) CAN1 Message Slot 4 Extended ID2 CAN1 Message Slot 4 Data Length Register (C1MSL4EID2) (C1MSL4DLC) CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 (C1MSL4DT0) (C1MSL4DT1) CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 (C1MSL4DT2) (C1MSL4DT3) CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 (C1MSL4DT4) (C1MSL4DT5) CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 (C1MSL4DT6) (C1MSL4DT7) CAN1 Message Slot 4 Timestamp (C1MSL4TSP) CAN1 Message Slot 5 Standard ID0 CAN1 Message Slot 5 Standard ID1 (C1MSL5SID0) (C1MSL5SID1) CAN1 Message Slot 5 Extended ID0 CAN1 Message Slot 5 Extended ID1 (C1MSL5EID0) (C1MSL5EID1) CAN1 Message Slot 5 Extended ID2 CAN1 Message Slot 5 Data Length Register (C1MSL5EID2) (C1MSL5DLC) CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 (C1MSL5DT0) (C1MSL5DT1) CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 (C1MSL5DT2) (C1MSL5DT3) CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 (C1MSL5DT4) (C1MSL5DT5) CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 (C1MSL5DT6) (C1MSL5DT7) CAN1 Message Slot 5 Timestamp (C1MSL5TSP) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-37 3 SFR Area Register Map (30/37) Address b0 H'0080 1560 H'0080 1562 H'0080 1564 H'0080 1566 H'0080 1568 H'0080 156A H'0080 156C H'0080 156E H'0080 1570 H'0080 1572 H'0080 1574 H'0080 1576 H'0080 1578 H'0080 157A H'0080 157C H'0080 157E H'0080 1580 H'0080 1582 H'0080 1584 H'0080 1586 H'0080 1588 H'0080 158A H'0080 158C H'0080 158E H'0080 1590 H'0080 1592 H'0080 1594 H'0080 1596 H'0080 1598 H'0080 159A H'0080 159C H'0080 159E H'0080 15A0 H'0080 15A2 H'0080 15A4 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 CAN1 Message Slot 6 Standard ID0 CAN1 Message Slot 6 Standard ID1 (C1MSL6SID0) (C1MSL6SID1) CAN1 Message Slot 6 Extended ID0 CAN1 Message Slot 6 Extended ID1 (C1MSL6EID0) (C1MSL6EID1) CAN1 Message Slot 6 Extended ID2 CAN1 Message Slot 6 Data Length Register (C1MSL6EID2) (C1MSL6DLC) CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 (C1MSL6DT0) (C1MSL6DT1) CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 (C1MSL6DT2) (C1MSL6DT3) CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 (C1MSL6DT4) (C1MSL6DT5) CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 (C1MSL6DT6) (C1MSL6DT7) CAN1 Message Slot 6 Timestamp (C1MSL6TSP) CAN1 Message Slot 7 Standard ID0 CAN1 Message Slot 7 Standard ID1 (C1MSL7SID0) (C1MSL7SID1) CAN1 Message Slot 7 Extended ID0 CAN1 Message Slot 7 Extended ID1 (C1MSL7EID0) (C1MSL7EID1) CAN1 Message Slot 7 Extended ID2 CAN1 Message Slot 7 Data Length Register (C1MSL7EID2) (C1MSL7DLC) CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 (C1MSL7DT0) (C1MSL7DT1) CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 (C1MSL7DT2) (C1MSL7DT3) CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 (C1MSL7DT4) (C1MSL7DT5) CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 (C1MSL7DT6) (C1MSL7DT7) CAN1 Message Slot 7 Timestamp (C1MSL7TSP) CAN1 Message Slot 8 Standard ID0 CAN1 Message Slot 8 Standard ID1 (C1MSL8SID0) (C1MSL8SID1) CAN1 Message Slot 8 Extended ID0 CAN1 Message Slot 8 Extended ID1 (C1MSL8EID0) (C1MSL8EID1) CAN1 Message Slot 8 Extended ID2 CAN1 Message Slot 8 Data Length Register (C1MSL8EID2) (C1MSL8DLC) CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 (C1MSL8DT0) (C1MSL8DT1) CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 (C1MSL8DT2) (C1MSL8DT3) CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 (C1MSL8DT4) (C1MSL8DT5) CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 (C1MSL8DT6) (C1MSL8DT7) CAN1 Message Slot 8 Timestamp (C1MSL8TSP) CAN1 Message Slot 9 Standard ID0 CAN1 Message Slot 9 Standard ID1 (C1MSL9SID0) (C1MSL9SID1) CAN1 Message Slot 9 Extended ID0 CAN1 Message Slot 9 Extended ID1 (C1MSL9EID0) (C1MSL9EID1) CAN1 Message Slot 9 Extended ID2 CAN1 Message Slot 9 Data Length Register (C1MSL9EID2) (C1MSL9DLC) CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 (C1MSL9DT0) (C1MSL9DT1) CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 (C1MSL9DT2) (C1MSL9DT3) CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 (C1MSL9DT4) (C1MSL9DT5) CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 (C1MSL9DT6) (C1MSL9DT7) CAN1 Message Slot 9 Timestamp (C1MSL9TSP) CAN1 Message Slot 10 Standard ID0 CAN1 Message Slot 10 Standard ID1 (C1MSL10SID0) (C1MSL10SID1) CAN1 Message Slot 10 Extended ID0 CAN1 Message Slot 10 Extended ID1 (C1MSL10EID0) (C1MSL10EID1) CAN1 Message Slot 10 Extended ID2 CAN1 Message Slot 10 Data Length Register (C1MSL10EID2) (C1MSL10DLC) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-38 3 SFR Area Register Map (31/37) Address b0 H'0080 15A6 H'0080 15A8 H'0080 15AA H'0080 15AC H'0080 15AE H'0080 15B0 H'0080 15B2 H'0080 15B4 H'0080 15B6 H'0080 15B8 H'0080 15BA H'0080 15BC H'0080 15BE H'0080 15C0 H'0080 15C2 H'0080 15C4 H'0080 15C6 H'0080 15C8 H'0080 15CA H'0080 15CC H'0080 15CE H'0080 15D0 H'0080 15D2 H'0080 15D4 H'0080 15D6 H'0080 15D8 H'0080 15DA H'0080 15DC H'0080 15DE H'0080 15E0 H'0080 15E2 H'0080 15E4 H'0080 15E6 H'0080 15E8 H'0080 15EA +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 (C1MSL10DT0) (C1MSL10DT1) CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 (C1MSL10DT2) (C1MSL10DT3) CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 (C1MSL10DT4) (C1MSL10DT5) CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 (C1MSL10DT6) (C1MSL10DT7) CAN1 Message Slot 10 Timestamp (C1MSL10TSP) CAN1 Message Slot 11 Standard ID0 CAN1 Message Slot 11 Standard ID1 (C1MSL11SID0) (C1MSL11SID1) CAN1 Message Slot 11 Extended ID0 CAN1 Message Slot 11 Extended ID1 (C1MSL11EID0) (C1MSL11EID1) CAN1 Message Slot 11 Extended ID2 CAN1 Message Slot 11 Data Length Register (C1MSL11EID2) (C1MSL11DLC) CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 (C1MSL11DT0) (C1MSL11DT1) CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 (C1MSL11DT2) (C1MSL11DT3) CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 (C1MSL11DT4) (C1MSL11DT5) CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 (C1MSL11DT6) (C1MSL11DT7) CAN1 Message Slot 11 Timestamp (C1MSL11TSP) CAN1 Message Slot 12 Standard ID0 CAN1 Message Slot 12 Standard ID1 (C1MSL12SID0) (C1MSL12SID1) CAN1 Message Slot 12 Extended ID0 CAN1 Message Slot 12 Extended ID1 (C1MSL12EID0) (C1MSL12EID1) CAN1 Message Slot 12 Extended ID2 CAN1 Message Slot 12 Data Length Register (C1MSL12EID2) (C1MSL12DLC) CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 (C1MSL12DT0) (C1MSL12DT1) CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 (C1MSL12DT2) (C1MSL12DT3) CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 (C1MSL12DT4) (C1MSL12DT5) CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 (C1MSL12DT6) (C1MSL12DT7) CAN1 Message Slot 12 Timestamp (C1MSL12TSP) CAN1 Message Slot 13 Standard ID0 CAN1 Message Slot 13 Standard ID1 (C1MSL13SID0) (C1MSL13SID1) CAN1 Message Slot 13 Extended ID0 CAN1 Message Slot 13 Extended ID1 (C1MSL13EID0) (C1MSL13EID1) CAN1 Message Slot 13 Extended ID2 CAN1 Message Slot 13 Data Length Register (C1MSL13EID2) (C1MSL13DLC) CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 (C1MSL13DT0) (C1MSL13DT1) CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 (C1MSL13DT2) (C1MSL13DT3) CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 (C1MSL13DT4) (C1MSL13DT5) CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 (C1MSL13DT6) (C1MSL13DT7) CAN1 Message Slot 13 Timestamp (C1MSL13TSP) CAN1 Message Slot 14 Standard ID0 CAN1 Message Slot 14 Standard ID1 (C1MSL14SID0) (C1MSL14SID1) CAN1 Message Slot 14 Extended ID0 CAN1 Message Slot 14 Extended ID1 (C1MSL14EID0) (C1MSL14EID1) CAN1 Message Slot 14 Extended ID2 CAN1 Message Slot 14 Data Length Register (C1MSL14EID2) (C1MSL14DLC) CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 (C1MSL14DT0) (C1MSL14DT1) CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 (C1MSL14DT2) (C1MSL14DT3) CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 (C1MSL14DT4) (C1MSL14DT5) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-39 3 SFR Area Register Map (32/37) Address b0 H'0080 15EC H'0080 15EE H'0080 15F0 H'0080 15F2 H'0080 15F4 H'0080 15F6 H'0080 15F8 H'0080 15FA H'0080 15FC H'0080 15FE H'0080 1600 H'0080 1602 H'0080 1604 H'0080 1606 H'0080 1608 H'0080 160A H'0080 160C H'0080 160E H'0080 1610 H'0080 1612 H'0080 1614 H'0080 1616 H'0080 1618 H'0080 161A H'0080 161C H'0080 161E H'0080 1620 H'0080 1622 H'0080 1624 H'0080 1626 H'0080 1628 H'0080 162A H'0080 162C H'0080 162E H'0080 1630 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-109 13-111 13-113 13-85 13-87 13-89 13-91 13-93 13-95 13-97 13-99 13-101 13-103 13-105 13-107 13-109 13-111 13-113 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 (C1MSL14DT6) (C1MSL14DT7) CAN1 Message Slot 14 Timestamp (C1MSL14TSP) CAN1 Message Slot 15 Standard ID0 CAN1 Message Slot 15 Standard ID1 (C1MSL15SID0) (C1MSL15SID1) CAN1 Message Slot 15 Extended ID0 CAN1 Message Slot 15 Extended ID1 (C1MSL15EID0) (C1MSL15EID1) CAN1 Message Slot 15 Extended ID2 CAN1 Message Slot 15 Data Length Register (C1MSL15EID2) (C1MSL15DLC) CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 (C1MSL15DT0) (C1MSL15DT1) CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 (C1MSL15DT2) (C1MSL15DT3) CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 (C1MSL15DT4) (C1MSL15DT5) CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 (C1MSL15DT6) (C1MSL15DT7) CAN1 Message Slot 15 Timestamp (C1MSL15TSP) CAN1 Message Slot 16 Standard ID0 CAN1 Message Slot 16 Standard ID1 (C1MSL16SID0) (C1MSL16SID1) CAN1 Message Slot 16 Extended ID0 CAN1 Message Slot 16 Extended ID1 (C1MSL16EID0) (C1MSL16EID1) CAN1 Message Slot 16 Extended ID2 CAN1 Message Slot 16 Data Length Register (C1MSL16EID2) (C1MSL16DLC) CAN1 Message Slot 16 Data 0 CAN1 Message Slot 16 Data 1 (C1MSL16DT0) (C1MSL16DT1) CAN1 Message Slot 16 Data 2 CAN1 Message Slot 16 Data 3 (C1MSL16DT2) (C1MSL16DT3) CAN1 Message Slot 16 Data 4 CAN1 Message Slot 16 Data 5 (C1MSL16DT4) (C1MSL16DT5) CAN1 Message Slot 16 Data 6 CAN1 Message Slot 16 Data 7 (C1MSL16DT6) (C1MSL16DT7) CAN1 Message Slot 16 Timestamp (C1MSL16TSP) CAN1 Message Slot 17 Standard ID0 CAN1 Message Slot 17 Standard ID1 (C1MSL17SID0) (C1MSL17SID1) CAN1 Message Slot 17 Extended ID0 CAN1 Message Slot 17 Extended ID1 (C1MSL17EID0) (C1MSL17EID1) CAN1 Message Slot 17 Extended ID2 CAN1 Message Slot 17 Data Length Register (C1MSL17EID2) (C1MSL17DLC) CAN1 Message Slot 17 Data 0 CAN1 Message Slot 17 Data 1 (C1MSL17DT0) (C1MSL17DT1) CAN1 Message Slot 17 Data 2 CAN1 Message Slot 17 Data 3 (C1MSL17DT2) (C1MSL17DT3) CAN1 Message Slot 17 Data 4 CAN1 Message Slot 17 Data 5 (C1MSL17DT4) (C1MSL17DT5) CAN1 Message Slot 17 Data 6 CAN1 Message Slot 17 Data 7 (C1MSL17DT6) (C1MSL17DT7) CAN1 Message Slot 17 Timestamp (C1MSL17TSP) CAN1 Message Slot 18 Standard ID0 CAN1 Message Slot 18 Standard ID1 (C1MSL18SID0) (C1MSL18SID1) CAN1 Message Slot 18 Extended ID0 CAN1 Message Slot 18 Extended ID1 (C1MSL18EID0) (C1MSL18EID1) CAN1 Message Slot 18 Extended ID2 CAN1 Message Slot 18 Data Length Register (C1MSL18EID2) (C1MSL18DLC) CAN1 Message Slot 18 Data 0 CAN1 Message Slot 18 Data 1 (C1MSL18DT0) (C1MSL18DT1) CAN1 Message Slot 18 Data 2 CAN1 Message Slot 18 Data 3 (C1MSL18DT2) (C1MSL18DT3) CAN1 Message Slot 18 Data 4 CAN1 Message Slot 18 Data 5 (C1MSL18DT4) (C1MSL18DT5) CAN1 Message Slot 18 Data 6 CAN1 Message Slot 18 Data 7 (C1MSL18DT6) (C1MSL18DT7) CAN1 Message Slot 18 Timestamp (C1MSL18TSP) CAN1 Message Slot 19 Standard ID0 CAN1 Message Slot 19 Standard ID1 (C1MSL19SID0) (C1MSL19SID1) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-40 3 SFR Area Register Map (33/37) Address b0 H'0080 1632 H'0080 1634 H'0080 1636 H'0080 1638 H'0080 163A H'0080 163C H'0080 163E H'0080 1640 H'0080 1642 H'0080 1644 H'0080 1646 H'0080 1648 H'0080 164A H'0080 164C H'0080 164E H'0080 1650 H'0080 1652 H'0080 1654 H'0080 1656 H'0080 1658 H'0080 165A H'0080 165C H'0080 165E H'0080 1660 H'0080 1662 H'0080 1664 H'0080 1666 H'0080 1668 H'0080 166A H'0080 166C H'0080 166E H'0080 1670 H'0080 1672 H'0080 1674 H'0080 1676 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 CAN1 Message Slot 19 Extended ID0 CAN1 Message Slot 19 Extended ID1 (C1MSL19EID0) (C1MSL19EID1) CAN1 Message Slot 19 Extended ID2 CAN1 Message Slot 19 Data Length Register (C1MSL19EID2) (C1MSL19DLC) CAN1 Message Slot 19 Data 0 CAN1 Message Slot 19 Data 1 (C1MSL19DT0) (C1MSL19DT1) CAN1 Message Slot 19 Data 2 CAN1 Message Slot 19 Data 3 (C1MSL19DT2) (C1MSL19DT3) CAN1 Message Slot 19 Data 4 CAN1 Message Slot 19 Data 5 (C1MSL19DT4) (C1MSL19DT5) CAN1 Message Slot 19 Data 6 CAN1 Message Slot 19 Data 7 (C1MSL19DT6) (C1MSL19DT7) CAN1 Message Slot 19 Timestamp (C1MSL19TSP) CAN1 Message Slot 20 Standard ID0 CAN1 Message Slot 20 Standard ID1 (C1MSL20SID0) (C1MSL20SID1) CAN1 Message Slot 20 Extended ID0 CAN1 Message Slot 20 Extended ID1 (C1MSL20EID0) (C1MSL20EID1) CAN1 Message Slot 20 Extended ID2 CAN1 Message Slot 20 Data Length Register (C1MSL20EID2) (C1MSL20DLC) CAN1 Message Slot 20 Data 0 CAN1 Message Slot 20 Data 1 (C1MSL20DT0) (C1MSL20DT1) CAN1 Message Slot 20 Data 2 CAN1 Message Slot 20 Data 3 (C1MSL20DT2) (C1MSL20DT3) CAN1 Message Slot 20 Data 4 CAN1 Message Slot 20 Data 5 (C1MSL20DT4) (C1MSL20DT5) CAN1 Message Slot 20 Data 6 CAN1 Message Slot 20 Data 7 (C1MSL20DT6) (C1MSL20DT7) CAN1 Message Slot 20 Timestamp (C1MSL20TSP) CAN1 Message Slot 21 Standard ID0 CAN1 Message Slot 21 Standard ID1 (C1MSL21SID0) (C1MSL21SID1) CAN1 Message Slot 21 Extended ID0 CAN1 Message Slot 21 Extended ID1 (C1MSL21EID0) (C1MSL21EID1) CAN1 Message Slot 21 Extended ID2 CAN1 Message Slot 21 Data Length Register (C1MSL21EID2) (C1MSL21DLC) CAN1 Message Slot 21 Data 0 CAN1 Message Slot 21 Data 1 (C1MSL21DT0) (C1MSL21DT1) CAN1 Message Slot 21 Data 2 CAN1 Message Slot 21 Data 3 (C1MSL21DT2) (C1MSL21DT3) CAN1 Message Slot 21 Data 4 CAN1 Message Slot 21 Data 5 (C1MSL21DT4) (C1MSL21DT5) CAN1 Message Slot 21 Data 6 CAN1 Message Slot 21 Data 7 (C1MSL21DT6) (C1MSL21DT7) CAN1 Message Slot 21 Timestamp (C1MSL21TSP) CAN1 Message Slot 22 Standard ID0 CAN1 Message Slot 22 Standard ID1 (C1MSL22SID0) (C1MSL22SID1) CAN1 Message Slot 22 Extended ID0 CAN1 Message Slot 22 Extended ID1 (C1MSL22EID0) (C1MSL22EID1) CAN1 Message Slot 22 Extended ID2 CAN1 Message Slot 22 Data Length Register (C1MSL22EID2) (C1MSL22DLC) CAN1 Message Slot 22 Data 0 CAN1 Message Slot 22 Data 1 (C1MSL22DT0) (C1MSL22DT1) CAN1 Message Slot 22 Data 2 CAN1 Message Slot 22 Data 3 (C1MSL22DT2) (C1MSL22DT3) CAN1 Message Slot 22 Data 4 CAN1 Message Slot 22 Data 5 (C1MSL22DT4) (C1MSL22DT5) CAN1 Message Slot 22 Data 6 CAN1 Message Slot 22 Data 7 (C1MSL22DT6) (C1MSL22DT7) CAN1 Message Slot 22 Timestamp (C1MSL22TSP) CAN1 Message Slot 23 Standard ID0 CAN1 Message Slot 23 Standard ID1 (C1MSL23SID0) (C1MSL23SID1) CAN1 Message Slot 23 Extended ID0 CAN1 Message Slot 23 Extended ID1 (C1MSL23EID0) (C1MSL23EID1) CAN1 Message Slot 23 Extended ID2 CAN1 Message Slot 23 Data Length Register (C1MSL23EID2) (C1MSL23DLC) CAN1 Message Slot 23 Data 0 CAN1 Message Slot 23 Data 1 (C1MSL23DT0) (C1MSL23DT1) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-41 3 SFR Area Register Map (34/37) Address b0 H'0080 1678 H'0080 167A H'0080 167C H'0080 167E H'0080 1680 H'0080 1682 H'0080 1684 H'0080 1686 H'0080 1688 H'0080 168A H'0080 168C H'0080 168E H'0080 1690 H'0080 1692 H'0080 1694 H'0080 1696 H'0080 1698 H'0080 169A H'0080 169C H'0080 169E H'0080 16A0 H'0080 16A2 H'0080 16A4 H'0080 16A6 H'0080 16A8 H'0080 16AA H'0080 16AC H'0080 16AE H'0080 16B0 H'0080 16B2 H'0080 16B4 H'0080 16B6 H'0080 16B8 H'0080 16BA H'0080 16BC +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 13-114 13-86 13-88 13-90 13-92 13-94 13-96 13-98 13-100 13-102 13-104 13-106 13-108 13-110 13-112 CAN1 Message Slot 23 Data 2 CAN1 Message Slot 23 Data 3 (C1MSL23DT2) (C1MSL23DT3) CAN1 Message Slot 23 Data 4 CAN1 Message Slot 23 Data 5 (C1MSL23DT4) (C1MSL23DT5) CAN1 Message Slot 23 Data 6 CAN1 Message Slot 23 Data 7 (C1MSL23DT6) (C1MSL23DT7) CAN1 Message Slot 23 Timestamp (C1MSL23TSP) CAN1 Message Slot 24 Standard ID0 CAN1 Message Slot 24 Standard ID1 (C1MSL24SID0) (C1MSL24SID1) CAN1 Message Slot 24 Extended ID0 CAN1 Message Slot 24 Extended ID1 (C1MSL24EID0) (C1MSL24EID1) CAN1 Message Slot 24 Extended ID2 CAN1 Message Slot 24 Data Length Register (C1MSL24EID2) (C1MSL24DLC) CAN1 Message Slot 24 Data 0 CAN1 Message Slot 24 Data 1 (C1MSL24DT0) (C1MSL24DT1) CAN1 Message Slot 24 Data 2 CAN1 Message Slot 24 Data 3 (C1MSL24DT2) (C1MSL24DT3) CAN1 Message Slot 24 Data 4 CAN1 Message Slot 24 Data 5 (C1MSL24DT4) (C1MSL24DT5) CAN1 Message Slot 24 Data 6 CAN1 Message Slot 24 Data 7 (C1MSL24DT6) (C1MSL24DT7) CAN1 Message Slot 24 Timestamp (C1MSL24TSP) CAN1 Message Slot 25 Standard ID0 CAN1 Message Slot 25 Standard ID1 (C1MSL25SID0) (C1MSL25SID1) CAN1 Message Slot 25 Extended ID0 CAN1 Message Slot 25 Extended ID1 (C1MSL25EID0) (C1MSL25EID1) CAN1 Message Slot 25 Extended ID2 CAN1 Message Slot 25 Data Length Register (C1MSL25EID2) (C1MSL25DLC) CAN1 Message Slot 25 Data 0 CAN1 Message Slot 25 Data 1 (C1MSL25DT0) (C1MSL25DT1) CAN1 Message Slot 25 Data 2 CAN1 Message Slot 25 Data 3 (C1MSL25DT2) (C1MSL25DT3) CAN1 Message Slot 25 Data 4 CAN1 Message Slot 25 Data 5 (C1MSL25DT4) (C1MSL25DT5) CAN1 Message Slot 25 Data 6 CAN1 Message Slot 25 Data 7 (C1MSL25DT6) (C1MSL25DT7) CAN1 Message Slot 25 Timestamp (C1MSL25TSP) CAN1 Message Slot 26 Standard ID0 CAN1 Message Slot 26 Standard ID1 (C1MSL26SID0) (C1MSL26SID1) CAN1 Message Slot 26 Extended ID0 CAN1 Message Slot 26 Extended ID1 (C1MSL26EID0) (C1MSL26EID1) CAN1 Message Slot 26 Extended ID2 CAN1 Message Slot 26 Data Length Register (C1MSL26EID2) (C1MSL26DLC) CAN1 Message Slot 26 Data 0 CAN1 Message Slot 26 Data 1 (C1MSL26DT0) (C1MSL26DT1) CAN1 Message Slot 26 Data 2 CAN1 Message Slot 26 Data 3 (C1MSL26DT2) (C1MSL26DT3) CAN1 Message Slot 26 Data 4 CAN1 Message Slot 26 Data 5 (C1MSL26DT4) (C1MSL26DT5) CAN1 Message Slot 26 Data 6 CAN1 Message Slot 26 Data 7 (C1MSL26DT6) (C1MSL26DT7) CAN1 Message Slot 26 Timestamp (C1MSL26TSP) CAN1 Message Slot 27 Standard ID0 CAN1 Message Slot 27 Standard ID1 (C1MSL27SID0) (C1MSL27SID1) CAN1 Message Slot 27 Extended ID0 CAN1 Message Slot 27 Extended ID1 (C1MSL27EID0) (C1MSL27EID1) CAN1 Message Slot 27 Extended ID2 CAN1 Message Slot 27 Data Length Register (C1MSL27EID2) (C1MSL27DLC) CAN1 Message Slot 27 Data 0 CAN1 Message Slot 27 Data 1 (C1MSL27DT0) (C1MSL27DT1) CAN1 Message Slot 27 Data 2 CAN1 Message Slot 27 Data 3 (C1MSL27DT2) (C1MSL27DT3) CAN1 Message Slot 27 Data 4 CAN1 Message Slot 27 Data 5 (C1MSL27DT4) (C1MSL27DT5) CAN1 Message Slot 27 Data 6 CAN1 Message Slot 27 Data 7 (C1MSL27DT6) (C1MSL27DT7) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-42 3 SFR Area Register Map (35/37) Address b0 H'0080 16BE H'0080 16C0 H'0080 16C2 H'0080 16C4 H'0080 16C6 H'0080 16C8 H'0080 16CA H'0080 16CC H'0080 16CE H'0080 16D0 H'0080 16D2 H'0080 16D4 H'0080 16D6 H'0080 16D8 H'0080 16DA H'0080 16DC H'0080 16DE H'0080 16E0 H'0080 16E2 H'0080 16E4 H'0080 16E6 H'0080 16E8 H'0080 16EA H'0080 16EC H'0080 16EE H'0080 16F0 H'0080 16F2 H'0080 16F4 H'0080 16F6 H'0080 16F8 H'0080 16FA H'0080 16FC H'0080 16FE +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas | +1 address See pages b7 b8 b15 CAN1 Message Slot 27 Timestamp 13-114 (C1MSL27TSP) CAN1 Message Slot 28 Standard ID0 CAN1 Message Slot 28 Standard ID1 13-86 (C1MSL28SID0) (C1MSL28SID1) 13-88 CAN1 Message Slot 28 Extended ID0 CAN1 Message Slot 28 Extended ID1 13-90 (C1MSL28EID0) (C1MSL28EID1) 13-92 CAN1 Message Slot 28 Extended ID2 CAN1 Message Slot 28 Data Length Register 13-94 (C1MSL28EID2) (C1MSL28DLC) 13-96 CAN1 Message Slot 28 Data 0 CAN1 Message Slot 28 Data 1 13-98 (C1MSL28DT0) (C1MSL28DT1) 13-100 CAN1 Message Slot 28 Data 2 CAN1 Message Slot 28 Data 3 13-102 (C1MSL28DT2) (C1MSL28DT3) 13-104 CAN1 Message Slot 28 Data 4 CAN1 Message Slot 28 Data 5 13-106 (C1MSL28DT4) (C1MSL28DT5) 13-108 CAN1 Message Slot 28 Data 6 CAN1 Message Slot 28 Data 7 13-110 (C1MSL28DT6) (C1MSL28DT7) 13-112 CAN1 Message Slot 28 Timestamp 13-114 (C1MSL28TSP) CAN1 Message Slot 29 Standard ID0 CAN1 Message Slot 29 Standard ID1 13-86 (C1MSL29SID0) (C1MSL29SID1) 13-88 CAN1 Message Slot 29 Extended ID0 CAN1 Message Slot 29 Extended ID1 13-90 (C1MSL29EID0) (C1MSL29EID1) 13-92 CAN1 Message Slot 29 Extended ID2 CAN1 Message Slot 29 Data Length Register 13-94 (C1MSL29EID2) (C1MSL29DLC) 13-96 CAN1 Message Slot 29 Data 0 CAN1 Message Slot 29 Data 1 13-98 (C1MSL29DT0) (C1MSL29DT1) 13-100 CAN1 Message Slot 29 Data 2 CAN1 Message Slot 29 Data 3 13-102 (C1MSL29DT2) (C1MSL29DT3) 13-104 CAN1 Message Slot 29 Data 4 CAN1 Message Slot 29 Data 5 13-106 (C1MSL29DT4) (C1MSL29DT5) 13-108 CAN1 Message Slot 29 Data 6 CAN1 Message Slot 29 Data 7 13-110 (C1MSL29DT6) (C1MSL29DT7) 13-112 CAN1 Message Slot 29 Timestamp 13-114 (C1MSL29TSP) CAN1 Message Slot 30 Standard ID0 CAN1 Message Slot 30 Standard ID1 13-86 (C1MSL30SID0) (C1MSL30SID1) 13-88 CAN1 Message Slot 30 Extended ID0 CAN1 Message Slot 30 Extended ID1 13-90 (C1MSL30EID0) (C1MSL30EID1) 13-92 CAN1 Message Slot 30 Extended ID2 CAN1 Message Slot 30 Data Length Register 13-94 (C1MSL30EID2) (C1MSL30DLC) 13-96 CAN1 Message Slot 30 Data 0 CAN1 Message Slot 30 Data 1 13-98 (C1MSL30DT0) (C1MSL30DT1) 13-100 CAN1 Message Slot 30 Data 2 CAN1 Message Slot 30 Data 3 13-102 (C1MSL30DT2) (C1MSL30DT3) 13-104 CAN1 Message Slot 30 Data 4 CAN1 Message Slot 30 Data 5 13-106 (C1MSL30DT4) (C1MSL30DT5) 13-108 CAN1 Message Slot 30 Data 6 CAN1 Message Slot 30 Data 7 13-110 (C1MSL30DT6) (C1MSL30DT7) 13-112 CAN1 Message Slot 30 Timestamp 13-114 (C1MSL30TSP) CAN1 Message Slot 31 Standard ID0 CAN1 Message Slot 31 Standard ID1 13-86 (C1MSL31SID0) (C1MSL31SID1) 13-88 CAN1 Message Slot 31 Extended ID0 CAN1 Message Slot 31 Extended ID1 13-90 (C1MSL31EID0) (C1MSL31EID1) 13-92 CAN1 Message Slot 31 Extended ID2 CAN1 Message Slot 31 Data Length Register 13-94 (C1MSL31EID2) (C1MSL31DLC) 13-96 CAN1 Message Slot 31 Data 0 CAN1 Message Slot 31 Data 1 13-98 (C1MSL31DT0) (C1MSL31DT1) 13-100 CAN1 Message Slot 31 Data 2 CAN1 Message Slot 31 Data 3 13-102 (C1MSL31DT2) (C1MSL31DT3) 13-104 CAN1 Message Slot 31 Data 4 CAN1 Message Slot 31 Data 5 13-106 (C1MSL31DT4) (C1MSL31DT5) 13-108 CAN1 Message Slot 31 Data 6 CAN1 Message Slot 31 Data 7 13-110 (C1MSL31DT6) (C1MSL31DT7) 13-112 CAN1 Message Slot 31 Timestamp 13-114 (C1MSL31TSP) (Use inhibited area) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-43 3 SFR Area Register Map (36/37) Address b0 H'0080 2000 H'0080 2002 H'0080 2004 H'0080 2006 H'0080 2008 H'0080 200A H'0080 200C H'0080 200E H'0080 2010 H'0080 2012 H'0080 2014 H'0080 2016 H'0080 2018 H'0080 201A DRI Transfer Counter (DRITRMCT) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 14-9 14-10 14-11 14-12 14-13 14-15 14-18 14-22 14-23 14-23 14-24 14-25 DIN Interrupt Request Status Register DIN Interrupt Request Enable Register (DRIDINIST) (DRIDINIEN) DEC Interrupt Request Status Register DEC Interrupt Request Enable Register (DRIDECIST) (DRIDECIEN) DRI Transfer Interrupt Request Status Register DRI Transfer Interrupt Request Enable Register (DRITRMIST) (DRITRMIEN) DRI Transfer Control Register DRI Special Mode Register (DRITRMCNT) (DRISPMOD) DRI Data Capture Control Register (DRIDCAPCNT) DRI Data Interleave Control Register DIN Input Event Select Register (DRIDSELCNT) (DINSEL) DD Input Enable Register 0 DD Input Enable Register 1 (DRIDDEN0) (DRIDDEN1) DD Input Enable Register 2 DD Input Enable Register 3 (DRIDDEN2) (DRIDDEN3) DRI Data Capture Event Count Setting Register (Upper) (DRIDCAPNUM) (Lower) DRI Capture Event Counter (DRIDCAPCT) (Upper) (Lower) (Upper) (Lower) (Use inhibited area) DRI Address Reload Register 0 (DRIADR0RLD) (Upper) (Lower) DRI Address Counter 0 (DRIADR0CT) (Upper) (Lower) DRI Address Reload Register 1 (DRIADR1RLD) (Upper) (Lower) DRI Address Counter 1 (DRIADR1CT) (Upper) (Lower) DIN Input Processing Control Register (DINCNT) DEC0 Control Register (Use inhibited area) (DEC0CNT) DEC0 Reload Register (DEC0RLD) DEC0 Counter (DEC0CT) DEC1 Control Register (Use inhibited area) (DEC1CNT) DEC1 Reload Register (DEC1RLD) DEC1 Counter (DEC1CT) DEC2 Control Register (Use inhibited area) (DEC2CNT) DEC2 Reload Register (DEC2RLD) DEC2 Counter (DEC2CT) DEC3 Control Register (Use inhibited area) (DEC3CNT) 14-26 14-27 | H'0080 2020 H'0080 2022 H'0080 2024 H'0080 2026 H'0080 2028 H'0080 202A H'0080 202C H'0080 202E H'0080 2030 H'0080 2032 H'0080 2034 H'0080 2036 H'0080 2038 H'0080 203A H'0080 203C H'0080 203E H'0080 2040 H'0080 2042 H'0080 2044 14-29 14-28 14-29 14-28 14-30 14-31 14-36 14-36 14-31 14-36 14-36 14-32 14-36 14-36 14-32 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-44 3 SFR Area Register Map (37/37) Address b0 H'0080 2046 H'0080 2048 H'0080 204A H'0080 204C H'0080 204E DEC4 Control Register (DEC4CNT) DEC4 Reload Register (DEC4RLD) DEC4 Counter (DEC4CT) (Use inhibited area) (Use inhibited area) +0 address b7 b8 DEC3 Reload Register (DEC3RLD) DEC3 Counter (DEC3CT) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 14-36 14-36 (Use inhibited area) 14-33 14-36 14-36 | H'0080 3FFE Note 1: Address H'0080 0600 to H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefinited. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area. Note 2: This area exists only in the 32186 and it is use prohibition area in the 32185. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-45 3 NBD Control Area Register Map Address b0 H'E000 0000 H'E000 0002 H'E000 0004 H'E000 0006 H'E000 0008 Event Generation Register (NEVNTGEN) NBD Pin Control Register (NBDCNT) (Use inhibited area) NBD Enable Register (NBDENB) (Use inhibited area) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 (Use inhibited area) See pages 16-6 (Use inhibited area) 16-4 (Use inhibited area) 16-12 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-46 3 3.5 EIT Vector Entry ADDRESS SPACE 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/external extension areas. The branch instruction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.” 0 31 H'0000 0000 H'0000 0004 RI (Reset Interrupt) H'0000 0008 H'0000 000C H'0000 0010 H'0000 0014 SBI (System Break Interrupt) H'0000 0018 H'0000 001C H'0000 0020 H'0000 0024 RIE (Reserved Instruction Exception) H'0000 0028 H'0000 002C H'0000 0030 H'0000 0034 AE (Address Exception) H'0000 0038 H'0000 003C H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0090 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 EI (External Interrupt) (Note 1) FPE (Floating-Point Exception) Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000. Figure 3.5.1 EIT Vector Entry 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-47 3 3.6 ICU Vector Table ADDRESS SPACE 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.” ICU Vector Table Memory Map (1/3) Address b0 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 +0 address b7 b8 MJT Input Interrupt 4 Handler Start Address (A0–A15) MJT Input Interrupt 4 Handler Start Address (A16–A31) MJT Input Interrupt 3 Handler Start Address (A0–A15) MJT Input Interrupt 3 Handler Start Address (A16–A31) MJT Input Interrupt 2 Handler Start Address (A0–A15) MJT Input Interrupt 2 Handler Start Address (A16–A31) MJT Input Interrupt 1 Handler Start Address (A0–A15) MJT Input Interrupt 1 Handler Start Address (A16–A31) MJT Input Interrupt 0 Handler Start Address (A0–A15) MJT Input Interrupt 0 Handler Start Address (A16–A31) MJT Output Interrupt 7 Handler Start Address (A0–A15) MJT Output Interrupt 7 Handler Start Address (A16–A31) MJT Output Interrupt 6 Handler Start Address (A0–A15) MJT Output Interrupt 6 Handler Start Address (A16–A31) MJT Output Interrupt 5 Handler Start Address (A0–A15) MJT Output Interrupt 5 Handler Start Address (A16–A31) MJT Output Interrupt 4 Handler Start Address (A0–A15) MJT Output Interrupt 4 Handler Start Address (A16–A31) MJT Output Interrupt 3 Handler Start Address (A0–A15) MJT Output Interrupt 3 Handler Start Address (A16–A31) MJT Output Interrupt 2 Handler Start Address (A0–A15) MJT Output Interrupt 2 Handler Start Address (A16–A31) MJT Output Interrupt 1 Handler Start Address (A0–A15) MJT Output Interrupt 1 Handler Start Address (A16–A31) MJT Output Interrupt 0 Handler Start Address (A0–A15) MJT Output Interrupt 0 Handler Start Address (A16–A31) DMA0–4 Interrupt Handler Start Address (A0–A15) DMA0–4 Interrupt Handler Start Address (A16–A31) SIO1 Receive Interrupt Handler Start Address (A0–A15) SIO1 Receive Interrupt Handler Start Address (A16–A31) SIO1 Transmit Interrupt Handler Start Address (A0–A15) SIO1 Transmit Interrupt Handler Start Address (A16–A31) SIO0 Receive Interrupt Handler Start Address (A0–A15) SIO0 Receive Interrupt Handler Start Address (A16–A31) +1 address b15 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-48 3 ICU Vector Table Memory Map (2/3) Address b0 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E H'0000 0110 H'0000 0112 H'0000 0114 H'0000 0116 H'0000 0118 H'0000 011A H'0000 011C H'0000 011E H'0000 0120 H'0000 0122 TML1 Input Interrupt Handler Start Address (A0–A15) TML1 Input Interrupt Handler Start Address (A16–A31) +0 address b7 b8 SIO0 Transmit Interrupt Handler Start Address (A0–A15) SIO0 Transmit Interrupt Handler Start Address (A16–A31) A/D0 Conversion Interrupt Handler Start Address (A0–A15) ADDRESS SPACE 3.6 ICU Vector Table +1 address b15 A/D0 Conversion Interrupt Handler Start Address (A16–A31) TID0 Input Interrupt Handler Start Address (A0–A15) TID0 Input Interrupt Handler Start Address (A16–A31) TOU0 Output Interrupt Handler Start Address (A0–A15) TOU0 Output Interrupt Handler Start Address (A16–A31) DMA5–9 Interrupt Handler Start Address (A0–A15) DMA5–9 Interrupt Handler Start Address (A16–A31) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31) RTD Interrupt Handler Start Address (A0–A15) RTD Interrupt Handler Start Address (A16–A31) TID1 Input Interrupt Handler Start Address (A0–A15) TID1 Input Interrupt Handler Start Address (A16–A31) TOU1 Output Interrupt Handler Start Address (A0–A15) TOU1 Output Interrupt Handler Start Address (A16–A31) SIO4, 5 Transmit/receive Interrupt Handler Start Address (A0–A15) SIO4, 5 Transmit/receive Interrupt Handler Start Address (A16–A31) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) DRI Transfer Interrupt Handler Start Address (A0–A15) DRI Transfer Interrupt Handler Start Address (A16–A31) DRI Counter Interrupt Handler Start Address (A0–A15) DRI Counter Interrupt Handler Start Address (A16–A31) DRI Event Detection Interrupt Handler Start Address (A0–A15) DRI Event Detection Interrupt Handler Start Address (A16–A31) CAN0 Transmit/receive Completion Interrupt Handler Start Address (A0–A15) CAN0 Transmit/receive Completion Interrupt Handler Start Address (A16–A31) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-49 3 ICU Vector Table Memory Map (3/3) Address b0 H'0000 0124 H'0000 0126 H'0000 0128 H'0000 012A H'0000 012C H'0000 012E H'0000 0130 H'0000 0132 H'0000 0134 H'0000 0136 H'0000 0138 H'0000 013A +0 address b7 b8 ADDRESS SPACE 3.6 ICU Vector Table +1 address b15 CAN0 Single-shot Interrupt Handler Start Address (A0–A15) CAN0 Single-shot Interrupt Handler Start Address (A16–A31) CAN0 Error Interrupt Handler Start Address (A0–A15) CAN0 Error Interrupt Handler Start Address (A16–A31) CAN1 Transmit/receive Completion Interrupt Handler Start Address (A0–A15) CAN1 Transmit/receive Completion Interrupt Handler Start Address (A16–A31) CAN1 Single-shot Interrupt Handler Start Address (A0–A15) CAN1 Single-shot Interrupt Handler Start Address (A16–A31) CAN1 Error Interrupt Handler Start Address (A0–A15) CAN1 Error Interrupt Handler Start Address (A16–A31) RAM Write Monitor Interrupt Handler Start Address (A0–A15) RAM Write Monitor Interrupt Handler Start Address (A16–A31) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-50 3 3.7 Notes on Address Space • Virtual flash emulation function ADDRESS SPACE 3.7 Notes on Address Space The microcomputer has the function to map 8-Kbyte memory blocks of the internal RAM (maximum for 32185 is 4 blocks, for 32186 is 8 blocks) into areas (L banks) of the internal flash memory that are divided in 8-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This is the function allows shift from the contents of internal flash memory at the addresses specified by the Virtual Flash L Bank Register to the data located in 8-Kbyte blocks of the internal RAM. That way, the relevant RAM data can read out by reading the content of internal flash memory. • Dummy access areas Address H'0080 0600 to H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefinited. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-51 3 ADDRESS SPACE 3.7 Notes on Address Space This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 3-52 CHAPTER 4 EIT 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring PC and PSW EIT Vector Entry Exception Processing Interrupt Processing Trap Processing EIT Priority Levels Example of EIT Processing Notes on EIT 4 4.1 Outline of EIT EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and Floating-Point Exception (FPE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS’s system call by the programmer. EIT Exception (Exception) Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Interrupt (Interrupt) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (Trap) Trap (TRAP) Figure 4.1.1 Classification of EITs 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-2 4 4.2 EIT Events 4.2.1 Exception (1) Reserved Instruction Exception (RIE) EIT 4.2 EIT Events Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. (3) Floating-point Exception (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is outlined below. 1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF occurs. Table 4.2.1 Operation Results When an OVF Occurred Operation Result (Content of the Destination Register) Rounding Mode Sign of the Result When the OVF EIT processing is masked (Note 1) +MAX -Infinity +Infinity -MAX +MAX -MAX +Infinity -Infinity No Change When the OVF EIT processing is executed (Note 2) -Infinity +Infinity 0 Nearest + + + + - Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1" Notes: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time. • +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF 2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs. Table 4.2.2 Operation Results when a UDF Occurred Operation Result (Content of the Destination Register) When UDF EIT processing is masked (Note 1) DN = 0 : An unimplemented exception occurs DN = 0 : An unimplemented exception occurs Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1" When UDF EIT processing is executed (Note 2) No change 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-3 4 EIT 4.2 EIT Events 3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Table 4.2.3 Operation Results when an IXCT Occurred Operation Result (Content of the Destination Register) Occurrence Condition Overflow occurs in OVF masked condition Rounding occurs Rounded value Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1" No change When the IXCT EIT processing is masked (Note 1) Reference OVF operation results When the IXCT EIT processing is executed (Note 2) No change 4) Zero Division Exception (DIV0) The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 is occurs. Table 4.2.4 Operation Results When a DIV0 Occurred Operation Result (Content of the Destination Register) Dividend When the DIV0 EIT processing is masked (Note 1) +-Infinity (Sign is derived by Nonzero finite value exclusive ORing the signs of the divisor and dividend.) Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1" No change When the DIV0 EIT processing is executed (Note 2) Please note that the DIV0 EIT processing does not occur in the following conditions. Table 4.2.5 Cases in Which No DIV0 Occur Dividend 0 Infinity Behavior An invalid operation exception occurs No exceptions occur (with the result = "Infinity") 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-4 4 Table 4.2.6 Operation Results When an IVLD Occurred EIT 4.2 EIT Events 5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Operation Result (Content of the Destination Register) Occurrence Condition When the IVLD EIT processing is masked (Note 1) When the IVLD EIT processing is executed (Note 2) Operation for SNaN operand +Infinity-(+Infinity), -Infinity-(-Infinity) 0 x Infinity 0/0, Infinity / Infinity When FTOI instruction was executed When FTOS instruction was executed When < or > comparison was performed on NaN Return value when pre-conversion signed bit is: "0": H'7FFF FFFF "1": H'8000 0000 Return value when pre-conversion signed bit is: "0": H'7FFF FFFF "1": H'8000 0000 Comparison results (comparison invalid) QNaN • When an integer conversion overflowed No change • When NaN or Infinity was converted into an integer Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1" Note: • NaN (Not a Number) SNaN (Signaling NaN): a NaN in which the MSB of the mantissa field is "0." When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the mantissa field is "1." Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be influenced by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware. 6) Unimplemented Exception (UIPL) The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand. (Note 1) Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged. Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0," an UIPL occurs. 4.2.2 Interrupt (1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. For details about the reset interrupt, see Chapter 7, “Reset.” (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-5 4 4.2.3 Trap EIT 4.2 EIT Events Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15. 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a reset interrupt, is shown below. EIT request generated Program execution restarted Instruction Instruction Instruction A B C Program suspended and EIT request accepted Instruction Instruction C D Instruction processing-canceled type (RIE, AE) Instruction processing-completed type (FPE, EI, TRAP) PC→BPC PSW→BPSW Hardware preprocessing (Note 1) Hardware postprocessing (Note 1) BPSW→PSW BPC→PC User-created EIT handler EIT vector entry Branch instruction BPC, PSW, FPSR and general-purpose registers are saved to the stack EIT handler except for SBI Processing by handler BPC, PSW, FPSR and general-purpose registers are restored from the stack RTE instruction (SBI) SBI (System Break Interrupt processing) Program terminated or system is reset Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. Figure 4.3.1 Outline of the EIT Processing Procedure When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s PSW field is transferred to the BPSW field in that register. Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-6 4 4.4 EIT Processing Mechanism EIT 4.4 EIT Processing Mechanism The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below. M32R/ECU M32R CPU core RESET# RI RI AE, RIE, FPE, TRAP High Priority SBI# Interrupt controller (ICU) SBI SBI Internal peripheral I/Os EI EI Low IE flag (PSW) BPC register BPSW PSW PC register PSW register Figure 4.4.1 EIT Processing Mechanism 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-7 4 4.5 Acceptance of EIT Events EIT 4.5 Acceptance of EIT Events When an EIT event occurs, the CPU suspends the program it has hitherto been executed and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Type of Processing Instruction processingcanceled type Instruction processingcanceled type Instruction processingcompleted type Instruction processingaborted type Instruction processingcompleted type Instruction processingcompleted type Instruction processingcompleted type Acceptance Timing During instruction execution During instruction execution Break in instructions Each machine cycle Break in instructions (word boundary only) Break in instructions (word boundary only) Break in instructions Values Set in BPC Register PC value of the instruction that generated RIE PC value of the instruction that generated AE PC value of the instruction that generated FPE + 4 Undefined value PC value of the next instruction PC value of the next instruction PC value of TRAP instruction + 4 4.6 Saving and Restoring PC and PSW The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction. (1) Hardware preprocessing when an EIT is accepted [1] Save the BSM BIE BC PSW ← ← ← register’s SM, IE and C bits in its backup field. SM IE C [2] Update the PSW register’s SM, IE and C bits SM ← Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI) IE ← Cleared to "0" C ← Cleared to "0" [3] Save the PC register BPC ← PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the RTE instruction is executed [A] Restore SM IE C the PSW register’s SM, IE and C bits from its backup field. ← BSM ← BIE ← BC [B] Restore the PC register from the BPC register. PC ← BPC Note: • The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE instruction are undefined. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-8 4 [1] Saving the SM, IE and C bits BSM BIE BC ← ← ← SM IE C EIT 4.6 Saving and Restoring PC and PSW [3] Saving the PC BPC ← PC [4] Setting the vector address in the PC PC ← Vector address [2] Updating the SM, IE and C bits SM IE C ← ← ← Unchanged or 0 0 0 [A] Restoring the SM, IE and C bits from the backup field SM IE C ← ← ← BSM BIE BC [B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined. The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined. PSW BPC PC When EIT is accepted [1] [2] [3] [4] When RTE instruction is executed [A] [B] BPSW field 0(MSB) 7 8 15 16 17 23 24 25 PSW field 31(LSB) PSW 0000000000000000 00000 00000 BSM BIE BC SM IE C Figure 4.6.1 Saving and Restoring the PC and PSW 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-9 4 4.7 EIT Vector Entry EIT 4.7 EIT Vector Entry The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry and the status of SM, IE and BPC bits after each EIT events occured. Table 4.7.1 EIT Vector Entry Name Reset Interrupt System Break Interrupt Reserved Instruction Exception Address Exception Trap AE TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 External Interrupt Floating-Point Exception EI FPE H'0000 0030 H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0090 Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC of the instruction that generated AE PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of the next instruction PC of the instruction that generated FPE + 4 RIE H'0000 0020 Unchanged 0 PC of the instruction that generated RIE Abbreviation Vector Address RI SBI H'0000 0010 SM 0 IE 0 0 BPC Undefined PC of the next instruction H'0000 0000 (Note 1) 0 H'0000 0080 (Note 2) 0 Note 1: During boot mode, the CPU starts executing the boot program after exiting the reset state. For details, see Section 6.6, “Programming the Internal Flash Memory.” Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080 4000). For details, see Section 6.6, “Programming the Internal Flash Memory.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-10 4 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) EIT 4.8 Exception Processing [Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) +0 Address H'00 Return address +1 +2 +3 Address H'00 Return address +0 +1 +2 +3 H'04 H'08 H'0C RIE occurred H'04 H'08 H'0C RIE occurred BPC H'04 BPC H'06 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-11 4 EIT 4.8 Exception Processing (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred. 4.8.2 Address Exception (AE) [Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur. • Two low-order address bits accessed in the LDH, LDUH or STH instruction are "01" or "11" • Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are "01," "10" or "11" When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-12 4 +0 Address H'00 Return address EIT 4.8 Exception Processing +1 +2 +3 Address H'00 Return address +0 +1 +2 +3 H'04 H'08 H'0C AE occurred H'04 H'08 H'0C AE occurred BPC H'04 BPC H'06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred. 4.8.3 Floating-Point Exception (FPE) [Occurrence Conditions] Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected. Note, however, that the EIT processing described below is executed only when the exception that occurred is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-13 4 EIT 4.8 Exception Processing (3) Saving the PC The PC value of the instruction that generated the FPE + 4 is set in the BPC register. Because all of the instructions that generate an FPE are 32 bits long, the address to which the RTE instruction returns is always the instruction next to the one that generated the FPE. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0090 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0090 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-14 4 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) EIT 4.9 Interrupt Processing [Occurrence Conditions] A reset interrupt is accepted in machine cycle by pulling the RESET# input signal "L." The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below. SM ← 0 IE ← 0 C ← 0 For the reset interrupt, the values of BSM, BIE and BC bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.6, “Programming the Internal Flash Memory.” (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program. 4.9.2 System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-15 4 Address 1000 Address 1002 Address 1004 EIT 4.9 Interrupt Processing Order in which instructions are executed Address 1008 16-bit instruction 16-bit instruction 32-bit instruction × Interrupt may be accepted Interrupt cannot Interrupt may be accepted be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The address of the next instruction (always on word boundary) following one in which the interrupt was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-16 4 4.9.3 External Interrupt (EI) EIT 4.9 Interrupt Processing An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the microcomputer’s internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1," accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Order in which instructions are executed Address 1000 Address 1002 Address 1004 Address 1008 16-bit instruction 16-bit instruction 32-bit instruction × Interrupt may be accepted Interrupt cannot be accepted Interrupt may be accepted Interrupt may be accepted Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.6, “Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-17 4 4.10 Trap Processing 4.10.1 Trap EIT 4.10 Trap Processing [Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to "00" when returned to the PC.) +0 Address H'00 Return address +1 +2 +3 Address H'00 H'04 H'08 H'0C +0 +1 +2 +3 H'04 H'08 H'0C TRAP instruction TRAP instruction Return address BPC H'08 BPC H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-18 4 EIT 4.10 Trap Processing (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary generalpurpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including the instruction that generates a trap (see Figure 4.10.1). 4.11 EIT Priority Levels The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority Highest 1 2 EIT Event Reset Interrupt (RI) Address Exception (AE) Reserved Instruction Exception (RIE) Floating-Point Exception (FPE) Trap (TRAP) 3 Lowest 4 System Break Interrupt (SBI) External Interrupt (EI) Instruction processing-completed type PC of the next instruction Instruction processing-completed type Instruction processing-completed type Instruction processing-completed type Type of Processing Instruction processing-aborted type Instruction processing-canceled type Instruction processing-canceled type Values Set in BPC Register Undefined PC of the instruction that generated AE PC of the instruction that generated RIE PC of the instruction that generated FPE + 4 TRAP instruction + 4 PC of the next instruction Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-19 4 4.12 Example of EIT Processing (1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly EIT 4.12 Example of EIT Processing IE = 1 BPC register = Return address A IE = 0 RIE, AE, FPE, SBI, EI or TRAP occurs singly Return address A: IE = 1 RTE instruction If IE = 0, no events but reset and SBI are accepted. : EIT handler Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly (2) When RIE, AE, FPE or TRAP and EI occur simultaneously IE = 1 IE = 0 RIE, AE, FPE or TRAP and EI occur simultaneously Return address A: RIE, AE, FPE or TRAP is accepted first. BPC register = Return address A RTE instruction IE = 1 IE = 0 IE = 1 EI is accepted next. BPC register = Return address A RTE instruction : EIT handler Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-20 4 EIT vector entry BRA instruction EIT 4.12 Example of EIT Processing (Other than SBI) EIT handler (SBI) PC→BPC Hardware PSW→BPSW preprocessing (Note 1) Save BPC to the stack Save PSW to the stack System Break Interrupt (SBI) processing Program being executed Save general-purpose registers to the stack EIT event occurs Processing by EIT handler Program terminated or system reset Restore general-purpose registers from the stack (Note 1) Hardware BPSW→PSW postprocessing BPC→PC Restore PSW from the stack Restore BPC from the stack RTE Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. Figure 4.12.3 Example of EIT Processing 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-21 4 4.13 Notes on EIT EIT 4.13 Notes on EIT The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes. • Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 5.2 5.3 5.4 5.5 5.6 Outline of Interrupt Controller ICU Related Registers Interrupt Request Sources in Internal Peripheral I/O ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation 5 5.1 Outline of Interrupt Controller INTERRUPT CONTROLLER (ICU) 5.1 Outline of Interrupt Controller The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Interrupt request source Priority management Specification Maskable interrupt requests from internal peripheral I/Os : 40 sources (Note 1) System break interrupt request : 1 source (entered from SBI# pin) 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: It is the number which summarized the number of interrupt requests for every group, and they are 257 factors as an interrupt request factor total. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-2 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller Interrupt Controller (ICU) System Break Interrupt (SBI) request generated (nonmaskable) SBI Control Register (SBICR) SBI# SBIREQ SBI To the CPU core Peripheral circuits Interrupt request Interrupt request Interrupt request Edge Edge Edge Priority resolved by interrupt priority levels set IREQ IREQ IREQ Priority resolved by fixed hardware priority ILEVEL External Interrupt (EI) request generated (maskable) Interrupt Vector Register (IVECT) IMASK comparison EI To the CPU core NEW_IMASK (Note 1) Interrupt control circuit Interrupt control circuit Interrupt control circuit Level Level Level IREQ IREQ IREQ Interrupt Request Mask Register (IMASK) Interrupt Control Register Note 1: Interrupt control circuit indicates Interrupt request status register and Interrupt request mask register in each peripheral function. Figure 5.1.1 Block Diagram of the Interrupt Controller 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-3 5 5.2 ICU Related Registers INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (Use inhibited area) (Use inhibited area) (Use inhibited area) +1 address b15 5-5 See pages 5-6 5-7 | H'0080 0056 RAM Write Monitor Interrupt Control Register CAN1 Error Interrupt Control Register (IRAMWRCR) (ICAN1ERCR) H'0080 0058 CAN1 Single-Shot Interrupt Control Register CAN1 Transmit/Receive Interrupt Control Register (ICAN1SSCR) (ICAN1TRCR) H'0080 005A CAN0 Error Interrupt Control Register CAN0 Single-Shot Interrupt Control Register (ICAN0ERCR) (ICAN0SSCR) H'0080 005C CAN0 Transmit/Receive Interrupt Control Register DRI Event Detection Interrupt Control Register (ICAN0TRCR) (IDRIEVCR) H'0080 005E DRI Counter Interrupt Control Register DRI Transfer Interrupt Control Register (IDRICNTCR) (IDRITRCR) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register TML1 Input Interrupt Control Register (ICAN0CR) (ITML1CR) H'0080 0062 (Use inhibited area) H'0080 0064 H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TID1 Output Interrupt Control Register ( ITID1CR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) TOU0 Output Interrupt Control Register (ITOU0CR) A/D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 6 (IMJTOCR6) MJT Input Interrupt Control Register 0 (IMJTICR0) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 4 (IMJTICR4) TOU1 Output Interrupt Control Register (ITOU1CR) RTD Interrupt Control Register (IRTDCR) DMA5–9 Interrupt Control Register (IDMA59CR) TID0 Output Interrupt Control Register (ITID0CR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 3 (IMJTICR3) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-4 5 5.2.1 Interrupt Vector Register Interrupt Vector Register (IVECT) b0 ? INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5 ? 1 ? 2 ? 3 ? 4 ? 6 ? 7 IVECT ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? b 0−15 Bit Name IVECT 16 low-order bits of ICU vector table address Function When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted R R W N interrupt request source are stored in this register. Note: • This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-loworder bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 013B) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK regis ter as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for levelrecognized interrupt request sources). (3) The interrupt request (EI) to the CPU core is dropped. (4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: • Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are dis abled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register. • To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), execute the following processing in the order given: (1) Read the Interrupt Vector Register (IVECT) (2) Perform a read access to the SFR at least once (3) Perform a dumy access to the internal memory, SFR, etc. at least once (4) Enable interrupts (by setting the IE bit to "1") 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-5 5 5.2.2 Interrupt Request Mask Register Interrupt Request Mask Register (IMASK) b0 0 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 6 b7 1 1 0 2 0 3 0 4 0 5 1 IMASK 1 b 0–4 5–7 Bit Name No function assigned. Fix to "0" IMASK Interrupt request mask bit 000: Disable maskable interrupts 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1 011: Accept interrupts with priority levels 0–2 100: Accept interrupts with priority levels 0–3 101: Accept interrupts with priority levels 0–4 110: Accept interrupts with priority levels 0–5 111: Accept interrupts with priority levels 0–6 Function R 0 R W 0 W The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: • Do not write to the Interrupt Request Mask Register (IMASK) unless interrupts are disabled (PSW register IE bit = "0"). • To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), execute the following processing in the order given: (1) Write to the Interrupt Request Mask Register (IMASK) (2) Perform a read access to the SFR at least once (3) Perform a dumy access to the internal memory, SFR, etc. at least once (4) Enable interrupts (by setting the IE bit to "1") or (1) Write to the Interrupt Request Mask Register (IMASK) (2) Perform a dumy access to the internal memory, SFR, etc. twice or more (3) Issue four or more instructions (Note 1) (4) Enable interrupts (by setting the IE bit to "1") Note 1: Any instructions other than NOP that does not require clock cycles (one that is automatically inserted by the assembler for alignment adjustment: instruction code H'F000). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-6 5 SBI (System Break Interrupt) Control Register (SBICR) b0 0 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.3 SBI (System Break Interrupt) Control Register 1 0 2 0 3 0 4 0 5 0 6 0 b7 SBIREQ 0 b 0–6 7 Bit Name No function assigned. Fix to "0" SBIREQ 0: SBI not requested 1: SBI requested Function R 0 W 0 R(Note 1) SBI request bit Note 1: This bit can only be cleared (see below) The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1," a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0," follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Notes: • Unless this bit is set to "1," do not perform the above clearing operation. • If falling edge is inputted to SBI# pin again, system break is not occured while SBI request bit is set to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-7 5 5.2.4 Interrupt Control Registers RAM Write Monitor Interrupt Control Register (IRAMWRCR) CAN1 Error Interrupt Control Register (ICAN1ERCR) CAN1 Single-Shot Interrupt Control Register (ICAN1SSCR) CAN1 Transmit/Receive Interrupt Control Register (ICAN1TRCR) CAN0 Error Interrupt Control Register (ICAN0ERCR) CAN0 Single-Shot Interrupt Control Register (ICAN0SSCR) CAN0 Transmit/Receive Interrupt Control Register (ICAN0TRCR) DRI Event Detection Interrupt Control Register (IDRIEVCR) DRI Counter Interrupt Control Register (IDRICNTCR) DRI Transfer Interrupt Control Register (IDRITRCR) INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) TML1 Input Interrupt Control Register (ITML1CR) SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TOU1 Output Interrupt Control Register (ITOU1CR) TID1 Output Interrupt Control Register (ITID1CR) RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5–9 Interrupt Control Register (IDMA59CR) TOU0 Output Interrupt Control Register (ITOU0CR) TID0 Output Interrupt Control Register (ITID0CR) A/D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) DMA0–4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 6 (IMJTOCR6) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 0 (IMJTICR0) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 3 (IMJTICR3) MJT Input Interrupt Control Register 4 (IMJTICR4) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-8 5 b0 (b8 0 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 1 9 0 2 10 0 3 11 IREQ 0 4 12 0 5 13 1 6 14 ILEVEL 1 b7 b15) 1 b 0–2 (8–10) 3 (11) IREQ Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request At read 0: Interrupt not requested 1: Interrupt requested 4 (12) 5–7 (13–15) No function assigned. Fix to "0" ILEVEL Interrupt priority level bits 000: Interrupt priority level 0 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) 0 R 0 W R 0 R W Bit Name No function assigned. Fix to "0" Function R 0 W 0 (1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1." This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-9 5 Interrupt request from each internal peripheral I/O Bits 3 or bits 11 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers IREQ Set F/F Interrupt enabled Reset IVECT read IMASK write Data bus Set/clear Clear Bits 5-7 or bits 13-15 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type) Group interrupt request from each internal peripheral I/O Group interrupt Read Data bus Bit 3 or 11 Read-only circuit IREQ Reset IVECT read IMASK write Interrupt enabled Bits 5-7 or bits 13-15 Clear 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type) (2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to "111" to disable or any value "000" through "110" to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") IMASK values at which interrupts are accepted Accepted when IMASK is 1–7 Accepted when IMASK is 2–7 Accepted when IMASK is 3–7 Accepted when IMASK is 4–7 Accepted when IMASK is 5–7 Accepted when IMASK is 6–7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-10 5 INTERRUPT CONTROLLER (ICU) 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.3 Interrupt Request Sources in Internal Peripheral I/O The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial interface, A/D converter, RTD, CAN, DRI and RAM write monitor. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources MJT input interrupt 4 MJT input interrupt 3 MJT input interrupt 2 MJT input interrupt 1 MJT input interrupt 0 MJT output interrupt 7 MJT output interrupt 6 MJT output interrupt 5 MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 MJT output interrupt 0 DMA0–4 interrupt SIO1 receive interrupt SIO1 transmit interrupt SIO0 receive interrupt SIO0 transmit interrupt A/D0 conversion interrupt TID0 output interrupt TOU0 output interrupt DMA5–9 interrupt SIO2,3 transmit/receive interrupt RTD interrupt TID1 output interrupt TOU1 output interrupt SIO4,5 transmit/receive interrupt TML1 input interrupt CAN0 transmit/receive & error interrupt CAN1 transmit/receive & error interrupt DRI transfer interrupt Number of Input Sources MJT input interrupt group 4 (TIN3–TIN6 inputs) 4 MJT input interrupt group 3 (TIN20–TIN27 inputs) 8 MJT input interrupt group 2 (TIN16–TIN19 inputs) 4 MJT input interrupt group 1 (TIN0 input) 1 MJT input interrupt group 0 (TIN7–TIN11 inputs) 5 MJT output interrupt group 7 (TMS0, TMS1 output) 2 MJT output interrupt group 6 (TOP8, TOP9 output) 2 MJT output interrupt group 5 (TOP10 output) 1 MJT output interrupt group 4 (TIO4–TIO7 outputs) 4 MJT output interrupt group 3 (TIO8, TIO9 outputs) 2 MJT output interrupt group 2 (TOP0–TOP5 outputs) 6 MJT output interrupt group 1 (TOP6, TOP7 outputs) 2 MJT output interrupt group 0 (TIO0–TIO3 outputs) 4 DMA0–4 transfer-completed 5 SIO1 reception-completed or receive error interrupt 1 SIO1 transmission-completed or transmit buffer empty interrupt 1 SIO0 reception-completed or receive error interrupt 1 SIO0 transmission-completed or transmit buffer empty interrupt 1 A/D0 conversion (single mode, scan single-shot mode, or 1 cycle 1 of scan continuous mode) completed and comparate-completed TID0 output 1 TOU0_0–TOU0_7 outputs 8 DMA5–9 transfer-completed 5 SIO2,3 reception-completed or receive error interrupt, 4 transmission-completed or transmit buffer empty interrupt RTD interrupt generation command 1 TID1 output 1 TOU1_0–TOU1_7 outputs 8 SIO4,5 reception-completed or receive error interrupt, 4 transmission-completed or transmit buffer empty interrupt TML1 input (TIN30–TIN33 inputs) 4 CAN0 transmission or reception completed, CAN0 bus error, 67 CAN0 error passive, CAN0 bus-off, CAN0 single-shot CAN1 transmission or reception completed, CAN1 bus error, 67 CAN1 error passive, CAN1 bus-off, CAN1 single-shot DRI address counter 0 transfer-completed, 5 DRI address counter 1 transfer-completed, overrun error, latch enable error and DRI transfer counter underflow DEC0–DEC4 underflow 5 DIN0–DIN5 event detected 6 CAN0 transmission-completed, CAN0 reception-completed 32 CAN0 single-shot 32 CAN0 bus error, CAN0 error passive, CAN0 bus off 3 CAN1 transmission-completed, CAN1 reception-completed 32 CAN1 single-shot 32 CAN1 bus error, CAN1 error passive, CAN1 bus off 3 RAM write 16 Contents ICU Type of Input Source ( Note 1) Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized DRI counter interrupt Level-recognized DRI event detection interrupt Level-recognized CAN0 transmit/receive interrupt Level-recognized CAN0 single-shot interrupt Level-recognized CAN0 error interrupt Level-recognized CAN1 transmit/receive interrupt Level-recognized CAN1 single-shot interrupt Level-recognized CAN1 error interrupt Level-recognized RAM write monitor interrupt Level-recognized Note 1: ICU type of input source • Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. • Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held "L." For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-11 5 5.4 ICU Vector Table INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 40-source interrupt requests are assigned the following vector table addresses. The interrupt request sources are also assigned the following hardware fixed priority levels. Table 5.4.1 ICU Vector Table Priority High Interrupt Request Source MJT input interrupt 4 MJT input interrupt 3 MJT input interrupt 2 MJT input interrupt 1 MJT input interrupt 0 MJT output interrupt 7 MJT output interrupt 6 MJT output interrupt 5 MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 MJT output interrupt 0 DMA0–4 interrupt SIO1 receive interrupt SIO1 transmit interrupt SIO0 receive interrupt SIO0 transmit interrupt A/D0 conversion interrupt TID0 output interrupt TOU0 output interrupt DMA5–9 interrupt SIO2,3 transmit/receive interrupt RTD interrupt TID1 output interrupt TOU1 output interrupt SIO4,5 transmit/receive interrupt TML1 input interrupt CAN0 transmit/receive & error interrupt CAN1 transmit/receive & error interrupt DRI transfer interrupt DRI counter interrupt DRI event detection interrupt CAN0 transmit/receive interrupt CAN0 single-shot interrupt CAN0 error interrupt CAN1 transmit/receive interrupt CAN1single-shot interrupt CAN1 error interrupt RAM write monitor interrupt ICU Vector Table Address H'0000 0094 H'0000 0098 H'0000 009C H'0000 00A0 H'0000 00A4 H'0000 00A8 H'0000 00AC H'0000 00B0 H'0000 00B4 H'0000 00B8 H'0000 00BC H'0000 00C0 H'0000 00C4 H'0000 00C8 H'0000 00CC H'0000 00D0 H'0000 00D4 H'0000 00D8 H'0000 00DC H'0000 00E0 H'0000 00E4 H'0000 00E8 H'0000 00EC H'0000 00F0 H'0000 00F4 H'0000 00F8 H'0000 00FC H'0000 0108 H'0000 010C H'0000 0110 H'0000 0114 H'0000 0118 H'0000 011C H'0000 0120 H'0000 0124 H'0000 0128 H'0000 012C H'0000 0130 H'0000 0134 H'0000 0138 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – H'0000 0097 H'0000 009B H'0000 009F H'0000 00A3 H'0000 00A7 H'0000 00AB H'0000 00AF H'0000 00B3 H'0000 00B7 H'0000 00BB H'0000 00BF H'0000 00C3 H'0000 00C7 H'0000 00CB H'0000 00CF H'0000 00D3 H'0000 00D7 H'0000 00DB H'0000 00DF H'0000 00E3 H'0000 00E7 H'0000 00EB H'0000 00EF H'0000 00F3 H'0000 00F7 H'0000 00FB H'0000 00FF H'0000 010B H'0000 010F H'0000 0113 H'0000 0117 H'0000 011B H'0000 011F H'0000 0123 H'0000 0127 H'0000 012B H'0000 012F H'0000 0133 H'0000 0137 H'0000 013B Number of Input Source 4 8 4 1 5 2 2 1 4 2 6 2 4 5 1 1 1 1 1 1 8 5 4 1 1 8 4 4 67 67 5 5 6 32 32 3 32 32 3 16 ICU Type of Input Source (Note 1) Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Low Note 1: ICU type of input source • Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. • Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held "L." For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-12 5 5.5 Description of Interrupt Operation INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests following the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit. 1) Interrupt requested or not Resolve priority according to Interrupt Priority Level (ILEVEL) 2) Resolve priority according to hardware priority 3) Compare with IMASK value Accept interrupt if PSW register IE bit = 1 (ILEVEL settings) TIN3 input interrupt request (MJT input interrupt 4) TIO5 output interrupt request (MJT output interrupt 4) TOP8 output interrupt request (MJT output interrupt 6) SIO0 transmit interrupt request DMA1 interrupt request (DMA0-4 interrupt) A/D0 conversion interrupt request Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Requested Requested Requested Requested Not requested Requested Level 3 Level 3 Hardware fixed priority Level 3 Can be accepted when IMASK = 4-7 Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests Table 5.5.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 IMASK values at which interrupts are accepted Accepted when IMASK is 1–7 Accepted when IMASK is 2–7 Accepted when IMASK is 3–7 Accepted when IMASK is 4–7 Accepted when IMASK is 5–7 Accepted when IMASK is 6–7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 5-13 5 (1) Branching to the interrupt handler INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware: • The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) • The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). • The interrupt request (EI) to the CPU core is dropped. • Internal sequencer of ICC is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware: • The interrupt request (EI) to the CPU core is dropped. • Internal sequencer of ICC is activated to start internal processing (interrupt priority resolution). [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-14 5 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1." Notes: • There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT). For details, see the Section 5.2.1, "Interrupt Vector Register (IVECT)." The precautions apply to the Process [4], therefore, other processes are not required to add. • There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt Request Mask Register (IMASK)." [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the interrupt request currently being processed was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: • Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from Internal Peripheral I/O." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-15 5 EI (External Interrupt) vector entry INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation H'0000 0080 BRA instruction EI (External Interrupt) handler Hardware preprocessing when EIT is accepted (Note 1) Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack [1] Program being executed [2] Interrupt generated Read and save Interrupt Request Mask Register (IMASK) to the stack Read Interrupt Vector Register (IVECT) Read and overwrite Interrupt Request Mask Register (IMASK) H'0080 0004 IMASK [3] H'0080 0000 (Note 2) IVECT [4] (Note 2) [5] [6] [7] Hardware postprocessing when RTE instruction is executed (Note 1) ICU vector table Read ICU vector table H'0000 0094 Set PSW register IE bit to 1 (Note 3) (Note 4) Interrupt handler start address H'0000 013B Branch to the interrupt handler for each internal peripheral I/O Interrupt handler Interrupt handler [8] [9] [10] Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack Restore general-purpose registers from the stack (Note 3) (Note 2) [11] Restore PSW from the stack [1] to [12]: Processing of EI by interrupt handler Restore BPC from the stack [12] RTE Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: To enable multiple interrupts, execute processing in [6] and [9]. Note 4: There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT). For details, see the Section 5.2.1, "Interrupt Vector Register (IVECT)." The precautions apply to the Process [4], therefore, other processes are not required to add. Also, there are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt Request Mask Register (IMASK)." Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-16 5 5.6.1 Acceptance of SBI INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked. If falling edge is inputted to SBI# pin again, system break is not occured while SBI request bit is set to "1." 5.6.2 SBI Processing by Handler When the system break interrupt generated has been serviced, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. SBI (System Break Interrupt) vector entry H'0000 0010 BRA instruction SBI (System Break Interrupt) handler Program being executed Processing to shut down the system (Note 1) SBI generated Shut down or reset the system Note 1: Do not return to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-17 5 INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5-18 CHAPTER 6 INTERNAL MEMORY 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Outline of Internal Memory Internal RAM Internal RAM Protect Function Internal Flash Memory Registers Associated with Internal Flash Memory Programming Internal Flash Memory Virtual Flash Emulation Function Connecting to Serial Programmer (CSIO Mode) Connecting to Serial Programmer (UART Mode) Internal Flash Memory Protect Function Notes on Internal RAM Notes on Internal Flash Memory 6 6.1 Outline of Internal Memory The 32185/32186 internally contain the following types of memory: • 64-Kbyte and 32-Kbyte RAM • 1-Mbyte (1024 Kbytes) and 512-Kbyte flash memories INTERNAL MEMORY 6.1 Outline of Internal Memory 6.2 Internal RAM Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Size Location address Wait insertion Internal bus connection Dual port Specification M32185F4: 32 Kbytes M32186F8: 64 Kbytes M32185F4: H'0080 4000 to H'0080 BFFF M32186F8: H’0080 4000 to H’0081 3FFF Operates with zero wait states Connected by 32-bit bus By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 15, “Real-Time Debugger.”) Note: • Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the RAM is undefined. However when RAM back up mode is used(power for only VDDE is on) RAM retains the value before exiting reset for only RAM back up area. 6.3 Internal RAM Protect Function This function monitors writes to the internal RAM. Writes to the RAM can be disabled in 16-Kbyte units for H'0080 4000 to H'0084 3FFF. If the area where disabled a write is accessed for write, an interrupt can be generated. Note: • The internal resources that are likely to access the internal RAM for write include six modules: CPU, DMA, SDI (tool), NBD, RTD, and DRI. Of these, the RTD and DRI are not subject to the RAM protect function, so that write accesses made to the internal RAM by the RTD or DRI cannot be detected. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-2 6 Table 6.3.1 Definition of the Write Disabled Area Area Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Area 8 Area 9 Area 10 Area 11 Area 12 Area 13 Area 14 Area 15 Target address H'0080 4000 - H'0080 7FFF H'0080 8000 - H'0080 BFFF H'0080 C000 - H'0080 FFFF H'0081 0000 - H'0081 3FFF H'0081 4000 - H'0081 7FFF H'0081 8000 - H'0081 BFFF H'0081 C000 - H'0081 FFFF H'0082 0000 - H'0082 3FFF H'0082 4000 - H'0082 7FFF H'0082 8000 - H'0082 BFFF H'0082 C000 - H'0082 FFFF H'0083 0000 - H'0083 3FFF H'0083 4000 - H'0083 7FFF H'0083 8000 - H'0083 BFFF H'0083 C000 - H'0083 FFFF H'0084 0000 - H'0084 3FFF INTERNAL MEMORY 6.3 Internal RAM Protect Function The diagram below shows the areas in 16-Kbyte units of the internal RAM that can individually be disabled against write by the RAM protect function. M32185F4 M32185F4 Internal RAM 32 KB M32186F8 M32186F8 Internal RAM 64KB External area 224 KB External area 192 KB A register map associated with the internal RAM protect function is shown below. Internal RAM Protect Related Register Map Address b0 H'0080 0530 H'0080 0532 H'0080 0534 H'0080 0536 H'0080 0538 H'0080 053A H'0080 053C (Use inhibited area) +0 address b7 b8 RAM Write Monitor Interrupt Status Register (RAMWRIST) (Use inhibited area) RAM Write Source Status Register (RAMWRFST) (Use inhibited area) RAM Write Disable Control Register (RAMWRCNT) (Use inhibited area) RAM Write Disable Protect Register (RAMWRPROT) +1 address b15 6-4 See pages 6-5 6-6 6-7 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-3 6 RAM Write Monitor Interrupt Status Register (RAMWRIST) b0 0 INTERNAL MEMORY 6.3 Internal RAM Protect Function 9 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 10 0 11 0 12 0 13 0 14 0 b15 0 RAMWRIST0 RAMWRIST1 RAMWRIST2 RAMWRIST3 RAMWRIST4 RAMWRIST5 RAMWRIST6 RAMWRIST7 RAMWRIST8 RAMWRIST9 RAMWRIST10 RAMWRIST11 RAMWRIST12 RAMWRIST13 RAMWRIST14 RAMWRIST15 7 0 1 0 2 0 3 0 4 0 5 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 RAMWRFST0 RAMWRFST1 RAMWRFST2 RAMWRFST3 RAMWRFST4 RAMWRFST5 RAMWRFST6 RAMWRFST7 RAMWRFST8 RAMWRFST9 RAMWRFST10 RAMWRFST11 RAMWRFST12 RAMWRFST13 RAMWRFST14 RAMWRFST15 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name RAMWRCNT0 (Area 0 RAM write disable control bit) RAMWRCNT1 (Area 1 RAM write disable control bit) RAMWRCNT2 (Area 2 RAM write disable control bit) RAMWRCNT3 (Area 3 RAM write disable control bit) RAMWRCNT4 (Area 4 RAM write disable control bit) RAMWRCNT5 (Area 5 RAM write disable control bit) RAMWRCNT6 (Area 6 RAM write disable control bit) RAMWRCNT7 (Area 7 RAM write disable control bit) RAMWRCNT8 (Area 8 RAM write disable control bit) RAMWRCNT9 (Area 9 RAM write disable control bit) RAMWRCNT10 (Area 10 RAM write disable control bit) RAMWRCNT11 (Area 11 RAM write disable control bit) RAMWRCNT12 (Area 12 RAM write disable control bit) RAMWRCNT13 (Area 13 RAM write disable control bit) RAMWRCNT14 (Area 14 RAM write disable control bit) RAMWRCNT15 (Area 15 RAM write disable control bit) Function 0: Enable write to area 0 1: Disable write to area 0 0: Enable write to area 1 1: Disable write to area 1 0: Enable write to area 2 1: Disable write to area 2 0: Enable write to area 3 1: Disable write to area 3 0: Enable write to area 4 1: Disable write to area 4 0: Enable write to area 5 1: Disable write to area 5 0: Enable write to area 6 1: Disable write to area 6 0: Enable write to area 7 1: Disable write to area 7 0: Enable write to area 8 1: Disable write to area 8 0: Enable write to area 9 1: Disable write to area 9 0: Enable write to area 10 1: Disable write to area 10 0: Enable write to area 11 1: Disable write to area 11 0: Enable write to area 12 1: Disable write to area 12 0: Enable write to area 13 1: Disable write to area 13 0: Enable write to area 14 1: Disable write to area 14 0: Enable write to area 15 1: Disable write to area 15 R W R W R W R W R W R W R W R R R R R W W W W W R W R W R W R R W W This register controls accesses for write to the RAM by enabling or disabling the access. Controlled by this register are the accesses made by the CPU, DMA, SDI (tool), and NBD. If one of these modules attempted to access any area for write that is disabled against write, the corresponding RAM write monitor interrupt status is set to "1," with no data actually written to the RAM. Before this register can be rewritten, the RAMWRCNTPRO bit in the RAM Write Disable Protect Register must be "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-6 6 RAM Write Disable Protect Register (RAMWRPROT) b8 0 INTERNAL MEMORY 6.3 Internal RAM Protect Function b 8−13 14 15 Bit Name No function assigned. Fix to "0." RAMWRCNTP RAMWRCNTPRO write control bit RAMWRCNTPRO RAM write disable protect bit 0: Enable write to RAMWRCNTn 1: Disable write to RAMWRCNTn R W Function R 0 0 W 0 W This register controls writes to the RAM Write Disable Control Register by enabling or disabling the write. If a write to the RAM Write Disable Control Register (RAMWRCNT) is attempted when the RAMWRCNTPRO bit = "1," the attempted write is ignored. To set this register, follow the procedure described below. 1. Write a "1" to RAMWRCNTP. 2. Subsequent to 1 above, write a "0" to RAMWRCNTP and a set value ("0" or "1") to RAMWRCNTPRO. Note: • If there are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-7 6 • Example of correct settings INTERNAL MEMORY 6.3 Internal RAM Protect Function RAMWRCNTP "1" If a write cycle to any other area occurs during this interval, the value that was set in the RAMWRCNTPRO bits is not reflected. (Note 1) RAMWRCNTP RAMWRCNTPRO "0" Set value • Cases where settings have no effect (1) RAMWRCNTP "1" Write to other area Because a write cycle to other area exists, the set value is not reflected. (Note 1) RAMWRCNTP RAMWRCNTPRO "0" Set value (2) RAMWRCNTP "1" Because these two consecutive writes comprise a pair, the next set value is not reflected. RAMWRCNTP "1" RAMWRCNTP RAMWRCNTPRO "0" Set value Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, SDI (tool), NBD to any other area. The writing cycle from RTD and DRI are not effected. Figure 6.3.1 RAMWRCNTPRO Setting Procedure 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-8 6 RAM write disable protect (RAMWRCNTPRO) F/F WR WR Data bus b0 b0 Write to area 0 RAMWRIST (H'0080 0530) RAMWRCNT (H'0080 0538) INTERNAL MEMORY 6.3 Internal RAM Protect Function RAMWRCNT0 F/F RAMWRIST0 F/F WR Write to area 1 16-source inputs (Level) RAM write monitor interrupt request b1 b1 RAMWRCNT1 F/F RAMWRIST1 F/F WR Write to area 2 b2 b2 RAMWRCNT2 F/F RAMWRIST2 F/F WR Write to area 3 b3 b3 RAMWRCNT3 F/F RAMWRIST3 F/F WR Write to area 4 b4 b4 RAMWRCNT4 F/F RAMWRIST4 F/F WR Write to area 5 b5 b5 RAMWRCNT5 F/F RAMWRIST5 F/F WR Write to area 6 b6 b6 RAMWRCNT6 F/F RAMWRIST6 F/F WR Write to area 7 b7 b7 RAMWRCNT7 F/F RAMWRIST7 F/F To the next page The remaining 8-source inputs in the next page Figure 6.3.2 Block Diagram of RAM Write Monitor Interrupt Request (1/2) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-9 6 RAMWRIST (H'0080 0530) RAMWRCNT (H'0080 0538) From the previous page Write to area 8 INTERNAL MEMORY 6.3 Internal RAM Protect Function WR Data bus b8 b8 RAMWRCNT8 F/F RAMWRIST8 F/F WR Write to area 9 8-source inputs (Level) To the previous page b9 b9 RAMWRCNT9 F/F RAMWRIST9 F/F WR Write to area 10 b10 b10 RAMWRCNT10 F/F RAMWRIST10 F/F WR Write to area 11 b11 b11 RAMWRCNT11 F/F RAMWRIST11 F/F WR Write to area 12 b12 b12 RAMWRCNT12 F/F RAMWRIST12 F/F WR Write to area 13 b13 b13 RAMWRCNT13 F/F RAMWRIST13 F/F WR Write to area 14 b14 b14 RAMWRCNT14 F/F RAMWRIST14 F/F WR Write to area 15 b15 b15 RAMWRCNT15 F/F RAMWRIST15 F/F Figure 6.3.3 Block Diagram of RAM Write Monitor Interrupt Request (2/2) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-10 6 6.4 Internal Flash Memory Specifications of the internal flash memory are shown below. Table 6.4.1 Specifications of the Internal Flash Memory Item Size Location address Wait insertion Durability Internal bus connection Other Specification M32185F4: 512 Kbytes M32186F8: 1 Mbyte (1024 Kbytes) M32185F4: H'0000 0000 to H'0007 FFFF M32186F8: H’0000 0000 to H’000F FFFF Operates with one wait state Standard product : 100 times INTERNAL MEMORY 6.4 Internal Flash Memory Instruction access: Connected by 64-bit bus (32-bit: Transfer rate equivalent to zero-wait states achieved) Data access: Connected by 32-bit bus Virtual flash emulation function (See Section 6.7, “Virtual Flash Emulation function.”) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-11 6 Internal flash memory area of the M32185F4 (512 Kbytes) H'0000 0000 H'0000 1FFF H'0000 2000 H'0000 2FFF H'0000 3000 H'0000 3FFF INTERNAL MEMORY 6.4 Internal Flash Memory 8KB 4KB 4KB 16KB 32KB Block 0 Block 1 Block 2 Block 3 Unequal blocks H'0000 4000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 64KB H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF H'0004 0000 64KB H'0004 FFFF H'0005 0000 64KB H'0005 FFFF H'0006 0000 64KB H'0006 FFFF H'0007 0000 64KB H'0007 FFFF Block 4 Block 5 Block 6 Block 7 Block 8 Equal blocks Block 9 Block 10 Block 11 Figure 6.4.1 Block Configuration of the Internal Flash Memory for the M32185F4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-12 6 Internal flash memory area of the M32186F8 (1024 Kbytes) H'0000 0000 H'0000 1FFF H'0000 2000 H'0000 2FFF H'0000 3000 H'0000 3FFF INTERNAL MEMORY 6.4 Internal Flash Memory 8KB 4KB 4KB 16KB 32KB Block 0 Block 1 Block 2 Block 3 Unequal blocks H'0000 4000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 64KB H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF H'0004 0000 64KB H'0004 FFFF H'0005 0000 64KB H'0005 FFFF H'0006 0000 64KB H'0006 FFFF H'0007 0000 64KB H'0007 FFFF H'0008 0000 64KB H'0008 FFFF H'0009 0000 64KB H'0009 FFFF H'000A 0000 64KB H'000A FFFF H'000B 0000 64KB H'000B FFFF H'000C 0000 64KB H'000C FFFF H'000D 0000 64KB H'000D FFFF H'000E 0000 64KB H'000E FFFF H'000F 0000 64KB H'000F FFFF Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Equal blocks Block 10 Block 11 Block 12 Block 13 Block 14 Block 15 Block 16 Block 17 Block 18 Block 19 Figure 6.4.2 Block Configuration of the Internal Flash Memory for the M32186F8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-13 6 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 6.5 Registers Associated with Internal Flash Memory A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address b0 H'0080 01E0 H'0080 01E2 H'0080 01E4 Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) +0 address b7 b8 Flash Status Register (FSTAT) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) +1 address b15 6-15 6-16 6-17 6-18 6-19 6-22 See pages | H'0080 07E8 H'0080 07EA H'0080 07EC H'0080 07EE H'0080 07F0 H'0080 07F2 H'0080 07F4 H'0080 07F6 Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash L Bank Register 1 (FELBANK1) Virtual Flash L Bank Register 2 (FELBANK2) Virtual Flash L Bank Register 3 (FELBANK3) Virtual Flash L Bank Register 4 (Note 1) (FELBANK4) Virtual Flash L Bank Register 5 (Note 1) (FELBANK5) Virtual Flash L Bank Register 6 (Note 1) (FELBANK6) Virtual Flash L Bank Register 7 (Note 1) (FELBANK7) Note 1: This area exists only in the 32186 and it is use prohibitation area in the 32185. 6-24 6-24 6-24 6-24 6-24 6-24 6-24 6-24 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-14 6 6.5.1 Flash Mode Register Flash Mode Register (FMOD) b0 0 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 3 FAENS 1 1 0 2 0 4 0 5 0 6 0 b7 FPMOD ? b 0–2 3 4–6 7 Bit Name No function assigned. Fix to "0." FAENS Flash access enable status bit No function assigned. Fix to "0." FPMOD External FP pin status bit 0: FP pin = "L" 1: FP pin = "H" 0: Flash access disabled 1: Flash access enabled 0 R 0 – Function R 0 R W 0 – (1) FAENS (Flash Access Enable Status) bit (Bit 3) The FAENS bit shows whether access to the flash memory is enabled or disabled. When the flash memory is reset by the FRESET bit in Flash Control Register 4 (FCNT4) or accessed for programming/erasure, this bit is cleared to "0," resulting in the flash memory being disabled against access. When the flash memory becomes ready for access, this bit is set to "1." However, it requires up to 30 µs for FAENS bit to be "1" from "0" after exiting Flash reset by FRESET bit or executing programming and erasing operation for Flash memory. (2) FPMOD (External FP Pin Status) bit (Bit 7) The FPMOD is a status bit which indicates the FP (Flash Protect) pin status. The internal flash memory is enabled for programming or erase operation only when FPMOD = "1," and is protected against programming or erase operation when FPMOD = "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-15 6 6.5.2 Flash Status Register Flash Status Register (FSTAT) b8 FBUSY 1 0 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 11 12 0 9 10 ERASE 0 13 FESQ1 0 14 FESQ2 0 b15 0 WRERR 0 b 8 9 10 11 12 13 14 15 Bit Name FBUSY Flash busy bit No function assigned. Fix to "0." ERASE Erase status confirmation bit WRERR Write status confirmation bit No function assigned. Fix to "0." FESQ1 Reserved bit FESQ2 Reserved bit No function assigned. Fix to "0." 0 0 ? – 0: Erase normally operating or terminated 1: Erase error occurred 0: Programming normally operating or terminated 1: Programming error occurred 0 ? 0 – R – Function 0: Being programmed or erased 1: Ready state 0 R 0 – R R W – Flash Status Register (FSTAT) consists of the following status bits that indicate the operation condition of the flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the flash memory is finished when it is being programmed or erased. When FBUSY = "0," it means that the programming or erase operation is being executed; when FBUSY = "1," the operation is finished. Note: • Except when programming/erase processing on the flash memory is forcibly terminated, do not manipulate the FRESET bit in Flash Control Register 4 (FCNT4) while the FBUSY bit = "0" (programming/erasure in progress). (2) ERASE (Erase Status Confirmation) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erase operation performed on the flash memory resulted in an error. When ERASE = "0," it means that the erase operation terminated normally; when ERASE = "1," the erase operation terminated in an error. This bit is set to "1" (Erase error occurred) in the following cases: • An invalid command is issued • The operation is not executed under normal erase conditions (power voltage, temperature) • Protect function by lock bit attempts to erase the valid area • Erase operation is not available because of the internal flash memory failure (3) WRERR (Write Status Confirmation) bit (Bit 11) The WRERR bit is used to determine after completion of processing whether the programming operation performed on the flash memory resulted in an error. When WRERR = "0," it means that the programming operation terminated normally; when WRERR = "1," the programming operation terminated in an error. This bit is set to "1" (Programming error occurred) in the following cases: • An invalid command is issued • The operation is not executed under normal programming conditions (power voltage, temperature) • Protect function by lock bit attempts to write to the valid area • Write operation is not available because of the internal flash memory failure 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-16 6 6.5.3 Flash Control Registers Flash Control Register 1 (FCNT1) b0 0 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 4 0 1 0 2 0 3 FENTRY 0 5 0 6 0 b7 FEMMOD 0 b 0–2 3 4–6 7 Bit Name No function assigned. Fix to "0." FENTRY Flash E/W enable mode entry bit No function assigned. Fix to "0." FEMMOD Virtual flash emulation mode bit 0: Normal mode 1: Virtual flash emulation mode 0: Normal read 1: Program/erase enable 0 R 0 W Function R 0 R W 0 W Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash E/W Enable Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1." To set the FENTRY bit to "1," write "0" and then "1" to the FENTRY bit in succession while the FP pin = "H." To clear the FENTRY bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready), issue Read Array comands (or Flash memory reset by FRESET bit),make sure that FAENS bit ="1," and then write "0" to the FENTRY bit. However, when Flash memory is not reset by FRESET bit, it is not required to check the FAENS bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT FBUSY bit = "0"). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a "L" level signal to the FP pin 3) Entering a "L" level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0," the EI vector entry is located at the address H’0000 0080 of the internal flash memory. When running the flash write/ erase program in the RAM while the FENTRY bit = "1," the EI vector entry is located at the address H’0080 4000 of the RAM, allowing the flash programming/erase operation to be controlled using interrupts. Table 6.5.1 Changes of the EI Vector Entry by FENTRY FENTRY 0 1 EI Vector Entry Internal flash memory area Internal RAM area Address H'0000 0080 H'0080 4000 (2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0." (For details, see Section 6.7, “Virtual Flash Emulation Function.”) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-17 6 Flash Control Register 2 (FCNT2) b8 0 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 12 0 9 0 10 0 11 FLOCKS 0 13 0 14 0 b15 FPROT 0 b 8–10 11 12–14 15 Bit Name No function assigned. Fix to "0." FLOCKS Lock bit read mode select bit No function assigned. Fix to "0." FPROT Lock bit protect control bit 0: Protection by lock bit effective 1: Protection by lock bit invalidated 0: Memory area read mode 1: Register read mode 0 0 Function R 0 W 0 R(Note 1) R(Note 1) Note 1: It can be accessed for write only during the Flash E/W entry mode (FENTRY bit = "1"). (1) FLOCKS (Lock Bit Read Mode Select) bit (Bit 11) The FLOCKS bit is used to select a method for reading out the lock bit status. When the FLOCKS bit = "0," the internal flash memory is placed in memory area read mode, so that it is possible to inspect the lock bit status by issuing command data H’7171 to any address of the flash memory and then reading the last even address of the target block. When the FLOCKS bit = "1," the internal flash memory is placed in register read mode, so that it is possible to inspect the lock bit status by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1," by reading the FLOCKST bit in Flash Control Register 4. The FLOCKS bit can only be accessed for write when the FENTRY bit = "1." If one of the following operations is attempted, the FLOCKS bit is cleared to "0." 1) Writing "0" to the FLOCKS bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin (2) FPROT (Lock Bit Protect Control) bit (Bit 15) The FPROT bit controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1," so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1," write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1." To clear the FPROT bit to "0," write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0." 1) Writing "0" to the FPROT bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-18 6 FENTRY = 1 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory NO YES FENTRY = 1 FPROT = 0 FPROT = 0 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPROT = 1 Figure 6.5.1 Protection Unlocking Flow Flash Control Register 3 (FCNT3) b0 0 FPROT = 1 4 0 1 0 2 0 3 FBSYCK 1 5 0 6 0 b7 FPBSYCK 1 b 0–2 3 4–6 7 Bit Name No function assigned. Fix to "0." FBSYCK Busy check bit No function assigned. Fix to "0." FPBSYCK Prebusy check bit 0: Command accepted normally 1: Command not accepted normally 0: Command accepted normally 1: Command not accepted normally Function R 0 R 0 R W 0 – 0 – Flash Control Register 3 (FCNT3) is used when developing an internal flash memory write/erase program to check whether commands have been accepted normally. This register does not need to be used for a program that has been verified to be able to operate properly. (1) FBSYCK (Busy Check) bit (Bit 3) The FBSYCK bit is used to check whether the command of two or more cycles (confirmation command H'D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted normally. Commands of two or more cycles are shown in Table 6.5.2. If the FBSYCK bit is found to be "0" after issuing the busy check target command (See Table 6.5.2), it means that the busy check target command has been accepted normally. Conversely, if the FBSYCK bit is found to be "1," it means that the busy check target command has not been accepted normally. In addition to the above, the FBSYCK bit is set to "1" in the following cases: 1) When a prebusy check target command has been accepted 2) When the FRESET bit = "1" 3) When input on RESET# pin is pulled "L" 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-19 6 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory (2) FPBSYCK (Prebusy Check) bit (Bit 7) The FPBSYCK bit is used to check whether the command of two or more cycles (confirmation command H'D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted normally. If the FPBSYCK bit is found to be "0" after issuing the prebusy check target command (See Table 6.5.2), it means that the prebusy check target command has been accepted normally. Conversely, if the FPBSYCK bit is found to be "1," it means that the prebusy check target command has not been accepted normally. In addition to the above, the FPBSYCK bit is set to "1" in the following cases: 1) When in a ready state (FBUSY bit = "H" after a prebusy check target command has been accepted) 2) When the Clear Status Register command is issued 3) When the FRESET bit = "1" 4) When input on RESET# pin is pulled "L" Table 6.5.2 Prebusy, Busy Check Target Comand Lock bit Program Write H'7777 (Lock bit program command) Block Erase Write H'2020 (Note 1) (Block erase command) (Note 1) Read Lock bit Status (during Register read mode) Write H'7171 (Read lock bit status command) (Note 1) 4 Halfword Program Write H'4343 (4 halfword program command) Write halfword data _ Write H'D0D0 Write H'D0D0 Write H'D0D0 (Note 2) (Note 2) (Note 2) (Confirmation command) (Confirmation command) (Confirmation command) _ _ _ _ _ _ _ Write halfword data _ _ _ _ _ _ _ Write halfword data (Note 1) _ _ _ _ _ _ Write halfword data (Note 2) Note 1: Prebusy check target command Note 2: Busy check target command 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-20 6 START INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory Write a prebusy check target command (Note 1) FPBSYCK = "0" YES NO Write a busy check target command (Note 1) Operation starts 1 µs wait (by hardware timer or software timer) (Note 2) NO FBSYCK = "0" YES NO FBUSY = "1" YES NO TIME OUT ? YES Confirm execution result (Note 3) Forcibly terminate Write a clear status command, H'5050 END Note 1: Refer to Table 6.5.2 for prebusy check target command and busy check target command. Note 2: It is not required during read lock bit status command (during register read command). Note 3: Confirm by ERASE bit of the FSTAT register, WRERR bit, or FLOCKST bit of the FCNT4 register depending on the respective commands. Figure 6.5.2 Method to Confirm the Command Acceptance by Checking FCNT3 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-21 6 Flash Control Register 4 (FCNT4) b8 0 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 12 0 9 0 10 0 11 FLOCKST 0 13 0 14 0 b15 FRESET 0 b 8–10 11 12–14 15 Bit Name No function assigned. Fix to "0." FLOCKST Lock bit status bit No function assigned. Fix to "0." FRESET Flash reset bit 0: No operation 1: Reset 0: Protected 1: Unprotected 0 R 0 W Function R 0 W 0 (Note1) – Note1: Under setting FLOCKS bit of the flash control register 2 as "1" (register read mode), only the reading out value becomes effective after issuing read rock bit status command . The reading out value is undefined after issuing that read rock bit status command under setting FLOCKS bit as "0"(memory area read mode) and that other internal flash control command. (1) FLOCKST (Lock Bit Status) bit (Bit 11) The FLOCKST bit is used to read the lock bit status. If the FLOCKST bit = "0," it means that the relevant memory block is protected. If the FLOCKST bit = "1," it means that the relevant memory block is not protected. Confirmation of the lock bit status by the FLOCKST bit is possible when the FLOCKS bit = "1." In this case, the lock bit status can be checked by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1," by reading the FLOCKST bit. (2) FRESET (Flash Reset) bit (Bit 15) The FRESET bit controls forcible termination of the internal flash memory programming/erase operation, initialization (to H’80) of each status bit in the Flash Status Register (FSTAT), and initialization of the FPBSYCK bit in Flash Control Register 3 (FCNT3). Setting the FRESET bit to "1" forcibly terminates programming/erase operation and initializes each status bit in the FSTAT (to H’80) and the FPBSYCK bit in FCNT3. Make sure FRESET is held high (= "1") for at least 10 µs during a flash reset. After a flash reset, the internal flash memory is disabled against access until the FAENS bit is set to "1." The FRESET bit is effective only when the FENTRY bit = "1." Unless the FENTRY bit = "1," settings made to the FRESET bit are ignored. Make sure the FRESET bit = "0" while programming or erasing the flash memory. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-22 6 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory FENTRY = 0 FENTRY = 1 Program/erase the flash memory Error found YES FRESET = 1 NO Programming/erase operation terminated normally 10µs wait (by hardware timer or software timer) FRESET = 0 NO FMOD register FAENS = 1? YES Program/erase the flash memory Figure 6.5.3 Example 1 of FRESET Bit (Initializing Flash Status Register 2) Flash programming/erase operation has timed out Forcibly terminate FRESET = 1 10µs wait (by hardware timer or software timer) FRESET = 0 NO FMOD register FAENS = 1? YES Figure 6.5.4 Example 2 of FRESET Bit (Forcibly Terminating Programming/Erasing Operation) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-23 6 INTERNAL MEMORY 6.5 Registers Associated with Internal Flash Memory 6.5.4 Virtual Flash L Bank Registers Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash L Bank Register 1 (FELBANK1) Virtual Flash L Bank Register 2 (FELBANK2) Virtual Flash L Bank Register 3 (FELBANK3) Virtual Flash L Bank Register 4 (FELBANK4) (Note 2) Virtual Flash L Bank Register 5 (FELBANK5) (Note 2) Virtual Flash L Bank Register 6 (FELBANK6) (Note 2) Virtual Flash L Bank Register 7 (FELBANK7) (Note 2) b0 MOD ENL 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 LBANKAD 0 b 0 1–6 7–14 15 Bit Name MODENL Virtual flash emulation L enable bit No function assigned. Fix to "0." LBANKAD L bank address bit (Note 1) No function assigned. Fix to "0." 0 0 Start address A11–A18 of the relevant L bank Function 0: Disable virtual flash emulation function 1: Enable virtual flash emulation function 0 R 0 W R R W W Note 1: Because the internal flash memory of the M32186F8 is 1M (1,024K) bytes, the address b7 (A11) must always be set to "0." Also, because the initial flash memory of the M32185F4 is 512 Kbytes, the address b7 (A11) and b8 (A12) must always be set to "0." Note 2: This area exists only in the 32186 and it is use prohibitation area in the 32185. Note: • These registers must always be accessed in halfwords. (1) MODENL (Virtual Flash Emulation L Enable) bit (Bit 0) The MODENL bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the L bank area selected by the LBANKAD bits. (2) LBANKAD (L Bank Address) bits (Bits 7–14) The LBANKAD bits are provided for selecting one of the L banks that are separated every 8 Kbytes. Use these LBANKAD bits to set the eight bits A11–A18 of the 32-bit start address of the desired L bank. Note: • For details, see Section 6.7, “Virtual Flash Emulation Function.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-24 6 6.6 Programming Internal Flash Memory INTERNAL MEMORY 6.6 Programming Internal Flash Memory 6.6.1 Outline of Internal Flash Memory Programming To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "H," MOD0 = "H" and MOD1 = "L" to enter boot mode. In this case, the CPU starts running the boot program upon exiting the reset state. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the internal RAM and use the internal RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "H," MOD0 = "L" and MOD1 = "L" to enter single-chip mode. Transfer the flash write/erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the internal RAM and use the program transferred into the internal RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "H," MOD0 = "L" and MOD1 = "H." During flash E/W enable mode (FP pin = "H," FENTRY = "1"), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H’0080 4000) of the internal RAM. During normal mode (except for Flash E/W enable mode), it is located in the flash area (H’0000 0080). To use an external interrupt (EI) in flash E/W enable mode, write at the beginning of the internal RAM an instruction for branching to the external interrupt (EI) handler that has been transferred into the internal RAM. Furthermore, because the IVECT register which is read out in the external interrupt (EI) handler has stored in it the flash memory address of the ICU vector table, make sure the ICU vector table to be used during flash E/W enable mode is prepared in the internal RAM so that the value of the IVECT register will be converted into the internal RAM address of the ICU vector table (for example, by adding an offset) before performing branch processing. When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/ Erase program" is transferd to internal RAM. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-25 6 Flash E/W enable mode (FENTRY = 1) INTERNAL MEMORY 6.6 Programming Internal Flash Memory Normal mode (FENTRY = 0) H'0000 0000 Internal ROM area H'0000 0000 Internal ROM area EI vector entry (H'0000 0080) H'0080 3FFF H'0080 4000 Internal RAM EI vector entry (H'0080 4000) H'0080 3FFF H'0080 4000 Internal RAM H'00FF FFFF H'00FF FFFF Figure 6.6.1 EI Vector Entry during Flash E/W Enable Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-26 6 INTERNAL MEMORY 6.6 Programming Internal Flash Memory (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use SIO1 of serial interface in clock-synchronous serial interface or clock-asynchronous serial interface mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below. FP = L or H MOD1 = L MOD0 = L RESET# = L • Initial state (Flash write/erase program nonexistent in the internal flash memory) Internal RAM CPU Internal Flash memory Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU FP = H MOD1 = L • Set the FP pin "H," MOD0 pin "H" and MOD1 pin "L" to MOD0 = H RESET# = H place the flash memory in boot mode + flash E/W enable mode. • Deassert reset signal and start up with the boot program. • Transfer the flash write/erase program into the internal RAM. • Jump to the flash write/erase program in the internal RAM. CPU Internal RAM Flash write/ erase program Internal Flash memory Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU FP = H MOD1 = L Internal RAM Flash write/ erase program • Using the flash write/erase program in the RAM, MOD0 = H RESET# = H set Flash Control Register 1 (FCNT1) FENTRY bit to 1. • Program or erase the internal flash memory using the flash write/erase program. • When finished, set the MOD0 "L" and jump to the internal flash memory or apply a reset to enter normal mode. CPU Internal Flash memory Flash write data Boot program SIO1 M32R/ECU Write data External device (e.g., flash programmer) Note 1: When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/ Erase program" is transferd to internal RAM. Figure 6.6.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-27 6 POWER ON Mode selected INTERNAL MEMORY 6.6 Programming Internal Flash Memory Reset signal deasserted (Boot program starts) Reset signal deasserted Mode selected RESET# pin MOD0 pin MOD1 pin FP pin Settings by the boot program FENTRY bit Flash programming/erasing by the boot program Figure 6.6.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-28 6 INTERNAL MEMORY 6.6 Programming Internal Flash Memory (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial interface and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using SIO0 in single-chip mode. FP = L or H MOD1 = L MOD0 = L • Initial state (Flash write/erase program existing in the internal flash memory) • An ordinary program in the internal flash memory is being executed. Internal RAM CPU Flash write/ erase program SIO0 Write data External device M32R/ECU FP = H MOD1 = L MOD0 = L Internal RAM Flash write/ erase program CPU • Set the FP pin "H," MOD1 pin "L" and MOD0 pin "L" to place the flash memory in single-chip + flash E/W enable mode. • After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the internal RAM. • Jump to the flash write/erase program in the internal RAM. Internal Flash memory SIO0 Write data External device M32R/ECU FP = H MOD1 = L MOD0 = L Internal RAM Flash write/ erase program • Using the flash write/erase program in the internal RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. • Program or erase the internal flash memory using the flash write/erase program in the internal RAM. • When finished, jump to the program in the internal flash memory or apply a reset to enter normal mode. CPU Internal Flash memory Flash write data SIO0 Write data External device M32R/ECU Figure 6.6.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-29 6 INTERNAL MEMORY 6.6 Programming Internal Flash Memory Flash rewrite Flash mode turned on starts Flash mode turned off RESET# pin "H" or "L" MOD0 pin "L" MOD1 pin "H" or "L" (single-chip or external extension) FP pin "H" or "L" FENTRY bit Flash programming/erasing by the flash write/erase program Flash write/erase program transferred into the RAM Figure 6.6.5 Internal Flash Memory Write/Erase Control Pin Timing (when the flash write/erase program already exists in it) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-30 6 INTERNAL MEMORY 6.6 Programming Internal Flash Memory 6.6.2 Controlling Operation Modes during Flash Programming The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.6.1 Operation Modes Set during Flash Programming/Erase FP 0 1 0 MOD0 MOD1 FENTRY (Note 1) Operation Mode 0 0 1 0 0 0 0 0 0 Processor mode Single-chip mode Reset Vector Entry Start address of internal flash memory (H'0000 0000) Start address of external area (H'0000 0000) 0 1 1 0 0 0 1 1 0 0 0 1 External extension mode Single-chip mode + flash E/W enable 1 1 1 1 1 0 0 0 1 0 1 1 Boot mode Boot mode + flash E/W enable External extension mode + flash E/W enable – 1 1 – Setting inhibited Start address of internal flash memory (H'0000 0000) Start address of internal flash memory (H'0000 0000) Boot program startup address Boot program startup address Start address of internal flash memory (H'0000 0000) – – Flash area (H'0000 0080) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) (H'0000 0080) Flash area (H'0000 0080) External area EI Vector Entry Flash area (H'0000 0080) Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don’t care”). However, if FP = "0," writing "1" to FENTRY only results in it cleared to "0." Note: • Always make sure the MOD2 pin is connected low (= 0) to ground (GND). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-31 6 (1) Flash E/W enable mode INTERNAL MEMORY 6.6 Programming Internal Flash Memory Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the necessary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the internal RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "H" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operating in processor mode or the FP pin = "L." (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels ("H" or "L") can be known by checking the P8 Data Register (Port Data Register, H’0080 0708) MOD0DT and MOD1DT bits. P8 Data Register (P8DATA) b0 ? 4 P84DT ? 1 ? 2 ? 3 P83DT ? 5 P85DT ? 6 P86DT ? b7 P87DT ? MOD0DT MOD1DT P82DT b 0 1 2 3 4 5 6 7 Bit Name MOD0DT (P80DT) MOD0 data bit MOD1DT (P81DT) MOD1 data bit P82DT Port P82 data bit P83DT Port P83 data bit P84DT Port P84 data bit P85DT Port P85 data bit P86DT Port P86 data bit P87DT Port P87 data bit Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Function 0: MOD0 pin = "L" 1: MOD0 pin = "H" 0: MOD1 pin = "L" 1: MOD1 pin = "H" At read Depends on how the Port Direction Register is set • If direction bit = "0" (input mode) 0: Port input pin = "L" 1: Port input pin = "H" • If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "L" 1: Port output latch = "1" / Port pin level = "H" At write Write to the port output latch R W R – R R W – 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-32 6 START INTERNAL MEMORY 6.6 Programming Internal Flash Memory Enter one of the following modes: • Single-chip mode • Boot mode • External extension mode Check MOD0/1 and FP pin levels(Note 2) OK NO END Transfer the flash write/erase program into the internal RAM Set the Flash Control Register in SFR area (FCNT1) FENTRY bit to 0 Switched to the flash write/erase program Set the Flash Control Register in SFR area (FCNT1) FENTRY bit to 1 Go to flash E/W enable mode Wait for 1 µs (using a hardware or software timer) Execute flash write/erase command and various read commands (Note 1) Jump to the flash memory or apply reset Switched to normal mode END Note 1: For details about each command, see Section 6.6.3, "Procedure for Programming/Erasing the Internal Flash Memory." Note 2: Checked by FPMOD bit in FMOD register and MOD0DT and MOD1DT bits in P8DATA register Figure 6.6.6 Procedure for Entering Flash E/W Enable Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-33 6 START INTERNAL MEMORY 6.6 Programming Internal Flash Memory Execute flash write/erase command and various read commands FBUSY bit = 1 (Note 1) YES NO Execute read array command or reset flash memory with the FRESET bit in Flash Control Register 4 (FCNT4) FAENS bit = 1 (Note 2) YES NO Set the FENTRY bit of the Flash Control Register 1 (FCNT1) to 0 Switched to normal mode Wait for more than 8 CPUCLK cycles (Note 3) Jump to the flash memory or apply reset END Note 1: If it is checked that the value of FBUSY bit in Flash Status Register (FSTAT) is "1" after executing the command in flash E/W enable mode, it is not necessary to check that the value of FBUSY bit is "1." Note 2: If flash memory reset by FRESET bit in Flash Control Register 4 (FCNT4) is not executed, it is not necessary to check that the value of FAENS bit in Flash Mode Register (FMOD) is "1." Note 3: Insert any instructions for more than 8 CPUCLK waits other than NOP that do not require clock cycles (one that is automatically inserted by the assembler for alignment adjustment: instruction code H'F000). As the EI vector entry address is exchanged in the instructions for 8 CPUCLK waits, disenable the External Interrupt (EI). Note: • When switching to normal mode by entering a "L" level signal to the RESET# pin in flash E/W enable mode, enter the signal to the RESET# pin after checking that the value of FBUSY bit is "1"(ready). Figure 6.6.7 Procedure for Entering Normal Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-34 6 INTERNAL MEMORY 6.6 Programming Internal Flash Memory 6.6.3 Procedure for Programming/Erasing Internal Flash Memory To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. Once flash E/W enable mode is entered into, only flash command and no other commands can be used to access the internal flash memory. To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note: • During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.6.2 Commands in Flash E/W Enable Mode Command Name Read Array command 4 Halfword Program command Lock Bit Program command Block Erase command Clear Status Register command Read Lock Bit Status command Verify command (Note 1) Issued Command Data H'FFFF H'4343 H'7777 H'2020 H'5050 H'7171 H'D0D0 Note 1: This command must be issued immediately after the Lock Bit Program, Block Erase or Read Lock Bit Status command. If the Lock Bit Program, Block Erase or Read Lock Bit Status command is followed by other than the Verify (H'D0D0) command, the Lock Bit Program, Block Erase or Read Lock Bit Status command is not executed normally and terminated in error. (1) Read Array command Writing the Read Array command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. START Write the Read Array command (H'FFFF) to any address of the internal flash memory Read the desired flash memory address NO Final Address? YES END Figure 6.6.8 Read Array 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-35 6 (2) 4 Halfword Program command INTERNAL MEMORY 6.6 Programming Internal Flash Memory This command performs write (programming) to the flash memory by 2 bytes(halfword) x every 4 times of 4 halfwords (8 bytes unit). And the initial address when writing is 4 halfwords boundary (the lower address B'000). To program the flash memory, write the Program command (H’4343) to any address of the internal flash memory and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the 4 Halfword Program command. 4 halfword programming is automatically performed by the internal control circuit, and whether the 4 Halfword Program command has finished can be known by checking the Flash Status Register (FSTAT) FBUSY (Flash busy) bit. While the FBUSY bit = "0," the next programming cannot be performed. START Write the 4 Halfword Program command (H'4343) to any address of the internal flash memory Write the program data (2 bytes x 4) to the internal flash memory address to be programmed Internal flash memory is programmed by 4 Halfword Program Wait for 1 µs (using a hardware or software timer) NO FBUSY bit = 1 YES Confirm the result of execution of the programming process (Note 1) TIME OUT? 1600 µs (Note 2) YES NO To next 4 halfword Forcibly terminated NO Last address? YES END Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is a timeout period for 4-Kbyte block. The timeout period for other than 4 Kbytes is 800 µs. Figure 6.6.9 4 Halfword Program 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-36 6 (3) Lock Bit Program command INTERNAL MEMORY 6.6 Programming Internal Flash Memory The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT (Rock bit protect control) bit to invalidate protection by a lock bit and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Lock bit programming is automatically performed by the internal control circuit, and whether the Lock Bit Program command has finished can be known by checking the Flash Status Register (FSTAT) FBUSY (Flash busy) bit. While the FBUSY bit = "0," the next programming cannot be performed. The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command data. Table 6.6.3 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Specified Address H'0000 1FFE H'0000 2FFE H'0000 3FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE H'000A FFFE H'000B FFFE H'000C FFFE H'000D FFFE H'000E FFFE H'000F FFFE Note: • Block 12 to block 19 exist only in the 32186 and do not exist in the 32185. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-37 6 START INTERNAL MEMORY 6.6 Programming Internal Flash Memory Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Lock bit is programmed by Lock Bit Program Wait for 1 µs (using a hardware or software timer) NO FBUSY bit = 1 YES TIME OUT? NO 1600 µs (Note 2) Confirm the result of execution of the programming process (Note 1) YES Forcibly terminated END Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is a timeout period for 4-Kbyte block. The timeout period for other than 4 Kbytes is 800 µs. Figure 6.6.10 Lock Bit Program 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-38 6 (4) Block Erase command INTERNAL MEMORY 6.6 Programming Internal Flash Memory The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the command data (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Table 6.6.3, “Target Blocks and Specified Addresses”). The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking the Flash Status Register (FSTAT) FBUSY (Flash busy) bit. While the FBUSY bit = "0," the next block erase operation cannot be performed. START Write the Block Erase command (H'2020) to any address of the internal flash memory Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased Internal flash memory contents are erased by the Block Erase command Wait for 1 µs (using a hardware or software timer) NO FBUSY bit = 1 YES TIME OUT? 6s Confirm the result of execution of the erase process (Note 1) YES NO Forcibly terminated END Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Figure 6.6.11 Block Erase 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-39 6 (5) Clear Status Register command INTERNAL MEMORY 6.6 Programming Internal Flash Memory The Clear Status Register command clears the Flash Status Register (FSTAT) ERASE (erase status), and WRERR (write status) bits to "0." Write the command data (H’5050) to any address of the internal flash memory, and Flash Status Register is thereby initialized. Also, issue the Clear Status Register command, and Flash Status Register 3 (FCNT3) is initialized. If an error occurs when programming or erasing the flash memory and the Flash Status Register (FSTAT) ERASE (erase status) or WRERR (write status) bit is set to "1," the next programming or erase operation cannot be executed unless each status bit is cleared to "0." START Write the Clear Status Register command (H'5050) to any address of the internal flash memory END Figure 6.6.12 Clear Status Register 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-40 6 (6) Read Lock Bit Status command INTERNAL MEMORY 6.6 Programming Internal Flash Memory The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. The method for reading lock bit can be chosen from the following depends on the setting for Flash Control Register 2 (FCNT2) FLOCKS (Lock bit read mode select) bit. 1) Memory area read mode (FLOCKS bit = 0) Write the command data (H’7171) to any address of the internal flash memory. Next, read the last even address of the flash memory block to be checked (see Table 6.6.3, “Target Blocks and Specified Addresses”), and the read data shows whether the target block is protected. If the FLBST (lock bit) in the read data is "0," it means that the target memory block is protected. If the FLBST (lock bit) is "1," it means that the target memory block is not protected. Lock Bit Status Register (FLBST) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 FLBST 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? ? b 0–8 9 10–15 Bit Name No function assigned. FLBST Lock bit No function assigned. 0: Protected 1: Not protected Function R ? R ? W 0 – 0 The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. To read this register, Flash Control Register 2 (FCNT2) FLOCKS bit must be set to "0." START Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory Read the last even address of the flash memory block to be checked END Figure 6.6.13 Read Lock Bit Status (Memory Area Read Mode) 2) Register read mode (FLOCKS bit = 1) Write the command data (H’7171) to any address of the target block. Next, write the verify command data (H'D0D0), and the Flash Control Register 4 (FCNT4) FLOCKST (Lock Bit Status) bit shows whether the target block is protected. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-41 6 START INTERNAL MEMORY 6.6 Programming Internal Flash Memory Write the Read Lock Bit Status command (H'7171) to any address of the block to be read Write the Verify command (H'D0D0) to any address of the block NO FBUSY bit = 1 YES TIME OUT? 10 µs Confirm the Lock bit status bit (Note 1) YES Forcibly terminated NO END Note 1: Check Flash Control Register 4 (FCNT4) FLOCKST bit. Figure 6.6.14 Read Lock Bit Status (Register Read Mode) The following describes how to write to the lock bit. a) To clear the lock bit to "0" (flash protected) Issue the Lock Bit Program command (H’7777) to the memory block to be protected. b) To set the lock bit to "1" (flash unprotected) After setting the FPROT bit in Flash Control Register 2 to "1" (protection by lock bit disabled), use the Block Erase command (H’2020) to erase the memory block to be unprotected. The lock bit cannot be set to "1" directly by writing to it. c) Lock bit status when reset Because the lock bit is a nonvolatile bit, it remains unaffected when the microcomputer is reset or powered off. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-42 6 6.6.4 Flash Programming Time (Reference) (1) M32186F8 INTERNAL MEMORY 6.6 Programming Internal Flash Memory The following shows the time needed to program internal flash memory for reference. [1] Transfer time by SIO (When the capacity of transfer data : 1024KB) 1 / 57600bps x 1(fram) x 11(the number of transfer bit) x 1024KB = approx. 200.2 [s] [2] Flash writing time Other than 4KB block (1024KB - 4KB x 2) / 8byte x 100µs = approx.13.0 [s] 4KB block 4KB x 2 / 8byte x 200µs = approx.0.2 [s] Total 13.2 [s] [3] Erase time (all areas) 0.3s x 3block + 0.5s x 1block + 0.7s x 1block + 1.2s x 15block = 20.1 [s] [4] Total flash writing time (1024KB all areas) During 57600bps connection,flash writing time to serial connection is so short that it is able to be ignored For this reason, flash writing time is calculable with the following formula. [1] + [3] = approx.220.3 [s] In addition, the quickest data writing time with high speed is by speeding up serial connection or other means is calculable with the following formula. [2] + [3] = approx.33.3 [s] (2) M32185F4 [1] Transfer time by SIO (When the capacity of transfer data : 512KB) 1 / 57600bps x 1(fram) x 11(the number of transfer bit) x 512KB = approx. 100.1 [s] [2] Flash writing time Other than 4KB block (512KB - 4KB x 2) / 8byte x 100ms = approx.6.5 [s] 4KB block 4KB x 2 / 8byte x 200ms = approx.0.2 [s] Total 6.7 [s] [3] Erase time (all areas) 0.3s x 3block + 0.5s x 1block + 0.7s x 1block + 1.2s x 7block = 10.5 [s] [4] Total flash writing time (512KB all areas) During 57600bps connection,flash writing time to serial connection is so short that it is able to be ignored For this reason, flash writing time is calculable with the following formula. [1] + [3] = approx.110.6 [s] In addition, the quickest data writing time with high speed is by speeding up serial connection or other means is calculable with the following formula. [2] + [3] = approx.17.2 [s] 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-43 6 6.7 Virtual Flash Emulation Function INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The microcomputer has the function to map 8-Kbyte memory blocks of the internal RAM (maximum for 32185 is 4 blocks, for 32186 is 8 blocks) into areas (L banks) of the internal flash memory that are divided in 8-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This is the function allows shift from the contents of internal flash memory at the addresses specified by the Virtual Flash L Bank Register to the data located in 8-Kbyte blocks of the internal RAM. That way, the relevant RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant internal RAM data. The internal RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual internal RAM. This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitating data table tuning from an external device. Note: • Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. H'0080 4000 H'0080 5FFF H'0080 6000 H'0080 7FFF H'0080 8000 H'0080 9FFF H'0080 A000 H'0080 BFFF RAM bank L block 0 (FELBANK0) 8 Kbytes RAM bank L block 1 (FELBANK1) 8 Kbytes RAM bank L block 2 (FELBANK2) 8 Kbytes RAM bank L block 3 (FELBANK3) 8 Kbytes Figure 6.7.1 Internal RAM Bank Configuration of the 32185 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-44 6 H'0080 4000 H'0080 5FFF H'0080 6000 H'0080 7FFF H'0080 8000 H'0080 9FFF H'0080 A000 H'0080 BFFF H'0080 C000 H'0080 DFFF H'0080 E000 H'0080 FFFF H'0081 0000 H'0081 1FFF H'0081 2000 H'0081 3FFF INTERNAL MEMORY 6.7 Virtual Flash Emulation Function RAM bank L block 0 (FELBANK0) 8 Kbytes RAM bank L block 1 (FELBANK1) 8 Kbytes RAM bank L block 2 (FELBANK2) 8 Kbytes RAM bank L block 3 (FELBANK3) 8 Kbytes RAM bank L block 4 (FELBANK4) 8 Kbytes RAM bank L block 5 (FELBANK5) 8 Kbytes RAM bank L block 6 (FELBANK6) 8 Kbytes RAM bank L block 7 (FELBANK7) 8 Kbytes Figure 6.7.2 Internal RAM Bank Configuration of the 32186 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-45 6 6.7.1 Virtual Flash Emulation Area INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Figure 6.7.1 and Figure 6.7.2 show the internal flash memory areas in which the Virtual Flash Emulation Function is applicable. Using the Virtual Flash L Bank Register (M32185F4: FELBANK0 to FELBANK3, M32186F8: FELBANK0 to FELBANK 7), select one among all L banks of internal flash memory that are divided in 8-Kbyte units (by setting the eight start address bits A11–A18 of the desired L bank in the Virtual Flash L Bank Register LBANKAD bits). Then set the Virtual Flash L Bank Register’s flash emulation L enable bit (MODENL) to "1," and the selected L bank area will be replaced with 8-Kbyte blocks of the internal RAM (maximum for the M32185F4 is 4 blocks, for M32186 is 8 blocks). Notes: • If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers. • During virtual flash emulation mode, internal RAM can be accessed for read and write from the internal RAM area and the virtual flash set area. • Before reading any virtual flash set area after setting the Flash Control Register 1 virtual flash emulation mode bit to "1," be sure to check that the virtual flash emulation mode bit has been set to "1" by reading it once. • Before reading any virtual flash set area after setting the Virtual Flash L Bank Register virtual flash emulation L enable bit and L bank address bits, be sure to check that the virtual flash emulation L enable bit and L bank address bits have been set to the intended values by reading them once. H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes H'0080 6000 H'0080 8000 H'0080 A000 H'0007 C000 H'0007 E000 L bank 62 (8 Kbytes) L bank 63 (8 Kbytes) Notes: • If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers. • If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 to 3 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, internal RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. Figure 6.7.3 Virtual Flash Emulation Area divided in 8-Kbyte units for the M32185F4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-46 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) H'0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H'0080 6000 H'0080 8000 H'000F C000 H'000F E000 L bank 126 (8 Kbytes) L bank 127 (8 Kbytes) 8 Kbytes H'0081 2000 Notes: • If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers. • If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 to 7 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, internal RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. Figure 6.7.4 Virtual Flash Emulation Area divided in 8-Kbyte units for the M32186F8 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) Values set in L bank address (LBANKAD) bit H'000 H'002 H'004 H'0000 2000 (Note 1) H'0000 4000 (Note 1) L bank 62 L bank 63 H'0007 C000 (Note 1) H'07C H'07E H'0007 E000 (Note 1) Note 1: Set the eight start address bits A11-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note: • Because the internal flash memory of the M32185F4 is 512 Kbytes, the address b7 (A11) and b8 (A12) must always be set to "0." Figure 6.7.5 Values Set in Virtual Flash Bank Register when divided in 8-Kbyte units (32185) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-47 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Values set in L bank address (LBANKAD) bit H'000 H'002 H'004 H'0000 2000 (Note 1) H'0000 4000 (Note 1) L bank 126 L bank 127 H'000F C000 (Note 1) H'0FC H'0FE H'000F E000 (Note 1) Note 1: Set the eight start address bits A11-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note: • Because the internal flash memory of the M32186F8 is 1M (1,024K) bytes, the address b7 (A11) must always be set to "0." Figure 6.7.6 Values Set in Virtual Flash Bank Register when divided in 8-Kbyte units (32186) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-48 6 6.7.2 Entering Virtual Flash Emulation Mode INTERNAL MEMORY 6.7 Virtual Flash Emulation Function To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1." After entering virtual flash emulation mode, set the Virtual Flash L Bank Register MODENL bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area (M32185F4: H'0080 4000 to H'0080 BFFF, M32186: H’0080 4000 to H’0081 3FFF) can be accessed the same way as in usual internal RAM. Settings start Write flash data to RAM Enter virtual flash emulation mode FEMMOD ← 1 Set RAM location address in Virtual Flash L Bank Register LBANKAD ← Address A11–A18 Enable virtual flash emulation MODENL ← 1 Settings completed Figure 6.7.7 Virtual Flash Emulation Mode Sequence 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-49 6 INTERNAL MEMORY 6.8 Connecting to Serial Programmer (CSIO Mode) 6.8 Connecting to Serial Programmer (CSIO Mode) For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.8.1 Processing Microcomputer Pins before Using a Serial Programmer (CSIO Mode) Pin Name SCLKI1 RXD1 TXD1 P84 FP MOD0 MOD1 MOD2 RESET# XIN XOUT SBI# VREF0 AVCC0 AVSS0 VDDE VCCER VCCE EXCVCC EXCVDD VCC-BUS VSS JTRST Pin No. 71 70 69 68 94 92 93 123 91 4 5 77 42 43 60 108 65 95, 132 61, 137 73 6, 20 3, 21, 62, 72, 96, 138 111 Function SIO mode selection Serial data input (received data) Serial data output (transmit data) Transmit / receive enable output Flash memory protect Operation mode 0 Operation mode 1 Operation mode 2 Reset Clock input Clock output System Break interrupt (SBI) input Reference voltage input for A/D converter Analog power supply Analog ground RAM backup power supply Power supply for the internal voltage generator circuit Main power supply Connects external capacitance for the internal power supply Connects external capacitance for the RAM power supply External bus power supply Ground JTAG reset input Pull high or low Connect to the main power supply Connect to the main power supply Connect to ground Connect to the main power supply 5 V ± 10% or 3.3 V ± 10% 5 V ± 10% or 3.3 V ± 10% Need to be grounded to earth via capacitor Need to be grounded to earth via capacitor Depends on the target system 0V Pull low (0 - 100kΩ) Pull High Pull high Connect to the main power supply Connect to ground Connect to ground After setting MOD0 / MOD1, ground and back to main power supply Pull high Pull high Remark Note: • Pin processing is not required for those that are not listed above. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-50 6 INTERNAL MEMORY 6.8 Connecting to Serial Programmer (CSIO Mode) The diagram below shows an example of a user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the internal flash memory in clocksynchronous serial mode (CSIO mode). No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. User system board Connect to the VCCE (5 or 3.3 V) power supply rail VCCE VCCER VDDE AVCC0 VREF0 VCC-BUS Connect to the user system power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail EXCVCC EXCVDD Flash programmer signals Main power supply (for reference) Connector RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common) P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET# VSS AVSS0 To system circuit MOD1 MOD2 JTRST Set microcomputer operating conditions XIN XOUT (Note 1) SBI# 32185/32186 Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. Notes: • Turn on the power for the user system before writing to the internal flash memory. • If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. • The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition. • The typical pullup resistance values of P84, P86 and P87 are 4.7 to 10 KΩ. • The status of any other ports that are not shown here will not affect flash memory programming. • Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. Figure 6.8.1 Pin Connection Diagram (CSIO Mode) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-51 6 INTERNAL MEMORY 6.9 Connecting to Serial Programmer (UART Mode) 6.9 Connecting to Serial Programmer (UART Mode) For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.9.1 Processing Microcomputer Pins before Using a Serial Programmer (UART Mode) Pin Name SCLKI1 RXD1 TXD1 P84 FP MOD0 MOD1 MOD2 RESET# XIN XOUT SBI# VREF0 AVCC0 AVSS0 VDDE VCCER VCCE EXCVCC EXCVDD VCC-BUS VSS JTRST Pin No. 71 70 69 68 94 92 93 123 91 4 5 77 42 43 60 108 65 95, 132 61, 137 73 6, 20 3, 21, 62, 72, 96, 138 111 Function SIO mode selection Serial data input (received data) Serial data output (transmit data) General-purpose port input Flash memory protect Operation mode 0 Operation mode 1 Operation mode 2 Reset Clock input Clock output System Break interrupt (SBI) input Reference voltage input for A/D converter Analog power supply Analog ground RAM backup power supply Power supply for the internal voltage generator circuit Main power supply Connects external capacitance for the internal power supply Connects external capacitance for the RAM power supply External bus power supply Ground JTAG reset input Pull high or low Connect to the main power supply Connect to the main power supply Connect to ground Connect to the main power supply 5 V ± 10% or 3.3 V ± 10% 5 V ± 10% or 3.3 V ± 10% Need to be grounded to earth via capacitor Need to be grounded to earth via capacitor Depends on the target system 0V Pull low (0 - 100kΩ) Not used during UART mode Pull high or pull low Pull high Connect to the main power supply Connect to ground Connect to ground Remark Pull low (low level input) Pull high Note: • Pin processing is not required for those that are not listed above. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-52 6 INTERNAL MEMORY 6.9 Connecting to Serial Programmer (UART Mode) The diagram below shows an example of a user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the internal flash memory in clockasynchronous serial mode (UART mode). No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. User system board Connect to the VCCE (5 or 3.3 V) power supply rail VCCE Connect to the user system power supply rail VCCER VDDE AVCC0 Main power supply Connect to the VCCE (5 or 3.3V) power supply rail VREF0 VCC-BUS EXCVCC EXCVDD Flash programmer signals Main power supply (for reference) Connector RxD (input) TxD (output) Mode selection (output) P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET# GND (common) VSS AVSS0 MOD1 To system circuit Set microcomputer operating conditions MOD2 JTRST XIN XOUT (Note 1) SBI# 32185/32186 Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. Notes: • Turn on the power for the user system before writing to the internal flash memory. • If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. • The pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 must be selected to suit the system design condition. • The typical pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 are 4.7 to 10 KΩ. • The status of any other ports that are not shown here will not affect flash memory programming. • Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. Figure 6.9.1 Pin Connection Diagram (UART Mode) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-53 6 INTERNAL MEMORY 6.10 Internal Flash Memory Protect Function 6.10 Internal Flash Memory Protect Function The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, the internal flash memory cannot be read out, programmed nor erased. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erase operation by pulling the FP (Flash Protect) pin "L." For systems that do not require rewriting flash memory or systems in which flash reprogramming is prohibited as in the case of automotive applications, make sure the FP pin is fixed "L" except when programming or erasing the internal flash memory. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. For systems that do not require protection by setting external pins, the FP pin may be fixed "H" to simplify the operation to program/erase the internal flash memory. However, to prevent the flash memory from being inadvertently rewritten by an erratic operation in software, use the protection by a lock bit described in (4) below. When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to "1." To set the FENTRY bit to "1," write "0" and then "1" in succession while the FP pin is "H." (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0." That memory block is disabled against programming/erase operation. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-54 6 6.11 Notes on Internal RAM Precautions about the Internal Memory is shown below. INTERNAL MEMORY 6.11 Notes on Internal RAM • The writes from DRI,RTD to internal RAM uncompete with access from other bus masters (CPU, DMA, NBD, SDI), because of using dedicated bus not M32R-FPU. But in case DRI,RTD transfers and access from other bus masters for area in 16-Kbyte of internal RAM occur at same time, access competition occurs. When access competition occurs, arbitration is performed according to the following priority. NBD/SDI > DMA > CPU > DRI > RTD • When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/ Erase program" is transferd to internal RAM. 6.12 Notes on Internal Flash Memory The following describes precautions to be taken when programming/erasing the internal flash memory. • When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting/reset pin and power supply voltages do not fluctuate to prevent unintended changes of modes. • If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected. • If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F). • If the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF. • If the Flash Status Register (FSTAT)’s each error status is to be cleared (initialized to H’80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready) before clearing the error status. • Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0," check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready). • Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status Register (FSTAT) FBUSY bit = "0" (being programmed or erased). • When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-55 6 INTERNAL MEMORY 6.12 Notes on Internal Flash Memory This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 6-56 CHAPTER 7 RESET 7.1 7.2 7.3 7.4 Outline of Reset Reset Operation Internal State upon Exiting Reset Things to Be Considered upon Exiting Reset 7 7.1 Outline of Reset RESET 7.1 Outline of Reset The microcomputer is reset by applying "L" level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back "H," upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry. 7.2 Reset Operation When "L" level signal in width of more than 300 ns is applied to the RESET# pin, the microcomputer enters a reset state. At this time, the internal circuits (including the CPU) are reset. (For details about the pin state when reset, see Table 1.4.1, “Pin Assignments of the 32185/32186 Group”) When the RESET# input is returned "H," the internal circuits get out of a reset state (2333 to 2334 BCLK) periods after that. Flip-flop RESET# Noise Canceller S R Counter Pin reset signal OVF Internal circuit reset signal Figure 7.2.1 Reset Circuit Duration needed for noise cancellation(50 to 300ns) Extended for a duration during which the RESET# input is held "L" RESET# pin Reset signal (internal signal) past the noise canceller 2333 to 2334BCLK Internal circuit reset signal (internal signal) Figure 7.2.2 Reset Sequence 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 7-2 7 7.2.1 Reset at Power-on RESET 7.2 Reset Operation When powering on the microcomputer, hold the RESET# signal input pin "L" until the rated power supply voltage is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably. For details, see Section 22.2, "Power-On Sequence." 7.2.2 Reset during Operation To reset the microcomputer during operation, hold the RESET# signal input pin "L" for more than 300 ns. 7.2.3 Reset Vector Relocation during Flash Programming When the microcomputer is reset after entering boot mode, the reset vector entry address is moved to the boot program startup address. The boot program starts running after the reset state is deasserted. For details, see Section 6.6, “Programming the Internal Flash Memory.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 7-3 7 7.3 Internal State upon Exiting Reset RESET 7.3 Internal State upon Exiting Reset The table below lists the internal state of the microcomputer when it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State upon Exiting Reset Register PSW CBR SPI SPU BPC FPSR PC R0–R15 ACC (accumulator) RAM (CR0) (CR1) (CR2) (CR3) (CR6) (CR7) State upon exiting reset B'0000 0000 0000 0000 ??00 000? 0000 0000 H'0000 0000 (C bits = 0) Undefined Undefined Undefined H'0000 0100 (only DN bit = 1) H'0000 0000 Undefined Undefined Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program. (Executed beginning with the address H’0000 0000) (Note 1) (BSM, BIE, BC bits = undefined) 7.4 Things to Be Considered upon Exiting Reset • Input/output ports When exiting reset, the microcomputer’s input/output ports are disabled against input in order to prevent shootthrough current. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Outline of Input/Output Ports Selecting Pin Functions Input/Output Port Related Registers Port Input Level Switching Function Port Output Drive Capability Setting Function Noise Canceller Control Function Port Peripheral Circuits Notes on Input/Output Ports 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32185/32186 has a total of 97 input/output ports from P0–P13, P15, P17 and P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port has double or triple functions shared with other internal peripheral I/O or external bus interface related signal lines, or multiple functions shared with multi-function peripheral I/Os. Pin functions are selected depending on the operation mode of the CPU or by setting the operation mode register and peripheral function select register for the input/output port. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that internal peripheral I/O.) Abundant port functions are incorporated, including a port input level switching function, port output drive capability setting function, and noise canceller control function. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports Item Number of ports Specification Total 97 ports P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P15 P17 P22 Port function Pin function : : : : : : : : : : : : : : : : P00–P07 P10–P17 P20–P27 P30–P37 P41–P47 P61–P63 P70–P77 P82–P87 P93–P97 P100–P107 P110–P117 P124–P127 P130–P137 P150, P153 P174, P175 (8 ports) (8 ports) (8 ports) (8 ports) (7 ports) (3 ports) (8 ports) (6 ports) (5 ports) (8 ports) (8 ports) (4 ports) (8 ports) (2 ports) (2 ports) (4 ports) P220, P221, P224, P225 The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 is an input-only port.) Shared with peripheral I/O or external bus interface signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve multiple functions) Note: • P5, P14, P16, P18-P21 are nonexist. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-2 8 8.2 Selecting Pin Functions INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Each input/output port has double or triple functions shared with other internal peripheral I/O or external bus interface related signal lines, or multiple functions shared with multi-function peripheral I/Os. Pin functions are selected depending on the operation mode of the CPU or by setting the operation mode register and peripheral function select register for the input/output port. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that internal peripheral I/O.) P0–P4, P124, P125, P224 and P225, when the CPU is set to operate in processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0–P4, P124, P125, P224 and P225 Pin Functions MOD0 VSS VSS VCCE MOD1 VSS VCCE VSS Operation Mode Single-chip mode External extension mode Processor mode P0–P4, P124, P125, P224 and P225 Pin Function Input/output port pin Input/output port or external bus interface signal pin (Note 1) External bus interface signal pin VCCE VCCE (Settings inhibited) – Note 1: P41–P43 only function as external bus interface signal pins. Note: • VCCE and VSS are connected to main power supply and GND, respectively. Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode and peripheral function select registers. If any internal peripheral I/O has two or more pin functions, use the register provided for that internal peripheral I/O to select the desired pin function. Note that FP operations during internal flash memory programming do not affect the pin functions. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-3 8 0 P0 P1 Pin functions are selected by the settings for the port operation mode and port peripheral function select registers P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers P14 P15 P16 P17 P18 P19 P20 P21 P22 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 TO22 / DD1 TO30 / DD9 DD25 TIN5 / DD17 P41 (Port only) 2 TO23 / DD2 TO31 / DD10 DD26 TIN6 / DD18 P42 (Port only) 3 TO24 / DD3 TO32 / DD11 DD27 TIN7 / DD19 P43 (Port only) 4 TO25 / DD4 TO33 / DD12 DD28 TIN30 / DD20 TIN8 5 TO26 / DD5 TO34 / DD13 DD29 TIN31 / DD21 TIN9 6 TO27 / DD6 TO35 / DD14 DD30 TIN32 / DD22 TIN10 7 TO28 / DD7 TO36 / DD15 DD31 TIN33 / DD23 TIN11 TO21 / DD0 TO29 / DD8 DD24 TIN4 / DD16 P61 (Port only) CLKOUT / WR# / BCLK(Note 2) MOD0 (Note 1) WAIT# MOD1 (Note 1) P62 (Port only) HREQ# / TIN27 TXD0 / TO26 P63 (Port only) HACK# / TIN26 RXD0 / TO25 TO16 / SCLKI5 / SCLKO5 SBI# (Note 1) RTDTXD / TXD3 / NBDD0 SCLKI0 / SCLKO0 / TO24 TO17 / TXD5 / DD15 TO12 / TIN25 / DD3 TO4 / TO33 / DD7 TCLK0 / DD3 RTDRXD / RXD3 / NBDD1 TXD1 / TO23 TO18 / RXD5 / DD14 TO13 / SCLKI4 / SCLKO4 DD2 RTDACK / CTX1 / NBDD2 RXD1 / TO22 TO19 / DD13 TO14 / TXD4 / DD1 TO6 / TO35 / DD5 TCLK2 / DD1 TIN22 / CRX1 RTDCLK / CRX1 / NBDD3 SCLKI1 / SCLKO1 / TO21 TO20 / DD12 TO15 / RXD4 / DD0 TO7 / TO36 / DD4 TCLK3 / DD0 TIN23 / CTX1 TO8 TO0 / TO29 / DD11 TO9 / CRX0 TO1 / TO30 / DD10 TO10 / CTX0 TO2 / TO31 / DD9 TO11 / TIN24 TO3 / TO32 / DD8 TO5 / TO34 / DD6 TCLK1 / DD2 TIN21 / RXD3 TIN16 / TIN17 / PWMOFF0 / PWMOFF1 / DIN0 DIN1 TIN18 / DIN2 TIN19 / DIN3 TIN20 / TXD3 / DIN4 TIN0 / CLKOUT / WR#(Note 2) TIN3 / WAIT# TXD2 / TO28 RXD2 / TO27 CTX0 / HACK# CRX0 / HREQ# P224 (Port only) P225 (Port only) Note 1: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 2: Respective functions are selected by the Bus Mode Control Register. Notes: • P5, P14, P16, P18, P19, P20 and P21 are not provided. • Some functions have two separate pins assigned per function. For details, see Table 8.2.2. Figure 8.2.1 Input/Output Ports and Pin Function Assignments during Single Chip Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-4 8 0 P0 P1 Pin functions are selected by the settings for the port operation mode and port peripheral function select registers P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers P14 P15 P16 P17 P18 P19 P20 P21 P22 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 / TO22 / DD1 DB9 / TO30 / DD9 A24 / DD25 A16 / TIN5 / DD17 BLW# / BLE# (Note 1, 3) 2 DB2 / TO23 / DD2 DB10 / TO31 / DD10 A25 / DD26 A17 / TIN6 / DD18 BHW# / BHE# (Note 1, 3) 3 DB3 / TO24 / DD3 DB11 / TO32 / DD11 A26 / DD27 A18 / TIN7 / DD19 RD# (Note 1) 4 DB4 / TO25 / DD4 DB12 / TO33 / DD12 A27 / DD28 A19 / TIN30 / DD20 CS0# / TIN8 5 DB5 / TO26 / DD5 DB13 / TO34 / DD13 A28 / DD29 A20 / TIN31 / DD21 CS1# / TIN9 6 DB6 / TO27 / DD6 DB14 / TO35 / DD14 A29 / DD30 A21 / TIN32 / DD22 A13 / TIN10 7 DB7 / TO28 / DD7 DB15 / TO36 / DD15 A30 / DD31 A22 / TIN33 / DD23 A14 / TIN11 DB0 / TO21 / DD0 DB8 / TO29 / DD8 A23 / DD24 A15 / TIN4 / DD16 P61 (Port only) P62 (Port only) P63 (Port only) SBI# (Note 2) CLKOUT / WR# / BCLK(Note 3) MOD0 (Note 2) WAIT# MOD1 (Note 2) HREQ# / TIN27 TXD0 / TO26 HACK# / TIN26 RXD0 / TO25 TO16 / SCLKI5 / SCLKO5 RTDTXD / TXD3 / NBDD0 SCLKI0 / SCLKO0 / TO24 TO17 / TXD5 / DD15 TO12 / TIN25 / DD3 TO4 / TO33 / DD7 TCLK0 / A9 / DD3 RTDRXD / RXD3 / NBDD1 TXD1 / TO23 TO18 / RXD5 / DD14 TO13 / SCLKI4 / SCLKO4 DD2 RTDACK / CTX1 / NBDD2 RXD1 / TO22 TO19 / DD13 TO14 / TXD4 / DD1 TO6 / TO35 / DD5 TCLK2 / CS2# / DD1 TIN22 / CRX1 RTDCLK / CRX1 / NBDD3 SCLKI1 / SCLKO1 / TO21 TO20 / DD12 TO15 / RXD4 / DD0 TO7 / TO36 / DD4 TCLK3 / CS3# / DD0 TIN23 / CTX1 TO8 TO0 / TO29 / DD11 TO9 / CRX0 TO1 / TO30 / DD10 TO10 / CTX0 TO2 / TO31 / DD9 TO11 / TIN24 TO3 / TO32 / DD8 TO5 / TO34 / DD6 TCLK1 / A10 / DD2 TIN21 / RXD3 TIN16 / TIN17 / PWMOFF0 / PWMOFF1 / DIN0 DIN1 TIN18 / DIN2 TIN19 / DIN3 TIN20 / TXD3 / DIN4 TIN0 / CLKOUT / WR#(Note 3) TIN3 / WAIT# TXD2 / TO28 RXD2 / TO27 CTX0 / HACK# CRX0 / HREQ# A11 / CS2# A12 / CS3# Note 1: These ports cannot be used for input/output port function, function as external bus interface related signals. Note 2: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 3: Respective functions are selected by the Bus Mode Control Register. Notes: • P5, P14, P16, P18, P19, P20 and P21 are not provided. • Some functions have two separate pins assigned per function. For details, see Table 8.2.2. Figure 8.2.2 Input/Output Ports and Pin Function Assignments during External Extension Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-5 8 0 P0 P1 (Note 1) P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers P14 P15 P16 P17 P18 P19 P20 P21 P22 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 2 DB2 3 DB3 4 DB4 5 DB5 6 DB6 7 DB7 DB0 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 A23 A24 A25 A26 A27 A28 A29 A30 A15 A16 A17 A18 A19 A20 A21 A22 BLW# / BHW# / BLE#(Note 3) BHE#(Note 3) RD# CS0# CS1# A13 A14 P61 (Port only) P62 (Port only) P63 (Port only) SBI# (Note 2) CLKOUT / WR# / BCLK(Note 3) MOD0 (Note 2) WAIT# MOD1 (Note 2) HREQ# / TIN27 TXD0 / TO26 HACK# / TIN26 RXD0 / TO25 TO16 / SCLKI5 / SCLKO5 RTDTXD / TXD3 / NBDD0 SCLKI0 / SCLKO0 / TO24 TO17 / TXD5 / DD15 TO12 / TIN25 / DD3 TO4 / TO33 / DD7 A9 (Note 1) RTDRXD / RXD3 / NBDD1 TXD1 / TO23 TO18 / RXD5 / DD14 TO13 / SCLKI4 / SCLKO4 DD2 RTDACK / CTX1 / NBDD2 RXD1 / TO22 TO19 / DD13 TO14 / TXD4 / DD1 TO6 / TO35 / DD5 TCLK2 / CS2# / DD1 TIN22 / CRX1 RTDCLK / CRX1 / NBDD3 SCLKI1 / SCLKO1 / TO21 TO20 / DD12 TO15 / RXD4 / DD0 TO7 / TO36 / DD4 TCLK3 / CS3# / DD0 TIN23 / CTX1 TO8 TO0 / TO29 / DD11 TO9 / CRX0 TO1 / TO30 / DD10 TO10 / CTX0 TO2 / TO31 / DD9 TO11 / TIN24 TO3 / TO32 / DD8 TO5 / TO34 / DD6 A10 (Note 1) TIN16 / TIN17 / PWMOFF0 / PWMOFF1 / DIN0 DIN1 TIN18 / DIN2 TIN19 / DIN3 TIN20 / TXD3 / DIN4 TIN21 / RXD3 TIN0 / CLKOUT / WR#(Note 3) TIN3 / WAIT# TXD2 / TO28 RXD2 / TO27 CTX0 / HACK# CRX0 / HREQ# A11/CS2# (Note 1) A12/CS3# (Note 1) Note 1: These ports cannot be used for input/output port function, function as external bus interface related signals. Note 2: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 3: Respective functions are selected by the Bus Mode Control Register. Notes: • P5, P14, P16, P18, P19, P20 and P21 are not provided. • Some functions have two separate pins assigned per function. For details, see Table 8.2.2. Figure 8.2.3 Input/Output Ports and Pin Function Assignments during Processor Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-6 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions One peripheral I/O can be assigned to two separate pins by setting the CPU operation mode and peripheral function select register. Table 8.2.2 Peripheral I/Os Allowed for Input/Output at Two Pins and Pin Assignments (1/2) Module DRI Signal name DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 TOU TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 SIO CAN TXD3 RXD3 CTX0 CRX0 CTX1 CRX1 Pin group A P127/TCLK3/CS3#/DD0 P107/TO15/RXD4/DD0 P126/TCLK2/CS2/DD1 P106/TO14/TXD4/DD1 P125/TCLK1/A10/DD2 P105/TO13/SCLKI4/SCLKO4/DD2 P124/TCLK0/A9/DD3 P104/TO12/TIN25/DD3 P117/TO7/TO36/DD4 P116/TO6/TO35/DD5 P115/TO5/TO34/DD6 P114/TO4/TO33/DD7 P113/TO3/TO32/DD8 P112/TO2/TO31/DD9 P111/TO1/TO30/DD10 P110/TO0/TO29/DD11 P97/TO20/DD12 P96/TO19/DD13 P95/TO18/RXD5/DD14 P94/TO17/TXD5/DD15 P87/SCLKI1/SCLKO1/TO21 P86/RXD1/TO22 P85/TXD1/TO23 P84/SCLKI0/SCLKO0/TO24 P83/RXD0/TO25 P82/TXD0/TO26 P175/RXD2/TO27 P174/TXD2/TO28 P110/TO0/TO29/DD11 P111/TO1/TO30/DD10 P112/TO2/TO31/DD9 P113/TO3/TO32/DD8 P114/TO4/TO33/DD7 P115/TO5/TO34/DD6 P116/TO6/TO35/DD5 P117/TO7/TO36/DD4 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P102/TO10/CTX0 P101/TO9/CRX0 P137/TIN23/CTX1 P136/TIN22/CRX1 P04/DB4/TO25/DD4 P05/DB5/TO26/DD5 P06/DB6/TO27/DD6 P07/DB7/TO28/DD7 P10/DB8/TO29/DD8 P11/DB9/TO30/DD9 P12/DB10/TO31/DD10 P13/DB11/TO32/DD11 P14/DB12/TO33/DD12 P15/DB13/TO34/DD13 P16/DB14/TO35/DD14 P17/DB15/TO36/DD15 P00/DB0/TO21/DD0 P01/DB1/TO22/DD1 P02/DB2/TO23/DD2 P03/DB3/TO24/DD3 P04/DB4/TO25/DD4 P05/DB5/TO26/DD5 P06/DB6/TO27/DD6 P07/DB7/TO28/DD7 P10/DB8/TO29/DD8 P11/DB9/TO30/DD9 P12/DB10/TO31/DD10 P13/DB11/TO32/DD11 P14/DB12/TO33/DD12 P15/DB13/TO34/DD13 P16/DB14/TO35/DD14 P17/DB15/TO36/DD15 P74/RTDTXD/TXD3/NBDD0 P75/RTDRXD/RXD3/NBDD1 P220/CTX0/HACK# P221/CRX0/HREQ# P76/RTDACK/CTX1/NBDD2 P77/RTDCLK/CRX1/NBDD3 (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) Pin group B P00/DB0/TO21/DD0 P01/DB1/TO22/DD1 P02/DB2/TO23/DD2 P03/DB3/TO24/DD3 Note 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-7 8 Module (External bus interface related) Signal name CS2# CS3# CLKOUT WR# WAIT# HACK# HREQ# INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Table 8.2.2 Peripheral I/Os Allowed for Input/Output at Two Pins and Pin Assignments (2/2) Pin group A P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 P150/TIN0/CLKOUT/WR# P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# P220/CTX0/HACK# P221/CRX0/HREQ# Pin group B P224/A11/CS2# P225/A12/CS3# P70/CLKOUT/WR#/BCLK P70/CLKOUT/WR#/BCLK P71/WAIT# P73/HACK#/TIN26 P72/HREQ#/TIN27 (Note 1) (Note 2) (Note 1) (Note 2) Note Note 1: If Pin group A and Pin group B have the same internal peripheral input pin set, the setting for Pin group A comes into effect so that input from Pin group A is accepted as input for the relevant internal peripheral I/O. For the 16 high-order DD input bits of the DRI (DD0–DD15), which pins to use can be selected in the DRI related register. (For details, refer to the Chapter 14, "Direct RAM Interface.") Note 2: If Pin group A and Pin group B have the same internal peripheral input pin set, the signal is output from both pins. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-8 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/3) Address b0 H'0080 0500 H'0080 0502 H'0080 0504 H'0080 0506 H'0080 0508 H'0080 050A H'0080 050C H'0080 050E H'0080 0510 +0 address b7 b8 Port Group 0,1 Input Level Setting Register Port Group 3 Input Level Setting Register (PG01LEV) (PG3LEV) Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) Port Group 0,1 Output Drive Capability Setting Register Port Group 3 Output Drive Capability Setting Register (PG01DRV) (PG3DRV) Port Group 4,5 Output Drive Capability Setting Register Port Group 6,7 Output Drive Capability Setting Register (PG45DRV) (PG67DRV) Port Group 8 Output Drive Capability Setting Register P70 Output Drive Capability Setting Register (PG8DRV) (P70DRV) (Use inhibited area) Noise Canceller Control Register (NZCNSLCR) +1 address b15 8-33 8-33 8-33 See pages 8-35 8-35 8-35 8-36 8-38 | H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) (Use inhibited area) (Use inhibited area) (Use inhibited area) P22 Data Register (P22DATA) (Use inhibited area) (Use inhibited area) 8-12 P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) 8-12 8-12 8-12 8-12 8-12 8-12 8-12 8-12 8-12 | H'0080 0716 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-9 8 Input/Output Port Related Register Map (2/3) Address b0 H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) (Use inhibited area) (Use inhibited area) +0 address INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +1 address b7 b8 P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) (Use inhibited area) b15 See pages 8-13 8-13 8-13 8-13 8-13 8-13 8-13 8-13 8-13 | H'0080 0736 P22 Direction Register (P22DIR) (Use inhibited area) (Use inhibited area) 8-13 | H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) (Use inhibited area) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) (Use inhibited area) (Use inhibited area) | H'0080 0756 P22 Operation Mode Register (P22MOD) P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) (Use inhibited area) (Use inhibited area) (Use inhibited area) 8-14 8-15 8-16 8-17 8-18 8-29 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-10 8 Input/Output Port Related Register Map (3/3) Address b0 H'0080 0760 H'0080 0762 H'0080 0764 H'0080 0766 H'0080 0768 H'0080 076A H'0080 076C H'0080 076E H'0080 0770 +0 address INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +1 address b7 b8 b15 P1 Peripheral Function Select Register (P1SMOD) P3 Peripheral Function Select Register (P3SMOD) (Use inhibited area) See pages 8-14 8-15 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 P0 Peripheral Function Select Register (P0SMOD) (Use inhibited area) P4 Peripheral Function Select Register (P4SMOD) (Use inhibited area) | H'0080 0776 P7 Peripheral Function Select Register (P7SMOD) P8 Peripheral Function Select Register P9 Peripheral Function Select Register (P8SMOD) (P9SMOD) P10 Peripheral Function Select Register P11 Peripheral Function Select Register (P10SMOD) (P11SMOD) P12 Peripheral Function Select Register P13 Peripheral Function Select Register (P12SMOD) (P13SMOD) (Use inhibited area) P15 Peripheral Function Select Register (P15SMOD) (Use inhibited area) P17 Peripheral Function Select Register (P17SMOD) (Use inhibited area) P22 Peripheral Function Select Register (P22SMOD) (Use inhibited area) 8-28 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-11 8 8.3.1 Port Data Registers P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P7 Data Register (P7DATA) P8 Data Register (P8DATA) P9 Data Register (P9DATA) P10 Data Register (P10DATA) P11 Data Register (P11DATA) P12 Data Register (P12DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P22 Data Register (P22DATA) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers b0 (b8 Pn0DT ? 1 9 Pn1DT ? 2 10 Pn2DT ? 3 11 Pn3DT ? 4 12 Pn4DT ? 5 13 Pn5DT ? 6 14 Pn6DT ? b7 b15) Pn7DT ? Note: • n = 0–13, 15, 17, 22 (not including P5) b 0(8) 1(9) 2(10) 3(11) 4(12) 5(13) 6(14) 7(15) Bit Name Pn0DT Port Pn0 data bit Pn1DT Port Pn1 data bit Pn2DT Port Pn2 data bit Pn3DT Port Pn3 data bit Pn4DT Port Pn4 data bit Pn5DT Port Pn5 data bit Pn6DT Port Pn6 data bit Pn7DT Port Pn7 data bit Function Depends on how the Port Direction Register is set If direction bit = "0" (input mode) 0: Port input pin = "L" 1: Port input pin = "H" If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "L" 1: Port output latch = "1" / Port pin level = "H" Write to the port output latch R R W W Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Notes: • Following bits are not provided (read as "0," writing has no effect): P40, P60, P65–P67, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223, P226, P227 • The SBI# pin input level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect. • The MOD0 and MOD1 pin input levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect. • P221 is an input-only port. Writing to the P221DT bit has no effect. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-12 8 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P7 Direction Register (P7DIR) P8 Direction Register (P8DIR) P9 Direction Register (P9DIR) P10 Direction Register (P10DIR) P11 Direction Register (P11DIR) P12 Direction Register (P12DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P22 Direction Register (P22DIR) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers b0 (b8 Pn0DR 0 1 9 Pn1DR 0 2 10 Pn2DR 0 3 11 Pn3DR 0 4 12 Pn4DR 0 5 13 Pn5DR 0 6 14 Pn6DR 0 b7 b15) Pn7DR 0 Note: • n = 0–13, 15, 17, 22 (not including P5) b 0(8) 1(9) 2(10) 3(11) 4(12) 5(13) 6(14) 7(15) Bit Name Pn0DR Port Pn0 direction bit Pn1DR Port Pn1 direction bit Pn2DR Port Pn2 direction bit Pn3DR Port Pn3 direction bit Pn4DR Port Pn4 direction bit Pn5DR Port Pn5 direction bit Pn6DR Port Pn6 direction bit Pn7DR Port Pn7 direction bit Notes: • Following bits are not provided (read as 0, writing has no effect): P40, P60, P64–P67, P80, P81, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223, P226, P227 • All ports are set for input mode upon exiting the reset state. • P221 is an input-only port. Fix it to "0" when write. • After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period. Function 0: Input mode 1: Output mode R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-13 8 P0 Operation Mode Register (P0MOD) b0 P00MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode and Port Peripheral Function Select Registers 4 P04MD 0 1 P01MD 0 2 P02MD 0 3 P03MD 0 5 P05MD 0 6 P06MD 0 b7 P07MD 0 b 0 1 2 3 4 5 6 7 Bit Name P00MD Port P00 operation mode bit P01MD Port P01 operation mode bit P02MD Port P02 operation mode bit P03MD Port P03 operation mode bit P04MD Port P04 operation mode bit P05MD Port P05 operation mode bit P06MD Port P06 operation mode bit P07MD Port P07 operation mode bit Function 0: P00/DD0 (Note 1) 1: DB0/TO21 (Note 2) 0: P01/DD1 (Note 1) 1: DB1/TO22 (Note 2) 0: P02/DD2 (Note 1) 1: DB2/TO23 (Note 2) 0: P03/DD3 (Note 1) 1: DB3/TO24 (Note 2) 0: P04/DD4 (Note 1) 1: DB4/TO25 (Note 2) 0: P05/DD5 (Note 1) 1: DB5/TO26 (Note 2) 0: P06/DD6 (Note 1) 1: DB6/TO27 (Note 2) 0: P07/DD7 (Note 1) 1: DB7/TO28 (Note 2) R R R R R R R R R W W W W W W W W W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P0 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB0-DB7). P0 Peripheral Function Select Register (P0SMOD) b0 0 5 0 1 0 2 0 3 0 4 0 6 0 b7 0 P00SMD P01SMD P02SMD P03SMD P04SMD P05SMD P06SMD P07SMD b 0 1 2 3 4 5 6 7 Bit Name P00SMD Port P00 peripheral function select bit P01SMD Port P01 peripheral function select bit P02SMD Port P02 peripheral function select bit P03SMD Port P03 peripheral function select bit P04SMD Port P04 peripheral function select bit P05SMD Port P05 peripheral function select bit P06SMD Port P06 peripheral function select bit P07SMD Port P07 peripheral function select bit Function 0: DB0 1: TO21 0: DB1 1: TO22 0: DB2 1: TO23 0: DB3 1: TO24 0: DB4 1: TO25 0: DB5 1: TO26 0: DB6 1: TO27 0: DB7 1: TO28 R R R R R R R R R W W W W W W W W W Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB0-DB7). • The value of this register can only be modified when the corresponding P0 operation mode register bit = 0 (set for port). Then set the corresponging P0 operation mode register bit to "1." • During single-chip mode, selecting the external bus interface function is prohibited. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-14 8 P1 Operation Mode Register (P1MOD) b8 P10MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P14MD 0 9 P11MD 0 10 P12MD 0 11 P13MD 0 13 P15MD 0 14 P16MD 0 b15 P17MD 0 b 8 9 10 11 12 13 14 15 Bit Name P10MD Port P10 operation mode bit P11MD Port P11 operation mode bit P12MD Port P12 operation mode bit P13MD Port P13 operation mode bit P14MD Port P14 operation mode bit P15MD Port P15 operation mode bit P16MD Port P16 operation mode bit P17MD Port P17 operation mode bit Function 0: P10/DD8 (Note 1) 1: DB8/TO29 (Note 2) 0: P11/DD9 (Note 1) 1: DB9/TO30 (Note 2) 0: P12/DD10 (Note 1) 1: DB10/TO31 (Note 2) 0: P13/DD11 (Note 1) 1: DB11/TO32 (Note 2) 0: P14/DD12 (Note 1) 1: DB12/TO33 (Note 2) 0: P15/D13 (Note 1) 1: DB13/TO34 (Note 2) 0: P16/DD14 (Note 1) 1: DB14/TO35 (Note 2) 0: P17/DD15 (Note 1) 1: DB15/TO36 (Note 2) R R R R R R R R R W W W W W W W W W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P1 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB8-DB15). P1 Peripheral Function Select Register (P1SMOD) b8 0 13 0 9 0 10 0 11 0 12 0 14 0 b15 0 P10SMD P11SMD P12SMD P13SMD P14SMD P15SMD P16SMD P17SMD b 8 9 10 11 12 13 14 15 Bit Name P10SMD Port P10 peripheral function select bit P11SMD Port P11 peripheral function select bit P12SMD Port P12 peripheral function select bit P13SMD Port P13 peripheral function select bit P14SMD Port P14 peripheral function select bit P15SMD Port P15 peripheral function select bit P16SMD Port P16 peripheral function select bit P17SMD Port P17 peripheral function select bit Function 0: DB8 1: TO29 0: DB9 1: TO30 0: DB10 1: TO31 0: DB11 1: TO32 0: DB12 1: TO33 0: DB13 1: TO34 0: DB14 1: TO35 0: DB15 1: TO36 R R R R R R R R R W W W W W W W W W Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB8-DB15). • The value of this register can only be modified when the corresponding P1 operation mode register bit = 0 (set for port). Then set the corresponging P1 operation mode register bit to "1." • During single-chip mode, selecting the external bus interface function is prohibited. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-15 8 P2 Operation Mode Register (P2MOD) b0 P20MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P24MD 0 1 P21MD 0 2 P22MD 0 3 P23MD 0 5 P25MD 0 6 P26MD 0 b7 P27MD 0 b 0 1 2 3 4 5 6 7 Bit Name P20MD Port P20 operation mode bit P21MD Port P21 operation mode bit P22MD Port P22 operation mode bit P23MD Port P23 operation mode bit P24MD Port P24 operation mode bit P25MD Port P25 operation mode bit P26MD Port P26 operation mode bit P27MD Port P27 operation mode bit Function 0: P20/DD24 (Note 1) 1: A23 0: P21/DD25 (Note 1) 1: A24 0: P22/DD26 (Note 1) 1: A25 0: P23/DD27 (Note 1) 1: A26 0: P24/DD28 (Note 1) 1: A27 0: P25/DD29 (Note 1) 1: A28 0: P26/DD30 (Note 1) 1: A29 0: P27/DD31 (Note 1) 1: A30 R W R W R W R W R W R W R W R R W W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Notes: • During single-chip mode, settings of this register have no effect, and the port functions as port input/output or DD input pin. • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (A23-A30). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-16 8 P3 Operation Mode Register (P3MOD) b8 P30MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P34MD 0 9 P31MD 0 10 P32MD 0 11 P33MD 0 13 P35MD 0 14 P36MD 0 b15 P37MD 0 b 8 9 10 11 12 13 14 15 Bit Name P30MD Port P30 operation mode bit P31MD Port P31 operation mode bit P32MD Port P32 operation mode bit P33MD Port P33 operation mode bit P34MD Port P34 operation mode bit P35MD Port P35 operation mode bit P36MD Port P36 operation mode bit P37MD Port P37 operation mode bit Function 0: P30/DD16 (Note 1) 1: A15/TIN4 (Note 2) 0: P31/DD17 (Note 1) 1: A16/TIN5 (Note 2) 0: P32/DD18 (Note 1) 1: A17/TIN6 (Note 2) 0: P33/DD19 (Note 1) 1:A18/TIN17 (Note 2) 0: P34/DD20 (Note 1) 1:A19/TIN30 (Note 2) 0: P35/DD21 (Note 1) 1:A20/TIN31 (Note 2) 0: P36/DD22 (Note 1) 1: A21/TIN32 (Note 2) 0: P37/DD23 (Note 1) 1: A22/TIN33 (Note 2) R R R R R R R R R W W W W W W W W W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P3 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (A15-A22). P3 Peripheral Function Select Register (P3SMOD) b8 0 13 0 9 0 10 0 11 0 12 0 14 0 b15 0 P30SMD P31SMD P32SMD P33SMD P34SMD P35SMD P36SMD P37SMD b 8 9 10 11 12 13 14 15 Bit Name P30SMD Port P30 peripheral function select bit P31SMD Port P31 peripheral function select bit P32SMD Port P32 peripheral function select bit P33SMD Port P33 peripheral function select bit P34SMD Port P34 peripheral function select bit P35SMD Port P35 peripheral function select bit P36SMD Port P36 peripheral function select bit P37SMD Port P37 peripheral function select bit Function 0: A15 1: TIN4 0: A16 1: TIN5 0: A17 1: TIN6 0: A18 1: TIN7 0: A19 1: TIN30 0: A20 1: TIN31 0: A21 1: TIN32 0: A22 1: TIN33 R R R R R R R R R W W W W W W W W W Notes: • During processor mode, settings of this bit have no effect and the ports function as external bus interface signal pins (A15-A22). • The value of this register can only be modified when the corresponding P3 operation mode register bit = 0 (set for port). Then set the corresponging P3 operation mode register bit to "1." • During single-chip mode, selecting the external bus interface function is prohibited. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-17 8 P4 Operation Mode Register (P4MOD) b0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P44MD 0 0 0 0 1 2 3 5 P45MD 0 6 P46MD 0 b7 P47MD 0 b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0." P44MD Port P44 operation mode bit P45MD Port P45 operation mode bit P46MD Port P46 operation mode bit P47MD Port P47 operation mode bit 0: P44 1: CS0#/TIN8 (Note 1) 0: P45 1: CS1#/TIN9 (Note 1) 0: P46 1: A13/TIN10 (Note 1) 0: P47 1: A14/TIN11 (Note 1) R W R W R W Function R 0 R W 0 W Note 1: Which function of the pin is used depends on how the P4 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (CS0#, CS1#, A13 and A14). P4 Peripheral Function Select Register (P4SMOD) b0 0 5 0 1 0 2 0 3 0 4 0 6 0 b7 0 P44SMD P45SMD P46SMD P47SMD b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0." P44SMD Port P44 peripheral function select bit P45SMD Port P45 peripheral function select bit P46SMD Port P46 peripheral function select bit P47SMD Port P47 peripheral function select bit pins (CS0#, CS1#, A13 and A14). • The value of this register can only be modified when the corresponding P4 operation mode register bit = 0 (set for port). Then set the corresponging P4 operation mode register bit to "1." • During single-chip mode, selecting the external bus interface function is prohibited. 0: CS0# 1: TIN8 0: CS1# 1: TIN9 0: A13 1: TIN10 0: A14 1: TIN11 R W R W R W Function R 0 R W 0 W Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-18 8 P7 Operation Mode Register (P7MOD) b8 P70MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P74MD 0 9 P71MD 0 10 P72MD 0 11 P73MD 0 13 P75MD 0 14 P76MD 0 b15 P77MD 0 b 8 9 10 11 12 13 14 15 Bit Name P70MD Port P70 operation mode bit P71MD Port P71 operation mode bit P72MD Port P72 operation mode bit P73MD Port P73 operation mode bit P74MD Port P74 operation mode bit (Note 4) P75MD Port P75 operation mode bit (Note 4) P76MD Port P76 operation mode bit (Note 4) P77MD Port P77 operation mode bit (Note 4) Function 0: P70 1: CLKOUT/WR#/BCLK (Note 1) 0: P71 1: WAIT# (Note 2) 0: P72 1: HREQ#/TIN27 (Note 3) 0: P73 1: HACK#/TIN26 (Note 3) 0: P74 1: RTDTXD/TXD3/NBDD0 (Note 3) 0: P75 1: RTDRXD/RXD3/NBDD1 (Note 3) 0: P76 1: RTDACK/CTX1/NBDD2 (Note 3) 0: P77 1: RTDCLK/CRX1/NBDD3 (Note 3) R R R R R R R R R W W W W W W W W W Note 1: These functions are selected using the P7 Peripheral Function Select Register and Bus Mode Control Register. Note 2: During single-chip mode, settings of this register have no effect, and the port functions as port input/output pin. Note 3: These functions are selected using the P7 Peripheral Function Select Register. Note 4: If the NBD function is selected by the NBD Pin Control Register, the port functions as NBD pin no matter how this register is set. P7 Peripheral Function Select Register (P7SMOD) b8 P70SMD 0 0 13 0 9 10 0 11 0 12 0 14 0 b15 0 P72SMD P73SMD P74SMD P75SMD P76SMD P77SMD b 8 9 10 11 12 13 14 15 Bit Name P70SMD Port P70 peripheral function select bit No function assigned. Fix to "0." P72SMD Port P72 peripheral function select bit P73SMD Port P73 peripheral function select bit P74SMD (Note 2) Port P74 peripheral function select bit P75SMD (Note 2) Port P75 peripheral function select bit P76SMD (Note 2) Port P76 peripheral function select bit P77SMD (Note 2) Port P77 peripheral function select bit 0: HREQ# 1: TIN27 0: HACK# 1: TIN26 0: RTDTXD 1: TXD3 0: RTDRXD 1: RXD3 0: RTDACK 1: CTX1 0: RTDCLK 1: CRX1 Function 0: CLKOUT/WR# (Note 1) 1: BCLK R R 0 R R R R R R W W 0 W W W W W W Note 1: Which function of the pin is used depends on how the Bus Mode Control Register is set. Note 2: If the NBD function is selected by the NBD Pin Control Register, the port functions as NBD pin no matter how this register is set. Note: • The value of this register can only be modified when the corresponding P7 operation mode register bit = 0 (set for port). Then set the corresponging P7 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-19 8 P8 Operation Mode Register (P8MOD) b0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P84MD 0 1 0 2 P82MD 0 3 P83MD 0 5 P85MD 0 6 P86MD 0 b7 P87MD 0 b 0, 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." P82MD Port P82 operation mode bit P83MD Port P83 operation mode bit P84MD Port P84 operation mode bit P85MD Port P85 operation mode bit P86MD Port P86 operation mode bit P87MD Port P87 operation mode bit 0: P82 1: TXD0/TO26 (Note 1) 0: P83 1: RXD0/TO25 (Note 1) 0: P84 1: SCLKI0/SCLKO0/TO24 (Note 1) 0: P85 1: TXD1/TO23 (Note 1) 0: P86 1: RXD1/TO22 (Note 1) 0: P87 1: SCLKI1/SCLKO1/TO21 (Note 1) R W R W R W R W R W Function R 0 R W 0 W Note 1: Which function of the pin is used depends on how the P8 Peripheral Function Select Register is set. P8 Peripheral Function Select Register (P8SMOD) b0 0 5 0 1 0 2 0 3 0 4 0 6 0 b7 0 P82SMD P83SMD P84SMD P85SMD P86SMD P87SMD b 0, 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." P82SMD Port P82 peripheral function select bit P83SMD Port P83 peripheral function select bit P84SMD Port P84 peripheral function select bit P85SMD Port P85 peripheral function select bit P86SMD Port P86 peripheral function select bit P87SMD Port P87 peripheral function select bit 0: TXD0 1: TO26 0: RXD0 1: TO25 0: SCLKI0/SCLKO0 1: TO24 0:TXD1 1: TO23 0: RXD1 1: TO22 0: SCLKI1/SCLKO1 1: TO21 R W Function R 0 R R R R R W 0 W W W W W Note: • The value of this register can only be modified when the corresponding P8 operation mode register bit = 0 (set for port). Then set the corresponging P8 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-20 8 P9 Operation Mode Register (P9MOD) b8 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P94MD 0 9 0 10 0 11 P93MD 0 13 P95MD 0 14 P96MD 0 b15 P97MD 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." P93MD Port P93 operation mode bit P94MD Port P94 operation mode bit P95MD Port P95 operation mode bit P96MD Port P96 operation mode bit P97MD Port P97 operation mode bit 0: P93 1: TO16/SCLKI5/SCLKO5 (Note 2) 0: P94/DD15 (Note 1) 1: TO17/TXD5 (Note 2) 0: P95/DD14 (Note 1) 1: TO18/RXD5 (Note 2) 0: P96/DD13 (Note 1) 1: TO19 0: P97/DD12 (Note 1) 1: TO20 R W R W R W R W Function R 0 R W 0 W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P9 Peripheral Function Select Register is set. P9 Peripheral Function Select Register (P9SMOD) b8 0 13 0 9 0 10 0 11 0 12 0 14 0 b15 0 P93SMD P94SMD P95SMD b 8–10 11 12 13 14, 15 Bit Name No function assigned. Fix to "0." P93SMD Port P93 peripheral function select bit P94SMD Port P94 peripheral function select bit P95SMD Port P95 peripheral function select bit No function assigned. Fix to "0." 0: TO16 1: SCLKI5/SCLKO5 0: TO17 1: TXD5 0: TO18 1: RXD5 0 0 R W R W Function R 0 R W 0 W Note: • The value of this register can only be modified when the corresponding P9 operation mode register bit = 0 (set for port). Then set the corresponging P9 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-21 8 P10 Operation Mode Register (P10MOD) b0 P100MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P104MD 0 1 P101MD 0 2 P102MD 0 3 P103MD 0 5 P105MD 0 6 P106MD 0 b7 P107MD 0 b 0 1 2 3 4 5 6 7 Bit Name P100MD Port P100 operation mode bit P101MD Port P101 operation mode bit P102MD Port P102 operation mode bit P103MD Port P103 operation mode bit P104MD Port P104 operation mode bit P105MD Port P105 operation mode bit P106MD Port P106 operation mode bit P107MD Port P107 operation mode bit Function 0: P100 1: TO8 0: P101 1: TO9/CRX0 (Note 1) 0: P102 1: TO10/CTX0 (Note 1) 0: P103 1: TO11/TIN24 (Note 1) 0: P104/DD3 (Note 2) 1: TO12/TIN25 (Note 1) 0: P105/DD2 (Note 2) 1: TO13/SCLKI4/SCLKO4 (Note 1) 0: P106/DD1 (Note 2) 1: TO14/TXD4 (Note 1) 0: P107/DD0 (Note 2) 1: TO15/RXD4 (Note 1) R W R W R W R W R W R W R R R W W W Note 1: Which function of the pin is used depends on how the P10 Peripheral Function Select Register is set. Note 2: The DD input functions are effective depending on the settings of DD input pin select register (DDSEL). (For details, refer to the Chapter 14, "Direct RAM Interface") To use the port as DD input pin, set the port direction for input. P10 Peripheral Function Select Register (P10SMOD) b0 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 P101SMD P102SMD P103SMD P104SMD P105SMD P106SMD P107SMD b 0 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." P101SMD Port P101 peripheral function select bit (Note 1) P102SMD Port P102 peripheral function select bit P103SMD Port P103 peripheral function select bit P104SMD Port P104 peripheral function select bit P105SMD Port P105 peripheral function select bit P106SMD Port P106 peripheral function select bit P107SMD Port P107 peripheral function select bit 0: TO9 1: CRX0 0: TO10 1: CTX0 0: TO11 1: TIN24 0: TO12 1: TIN25 0:TO13 1: SCLKI4/SCLKO4 0: TO14 1: TXD4 0: TO15 1: RXD4 R W R W R W R W R W R W Function R 0 R W 0 W Note 1: When not using this pin as CRX0 pin, always be sure to set the bit to "0." Note: • The value of this register can only be modified when the corresponding P10 operation mode register bit = 0 (set for port). Then set the corresponging P10 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-22 8 P11 Operation Mode Register (P11MOD) b8 P110MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P114MD 0 9 P111MD 0 10 P112MD 0 11 P113MD 0 13 P115MD 0 14 P116MD 0 b15 P117MD 0 b 8 9 10 11 12 13 14 15 Bit Name P110MD Port P110 operation mode bit P111MD Port P111 operation mode bit P112MD Port P112 operation mode bit P113MD Port P113 operation mode bit P114MD Port P114 operation mode bit P115MD Port P115 operation mode bit P116MD Port P116 operation mode bit P117MD Port P117 operation mode bit Function 0: P110/DD11 (Note 1) 1: TO0/TO29 (Note 2) 0: P111/DD10 (Note 1) 1: TO1/TO30 (Note 2) 0: P112/DD9 (Note 1) 1: TO2/TO31 (Note 2) 0: P113/DD8 (Note 1) 1: TO3/TO32 (Note 2) 0: P114/DD7 (Note 1) 1: TO4/TO33 (Note 2) 0: P115/DD6 (Note 1) 1: TO5/TO34 (Note 2) 0: P116/DD5 (Note 1) 1: TO6/TO35 (Note 2) 0: P117/DD4 (Note 1) 1: TO7/TO36 (Note 2) R W R W R W R W R W R W R R R W W W Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P11 Peripheral Function Select Register is set. P11 Peripheral Function Select Register (P11SMOD) b8 0 14 0 9 0 10 0 11 0 12 0 13 0 b15 0 P110SMD P111SMD P112SMD P113SMD P114SMD P115SMD P116SMD P117SMD b 8 9 10 11 12 13 14 15 Bit Name P110SMD Port P110 peripheral function select bit P111SMD Port P111 peripheral function select bit P112SMD Port P112 peripheral function select bit P113SMD Port P113 peripheral function select bit P114SMD Port P114 peripheral function select bit P115SMD Port P115 peripheral function select bit P116SMD Port P116 peripheral function select bit P117SMD Port P117 peripheral function select bit Function 0: TO0 1: TO29 0: TO1 1: TO30 0: TO2 1: TO31 0: TO3 1: TO32 0: TO4 1: TO33 0: TO5 1: TO34 0: TO6 1: TO35 0: TO7 1: TO36 R W R W R R R R R W W W W W R R W W Note: • The value of this register can only be modified when the corresponding P11 operation mode register bit = 0 (set for port). Then set the corresponging P11 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-23 8 P12 Operation Mode Register (P12MOD) b0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P124MD 0 0 0 0 1 2 3 5 P125MD 0 6 P126MD 0 b7 P127MD 0 b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0." P124MD Port P124 operation mode bit (Note 3) P125MD Port P125 operation mode bit (Note 3) P126MD Port P126 operation mode bit P127MD Port P127 operation mode bit 0: P124/DD3 (Note 1) 1: TCLK0/A9 (Note 2) 0: P125/DD2 (Note 1) 1: TCLK1/A10 (Note 2) 0: P126/DD1 (Note 1) 1: TCLK2/CS2# (Note 2) 0: P127/DD0 (Note 1) 1: TCLK3/CS3# (Note 2) R W R W R W Function R 0 R W 0 W Note 1: The DD input functions are effective depending on the settings of DD input pin select register (DDSEL). (For details, refer to the Chapter 14, "Direct RAM Interface") To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P12 Peripheral Function Select Register is set. Note 3: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A9 or A10). P12 Peripheral Function Select Register (P12SMOD) b0 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 P124SMD P125SMD P126SMD P127SMD b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0." P124SMD Port P124 peripheral function select bit (Note 1) P125SMD Port P125 peripheral function select bit (Note 1) P126SMD Port P126 peripheral function select bit P127SMD Port P127 peripheral function select bit 0: TCLK0 1: A9 0: TCLK1 1: A10 0: TCLK2 1: CS2# 0: TCLK3 1: CS3# R W R W R W Function R 0 R W 0 W Note 1: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A9 or A10). Note: • The value of this register can only be modified when the corresponding P12 operation mode register bit = 0 (set for port). Then set the corresponging P12 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-24 8 P13 Operation Mode Register (P13MOD) b8 P130MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P134MD 0 9 P131MD 0 10 P132MD 0 11 P133MD 0 13 P135MD 0 14 P136MD 0 b15 P137MD 0 b 8 9 10 11 12 13 14 15 Bit Name P130MD Port P130 operation mode bit P131MD Port P131 operation mode bit P132MD Port P132 operation mode bit P133MD Port P133 operation mode bit P134MD Port P134 operation mode bit P135MD Port P135 operation mode bit P136MD Port P136 operation mode bit P137MD Port P137 operation mode bit Note 2: TIN input and DIN input functions both are effective. Note 3: Which function of the pin is used depends on how the P13 Peripheral Function Select Register is set. Function 0: P130 1: TIN16/PWMOFF0/DIN0 (Note 1) 0: P131 1: TIN17/PWMOFF1/DIN1 (Note 1) 0: P132 1: TIN18/DIN2 (Note 2) 0: P133 1: TIN19/DIN3 (Note 2) 0: P134 1: TIN20/TXD3/DIN4 (Note 3) 0: P135 1: TIN21/RXD3 (Note 3) 0: P136 1: TIN22/CRX1 (Note 3) 0: P137 1: TIN23/CTX1 (Note 3) R W R W R W R W R W R W R R R W W W Note 1: TIN input, DIN input, and PWMOFF input functions all are effective. P13 Peripheral Function Select Register (P13SMOD) b8 0 14 0 9 0 10 0 11 0 12 0 13 0 b15 0 P134SMD P135SMD P136SMD P137SMD b 8–11 12 13 14 15 Bit Name No function assigned. Fix to "0." P134SMD Port P134 peripheral function select bit P135SMD Port P135 peripheral function select bit (Note 2) P136SMD Port P136 peripheral function select bit (Note 3) P137SMD Port P137 peripheral function select bit Note 1: TIN input and DIN input functions both are effective. Note 2: When not using this pin as RXD3 pin, always be sure to set the bit to "0." Note 3: When not using this pin as CRX1 pin, always be sure to set the bit to "0." Note: • The value of this register can only be modified when the corresponding P13 operation mode register bit = 0 (set for port). Then set the corresponging P13 operation mode register bit to "1." 0: TIN20/DIN4 (Note 1) 1: TXD3 0: TIN21 1: RXD3 0: TIN22 1: CRX1 0: TIN23 1: CTX1 R W R W R W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-25 8 P15 Operation Mode Register (P15MOD) b8 P150MD 0 0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 0 9 10 11 P153MD 0 13 0 14 0 b15 0 b 8 9, 10 11 12–15 Bit Name P150MD Port P150 operation mode bit No function assigned. Fix to "0." P153MD Port P153 operation mode bit No function assigned. Fix to "0." Register are set. Note 2: Which function of the pin is used depends on how the P15 Peripheral Function Select Register is set. 0: P153 1: TIN3/WAIT# (Note 2) 0 0 Function 0: P150 1: TIN0/CLKOUT/WR# (Note 1) R R 0 R W W 0 W Note 1: Which function of the pin is used depends on how the P15 Peripheral Function Select Register and Bus Mode Control P15 Peripheral Function Select Register (P15SMOD) b8 P150SMD 0 0 0 14 0 9 10 11 P153SMD 0 12 0 13 0 b15 0 b 8 9, 10 11 12–15 Bit Name P150SMD Port P150 peripheral function select bit No function assigned. Fix to "0." P153SMD Port P153 peripheral function select bit (Note 2) No function assigned. Fix to "0." 0: TIN3 1: WAIT# 0 0 Function 0: TIN0 1: CLKOUT/WR# (Note 1) 0 R 0 W R R W W Note 1: Which function of the pin is used depends on how the Bus Mode Control Register is set. Note 2: During single-chip mode, selecting the external bus interface signal function is prohibited. Note: • The value of this register can only be modified when the corresponding P15 operation mode register bit = 0 (set for port). Then set the corresponging P15 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-26 8 P17 Operation Mode Register (P17MOD) b8 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 12 P174MD 0 0 0 0 9 10 11 13 P175MD 0 14 0 b15 0 b 8–11 12 13 14, 15 Bit Name No function assigned. Fix to "0." P174MD Port P174 operation mode bit P175MD Port P175 operation mode bit No function assigned. Fix to "0." 0: P174 1: TXD2/TO28 (Note 1) 0: P175 1: RXD2/TO27 (Note 1) 0 0 R W Function R 0 R W 0 W Note 1: Which function of the pin is used depends on how the P17 Peripheral Function Select Register is set. P17 Peripheral Function Select Register (P17SMOD) b8 0 14 0 9 0 10 0 11 0 12 0 13 0 b15 0 P174SMD P175SMD b 8–11 12 13 14, 15 Bit Name No function assigned. Fix to "0." P174SMD Port P174 peripheral function select bit P175SMD Port P175 peripheral function select bit No function assigned. Fix to "0." 0: TXD2 1: TO28 0: RXD2 1: TO27 R 0 W 0 Function R 0 R W 0 W Note: • The value of this register can only be modified when the corresponding P17 operation mode register bit = 0 (set for port). Then set the corresponging P17 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-27 8 P22 Operation Mode Register (P22MOD) b0 P220MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 4 P224MD 0 0 0 1 P221MD 0 2 3 5 P225MD 0 6 0 b7 0 b 0 1 2, 3 4 5 6, 7 Bit Name P220MD Port P220 operation mode bit P221MD Port P221 operation mode bit No function assigned. Fix to "0." P224MD Port P224 operation mode bit (Note 2) P225MD Port P225 operation mode bit (Note 2) No function assigned. Fix to "0." 0: P224 1: A11/CS2# (Note 1) 0: P225 1: A12/CS3# (Note 1) 0 0 R W Function 0: P220 1: CTX0/HACK# (Note 1) 0: P221 1: CRX0/HREQ# (Note 1) 0 R 0 W R R R W W W Note 1: Which function of the pin is used depends on how the P22 Peripheral Function Select Register is set. Note 2: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A11/CS2# or A12/CS3#). P22 Peripheral Function Select Register (P22SMOD) b0 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 P220SMD P221SMD P224SMD P225SMD b 0 1 2, 3 4 5 6, 7 Bit Name P220SMD Port P220 peripheral function select bit P221SMD Port P221 peripheral function select bit No function assigned. Fix to "0." P224SMD Port P224 peripheral function select bit (Note 1) P225SMD Port P225 peripheral function select bit (Note 1) No function assigned. Fix to "0." 0: A11 1: CS2# 0: A12 1: CS3# 0 0 R W Function 0: CTX0 1: HACK# 0: CRX0 1: HREQ# 0 R 0 W R W R R W W Note 1: During single-chip mode, selecting the external bus interface signal function is prohibited. Note: • The value of this register can only be modified when the corresponding P22 operation mode register bit = 0 (set for port). Then set the corresponging P22 operation mode register bit to "1." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-28 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.4 Port Input Special Function Control Register Port Input Special Function Control Register (PICNT) b8 0 9 0 10 0 11 XSTAT 0 12 0 13 0 14 PISEL 0 b15 PIEN0 0 b 8–10 11 12, 13 14 15 Bit Name No function assigned. Fix to "0." XSTAT XIN oscillation status bit No function assigned. Fix to "0." PISEL Port input data select bit PIEN0 Port input enable bit (Note 2) 0: Content of port output latch 1: Port pin level 0: Disable input 1: Enable input R W 0: XIN oscillating 1: XIN inactive 0 R 0 W Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note 2: After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period. (1) XSTAT (XIN oscillation status) bit (Bit 11) • Conditions under which XSTAT bit is set to "1" XSTAT bit is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods) on the basis of threshold, XIN oscillation is assumed to have stopped. When operating normally, XIN changes state ("H" or "L") once every BCLK period. • Conditions under which XSTAT bit is cleared to "0" XSTAT bit is cleared to "0" by a system reset or by writing "0." If XSTAT bit is cleared at the same time it is set XSTAT to "1" in above mentioned, the former has priority. Writing "1" to XSTAT bit is ignored. • Method for using XSTAT bit to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscillation has stopped. By reading XSTAT bit without clearing it once after exiting the reset state, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0," it is possible to know the current oscillating status of XIN. However, there must be an interval of at least 5 BCLK periods (20 CPU clock periods) between read and write. Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-29 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers (1) To know whether XIN oscillation has ever stopped after being reset Read XSTAT bit (2) To know the current status of XIN oscillation Write XSTAT bit = 0 Wait before inspecting XSTAT bit Wait for 20 CPU clock periods or more Read XSTAT bit Note: • Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc. Figure 8.3.1 Procedure for Setting XSTAT bit (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. At this time, this bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register Direction Register 0 (input) 1 (output) PISEL Settings 0/1 0 1 Target Data to Be Read Port pin level Port output latch Port pin level 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-30 8 (3) PIEN0 (Port input enable) bit (Bit 15) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers This bit is used to prevent shoot-through current from flowing into the port input pins. Because the input/output ports are disabled against input upon exiting reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1." When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has "L" level input applied. Consequently, if a peripheral input function (uncontrolled pin) is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the "L" level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid ("H" or "L") (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial interface functions are enabled for input and can therefore be protected against shoot-through current flowing in from the pins other than serial interface functions during flash programming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by Port Input Enable Bit Mode Name Controllable Pins P00–P07, P10–P17, P20–P27 P30–P37, P41–P47, P61–P63 P70–P77, P82–P87, P93–P97 P100–P107, P110–P117, P124–P127 P130–P137, P150, P153, P174, P175 P220, P224, P225 P61–P63, P70–P77, P82–P87 P93–P97, P100–P107, P110–P117 P126, P127, P130–P137 P150, P153, P174, P175, P220 P00–P07, P10–P17, P20–P27 P30–P37, P41–P47, P61–P63 P70–P77, P93–P97, P100–P107 P110–P117, P124–P127, P130–P137 P150, P153, P220, P224, P225 Uncontrolled Pins P221, FP, SBI#, MOD0, MOD1, MOD2, RESET# Single-chip External extension Microprocessor P00–P07, P10–P17 P20–P27, P30–P37 P41–P47, P124, P125, P221, P224, P225 FP, SBI#, MOD0, MOD1, MOD2, RESET# P82–P87, P174, P175, P221 FP, SBI#, MOD0, MOD1, MOD2, RESET# Boot (single-chip) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-31 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function 8.4 Port Input Level Switching Function The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. This can be set to the following registers in units of group. Note that port inputs are used for the DD input of DRI. Port Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224, P225 Port Group 1: P82–P87, P174, P175 Port Group 3: P93–P97, P110–P117 Port Group 4: P124–P127 Port Group 5: P61–P63, SBI# Port Group 6: P74–P77, P100–P107 Port Group 7: P220, P221 Port Group 8: P130–P137, P150, P153 0.7VCCE Pin 0.5VCCE S S VT+ Schmitt VTS Port input Port input enable PIEN0 0.35VCCE Threshold S VTnSEL CMOS PTnSEL S S WFnSEL Noise Canceller Peripheral function input Standard input level for each peripheral function pin Figure 8.4.1 Port Input Level Switching Function 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-32 8 b0 WF0SEL 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function Port Group 0,1 Input Level Setting Register (PG01LEV) 1 PT0SEL 0 6 VT1SEL0 0 2 VT0SEL0 0 3 VT0SEL1 1 4 WF1SEL 0 5 PT1SEL 0 b7 VT1SEL1 1 Port Group 3 Input Level Setting Register (PG3LEV) b8 0 14 VT3SEL0 0 9 0 10 0 11 0 12 WF3SEL 0 13 PT3SEL 0 b15 VT3SEL1 1 Note: • The PG3LEV register bits 8–11 have no functions assigned. Port Group 4,5 Input Level Setting Register (PG45LEV) b0 WF4SEL 0 6 VT5SEL0 0 1 PT4SEL 0 2 VT4SEL0 0 3 VT4SEL1 1 4 WF5SEL 0 5 PT5SEL 0 b7 VT5SEL1 1 Port Group 6,7 Input Level Setting Register (PG67LEV) b8 WF6SEL 0 14 VT7SEL0 0 9 PT6SEL 0 10 VT6SEL0 0 11 VT6SEL1 1 12 WF7SEL 0 13 PT7SEL 0 b15 VT7SEL1 1 Port Group 8 Input Level Setting Register (PG8LEV) b0 WF8SEL 0 6 0 1 PT8SEL 0 2 VT8SEL0 0 3 VT8SEL1 1 4 0 5 0 b7 0 Note: • The PG8LEV register bits 4–7 have no functions assigned. b7 2 0 3 G0DSEL 0 4 0 5 0 6 0 G1DSEL 0 Port Group 3 Output Drive Capability Setting Register (PG3DRV) b8 0 b7 G5DSEL 0 1 0 2 0 3 G4DSEL 0 4 0 5 0 6 0 Port Group 6,7 Output Drive Capability Setting Register (PG67DRV) b8 0 b7 0 1 0 2 0 3 G8DSEL 0 4 0 5 0 6 0 Note: • PG8DRV register bits 4–7 have no functions assigned. b 0–2 (8–10) 3 (11) 4–6 (12–14) 7 (15) GnDSEL (Note 1) Group n output drive capability select bit function. Note : • For the P70/CLKOUT/WR#/BCLK pin, the drive capability can be set to one of four capability levels by using the P70 Output Drive Capability Setting Register. Note that 50% of GnDSEL bit and 50% of P70DSEL bit drive capabilities are equivalent. 0: 50% 1: 100% R W GnDSEL (Note 1) Group n output drive capability select bit No function assigned. Fix to "0." 0: 50% 1: 100% 0 0 R W Bit Name No function assigned. Fix to "0." Function R 0 W 0 Note 1:The 50% drive capability is equivalent to that of the M32R/ECU series without the port output drive capability setting 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-35 8 b8 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Output Drive Capability Setting Function P70 Output Drive Capability Setting Register (P70DRV) 9 0 9 0 2 0 3 0 4 0 5 0 6 G6NSEL 7 0 8 G8NSEL 10 0 11 0 12 0 13 0 14 0 b15 0 G0NSEL G1NSEL G3NSEL G4NSEL 0 0 b 0 1 2 3 4 5 6 7 8 9–15 Bit Name G0NSEL Group 0 noise canceller disable bit G1NSEL Group 1 noise canceller disable bit No function assigned. Fix to "0." G3NSEL Group 3 noise canceller disable bit G4NSEL Group 4 noise canceller disable bit No function assigned. Fix to "0." G6NSEL Group 6 noise canceller disable bit No function assigned. Fix to "0." G8NSEL Group 8 noise canceller disable bit No function assigned. Fix to "0." 0: Group 8 noise canceller used 1: Group 8 noise canceller not used 0 0 0: Group 6 noise canceller used 1: Group 6 noise canceller not used 0 R 0 W 0: Group 3 noise canceller used 1: Group 3 noise canceller not used 0: Group 4 noise canceller used 1: Group 4 noise canceller not used 0 R 0 W R W Function 0: Group 0 noise canceller used 1: Group 0 noise canceller not used 0: Group 1 noise canceller used 1: Group 1 noise canceller not used 0 R 0 W R W R R W W Note: • This register must always be accessed in halfwords. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-38 8 8.7 Port Peripheral Circuits INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.7 Port Peripheral Circuits Figures 8.7.1 through 8.7.5 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P20−P27(A23/DD24−A30/DD31) P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P61−P63 P224(A11/CS2#) P225(A12/CS3#) Direction register Data bus Port output latch Port input data selection (Note 1) Port input level switching function (Standard: no peripheral input) Input function enable P30(A15/TIN4/DD16) P31(A16/TIN5/DD17) P32(A17/TIN6/DD18) P33(A18/TIN7/DD19) P34(A19/TIN30/DD20) P35(A20/TIN31/DD21) P36(A21/TIN32/DD22) P37(A22/TIN33/DD23) P44(CS0#/TIN8) P45(CS1#/TIN9) P46(A13/TIN10) P47(A14/TIN11) P73(HACK#/TIN26) P83(RXD0/TO25) P86(RXD1/TO22) P95(TO18/RXD5/DD14) P101(TO9/CRX0) P103(TO11/TIN24) P104(TO12/TIN25/DD3) P107(TO15/RXD4/DD0) P124(TCLK0/A9/DD3) P125(TCLK1/A10/DD2) P126(TCLK2/CS2#/DD1) P127(TCLK3/CS3#/DD0) P134(TIN20/TXD3/DIN4) P137(TIN23/CTX1) P150(TIN0/CLKOUT/WR#) P175(RXD2/TO27) Direction register Data bus Port output latch Port input data selection (Note 1) (Note 2) Port input level switching function (Standard: peripheral schmitt) Operation mode register Input function enable Peripheral function select register Peripheral function input (Note 3) Peripheral function output Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: The standard input level of TIN4-TIN11,TIN30-TIN33 is peripheral TTL. Note 3: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: • During external extension and processor modes, P20-P27, P41-P43, P224 and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted. • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage. • The input capacitance of each pin is approximately 10 pF. • The logic of peripheral function select register for P83, P86, P124, P125, P126, P127, P134, P137, P150, P175 are reversal, but it is not mentioned in this clock diagram. • DRI relative pin is not mentioned in this clock diagram. Figure 8.7.1 Port Peripheral Circuit Diagram (1) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-39 8 SBI# Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.7 Port Peripheral Circuits (Note 1) Port input level switching function (Standard: peripheral schmitt) SBI# P71(WAIT#) P130(TIN16/PWMOFF0/DIN0) P131(TIN17/PWMOFF1/DIN1) P132(TIN18/DIN2) Data bus P133(TIN19/DIN3) Direction register Port output latch Port input data selection Operation mode register Peripheral function input (Note 3) Input function enable (Note 1) (Note 2) Port input level switching function (Standard: peripheral schmitt) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: The standard input level of WAIT# is peripheral TTL. Note 3: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.7.2 Port Peripheral Circuit Diagram (2) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-40 8 P00-P07(DB0/TO21/DD0 -DB7/TO28/DD7) P10-P17(DB8/TO29/DD8 -DB15/TO36/DD15) P96(TO19/DD13) P97(TO20/DD12) P100(TO8) Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.7 Port Peripheral Circuits Direction register Port output latch Port input data selection Operation mode register (Note 1) Port input level switching function (Standard: no peripheral input) Peripheral function output Input function enable P84(SCLKI0/SCLKO0/TO24) P87(SCLKI1/SCLKO1/TO21) Data bus P93(TO16/SCLKI5/SCLKO5) P105(TO13/SCLKI4/SCLKO4/DD2) Direction register Port output latch Port input data selection Operation mode register UART/CSIO function select bit Internal/external clock select bit Peripheral function select register Peripheral function output SCLKOi output SCLKIi input (Note 2) Input function enable (Note 1) Port input level switching function (Standard: peripheral schmitt) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage. • The input capacitance of each pin is approximately 10 pF. • The logic of peripheral function select register for P93, P105 are reversal, but it is not mentioned in this clock diagram. • DRI relative pin is not mentioned in this clock diagram. Figure 8.7.3 Port Peripheral Circuit Diagram (3) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-41 8 P72(HREQ#/TIN27) P75(RTDRXD/RXD3/NBDD1) P77(RTDCLK/CRX1/NBDD3) P135(TIN21/RXD3) P136(TIN22/CRX1) P153(TIN3/WAIT#) Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.7 Port Peripheral Circuits Direction register Port output latch Port input data selection Operation mode register Peripheral function select register Peripheral function input 1 (Note 4) Peripheral function input 2 (Note 4) (Note 1) (Note 2) Port input level switching function (Standard: peripheral schmitt) Input function enable P221(CRX0/HREQ#) Data bus Operation mode register Peripheral function select register Port input data selection Peripheral function input 1 (Note 4) Peripheral function input 2 (Note 4) (Note 1) Port input level switching function (Standard: peripheral schmitt) Input function enable P70(CLKOUT/WR#/BCLK) P74(RTDTXD/TXD3/NBDD0) P76(RTDACK/CTX1/NBDD2) Data bus P82(TXD0/TO26) P85(TXD1/TO23) P94(TO17/TXD5/DD15) P102(TO10/CTX0) P106(TO14/TXD4/DD1) P110 - P117(TO0/TO29/DD11 -TO8/TO36/DD4) P174(TXD2/TO28) P220(CTX0/HACK#) Direction register Port output latch Port input data selection (Note 1) (Note 3) Port input level switching function (Standard: peripheral schmitt) Operation mode register Peripheral function select register Input function enable Peripheral function input 1 Peripheral function input 2 Note 1: Note 2: Note 3: Note 4: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." The standard input level of WAIT# is peripheral TTL. There is no standard input level in P70, P82, P85, P94, P102, P106, P110-P117, P174, and P220. "H" level is entered to the peripheral function input when it is set to the general-purpose port inthe operation mode register. Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.7.4 Port Peripheral Circuit Diagram (4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-42 8 MOD0 MOD1 MOD2 FP RESET# XIN JTRST JTMS JTDI/NBDSYNC# MOD0, MOD1, MOD2, FP,RESET#,XIN, JTRST, JTMS JTDI/NBDSYNC# INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.7 Port Peripheral Circuits JTCK/NBDCLK JTCK/NBDCLK JTDO/NBDEVNT# JTDO/NBDEVNT# VCC-BUS VCCE VDDE AVCC0 VCCER EXCVCC EXCVDD VCC-BUS, VCCE, VDDE, AVCC0 VCCER, EXCVCC, EXCVDD AD0IN0-AD0IN15 VREF0 XOUT AD0IN0-AD0IN15, VREF0, XOUT Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.7.5 Port Peripheral Circuit Diagram (5) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-43 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.8 Notes on Input/Output Ports 8.8 Notes on Input/Output Ports • When using input/output ports in output mode Because the value of the Port Data Register is undefined when exiting the reset state, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it. • When using input/output ports in intput mode After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period. • About the port input disable function Because the input/output ports are disabled against input upon exiting reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has "L" level input applied. Consequently, if a peripheral input function (uncontrolled pin) is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the "L" level input on it. • About the port peripheral function select register setting The Port Peripheral Function Select Register can only be set when the corresponding bit of the Port Operation Mode Register is "0." • About the pereipheral function input when it is set to the gereral-purpose port In the pin for both peripheral function input and general-purpose port, "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Therefore, when "L" level is entered to the peripheral function input pin, edge signal is entered to the peripheral function input at manipulating operation mode register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8-44 CHAPTER 9 DMAC 9.1 9.2 9.3 9.4 Outline of DMAC DMAC Related Registers Functional Description of DMAC Notes on DMAC 9 9.1 Outline of DMAC DMAC 9.1 Outline of DMAC The 32185/32186 group internally contains a 10-channel DMAC (Direction Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Number of channels Description 10 channels • Request from internal peripheral I/Os: A/D converter, multijunction timer, serial interface (reception completed, transmit buffer empty), CAN or DRI • DMA channels can be cascaded (Note 1) Maximum number of times transferred Transferable address space (Note 2) • 32185: 48 Kbytes (address space from H'0080 0000 to H'0080 BFFF) • 32186: 64 Kbytes + 16 Kbytes (address space from H’0080 0000 to H’0081 3FFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. Transfer data size Transfer method Transfer mode Direction of transfer 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dualaddress transfer Single transfer mode One of three modes can be selected for the source and destination: • Address fixed • Address incremental • Ring buffered (can be selected from 32, 16, 8, 4 or 2 times) Channel priority Maximum transfer rate Interrupt request Transfer area (Note 2) DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) 13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz) Group interrupt request can be generated when each transfer count register underflows. 32185: 48 Kbytes from H'0080 0000 to H'0080 BFFF 32186: 64 Kbytes + 16 Kbytes from H’0080 0000 to H’0081 3FFF (Transferable in the entire RAM/SFR area) Note 1: The DMA channels can be cascaded in the manner described below. • Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0 • Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register) • Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1 • Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2 • Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2 • Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3 • Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5 • Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6 • Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7 • Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7 • Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8 Note 2: The source address and destination address cannot go over the bank, which can be only transferred to the same bank or another one from a certain bank. 65,536 times Transfer request sources • Software trigger 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-2 9 Input event bus 3210 DMAC 9.1 Outline of DMAC Output event bus 0123 (Note 2) A/D0 conversion completed (Note 1) TIN0S TIO8_udf TIN30S TIO9_udf TID0_udf/ovf (Note 2) CAN0_S0/S31 TOU1_0irq (Note 2) DRI(DIN0) (Note 2) SIO4_TXD S (Note 2) A/D0 conversion completed TIO8_udf Software start S DMA0 udf end (Note 1) TIN3S TID1_udf/ovf TOU1_1irq (Note 2) DRI(DIN1) SIO4_RXD S Software start S DMA1 udf end (Note 2) CAN0_S1/S30 (Note 2) DRI(DIN2) SIO5_TXD S Software start (Note 1) TIN18S S DMA2 udf end (Note 1) TIN0S TOU1_6irq (Note 2) DRI(DIN3) SIO5_RXD S Software start (Note 2) SIO0_TXD (Note 2) SIO1_RXD S DMA3 udf end (Note 1) TIN19S (Note 2) SIO0_TXD TOU1_7irq (Note 1) TIN7S (Note 2) DRI(DIN4) S Software start (Note 2) SIO0_RXD S DMA4 udf end DMA0-4 interrupts Software start (Note 1) TIN20S TOU0_0irq (Note 1) TIN8S (Note 2) DRI(DEC0_udf) (Note 2) CAN1_S0/S31 S (Note 2) SIO2_RXD S DMA5 udf end TOU0_1irq (Note 2) SIO1_RXD (Note 2) DRI Address counter 0 transfer completed (Note 2) DRI(DEC1_udf) S (Note 2) CAN0_S0/S31 Software start (Note 2) SIO1_TXD S DMA6 udf end TOU0_2irq (Note 2) SIO3_TXD (Note 2) DRI Address counter 1 transfer completed (Note 2) DRI(DEC2_udf) (Note 2) CAN1_S1/S30 Software start (Note 2) SIO2_TXD S (Note 2) CAN0_S1/S30 S DMA7 udf end TOU0_6irq (Note 2) CAN1_S0/S31 (Note 2) DRI Latch event counter_udf (Note 2) DRI(DEC3_udf) S Software start (Note 2) SIO3_RXD S DMA8 udf end TOU0_7irq (Note 2) DRI Transfer counter_udf (Note 2) DRI(DEC4_udf) (Note 2) DRI(DIN5) 3210 Software start (Note 2) SIO3_TXD (Note 2) CAN1_S1/S30 S S DMA9 udf end DMA5-9 interrupts 0123 Note 1: Indicates edge select input at the timer input pin. Note 2: Indicates an input signal from each peripheral circuit. Figure 9.1.1 Block Diagram of the DMAC 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-3 9 9.2 DMAC Related Registers DMAC 9.2 DMAC Related Registers The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address b0 H'0080 0400 +0 address b7 b8 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register (DM04ITST) (DM04ITMK) (Use inhibited area) DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) DMA1 Channel Control Register 0 DMA1 Channel Control (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) DMA6 Channel Control Register 0 DMA6 Channel Control (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) DMA2 Channel Control Register 0 DMA2 Channel Control (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Transfer Count Register (DM2TCT) DMA7 Channel Control Register 0 DMA7 Channel Control (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) DMA3 Channel Control Register 0 DMA3 Channel Control (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) Register 1 +1 address b15 9-35 9-36 See pages | H'0080 0408 9-35 9-36 | H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 9-6 9-7 9-30 9-31 9-32 Register 1 9-16 9-17 9-30 9-31 9-32 Register 1 9-8 9-9 9-30 9-31 9-32 Register 1 9-18 9-19 9-30 9-31 9-32 Register 1 9-10 9-11 9-30 9-31 9-32 Register 1 9-20 9-21 9-30 9-31 9-32 Register 1 9-12 9-13 9-30 9-31 9-32 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-4 9 DMAC Related Register Map (2/2) Address b0 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 +0 address b7 b8 DMAC 9.2 DMAC Related Registers +1 address b15 See pages 9-22 9-23 9-30 9-31 9-32 9-14 9-15 9-30 9-31 9-32 9-24 9-25 9-30 9-31 9-32 9-29 9-29 9-29 9-29 9-29 | H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 (DM8CNT0) (DM8CNT1) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) (Use inhibited area) DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) Register Register Register Register Register 9-29 9-29 9-29 9-29 9-29 | H'0080 0480 H'0080 0482 H'0080 0484 H'0080 0486 H'0080 0488 | H'0080 0490 H'0080 0492 H'0080 0494 H'0080 0496 H'0080 0498 (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) DMA0 Channel Control (DM0CNT2) DMA1 Channel Control (DM1CNT2) DMA2 Channel Control (DM2CNT2) DMA3 Channel Control (DM3CNT2) DMA4 Channel Control (DM4CNT2) (Use inhibited area) DMA5 Channel Control (DM5CNT2) DMA6 Channel Control (DM6CNT2) DMA7 Channel Control (DM7CNT2) DMA8 Channel Control (DM8CNT2) DMA9 Channel Control (DM9CNT2) Register 2 Register 2 Register 2 Register 2 Register 2 9-26 9-26 9-26 9-26 9-26 Register 2 Register 2 Register 2 Register 2 Register 2 9-26 9-26 9-26 9-26 9-26 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-5 9 9.2.1 DMA Channel Control Registers DMA0 Channel Control Register 0 (DM0CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL0 0 3 0 4 TENL0 0 5 0 6 0 MDSEL0 TREQF0 TSZSL0 SADSL0 DADSL0 b 0 1 2, 3 Bit Name MDSEL0 DMA0 transfer mode select bit TREQF0 DMA0 transfer request flag bit REQSL0 DMA0 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start or one DMA2 transfer completed 01: A/D0 conversion completed 10: MJT (TIO8_udf) 11: Extended DMA0 transfer request source select (DMA0 Channel Control Register 1) 4 5 6 7 TENL0 DMA0 transfer enable bit TSZSL0 DMA0 transfer size select bit SADSL0 DMA0 source address direction select bit DADSL0 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed R R R R W W W W R W R(Note 1) R R W W DMA0 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-6 9 DMA0 Channel Control Register 1 (DM0CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN0 DADBN0 REQESEL0 b 8, 9 Bit Name SADBN0 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN0 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL0 Extended DMA0 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: MJT (input event bus 2) 0001: MJT (TID0_udf/ovf) 0010: CAN (CAN0_S0/S31) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_0irq) 1110: DRI (DIN0) 1111: SIO4_TXD (transimit buffer empty) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-7 9 DMA1 Channel Control Register 0 (DM1CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL1 0 3 0 4 TENL1 0 5 0 6 0 MDSEL1 TREQF1 TSZSL1 SADSL1 DADSL1 b 0 1 2, 3 Bit Name MDSEL1 DMA1 transfer mode select bit TREQF1 DMA1 transfer request flag bit REQSL1 DMA1 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (output event bus 0) 10: Settings inhibited 11: Extended DMA1 transfer request source select (DMA1 Channel Control Register 1) 4 5 6 7 TENL1 DMA1 transfer enable bit TSZSL1 DMA1 transfer size select bit SADSL1 DMA1 source address direction select bit DADSL1 DMA1 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-8 9 DMA1 Channel Control Register 1 (DM1CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN1 DADBN1 REQESEL1 b 8, 9 Bit Name SADBN1 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN1 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL1 Extended DMA1 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: One DMA0 transfer completed 0001: MJT(TIN3S) 0010: MJT(TID1_udf/ovf) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_1irq) 1110: DRI (DIN1) 1111: SIO4_RXD (reception completed) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-9 9 DMA2 Channel Control Register 0 (DM2CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL2 3 0 4 TENL2 5 TSZSL2 6 0 MDSEL2 TREQF2 SADSL2 DADSL2 0 0 0 b 0 1 2, 3 Bit Name MDSEL2 DMA2 transfer mode select bit TREQF2 DMA2 transfer request flag bit REQSL2 DMA2 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (output event bus 1) 10: MJT (TIN18S) 11: Extended DMA2 transfer request source select (DMA2 Channel Control Register 1) 4 5 6 7 TENL2 DMA2 transfer enable bit TSZSL2 DMA2 transfer size select bit SADSL2 DMA2 source address direction select bit DADSL2 DMA2 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-10 9 DMA2 Channel Control Register 1 (DM2CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN2 DADBN2 REQESEL2 b 8, 9 Bit Name SADBN2 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN2 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL2 Extended DMA2 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: One DMA1 transfer completed 0001: Settings inhibited 0010: CAN(CAN0_S1/S30) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: Settings inhibited 1110: DRI (DIN2) 1111: SIO5_TXD (transmit buffer empty) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-11 9 DMA3 Channel Control Register 0 (DM3CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL3 0 3 0 4 TENL3 0 5 TSZSL3 0 6 0 MDSEL3 TREQF3 SADSL3 DADSL3 b 0 1 2, 3 Bit Name MDSEL3 DMA3 transfer mode select bit TREQF3 DMA3 transfer request flag bit REQSL3 DMA3 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO0_TXD (transmit buffer empty) 10: SIO1_RXD (reception completed) 11: Extended DMA3 transfer request source select (DMA3 Channel Control Register 1) 4 5 6 7 TENL3 DMA3 transfer enable bit TSZSL3 DMA3 transfer size select bit SADSL3 DMA3 source address direction select bit DADSL3 DMA3 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-12 9 DMA3 Channel Control Register 1 (DM3CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN3 DADBN3 REQESEL3 b 8, 9 Bit Name SADBN3 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN3 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL3 Extended DMA3 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: MJT(TIN0S) 0001: One DMA2 transfer completed 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_6irq) 1110: DRI (DIN3) 1111: SIO5_RXD (reception completed) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-13 9 DMA4 Channel Control Register 0 (DM4CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL4 3 0 4 TENL4 5 TSZSL4 6 0 MDSEL4 TREQF4 SADSL4 DADSL4 0 0 0 b 0 1 2, 3 Bit Name MDSEL4 DMA4 transfer mode select bit TREQF4 DMA4 transfer request flag bit REQSL4 DMA4 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: One DMA3 transfer completed 10: SIO0_RXD (reception completed) 11: Extended DMA4 transfer request source select (DMA4 Channel Control Register 1) 4 5 6 7 TENL4 DMA4 transfer enable bit TSZSL4 DMA4 transfer size select bit SADSL4 DMA4 source address direction select bit DADSL4 DMA4 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-14 9 DMA4 Channel Control Register 1 (DM4CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN4 DADBN4 REQESEL4 b 8, 9 Bit Name SADBN4 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN4 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL4 Extended DMA4 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: MJT(TIN19S) 0001: SIO0_TXD (transmit buffer empty) 0010: MJT(TOU1_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TIN7S) 1110: DRI (DIN4) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-15 9 DMA5 Channel Control Register 0 (DM5CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 DADSL5 1 0 2 REQSL5 3 0 4 TENL5 5 TSZSL5 6 SADSL5 MDSEL5 TREQF5 0 0 0 0 0 b 0 1 2, 3 Bit Name MDSEL5 DMA5 transfer mode select bit TREQF5 DMA5 transfer request flag bit REQSL5 DMA5 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start or one DMA7 transfer completed 01: All DMA0 transfers completed 10: SIO2_RXD (reception completed) 11: Extended DMA5 transfer request source select (DMA5 Channel Control Register 1) 4 5 6 7 TENL5 DMA5 transfer enable bit TSZSL5 DMA5 transfer size select bit SADSL5 DMA5 source address direction select bit DADSL5 DMA5 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-16 9 DMA5 Channel Control Register 1 (DM5CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN5 DADBN5 REQESEL5 b 8, 9 Bit Name SADBN5 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN5 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL5 Extended DMA5 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: MJT(TIN20S) 0001: MJT(TOU0_0irq) 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TIN8S) 1110: DRI (DEC0_udf) 1111: CAN1_S0/S31 Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-17 9 DMA6 Channel Control Register 0 (DM6CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL6 3 0 4 TENL6 5 0 6 0 MDSEL6 TREQF6 TSZSL6 SADSL6 DADSL6 0 0 b 0 1 2, 3 Bit Name MDSEL6 DMA6 transfer mode select bit TREQF6 DMA6 transfer request flag bit REQSL6 DMA6 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO1_TXD (transmit buffer empty) 10: CAN0_S0/S31 11: Extended DMA6 transfer request source select (DMA6 Channel Control Register 1) 4 5 6 7 TENL6 DMA6 transfer enable bit TSZSL6 DMA6 transfer size select bit SADSL6 DMA6 source address direction select bit DADSL6 DMA6 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-18 9 DMA6 Channel Control Register 1 (DM6CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN6 DADBN6 REQESEL6 b 8, 9 Bit Name SADBN6 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN6 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL6 Extended DMA6 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: One DMA5 transfer completed 0001: MJT(TOU0_1irq) 0010: SIO1_RXD (reception completed) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (address counter 0 transfer) 1110: DRI (DEC1_udf) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-19 9 DMA7 Channel Control Register 0 (DM7CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL7 3 0 4 TENL7 5 TSZSL7 6 0 MDSEL7 TREQF7 SADSL7 DADSL7 0 0 0 b 0 1 2, 3 Bit Name MDSEL7 DMA7 transfer mode select bit TREQF7 DMA7 transfer request flag bit REQSL7 DMA7 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO2_TXD (transmit buffer empty) 10: CAN0_S1/S30 11: Extended DMA7 transfer request source select (DMA7 Channel Control Register 1) 4 5 6 7 TENL7 DMA7 transfer enable bit TSZSL7 DMA7 transfer size select bit SADSL7 DMA7 source address direction select bit DADSL7 DMA7 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-20 9 DMA7 Channel Control Register 1 (DM7CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN7 DADBN7 REQESEL7 b 8, 9 Bit Name SADBN7 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN7 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL7 Extended DMA7 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: One DMA6 transfer completed 0001: MJT(TOU0_2irq) 0010: SIO3_TXD (transmit buffer empty) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (address counter 1 transfer) 1110: DRI (DEC2_udf) 1111: CAN1_S1/S30 Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-21 9 DMA8 Channel Control Register 0 (DM8CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL8 3 0 4 TENL8 5 TSZSL8 6 0 MDSEL8 TREQF8 SADSL8 DADSL8 0 0 0 b 0 1 2, 3 Bit Name MDSEL8 DMA8 transfer mode select bit TREQF8 DMA8 transfer request flag bit REQSL8 DMA8 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (input event bus 0) 10: SIO3_RXD (reception completed) 11: Extended DMA8 transfer request source selected (DMA8 Channel Control Register 1) 4 5 6 7 TENL8 DMA8 transfer enable bit TSZSL8 DMA8 transfer size select bit SADSL8 DMA8 source address direction select bit DADSL8 DMA8 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-22 9 DMA8 Channel Control Register 1 (DM8CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN8 DADBN8 REQESEL8 b 8, 9 Bit Name SADBN8 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN8 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL8 Extended DMA8 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: CAN1_S0/S31 0001: MJT(TOU0_6irq) 0010: One DMA7 transfer completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (latch event counter_udf) 1110: DRI (DEC3_udf) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-23 9 DMA9 Channel Control Register 0 (DM9CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL9 3 0 4 TENL9 5 0 6 0 MDSEL9 TREQF9 TSZSL9 SADSL9 DADSL9 0 0 b 0 1 2, 3 Bit Name MDSEL9 DMA9 transfer mode select bit TREQF9 DMA9 transfer request flag bit REQSL9 DMA9 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO3_TXD (transmit buffer empty) 10: CAN1_S1/S30 11: Extended DMA9 transfer request source selected (DMA9 Channel Control Register 1) 4 5 6 7 TENL9 DMA9 transfer enable bit TSZSL9 DMA9 transfer size select bit SADSL9 DMA9 source address direction select bit DADSL9 DMA9 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R W R W R W R W R W R(Note 1) R R W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-24 9 DMA9 Channel Control Register 1 (DM9CNT1) b8 0 DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 SADBN9 DADBN9 REQESEL9 b 8, 9 Bit Name SADBN9 Source address bank select bit (Note 1) (Note 2) 10, 11 DADBN9 Destination address bank select bit (Note 1) (Note 2) 12–15 REQESEL9 Extended DMA9 transfer request source select bit Function 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 00: Bank 0 (A14=0, A15=0) 01: Bank 1 (A14=0, A15=1) 10: Settings inhibited 11: Settings inhibited 0000: One DMA8 transfer completed 0001: MJT(TOU0_7irq) 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (transfer counter_udf) 1110: DRI (DEC4_udf) 1111: DRI (DIN5) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the source/destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank1 does not exist in the 32185, setting Bank1 (A14=0, A15=1) is prohibited. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-25 9 DMA0 Channel Control Register 2 (DM0CNT2) DMA1 Channel Control Register 2 (DM1CNT2) DMA2 Channel Control Register 2 (DM2CNT2) DMA3 Channel Control Register 2 (DM3CNT2) DMA4 Channel Control Register 2 (DM4CNT2) DMA5 Channel Control Register 2 (DM5CNT2) DMA6 Channel Control Register 2 (DM6CNT2) DMA7 Channel Control Register 2 (DM7CNT2) DMA8 Channel Control Register 2 (DM8CNT2) DMA9 Channel Control Register 2 (DM9CNT2) b8 SELFEN DMAC 9.2 DMAC Related Registers b15 0 9 0 10 0 11 0 12 0 13 0 14 0 RINGSEL 0 b 8 9 10–15 Bit Name SELFEN Self channel transfer selection No function assigned. Fix to "0." RINGSEL Ring buffer select bit 00 0000: 32-time ring buffer mode 10 0000: 32-time ring buffer mode 11 0000: 16-time ring buffer mode 11 1000: 8-time ring buffer mode 11 1100: 4-time ring buffer mode 11 1110: 2-time ring buffer mode Settings other than above are inhibited Function 0: Disable self channel transfer 1: Enable self channel transfer 0 R – W R R W W The DMA Channel Control Register 0 consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions. The DMA Channel Control Register 1 consists of the bits to select a source/destination address bank and the cause or source of extended DMA transfer request on each DMA channel. The DMA Channel Control Register 2 consists of the bits to enable self channel transfer on each channel and set the number of transfers in the ring buffer mode. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-26 9 [DMnCNT0 Register] (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0) DMAC 9.2 DMAC Related Registers When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. The number of transfers in the ring buffer mode is selected with register DMnCNT2. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag indicates if there are DMA transfer requests for each channel. This bit is set to “1,” when DMA transfer requests are occurred in spite of TENLn bit setting value and then after completing transmission it is cleared to “0.” And when write “0” to this bit, it clear DMA transfer requests occurred. When write “1,” it keeps value which before writing. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1," the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2, 3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) When setting this bit to “1” (enable transfer), DMA transfer is enable and when all transmissions are completed (underflow of transfer count register), it is “0” cleared. And when DMA transfer request is already occurred and set to transfer enable, DMA transfer starts immediately so that make sure not to do that. When setting this bit to “0” (disable transfer), DMA transfer is disable. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1." (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental. Extended DMA transfer request source selected S DMAn transfer request source S DMAn Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-27 9 [DMnCNT1 Register] (1) SADBNx (DMAn Source Address Bank Select) bits (Bits 8, 9) DMAC 9.2 DMAC Related Registers These bits select a source address bank to be used from among Bank 0, Bank 1. But Bank1 does not exist in the 32185, setting Bank1 is prohibited. Also, no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is then to be transferred to the head address. (2) DADBNx (DMAn Destination Address Bank Select) bits (Bits 10, 11) These bits select a destination address bank to be used from among Bank 0, Bank 1. But Bank1 does not exist in the 32185, setting Bank1 is prohibited. Also, no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is then to be transferred to the head address. (3) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15) These bits select the cause or source of extended DMA transfer request on each DMA channel. Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer request source is selected with the DMA Channel Control Register’s DMA Request Source Select (REQSLn) bits. [DMnCNT2 Register] (1) SELFEN (DMAn Self Channel Transfer Select ) bit (Bit 8) Clearing this bit to “0” disables self channel transfer, and setting it to “1” enables self channel transfer. In case where self channel transfer was allowed, the DMA transfer request occurs for the self channel each time single DMA transfer is completed if the initial transfer request arises, and DMA transfer is carried out until all transfers are completed (transfer count register underflow). However the control of internal bus is relinquished each time single DMA transfer is completed. And if set DMA transfer n times, DMA transfer request is occured for its channel after completing all DMA transfer, so that it is necessary to pay attention of clearing DMA transfer request or so on when DMA transger is started again. (2) RINGSEL (DMAn Rign Buffer Select) bit (Bits 10–15) These bits select the number of DMA transfers to each channel in the ring buffer mode from among 32, 16, 8, 4 and 2 times. In the ring buffer mode, after transfer from the transfer start address, the bit returns to the transfer start address again, and the same operation is repeated by the number of transfers thus selected. In the ring buffer mode, the transfer count register is placed in the free run mode, and transfer operation is continued until the transfer enable bit is cleared to “0” (transfer disable). Also, during the ring buffer mode the DMA transfer completed interrupt request does not occur. Notes: • When the self channel transfer was allowed during ring buffer mode setting, care must be exercised to its endless transfer. • The transfer start address must be as follows: Transfer Size: 8 bits Low order 5 bits – B’00000 Low order 4 bits – B’0000 Low order 3 bits – B’000 Low order 2 bits – B’00 Low order 1 bits – B’0 Transfer Size: 16 bits Low order 6 bits – B’000000 Low order 5 bits – B’00000 Low order 4 bits – B’0000 Low order 3 bits – B’000 Low order 3 bits – B’00 32-time ring buffer mode 16-time ring buffer mode 8-time ring buffer mode 4-time ring buffer mode 2-time ring buffer mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-28 9 9.2.2 DMA Software Request Generation Registers DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 7 8 9 10 ? DMAC 9.2 DMAC Related Registers 11 ? 12 ? 13 ? 14 ? b15 ? DM0SRI–DM9SRI ? ? ? ? b 0–15 Bit Name DM0SRI–DM9SRI DMA software request generation bits Function DMA transfer request is generated by writing any data to these bits. R ? W W Note: • This register may be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when “Software start” has been selected for the cause of DMA transfer request. (1) DM0SRI–DM9SRI (DMA Software Request Generation) bits A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-29 9 9.2.3 DMA Source Address Registers DMA0 Source Address Register (DM0SA) DMA1 Source Address Register (DM1SA) DMA2 Source Address Register (DM2SA) DMA3 Source Address Register (DM3SA) DMA4 Source Address Register (DM4SA) DMA5 Source Address Register (DM5SA) DMA6 Source Address Register (DM6SA) DMA7 Source Address Register (DM7SA) DMA8 Source Address Register (DM8SA) DMA9 Source Address Register (DM9SA) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 8 9 ? 10 ? DMAC 9.2 DMAC Related Registers 11 ? 12 ? 13 ? 14 ? b15 ? DM0SA–DM9SA ? ? b 0–15 Bit Name DM0SA–DMA9SA Function Source address bits A16–A31 (Note 1) Note 1: A0 to A15 are fixed by DMAn Channel Control Register 1 (DMnCNT1) bits 8 and 9. Notes: • This register must always be accessed in halfwords. • Address other than SFR area and internal RAM area must be set. R R W W The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA–DM9SA (Source Address bits A16–A31) Set this register to specify the source address of DMA transfer in the SFR area or internal RAM area. For high-order 16 bits (A0 to A15) of the source address, Bank 0 to Bank 2 are selected according to the setting of DMAn channel control register 1 (DMnCNT1) bits 8 and 9, and the high-order 16 bits of the corresponding source address are fixed. In this register, the low-order 16 bits of the source address are set. (Bit 0 and bit 15 correspond to A16 and A31 of the source address, respectively) Note that no transfer over the bank is carried out when "increment" is selected in SADSLn bit of DMAn channel control register(DMnCNT0). Upon completion of bank transfer to the final address, the bank is to be transferred to the head address. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-30 9 9.2.4 DMA Destination Address Registers DMA0 Destination Address Register (DM0DA) DMA1 Destination Address Register (DM1DA) DMA2 Destination Address Register (DM2DA) DMA3 Destination Address Register (DM3DA) DMA4 Destination Address Register (DM4DA) DMA5 Destination Address Register (DM5DA) DMA6 Destination Address Register (DM6DA) DMA7 Destination Address Register (DM7DA) DMA8 Destination Address Register (DM8DA) DMA9 Destination Address Register (DM9DA) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 8 9 ? 10 ? DMAC 9.2 DMAC Related Registers 11 ? 12 ? 13 ? 14 ? b15 ? DM0DA–DM9DA ? ? b 0–15 Bit Name DM0DA–DM9DA Function Destination address bits A16–A31 (Note 1) Note 1: A0 to A15 are fixed by DMAn Channel Control Register 1 (DMnCNT1) bits 10 and 11. Notes: • This register must always be accessed in halfwords • Address other than SFR area and internal RAM area must be set. R R W W The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA–DM9DA (Destination Address bits A16–A31) Set this register to specify the destination address of DMA transfer in the SFR area or internal RAM area. For high-order 16 bits (A0 to A15) of the destination address, Bank 0 to Bank 2 are selected according to the setting of DMAn channel control register 1 (DMnCNT1) bits 10 and 11, and the highorder 16 bits of the corresponding destination address are fixed. In this register, the low-order 16 bits of the destination address are set. (Bit 0 and bit 15 correspond to A16 and A31 of the destination address, respectively) Note that no transfer over the bank is carried out when "increment" is selected in SADSLn bit of DMAn channel control register(DMnCNT0). Upon completion of bank transfer to the final address, the bank is to be transferred to the head address. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-31 9 9.2.5 DMA Transfer Count Registers DMA0 Transfer Count Register (DM0TCT) DMA1 Transfer Count Register (DM1TCT) DMA2 Transfer Count Register (DM2TCT) DMA3 Transfer Count Register (DM3TCT) DMA4 Transfer Count Register (DM4TCT) DMA5 Transfer Count Register (DM5TCT) DMA6 Transfer Count Register (DM6TCT) DMA7 Transfer Count Register (DM7TCT) DMA8 Transfer Count Register (DM8TCT) DMA9 Transfer Count Register (DM9TCT) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 7 8 9 10 ? DMAC 9.2 DMAC Related Registers 11 ? 12 ? 13 ? 14 ? b15 ? DM0TCT–DM15TCT ? ? ? ? b 0–15 Bit Name DM0TCT–DM9TCT (Has no effect during ring buffer mode) Note: • This register must always be accessed in halfwords. Function DMA transfer count R R W W The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the "value set in the transfer count register + 1." Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H’FFFF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-32 9 9.2.6 DMA Interrupt Related Registers DMAC 9.2 DMAC Related Registers The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0." Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Group interrupt Interrupt request from each peripheral function Set Data = 0 clear Interrupt request status Data bus F/F F/F Interrupt request enabled To the Interrupt Controller Figure 9.2.2 Interrupt Request Status and Mask Registers 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-33 9 Example for clearing interrupt request status Interrupt request status b4 5 0 6 0 b7 0 DMAC 9.2 DMAC Related Registers Initial state 0 Interrupt request Event occurs on bit 6 0 0 1 0 Event occurs on bit 4 Write to the interrupt request status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Event occurs on bit 6 0 Read 0 0 1 0 Event occurs on bit 4 1 0 1 0 Clear bit 6 (AND'ing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 9.2.3 Example for Clearing Interrupt Request Status 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-34 9 DMA0–4 Interrupt Request Status Register (DM04ITST) b0 0 DMAC 9.2 DMAC Related Registers 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 b 0–2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." DMITST4 (DMA4 interrupt request status bit) DMITST3 (DMA3 interrupt request status bit) DMITST2 (DMA2 interrupt request status bit) DMITST1 (DMA1 interrupt request status bit) DMITST0 (DMA0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5–9 Interrupt Request Status Register (DM59ITST) b0 0 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 b 0–2 3 4 5 6 Bit Name No function assigned. Fix to "0." DMITST9 (DMA9 interrupt request status bit) DMITST8 (DMA8 interrupt request status bit) DMITST7 (DMA7 interrupt request status bit) DMITST6 (DMA6 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) 7 DMITST5 (DMA5 interrupt request status bit) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0–9) is set to "1," it means that a DMA interrupt request on the corresponding channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note: • The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register’s “interrupt request bit” included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1." Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-35 9 DMA0–4 Interrupt Request Mask Register (DM04ITMK) b8 0 DMAC 9.2 DMAC Related Registers 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." DMITMK4 (DMA4 interrupt request mask bit) DMITMK3 (DMA3 interrupt request mask bit) DMITMK2 (DMA2 interrupt request mask bit) DMITMK1 (DMA1 interrupt request mask bit) DMITMK0 (DMA0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W DMA5–9 Interrupt Request Mask Register (DM59ITMK) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." DMITMK9 (DMA9 interrupt request mask bit) DMITMK8 (DMA8 interrupt request mask bit) DMITMK7 (DMA7 interrupt request mask bit) DMITMK6 (DMA6 interrupt request mask bit) DMITMK5 (DMA5 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. However, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-36 9 DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) DMA4UDF Data bus b3 b11 DMA3UDF b4 b12 DMA2UDF b5 b13 DMA1UDF b6 b14 DMA0UDF b7 b15 DMITST0 F/F DMITMK0 F/F DMITST1 F/F DMITMK1 F/F DMITST2 F/F DMITMK2 F/F DMITST3 F/F DMITMK3 F/F DMITST4 F/F DMITMK4 F/F 5-source inputs (Level) DMAC 9.2 DMAC Related Registers DMA transfer interrupt request 0 Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0 DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) DMA9UDF Data bus b3 b11 DMA8UDF b4 b12 DMA7UDF b5 b13 DMA6UDF b6 b14 DMA5UDF b7 b15 DMITST5 F/F DMITMK5 F/F DMITST6 F/F DMITMK6 F/F DMITST7 F/F DMITMK7 F/F DMITST8 F/F DMITMK8 F/F DMITST9 F/F DMITMK9 F/F 5-source inputs (Level) DMA transfer interrupt request 1 Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-37 9 9.3 Functional Description of DMAC 9.3.1 DMA Transfer Request Sources DMAC 9.3 Functional Description of DMAC For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, in software by a program, or upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0 REQSL0 0 0 DMA Transfer Request Source Software start or one DMA2 transfer completed 0 1 1 1 0 1 A/D0 conversion completed MJT (TIO8_udf) Extended DMA0 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA0 Software Request Generation Register (software start) or when one DMA2 transfer is completed (cascade mode) When A/D0 conversion is completed When MJT TIO8 underflows The source selected by the DMA0 Channel Control Register 1 (DM0CNT1) REQESEL0 bits (see below) REQESEL0 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MJT (input event bus 2) MJT (TID0_udf/ovf) CAN (CAN0_S0/S31) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited MJT (TOU1_0irq) DRI (DIN0) SIO4_TXD (transmit buffer empty) DMA Transfer Request Generation Timing When MJT input event bus 2 signal is generated When MJT TID0 underflow/overflow occurs When CAN0 slot 0 transmission failed or slot 31 transmission/reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When MJT TOU1_0 interrupt request is generated When DRI DIN0 event detection interrupt is generated When SIO4 transmit buffer empty interrupt is generated 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-38 9 REQSL1 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 0) Settings inhibited Extended DMA1 transfer request source selected DMAC 9.3 Functional Description of DMAC Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 DMA Transfer Request Generation Timing When any data is written to the DMA1 Software Request Generation Register When MJT output event bus 0 signal is generated – The source selected by the DMA1 Channel Control Register 1 (DM1CNT1) REQESEL1 bits (see below) DMA Transfer Request Generation Timing When one DMA0 transfer is completed (cascade mode) When MJT TIN3 input signal is generated When MJT TID1 underflow/overflow occurs When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When TOU1_1 interrupt request is generated When DRI DIN1 event detection interrupt is generated When SIO4 reception-completed interrupt is generated REQESEL1 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 One DMA0 transfer completed MJT (TIN3S) MJT (TID1_udf/ovf) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited MJT (TOU1_1irq) DRI (DIN1) SIO4_RXD (reception completed) Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 1) MJT (TIN18S) Extended DMA2 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA2 Software Request Generation Register When MJT output event bus 1 signal is generated When MJT TIN18 input signal is generated The source selected by the DMA2 Channel Control Register 1 (DM2CNT1) REQESEL2 bits (see below) DMA Transfer Request Generation Timing When one DMA1 transfer is completed (cascade mode) – When CAN0 slot 1 transmission failed or slot 30 transmission/reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – – When DRI DIN2 event detection interrupt is generated When SIO5 transmit buffer empty interrupt is generated REQESEL2 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 One DMA1 transfer completed Settings inhibited CAN(CAN0_S1/S30) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited Settings inhibited DRI (DIN2) SIO5_TXD (transmit buffer empty) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-39 9 REQSL3 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start SIO0_TXD (transmit buffer empty) SIO1_RXD (reception completed) Extended DMA3 transfer request source selected DMAC 9.3 Functional Description of DMAC Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 DMA Transfer Request Generation Timing When any data is written to the DMA3 Software Request Generation Register When SIO0 transmit buffer is empty When SIO1 reception is completed The source selected by the DMA3 Channel Control Register 1 (DM3CNT1) REQESEL3 bits (see below) DMA Transfer Request Generation Timing When MJT TIN0 input signal is generated When one DMA2 transfer is completed (cascade mode) – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When MJT TOU1_6 interrupt request is generated When DRI DIN3 event detection interrupt is generated When SIO5 reception-completed interrupt is generated REQESEL3 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MJT (TIN0S) One DMA2 transfer completed Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited MJT (TOU1_6irq) DRI (DIN3) SIO5_RXD (reception completed) Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start One DMA3 transfer completed SIO0_RXD (reception completed) Extended DMA4 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA4 Software Request Generation Register When one DMA3 transfer is completed (cascade mode) When SIO0 reception is completed The source selected by the DMA4 Channel Control Register 1 (DM4CNT1) REQESEL4 bits (see below) DMA Transfer Request Generation Timing When MJT TIN19 input signal is generated When SIO0 transmit buffer is empty MJT TOU1_7 interrupt source When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When MJT TIN7 input signal is generated When DRI DIN4 event detection interrupt is generated – REQESEL4 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MJT (TIN19S) SIO0_TXD (transmit buffer empty) MJT (TOU1_7irq) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited MJT (TIN7S) DRI (DIN4) Settings inhibited 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-40 9 REQSL5 00 0 1 1 1 0 1 DMA Transfer Request Source Software start or one DMA7 transfer completed All DMA0 transfers completed SIO2_RXD (reception completed) Extended DMA5 transfer request source selected DMA Transfer Request Source MJT (TIN20S) MJT (TOU0_0irq) Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited MJT (TIN8S) DRI (DEC0_udf) CAN1_S0/S31 DMAC 9.3 Functional Description of DMAC Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 DMA Transfer Request Generation Timing When any data is written to the DMA5 Software Request Generation Register or when one DMA7 transfer is completed (cascade mode) When all DMA0 transfers are completed (cascade mode) When SIO2 reception is completed The source selected by the DMA5 Channel Control Register 1 (DM5CNT1) REQESEL5 bits (see below) DMA Transfer Request Generation Timing When MJT TIN20 input signal is generated MJT TOU0_0 interrupt source – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When MJT TIN8 input signal is generated When DRI DEC0 underflow occurs When CAN1 slot 0 transmission failed or slot 31 transmission/reception finished REQESEL5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6 REQSL6 00 01 10 11 DMA Transfer Request Source Software start SIO1_TXD (transmit buffer empty) CAN0_S0/S31 Extended DMA6 transfer request source selected DMA Transfer Request Source One DMA5 transfer completed MJT (TOU0_1irq) SIO1_RXD (reception completed) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited DRI address counter 0 transfer completed DRI (DEC1_udf) Settings inhibited DMA Transfer Request Generation Timing When any data is written to the DMA6 Software Request Generation Register When SIO1 transmit buffer is empty When CAN0 slot 0 transmission failed or slot 31 transmission/reception finished The source selected by the DMA6 Channel Control Register 1 (DM6CNT1) REQESEL6 bits (see below) DMA Transfer Request Generation Timing When one DMA5 transfer is completed (cascade mode) MJT TOU0_1 interrupt source When SIO1 reception is completed When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When DRI address counter 0 transfer completed When DRI DEC1 underflow occurs – REQESEL6 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-41 9 REQSL7 00 01 10 11 DMA Transfer Request Source Software start SIO2_TXD (transmit buffer empty) CAN0_S1/S30 Extended DMA7 transfer request source selected DMA Transfer Request Source One DMA6 transfer completed MJT (TOU0_2irq) SIO3_TXD (transmit buffer empty) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited DRI address counter 1 transfer completed DRI (DEC2_udf) CAN1_S1/S30 DMAC 9.3 Functional Description of DMAC Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 DMA Transfer Request Generation Timing When any data is written to the DMA7 Software Request Generation Register When SIO2 transmit buffer is empty When CAN0 slot 1 transmission failed or slot 30 transmission/reception finished The source selected by the DMA7 Channel Control Register 1 (DM7CNT1) REQESEL7 bits (see below) DMA Transfer Request Generation Timing When one DMA6 transfer is completed (cascade mode) MJT TOU0_2 interrupt source When SIO3 transmit buffer is empty When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When DRI address counter 1 transfer completed When DRI DEC2 underflow occurs When CAN1 slot 1 transmission failed or slot 30 transmission/reception finished REQESEL7 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8 REQSL8 00 01 10 11 DMA Transfer Request Source Software start MJT (input event bus 0) SIO3_RXD (reception completed) Extended DMA8 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA8 Software Request Generation Register When MJT input event bus 0 signal is generated When SIO3 reception is completed The source selected by the DMA8 Channel Control Register 1 (DM8CNT1) REQESEL8 bits (see below) DMA Transfer Request Generation Timing When CAN1 slot 0 transmission failed or slot 31 transmission/reception finished MJT TOU0_6 interrupt source When one DMA7 transfer is completed (cascade mode) When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When DRI latch event counter underflow occurs When DRI DEC3 underflow occurs – REQESEL8 DMA Transfer Request Source 0000 CAN1_S0/S31 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MJT (TOU0_6irq) One DMA7 transfer completed Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited DRI latch event counter_udf DRI (DEC3_udf) Settings inhibited 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-42 9 REQSL9 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start SIO3_TXD (transmit buffer empty) CAN1_S1/S30 Extended DMA9 transfer request source selected DMAC 9.3 Functional Description of DMAC Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 DMA Transfer Request Generation Timing When any data is written to the DMA9 Software Request Generation Register When SIO3 transmit buffer is empty When CAN1 slot 1 transmission failed or slot 30 transmission/reception finished The source selected by the DMA9 Channel Control Register 1 (DM9CNT1) REQESEL9 bits (see below) REQESEL9 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 One DMA8 transfer completed MJT (TOU0_7irq) Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) A/D0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Common 8) MJT (TIN30S) Common 9) MJT (TIO9_udf) Common 10) Settings inhibited DRI transfer counter_udf DRI (DEC4_udf) DRI (DIN5) DMA Transfer Request Generation Timing When one DMA8 transfer is completed (cascade mode) MJT TOU0_7 interrupt source – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A/D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs When MJT TIN30 input signal is generated When MJT TIO9 underflow occurs – When DRI transfer counter underflow occurs When DRI DEC4 underflow occurs When DRI DIN5 event detection interrupt is generated 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-43 9 9.3.2 DMA Transfer Processing Procedure DMAC 9.3 Functional Description of DMAC Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0. DMA transfer processing starts Setting interrupt controller-related registers Set the interrupt controller's DMA0-4 Interrupt Control Register • Interrupt priority level Set DMA0 Channel Control Register 0 • Transfers disabled Set DMA0-4 Interrupt Request Status Register • Interrupt request status bits cleared • Interrupt request enabled Set DMA0-4 Interrupt Request Mask Register Setting DMAC-related registers Set DMA0 Source Address Register • Source address of transfer Set DMA0 Destination Address Register • Destination address of transfer Set DMA0 Count Register • Number of times DMA transfer is performed • Transfer mode, request source, transfer size, address direction, bank and transfer enable Set DMA0 Channel Control Registers 0, 1 and 2 Starting DMA transfer DMA transfer starts as requested by internal peripheral I/O Transfer count register underflows DMA transfer completed Interrupt request generated DMA operation completed Figure 9.3.1 Example of a DMA Transfer Processing Procedure 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-44 9 9.3.3 Starting DMA DMAC 9.3 Functional Description of DMAC Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1." DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1." Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to five cycles (250 ns when the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Chapter 23 ELECTRICAL CHARACTERISTICS) 9.3.4 DMA Channel Priority DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the channel that has the highest priority is selected. 9.3.5 Gaining and Releasing Control of Internal Bus For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write peripheral clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA. Requested Internal bus arbitration (requests from the DMAC) Gained Requested Gained Requested Gained CPU Internal bus Released Released Released DMAC R W R W R W One DMA transfer One DMA transfer R: Read W: Write One DMA transfer Figure 9.3.2 Gaining and Releasing Control of the Internal Bus 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-45 9 9.3.6 Transfer Units DMAC 9.3 Functional Description of DMAC Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. 9.3.8 Address Space The address space in which data can be transferred by DMA is SFR area or internal RAM area (32185: H'0080 0000 to H'0080 BFFF, 32186: H’0080 0000 to H’0081 3FFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register. Note that no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is to be transferred to the head address. 9.3.9 Transfer Operation (1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and the other for destination write access. (The transfer data is taken into the DMAC’s internal temporary register before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycles to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: 1 Maximum transfer rate [bytes per second] = 2 bytes × 1/f(BCLK) × 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds (“Address fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Address fixed Address incremental Transfer Unit 8 bits 16 bits 8 bits 16 bits Address Change for One DMA 0 0 +1 +2 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-46 9 (5) Transfer count value (6) Transfer byte positions DMAC 9.3 Functional Description of DMAC The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer. +0 b0 Source 8 bits b7 b8 8 bits +1 b15 +0 b0 b7 b8 16 bits +1 b15 Destination 8 bits 8 bits 16 bits Figure 9.3.3 Transfer Byte Positions (7) Ring buffer mode In the ring buffer mode, the number of DMA transfers to each channel can be selected from among 32, 16, 8, 4 and 2 times, and after transfer from the transfer start address, the bit returns to the transfer start address again: thus, the same operation is repeated by the selected frequency. Note: • The transfer start address must be as follows: Transfer Size: 8 bits Low order 5 bits – B’00000 Low order 4 bits – B’0000 Low order 3 bits – B’000 Low order 2 bits – B’00 Low order 1 bits – B’0 Transfer Size: 16 bits Low order 6 bits – B’000000 Low order 5 bits – B’00000 Low order 4 bits – B’0000 Low order 3 bits – B’000 Low order 2 bits – B’00 32-time ring buffer mode 16-time ring buffer mode 8-time ring buffer mode 4-time ring buffer mode 2-time ring buffer mode The address increment operation in the ring buffer mode is as follows. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to B’00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to B’000000 by the next increment operation, thus returning to the start address again. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-47 9 DMAC 9.3 Functional Description of DMAC If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1001 H'0080 1002 Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1002 H'0080 1004 | 31 32 ↓ 1 2 | H'0080 101E H'0080 101F ↓ H'0080 1000 H'0080 1001 | 31 32 ↓ 1 2 | H'0080 103C H'0080 103E ↓ H'0080 1000 H'0080 1002 | | | | Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode 9.3.10 End of DMA and Interrupt In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 Each Register Status after Completion of DMA Transfer When DMA transfer is completed, the status of the source and destination address registers becomes as follows: (1) Address fixed • The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental • For 8-bit transfer, the values of the address registers are the last transfer address + 1. • For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 65,536 times (H’FFFF). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-48 9 9.4 Notes on DMAC • About writing to the DMAC related registers DMAC 9.4 Notes on DMAC Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write upon exiting the reset state or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enabled Transfer disabled DMA transfer enable bit Can be accessed Can be accessed DMA transfer request flag bit Can be accessed Can be accessed DMAC interrupt related registers Can be accessed Can be accessed Other DMAC related registers Cannot be accessed Can be accessed Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register 0 transfer enable bit and transfer request flag For all bits other than transfer enable bit and transfer request flag in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself. • Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.) • About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write. • About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except transfer enable bits of the DMA channel control register 0, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-49 9 DMAC 9.4 Notes on DMAC This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 9-50 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Outline of Multijunction Timers Common Units of Multijunction Timers TOP (Output-Related 16-Bit Timer) TIO (Input/Output-Related 16-Bit Timer) TMS (Input-Related 16-Bit Timer) TML (Input-Related 32-Bit Timer) TID (Input-Related 16-Bit Timer) TOU (Output-Related 24-Bit Timer) 10 10.1 Outline of Multijunction Timers MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the “multijunction” timers. The 32185/32186 has six types of MJT as listed in the table below, providing a total of 55-channel timers. Table 10.1.1 Outline of MJT Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) No. of Channels 11 Description One of three output modes can be selected by software. • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TIO (Timer Input Output) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) TID (Timer Input Derivation) TOU (Timer Output Unification) Output-related 24-bit timer (down-counter) (16-bit timer during PWM output and single-shot PWM output modes) 16 Input-related 16-bit timer (up/down-counter)) 2 One of four input modes can be selected by software. • Fixed period mode • Event count mode • Multiply-by-4 event count mode • Up/down event count mode One of five output modes can be selected by software. • PWM output mode • Single-shot PWM output mode • Delayed single-shot output mode • Single-shot output mode • Continuous output mode Input-related 32-bit timer (up-counter) 8 32-bit input measure timer Input-related 16-bit timer (up-counter) 8 16-bit input measure timer 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-2 10 Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ18 TIO0–3 output TOP6, TOP7 output TOP0–5 output TIO8, TIO9 output TIO4–7 output TOP10 output TOP8, TOP9 output TMS0, TMS1 output TIN7–TIN11 input TIN0 input TIN16–TIN19 input TIN20–TIN27 input TIN3–TIN6 input TOU0_0–TOU0_7 output TID0 output TID1 output TOU1_0–TOU1_7 output TIN30–TIN33 input Source of Interrupt MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers No. of ICU Input Sources 4 2 6 2 4 1 2 2 5 1 4 8 4 8 1 1 8 4 MJT output interrupt 0 MJT output interrupt 1 MJT output interrupt 2 MJT output interrupt 3 MJT output interrupt 4 MJT output interrupt 5 MJT output interrupt 6 MJT output interrupt 7 MJT input interrupt 0 MJT input interrupt 1 MJT input interrupt 2 MJT input interrupt 3 MJT input interrupt 4 TOU0 output interrupt TID0 output interrupt TID1 output interrupt TOU1 output interrupt TML1 input interrupt Table 10.1.3 DMA Transfer Request Generation by MJT Corresponding DMAC Channel No. DMA0 DMA Transfer Request Source TIO8_udf Input event bus 2 TID0_udf/ovf TOU1_0irq Common transfer request source (see Table 10.1.4) DMA1 Output event bus 0 TIN3 input signal TID1_udf/ovf TOU1_1irq Common transfer request source (see Table 10.1.4) DMA2 Output event bus 1 TIN18 input signal Common transfer request source (see Table 10.1.4) DMA3 TIN0 input signal TOU1_6irq Common transfer request source (see Table 10.1.4) DMA4 TIN19 input signal TOU1_7irq TIN7 input signal Common transfer request source (see Table 10.1.4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-3 10 DMA5 TIN20 input signal TOU0_0irq TIN8 input signal MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Common transfer request source (see Table 10.1.4) DMA6 DMA7 DMA8 TOU0_1irq Common transfer request source (see Table 10.1.4) TOU0_2irq Common transfer request source (see Table 10.1.4) Input event bus 0 TOU0_6irq Common transfer request source (see Table 10.1.4) DMA9 TOU0_7irq Common transfer request source (see Table 10.1.4) Table 10.1.4 DMA Transfer Request Generation by MJT (Common) Corresponding DMAC Channel No. DMAn DMA Transfer Request Source Input event bus 1 Input event bus 3 Output event bus 2 Output event bus 3 TIN0 input signal TIN30 input signal TIO8_udf TIO9_udf Table 10.1.5 A/D Conversion Start Request by MJT Signal Name AD0TRG A/D Conversion Start Request Source Input event bus 2, input event bus 3, output event bus 3, TIN23 A/D Converter Can be input to A/D0 conversion start trigger 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-4 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus S TCLK0 (P124) TCLK0S IRQ9 clk clk clk IRQ2 0123 en en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 TOP 7 udf IRQ2 F/F0 F/F1 IRQ2 TO0 (P110) TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116) TO7 (P117) udf udf IRQ2 F/F2 F/F3 TIN0 (P150) TIN0S DMA3,DMA commom S clk clk clk udf IRQ2 BCLK 1/2 1/4 PRS0 PRS1 PRS2 udf IRQ2 F/F4 F/F5 IRQ1 udf udf IRQ1 S S S S S clk clk S S IRQ6 F/F6 F/F7 udf clk clk clk en en en en/cap en/cap en/cap en/cap en/cap TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf IRQ0 IRQ6 S S IRQ5 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106) TO15 (P107) S S IRQ0 IRQ12 S S clk clk S clk S clk udf udf IRQ0 TIN3 (P153) TIN4 (P30) TIN5 (P31) TIN3S TIN4S TIN5S DMA1 IRQ12 IRQ12 S S IRQ0 udf udf udf S IRQ4 IRQ12 S S clk S TIN6 (P32) TIN6S S TCLK1 (P125) TIN7 (P33) TCLK2 (P126) TIN8 (P44) TCLK1S TIN7S TCLK2S TIN8S DMA5 IRQ8 DMA4 IRQ8 IRQ4 IRQ8 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO16 (P93) S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO17 (P94) S S clk TIN9 (P45) TIN9S IRQ8 en/cap TIO 7 udf DMA0 DMA common IRQ3 S F/F18 TO18 (P95) S S clk TIN10 (P46) TIN10S IRQ8 en/cap TIO 8 udf S IRQ3 F/F19 TO19 (P96) S S 3210 3210 clk TIN11 (P47) TIN11S en/cap TIO 9 udf DMA common 0123 F/F20 TO20 (P97) PRS0-4 : Prescalers F/F : Output flip-flop S : Selector Notes: • IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts. • DMA0-9 and DMA common denote DMA request signals to the DMAC. • AD0TRG denotes trigger signal to the A/D0 converter. Figure 10.1.1 Block Diagram of MJT (1/4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-5 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0123 TCLK3 (P127) TCLK3S S S clk cap3 TMS 0 cap2 cap1 cap0 ovf IRQ7 S S S S IRQ10 clk cap3 S TMS 1 cap2 cap1 cap0 ovf IRQ7 TIN16/PWMOFF0 (P130) TIN17/PWMOFF1 (P131) TIN18 (P132) TIN16S IRQ10 TIN17S IRQ10 S TIN18S DMA2 IRQ10 S TIN19 (P133) BCLK 1/2 1/4 TIN19S DMA4 S S IRQ11 clk cap3 S TML 0 (32-bit) cap2 cap1 cap0 TIN20 (P134) TIN20S DMA5 IRQ11 TIN21 (P135) TIN21S IRQ11 S TIN22 (P136) TIN22S IRQ11 S TIN23 (P137) TIN23S S (To A/D0 converter) AD0TRG S IRQ18 clk cap3 S TML 1 (32-bit) cap2 cap1 cap0 TIN30 (P34) TIN30S DMA common IRQ18 TIN31 (P35) TIN31S IRQ18 S TIN32 (P36) TIN32S IRQ18 S AD0TRG (to A/D0 converter) TIN33 (P37) TIN33S AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) S 3210 3210 0123 Figure 10.1.2 Block Diagram of MJT (2/4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-6 10 TIN16/PWMOFF0 (P130) PWMOFF0S MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0 IRQ13 PO0DIS clk clk clk clk clk clk clk IRQ11 en TOU0_0 (24-bit) en TOU0_1 (24-bit) en TOU0_2 (24-bit) en TOU0_3 (24-bit) en TOU0_4 (24-bit) en TOU0_5 (24-bit) en TOU0_6 (24-bit) en TOU0_7 (24-bit) CLK1 CLK2 TID 0 S udf DMA5 IRQ13 F/F21 F/F22 DMA6 IRQ13 TO21 (P00/P87) TO22 (P01/P86) TO23 (P02/P85) TO24 (P03/P84) TO25 (P04/P83) TO26 (P05/P82) TO27 (P06/P175) TO28 (P07/P174) udf udf DMA7 IRQ13 F/F23 F/F24 udf IRQ13 udf IRQ13 F/F25 F/F26 IRQ13 udf udf DMA8 IRQ13 F/F27 F/F28 DMA9 IRQ14 DMA0 TIN24S BCLK 1/4 PRS3 S clk clk udf ovf udf TIN24 (P103) TIN25 (P104) TIN25S TIN17/PWMOFF1 (P131) PWMOFF1S IRQ11 clk clk clk clk clk clk clk IRQ11 IRQ16 PO1DIS en TOU1_0 (24-bit) en TOU1_1 (24-bit) en TOU1_2 (24-bit) en TOU1_3 (24-bit) en TOU1_4 (24-bit) en TOU1_5 (24-bit) en TOU1_6 (24-bit) en TOU1_7 (24-bit) CLK1 CLK2 TID 1 S udf udf udf DMA0 IRQ16 DMA1 IRQ16 F/F29 F/F30 F/F31 F/F32 TO29 (P10/P110) TO30 (P11/P111) TO31 (P12/P112) TO32 (P13/P113) TO33 (P14/P114) TO34 (P15/P115) TO35 (P16/P116) TO36 (P17/P117) IRQ16 udf IRQ16 udf IRQ16 F/F33 F/F34 IRQ16 udf udf udf DMA4 DMA3 IRQ16 F/F35 F/F36 TIN26S BCLK 1/4 PRS4 S clk clk ovf udf TIN26 (P73) TIN27 (P72) TIN27S IRQ15 DMA1 IRQ11 Figure 10.1.3 Block Diagram of MJT (3/4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-7 10 Input event bus 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0123 (Note 2) A/D0 conversion completed (Note 1) TIN0S TIO8_udf TIN30S TIO9_udf TID0_udf/ovf (Note 2) CAN0_S0/S31 TOU1_0irq (Note 2) DRI(DIN0) (Note 2) SIO4_TXD S (Note 2) A/D0 conversion completed TIO8_udf Software start S DMA0 udf end (Note 1) TIN3S TID1_udf/ovf TOU1_1irq (Note 2) DRI(DIN1) SIO4_RXD S Software start S DMA1 udf end (Note 2) CAN0_S1/S30 (Note 2) DRI(DIN2) SIO5_TXD S Software start (Note 1) TIN18S S DMA2 udf end (Note 1) TIN0S TOU1_6irq (Note 2) DRI(DIN3) SIO5_RXD S Software start (Note 2) SIO0_TXD (Note 2) SIO1_RXD S DMA3 udf end (Note 1) TIN19S (Note 2) SIO0_TXD TOU1_7irq (Note 1) TIN7S (Note 2) DRI(DIN4) S Software start (Note 2) SIO0_RXD S DMA4 udf end DMA0-4 interrupts Software start (Note 1) TIN20S TOU0_0irq (Note 1) TIN8S (Note 2) DRI(DEC0_udf) (Note 2) CAN1_S0/S31 S (Note 2) SIO2_RXD S DMA5 udf end TOU0_1irq (Note 2) SIO1_RXD (Note 2) DRI Address counter 0 transfer completed (Note 2) DRI(DEC1_udf) S (Note 2) CAN0_S0/S31 Software start (Note 2) SIO1_TXD S DMA6 udf end TOU0_2irq (Note 2) SIO3_TXD (Note 2) DRI Address counter 1 transfer completed (Note 2) DRI(DEC2_udf) (Note 2) CAN1_S1/S30 Software start (Note 2) SIO2_TXD S (Note 2) CAN0_S1/S30 S DMA7 udf end TOU0_6irq (Note 2) CAN1_S0/S31 (Note 2) DRI Latch event counter_udf (Note 2) DRI(DEC3_udf) S Software start (Note 2) SIO3_RXD S DMA8 udf end TOU0_7irq (Note 2) DRI Transfer counter_udf (Note 2) DRI(DEC4_udf) (Note 2) DRI(DIN5) 3210 Software start (Note 2) SIO3_TXD S (Note 2) CAN1_S1/S30 S DMA9 udf end DMA5-9 interrupts 0123 Note 1: Indicates edge select input at the timer input pin. Note 2: Indicates an input signal from each peripheral circuit. Figure 10.1.4 Block Diagram of MJT (4/4) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-8 10 The common units of MJT include the following: MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2 Common Units of Multijunction Timers • Prescaler Unit • Clock Bus and Input/Output Event Bus Control Unit • Input Processing Control Unit • Output Flip-flop Control Unit • Interrupt Control Unit 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-9 10 10.2.1 MJT Common Unit Register Map MJT Common Unit Register Map (1/2) Address b0 H'0080 0200 H'0080 0202 H'0080 0204 +0 address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The table below shows a common unit register map of MJT. +1 address b7 b8 b15 See pages 10-12 10-17 10-13 10-13 10-18 | H'0080 0210 H'0080 0212 H'0080 0214 H'0080 0216 H'0080 0218 H'0080 021A Common Count Clock Select Register Clock Bus & Input Event Bus Control Register (CNTCKSEL) (CKIEBCR) Prescaler Register 0 Prescaler Register 1 (PRS0) (PRS1) Prescaler Register 2 Output Event Bus Control Register (PRS2) (OEBCR) (Use inhibited area) TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 1 (TINCR1) TIN Input Processing Control Register 2 (TINCR2) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) (Use inhibited area) F/F Source Select Register 0 (FFS0) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) (Use inhibited area) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 3 (TINIR3) TIN Interrupt Control Register 5 (TINIR5) TIN Interrupt Control Register 7 (TINIR7) 10-21 10-22 10-23 10-24 10-25 10-25 | H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A 10-28 10-29 10-30 10-32 10-30 10-32 (Use inhibited area) (Use inhibited area) (Use inhibited area) | H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 2 (TINIR2) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) 10-38 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-50 10-52 10-55 | H'0080 07D0 H'0080 07D2 H'0080 07D4 H'0080 07D6 Prescaler Register 3 (PRS3) TOU0 Interrupt Request Mask Register (TOU0IMA) 10-13 TOU0 Interrupt Request Status Register (TOU0IST) F/F21-28 Protect Register (FF2128P) F/F21-28 Data Register (FF2128D) 10-56 10-31 10-33 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-10 10 MJT Common Unit Register Map (2/2) Address b0 H'0080 07E0 H'0080 07E2 TIN24,25 Interrupt Request Mask Register (TIN2425IMA) +0 address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers +1 address b7 b8 TIN24,25 Input Processing Control Register (TIN2425CR) TIN24,25 Interrupt Request Status Register (TIN2425IST) b15 See pages 10-26 10-52 | H'0080 0BD0 H'0080 0BD2 H'0080 0BD4 H'0080 0BD6 Prescaler Register 4 (PRS4) TOU1 Interrupt Request Mask Register (TOU1IMA) 10-13 TOU1 Interrupt Request Status Register (TOU1IST) F/F29-36 Protect Register (FF2936P) F/F29-36 Data Register (FF2936D) 10-58 10-31 10-33 | H'0080 0BE0 H'0080 0BE2 TIN26,27 Interrupt Request Mask Register (TIN2627IMA) TIN26,27 Input Processing Control Register (TIN2627CR) TIN26,27 Interrupt Request Status Register (TIN2627IST) 10-26 10-53 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-11 10 Common Count Clock Select Register (CNTCKSEL) b0 PRS012CKS MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.2 Common Count Clock Select Function 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 0 b 0 1–7 Bit Name PRS012CKS Prescaler 0-2, TML0,1 supplied clock select bit No function assigned. Fix to "0." 1, 2 and the TML0, 1 counters are set when the TOP/TIO/TMS are inactive. Function 0: BCLK/4 1: BCLK/2 0 0 R R W W Note 1: Clock switchover takes effect asynchronously with the count clock. This bit can only be set or reset before the prescalers 0, This register is used to select the clock supplied to the prescalers 0–2 and the timers (TML0, 1). (1) PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit (Bit 0) This bit selects the clock supplied to the prescalers 0–2 and the timers TML0 and 1. Setting this bit to 0 selects BCLK/4 (5 MHz when f(CPUCLK) = 80 MHz); setting this bit to 1 selects BCLK/2 (10 MHz when f(CPUCLK) = 80 MHz). BCLK 1/2 BCLK/2 BCLK/4 PRS0 PRS1 PRS2 Clock bus 0 Clock bus 1 Clock bus 2 1/4 S TML0 S TML1 Figure 10.2.1 Block Diagram of the Common Count Clock Select Function 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-12 10 10.2.3 Prescaler Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Prescalers PRS0 to 2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID and TOU) from the internal peripheral clock (BCLK) divided by 2 or 4. The Prescalers PRS3 and 4 are an 8-bit counter, which generates clocks supplied to timerTID and TOU from the internal peripheral clock BCLK or BCLK divided by 4. The values of prescaler registers are initialized to H’00 upon exting the reset state. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation below: 1 Prescaler divide-by ratio = prescaler set value + 1 Prescaler Register 0 (PRS0) Prescaler Register 1 (PRS1) Prescaler Register 2 (PRS2) Prescaler Register 3 (PRS3) Prescaler Register 4 (PRS4) b0 b8 0 0 3 11 4 12 5 13 0 1 9 0 2 10 0 6 14 0 b7 b15 PRS0-PRS4 0 0 b 0–7 (8–15) Bit Name PRS0–PRS4 Prescaler Function Set the prescaler divide-by value R R W W Prescaler Registers 0–2 start counting after exiting the reset state. Prescaler Registers 3, 4 each are activated by setting the TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) or TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) prescaler-n enable (PRSnEN) bit to "1" (count start), upon which the prescaler register value is reloaded and the prescaler starts counting. For details, see Section 10.7, “TID (Input-Related 16-Bit Timer).” If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-13 10 (1) Clock bus MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.4 Clock Bus and Input/Output Event Bus Control Unit The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals Clock Bus 3 2 1 0 Acceptable Signal TCLK0 input Internal prescaler (PRS2) or TCLK3 input Internal prescaler (PRS1) Internal prescaler (PRS0) (2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A/D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals Input Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TIN3 input, output event bus 2 or TIO7 underflow signal TIN0 input or TIN4 input TIO6 underflow signal, TIN5 input TIO5 underflow signal, TIN6 input Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0–3. Output event bus signals are connected to output flip-flops, and can also be connected to the A/D converter and DMAC. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals Output Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TOP8, TIO3, TIO4 or TIO8 underflow signal TOP9 or TIO2 underflow signal TOP7 or TIO1 underflow signal TOP6 or TIO0 underflow signal Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-14 10 Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO(Note 1) Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML TID (16-bit measure input) (32-bit measure input) Fixed period mode Event count mode Multiply-by-4 event count mode Up/down event count mode TOU PWM output mode Single-shot PWM mode Delayed single-shot output mode Single-shot output mode Continuous output mode MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timing at which signals are generated to the output event bus When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated Note 1: TIO5–7 output an underflow signal to the input event bus. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-15 10 Clock bus 3210 3210 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Input event bus Output event bus 0123 TCLK0 (P124) TIN0 (P150) BCLK 1/2 1/4 TCLK0S clk clk clk clk en en en en TOP 6 TOP 7 TOP 8 TOP 9 udf udf udf udf TIN0S PRS0 PRS1 PRS2 TIO 0 TIN3 (P153) TIN3S TIO 1 TIN4 (P30) TIN4S TIO 2 TIO 3 TIO 4 TIN6 (P32) TIN6S udf udf udf udf udf TIN5 (P31) TIN5S S TIO 5 TCLK3 (P127) TCLK3S TIO 6 3210 3210 udf udf udf udf 0123 TIO 7 TIO 8 PRS0–2 : Prescaler Note: S : Selector . This diagram only illustrates the clock bus and input/output event bus, and is partly omitted. Figure 10.2.2 Conceptual Diagram of the Clock Bus and Input/Output Event Bus 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-16 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Clock Bus and Input/Output Event Bus Control Unit has the following registers: • Clock Bus & Input Event Bus Control Register (CKIEBCR) • Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) b8 IEB3S 0 0 0 14 0 9 10 IEB2S 11 0 12 IEB1S 0 13 IEB0S 0 b15 CKB2S 0 b 8, 9 Bit Name IEB3S Input event bus 3 input select bit Function 00: Select external input 3 (TIN3) 01: Select external input 3 (TIN3) 10: Select output event bus 2 11: Select TIO7 output 10, 11 IEB2S Input event bus 2 input select bit 00: Select external input 0 (TIN0) 01: Does not use input event bus 2 10: Select external input 4 (TIN4) 11: Select external input 4 (TIN4) 12 13 14 15 IEB1S Input event bus 1 input select bit IEB0S Input event bus 0 input select bit No function assigned. Fix to "0." CKB2S Clock bus 2 input select bit 0: Select prescaler 2 1: Select external clock 3 (TCLK3) 0: Select external input 5 (TIN5) 1: Select TIO6 output 0: Select external input 6 (TIN6) 1: Select TIO5 output 0 R 0 W R W R W R W R R W W The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-17 10 Output Event Bus Control Register (OEBCR) b8 OEB3S 0 0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 9 10 11 OEB2S 0 12 0 13 OEB1S 0 14 0 b15 OEB0S 0 b 8, 9 Bit Name OEB3S Output event bus 3 input select bit Function 00: Select TOP8 output 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 11 12 13 14 15 No function assigned. Fix to "0." OEB2S Output event bus 2 input select bit No function assigned. Fix to "0." OEB1S Output event bus 1 input select bit No function assigned. Fix to "0." OEB0S Output event bus 0 input select bit 0: Select TOP6 output 1: Select TIO0 output 0: Select TOP7 output 1: Select TIO1 output 0 R 0 W 0: Select TOP9 output 1: Select TIO2 output 0 R 0 W 0 R 0 W R R W W The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus. 10.2.5 Input Processing Control Unit The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input processing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included: • TLCK Input Processing Control Register (TCLKCR) • TIN Input Processing Control Register 0 (TINCR0) • TIN Input Processing Control Register 1 (TINCR1) • TIN Input Processing Control Register 2 (TINCR2) • TIN Input Processing Control Register 3 (TINCR3) • TIN Input Processing Control Register 4 (TINCR4) • TIN24,25 Input Processing Control Register (TIN2425CR) • TIN26,27 Input Processing Control Register (TIN2627CR) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-18 10 Item BCLK/2 or BCLK/4 (Note 1) MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (1) Functions of TCLK Input Processing Control Registers Function BCLK/2 or BCLK/4 (Note 1) Count clock Rising edge TCLK Count clock Falling edge TCLK Count clock Both edges TCLK Count clock "L" level TCLK BCLK/2 or BCLK/4 (Note 1) Count clock "H" level TCLK BCLK/2 or BCLK/4 (Note 1) Count clock Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit of the Common Count Clock Select Register (CNTCKSEL). For details, refer to Section 10.2.2, “Common Count Clock Select Function.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-19 10 Item Rising edge TIN MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (2) Functions of TIN Input Processing Control Registers Function Internal edge signal Falling edge TIN Internal edge signal Both edges TIN Internal edge signal "L" level TIN Prescaler output period or TCLK input period Internal edge signal "H" level TIN Prescaler output period or TCLK input period Internal edge signal 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-20 10 TCLK Input Processing Control Register (TCLKCR) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10 TCLK1S 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 TCLK2S 0 7 8 9 11 12 13 14 0 b15 0 TCLK3S TCLK0S b 0, 1 2, 3 Bit Name No function assigned. Fix to "0." TCLK3S TCLK3 input processing select bit 00: BCLK/2 or BCLK/4 (Note 1) 01: Rising edge 10: Falling edge 11: Both edges 4 5–7 No function assigned. Fix to "0." TCLK2S TCLK2 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 9–11 No function assigned. Fix to "0." TCLK1S TCLK1 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12,13 14,15 No function assigned. Fix to "0." TCLK0S TCLK0 input processing select bit 00: BCLK/2 or BCLK/4 (Note 1) 01: Rising edge 10: Falling edge 11: Both edges110 Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit of the Common Count Clock Select Register (CNTCLKSEL). For details, refer to Section 10.2.2, “Common Count Clock Select Function.” Note: • This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W 0 R 0 W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-21 10 TIN Input Processing Control Register 0 (TINCR0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 9 0 1 0 2 TIN4S 0 3 0 4 0 5 0 6 TIN3S 0 7 0 8 0 10 0 11 0 12 TIN1S 0 13 0 14 0 b15 0 TIN2S TIN0S b 0 1–3 Bit Name No function assigned. Fix to "0." TIN4S TIN4 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 4 5–7 No function assigned. Fix to "0." TIN3S TIN3 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8,9 10,11 12,13 14,15 No function assigned. Fix to "0." TIN2S Reserved bit TIN1S Reserved bit TIN0S TIN0 input processing select bit 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Note: • This register must always be accessed in halfwords. R W Fix to "0." 0 0 Fix to "0." 0 0 0 0 0 R 0 W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-22 10 TIN Input Processing Control Register 1 (TINCR1) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 9 0 1 0 2 TIN8S 0 3 0 4 0 5 0 6 TIN7S 0 7 0 8 0 10 TIN6S 0 11 0 12 0 13 0 14 TIN5S 0 b15 0 b 0 1–3 Bit Name No function assigned. Fix to "0." TIN8S TIN8 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 4 5–7 No function assigned. Fix to "0." TIN7S TIN7 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 9–11 No function assigned. Fix to "0." TIN6S TIN6 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12 13–15 No function assigned. Fix to "0." TIN5S TIN5 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level Note: • This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W 0 R 0 W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-23 10 TIN Input Processing Control Register 2 (TINCR2) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 9 0 1 0 2 0 3 0 4 0 5 0 6 TIN11S 0 7 0 8 0 10 TIN10S 0 11 0 12 0 13 0 14 TIN9S 0 b15 0 b 0–4 5–7 Bit Name No function assigned. Fix to "0." TIN11S TIN11 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 9–11 No function assigned. Fix to "0." TIN10S TIN10 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12 13–15 No function assigned. Fix to "0." TIN9S TIN9 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level Note: • This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-24 10 TIN Input Processing Control Register 3 (TINCR3) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 9 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 10 0 11 0 12 0 13 0 14 0 b15 0 TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN19S (TIN19 input processing select bit) TIN18S (TIN18 input processing select bit) TIN17S (TIN17 input processing select bit) TIN16S (TIN16 input processing select bit) TIN15S (Reserved bit) TIN14S (Reserved bit) TIN13S (Reserved bit) TIN12S (Reserved bit) Function 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Fix to "0." 0 0 R R W W Note: • This register must always be accessed in halfwords. TIN Input Processing Control Register 4 (TINCR4) b0 0 9 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 10 0 11 0 12 0 13 0 14 0 b15 0 TIN33S TIN32S TIN31S TIN30S TIN29S TIN28S TIN27S TIN26S b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN33S (TIN33 input processing select bit) TIN32S (TIN32 input processing select bit) TIN31S (TIN31 input processing select bit) TIN30S (TIN30 input processing select bit) TIN23S (TIN23 input processing select bit) TIN22S (TIN22 input processing select bit) TIN21S (TIN21 input processing select bit) TIN20S (TIN20 input processing select bit) Function 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges R R W W Note: • This register must always be accessed in halfwords. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-25 10 b8 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 14 TIN24S 0 0 0 TIN24,25 Input Processing Control Register (TIN2425CR) 9 0 10 0 11 0 12 TIN25S 0 13 b15 b 8–11 12, 13 14, 15 Bit Name No function assigned. Fix to "0." TIN25S (TIN25 input processing select bit) TIN24S (TIN24 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W TIN26,27 Input Processing Control Register (TIN2627CR) b8 0 14 TIN26S 0 9 0 10 0 11 0 12 TIN27S 0 13 0 b15 0 b 8–11 12, 13 14, 15 Bit Name No function assigned. Fix to "0." TIN27S (TIN27 input processing select bit) TIN26S (TIN26 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W 10.2.6 Output Flip-flop Control Unit The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included: • F/F Source Select Register 0 (FFS0) • F/F Source Select Register 1 (FFS1) • F/F Protect Register 0 (FFP0) • F/F Protect Register 1 (FFP1) • F/F21–28 Protect Register (FF2128P) • F/F29–36 Protect Register (FF2936P) • F/F Data Register 0 (FFD0) • F/F Data Register 1 (FFD1) • F/F21–28 Data Register (FF2128D) • F/F29–36 Data Register (FF2936D) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-26 10 Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML TID (16-bit measure input) (32-bit measure input) Fixed period count mode Event count mode Multiply-by-4 event count mode Up/down event count mode TOU PWM output mode Single-shot PWM output mode Delayed single-shot output mode Single-shot output mode Continuous output mode MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Table 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timing at which signals are generated to the output flip-flop When count is enabled or underflows When counter underflows When count is enabled or underflows When counter underflows When counter underflows When counter underflows When count is enabled or underflows When count is enabled or underflows When counter underflows When count is enabled or underflows No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated When count is enabled or underflows When counter underflows When counter underflows When count is enabled or underflows When count is enabled or underflows F/F source selection (FSn) Port operation mode register (PnMOD) F/F TOP/TIO/TOU udf Output event bus 0 Output event bus 1 Output event bus 2 Output event bus 3 Internal edge signal F/Fn output data (FDn) Data bus WR F/F protect (FPn) Data bus F/F F/F TOn Output control (ON/OFF) Figure 10.2.3 Configuration of the F/F Output Circuit 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-27 10 F/F Source Select Register 0 (FFS0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 7 0 1 0 2 0 3 0 4 0 5 0 6 0 8 FS10 0 9 0 10 FS9 0 11 0 12 FS8 0 13 0 14 FS7 0 b15 FS6 0 FS15 FS14 FS13 FS12 FS11 b 0–2 3 4 5 6 7 8, 9 Bit Name No function assigned. Fix to "0." FS15 F/F15 source select bit FS14 F/F14 source select bit FS13 F/F13 source select bit FS12 F/F12 source select bit FS11 F/F11 source select bit FS10 F/F10 source select bit 0: TIO4 output 1: Output event bus 0 0: TIO3 output 1: Output event bus 0 0: TIO2 output 1: Output event bus 3 0: TIO1 output 1: Output event bus 2 0: TIO0 output 1: Output event bus 1 00: TOP10 output 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS9 F/F9 source select bit 00: TOP9 output 01: TOP9 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS8 F/F8 source select bit 00: TOP8 output 01: Output event bus 0 10: Output event bus 1 11: Output event bus 2 14 15 FS7 F/F7 source select bit FS6 F/F6 source select bit Note: • This register must always be accessed in halfwords. 0: TOP7 output 1: Output event bus 0 0: TOP6 output 1: Output event bus 1 R W R W R W R W R W R W R W R W R W Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-28 10 F/F Source Select Register 1 (FFS1) b8 FS19 0 0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 12 FS17 0 0 0 0 9 10 FS18 11 13 14 FS16 b15 0 b 8, 9 Bit Name FS19 F/F19 source select bit Function 00: TIO8 output 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18 F/F18 source select bit 00: TIO7 output 01: TIO7 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS17 F/F17 source select bit 00: TIO6 output 01: TIO6 output 10: Output event bus 0 11: Output event bus 1 14, 15 FS16 F/F16 source select bit 00: TIO5 output 01: Output event bus 0 10: Output event bus 1 11: Output event bus 3 R W R W R W R R W W These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-29 10 F/F Protect Register 0 (FFP0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 6 FP9 0 1 0 2 0 3 0 4 0 5 0 7 FP8 0 8 FP7 0 9 FP6 0 10 FP5 0 11 FP4 0 12 FP3 0 13 FP2 0 14 FP1 0 b15 FP0 0 FP15 FP14 FP13 FP12 FP11 FP10 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FP15 (F/F15 protect bit) FP14 (F/F14 protect bit) FP13 (F/F13 protect bit) FP12 (F/F12 protect bit) FP11 (F/F11 protect bit) FP10 (F/F10 protect bit) FP9 (F/F9 protect bit) FP8 (F/F8 protect bit) FP7 (F/F7 protect bit) FP6 (F/F6 protect bit) FP5 (F/F5 protect bit) FP4 (F/F4 protect bit) FP3 (F/F3 protect bit) FP2 (F/F2 protect bit) FP1 (F/F1 protect bit) FP0 (F/F0 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W Note: • This register must always be accessed in halfwords. F/F Protect Register 1 (FFP1) b8 0 11 FP20 0 9 0 10 0 12 FP19 0 13 FP18 0 14 FP17 0 b15 FP16 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." FP20 (F/F20 protect bit) FP19 (F/F19 protect bit) FP18 (F/F18 protect bit) FP17 (F/F17 protect bit) FP16 (F/F16 protect bit) 0: Enable write to F/F output bit 1: Disable write to F/F output bit Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-30 10 F/F21–28 Protect Register (FF2128P) b8 FP21 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 12 FP25 0 9 FP22 0 10 FP23 0 11 FP24 0 13 FP26 0 14 FP27 0 b15 FP28 0 b 8 9 10 11 12 13 14 15 Bit Name FP21 (F/F21 protect bit) FP22 (F/F22 protect bit) FP23 (F/F23 protect bit) FP24 (F/F24 protect bit) FP25 (F/F25 protect bit) FP26 (F/F26 protect bit) FP27 (F/F27 protect bit) FP28 (F/F28 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W F/F29–36 Protect Register (FF2936P) b8 FP29 0 12 FP33 0 9 FP30 0 10 FP31 0 11 FP32 0 13 FP34 0 14 FP35 0 b15 FP36 0 b 8 9 10 11 12 13 14 15 Bit Name FP29 (F/F29 protect bit) FP30 (F/F30 protect bit) FP31 (F/F31 protect bit) FP32 (F/F32 protect bit) FP33 (F/F33 protect bit) FP34 (F/F34 protect bit) FP35 (F/F35 protect bit) FP36 (F/F36 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W These registers control write to each output F/F (flip-flop) by enabling or disabling. If write to any output F/F is disabled, writing to the F/F data register has no effect. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-31 10 F/F Data Register 0 (FFD0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 0 1 0 2 0 3 0 4 0 6 FD9 0 7 FD8 0 8 FD7 0 9 FD6 0 10 FD5 0 11 FD4 0 12 FD3 0 13 FD2 0 14 FD1 0 b15 FD0 0 FD15 FD14 FD13 FD12 FD11 FD10 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FD15 (F/F15 output data bit) FD14 (F/F14 output data bit) FD13 (F/F13 output data bit) FD12 (F/F12 output data bit) FD11 (F/F11 output data bit) FD10 (F/F10 output data bit) FD9 (F/F9 output data bit) FD8 (F/F8 output data bit) FD7 (F/F7 output data bit) FD6 (F/F6 output data bit) FD5 (F/F5 output data bit) FD4 (F/F4 output data bit) FD3 (F/F3 output data bit) FD2 (F/F2 output data bit) FD1 (F/F1 output data bit) FD0 (F/F0 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W Note: • This register must always be accessed in halfwords. F/F Data Register 1 (FFD1) b8 0 11 FD20 0 9 0 10 0 12 FD19 0 13 FD18 0 14 FD17 0 b15 FD16 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." FD20 (F/F20 output data bit) FD19 (F/F19 output data bit) FD18 (F/F18 output data bit) FD17 (F/F17 output data bit) FD16 (F/F16 output data bit) 0: F/F output data = 0 1: F/F output data = 1 Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-32 10 F/F21–28 Data Register (FF2128D) b8 FD21 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 12 FD25 0 9 FD22 0 10 FD23 0 11 FD24 0 13 FD26 0 14 FD27 0 b15 FD28 0 b 8 9 10 11 12 13 14 15 Bit Name FD21 (F/F21 output data bit) FD22 (F/F22 output data bit) FD23 (F/F23 output data bit) FD24 (F/F24 output data bit) FD25 (F/F25 output data bit) FD26 (F/F26 output data bit) FD27 (F/F27 output data bit) FD28 (F/F28 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W F/F29–36 Data Register (FF2936D) b8 FD29 0 12 FD33 0 9 FD30 0 10 FD31 0 11 FD32 0 13 FD34 0 14 FD35 0 b15 FD36 0 b 8 9 10 11 12 13 14 15 Bit Name FD29 (F/F29 output data bit) FD30 (F/F30 output data bit) FD31 (F/F31 output data bit) FD32 (F/F32 output data bit) FD33 (F/F33 output data bit) FD34 (F/F34 output data bit) FD35 (F/F35 output data bit) FD36 (F/F36 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W These registers are used to set data in each output F/F (flip-flop). Although F/F output normally changes with timer output, setting data 0 or 1 in this register allows to produce desired output from any F/F. The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-33 10 10.2.7 Interrupt Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer: • TOP Interrupt Control Register 0 (TOPIR0) • TOP Interrupt Control Register 1 (TOPIR1) • TOP Interrupt Control Register 2 (TOPIR2) • TOP Interrupt Control Register 3 (TOPIR3) • TIO Interrupt Control Register 0 (TIOIR0) • TIO Interrupt Control Register 1 (TIOIR1) • TIO Interrupt Control Register 2 (TIOIR2) • TMS Interrupt Control Register (TMSIR) • TIN Interrupt Control Register 0 (TINIR0) • TIN Interrupt Control Register 1 (TINIR1) • TIN Interrupt Control Register 2 (TINIR2) • TIN Interrupt Control Register 3 (TINIR3) • TIN Interrupt Control Register 4 (TINIR4) • TIN Interrupt Control Register 5 (TINIR5) • TIN Interrupt Control Register 6 (TINIR6) • TIN24,25 Interrupt Request Mask Register (TIN2425IMA) • TIN24,25 Interrupt Request Status Register (TIN2425IST) • TIN26,27 Interrupt Request Mask Register (TIN2627IMA) • TIN26,27 Interrupt Request Status Register (TIN2627IST) • TIN Interrupt Control Register 7 (TINIR7) • TOU0 Interrupt Request Mask Register (TOU0IMA) • TOU0 Interrupt Request Status Register (TOU0IST) • TOU1 Interrupt Request Mask Register (TOU1IMA) • TOU1 Interrupt Request Status Register (TOU1IST) For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt request status flags are automatically managed within the Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.” • TOP10 • TID0 • TID1 TOP10 Output Interrupt Request (IRQ5) TID0 Output Interrupt Request (IRQ14) TID1 Output Interrupt Request (IRQ15) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-34 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0." Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the interrupt request status grouped as a group interrupt, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupts within the interrupt request grouped as a group interrupt. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Group interrupt Timer or TIN input interrupt request Set Data = 0 clear Interrupt request status Data bus F/F F/F Interrupt request enabled To the Interrupt Controller Figure 10.2.4 Interrupt Request Status and Mask Registers 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-35 10 Example for clearing interrupt request status MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Interrupt request status b4 5 0 6 b7 0 Initial state 0 0 Interrupt request Event occurs on bit 6 0 0 1 0 Event occurs on bit 4 Write to the interrupt request status b4 1 5 1 6 1 0 1 0 b7 1 1 0 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Event occurs on bit 6 0 Read 0 0 1 0 Event occurs on bit 4 1 0 1 0 Clear bit 6 (ANDing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 10.2.5 Example for Clearing Interrupt Request Status 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-36 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT Signal Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ16 IRQ18 Generated by TIO0, TIO1, TIO2, TIO3 TOP6, TOP7 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TIO8, TIO9 TIO4, TIO5, TIO6, TIO7 TOP8, TOP9 TMS0, TMS1 TIN7, TIN8, TIN9, TIN10, TIN11 TIN0 TIN16, TIN17, TIN18, TIN19 TIN20, TIN21, TIN22, TIN23, TIN24, TIN25 TIN26, TIN27 TIN3, TIN4, TIN5, TIN6 TOU0_0, TOU0_1, TOU0_2, TOU0_3 TOU0_4, TOU0_5, TOU0_6, TOU0_7 TOU1_0, TOU1_1, TOU1_2, TOU1_3 TOU1_4, TOU1_5, TOU1_6, TOU1_7 TIN30, TIN31, TIN32, TIN33 TML1 input interrupt 4 Note 1: See Chapter 5, “Interrupt Controller (ICU).” Note: • TOP10, TID0 and TID1 have only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) TOU1 output interrupt 8 MJT input interrupt 4 TOU0 output interrupt 4 8 Interrupt Request Source (Note 1) MJT output interrupt 0 MJT output interrupt 1 MJT output interrupt 2 MJT output interrupt 3 MJT output interrupt 4 MJT output interrupt 5 MJT output interrupt 6 MJT input interrupt 0 MJT input interrupt 1 MJT input interrupt 2 MJT input interrupt 3 No. of ICU Input Sources 4 2 6 2 4 2 2 5 1 4 8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-37 10 TOP Interrupt Control Register 0 (TOPIR0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 TOPIS2 0 1 0 2 TOPIS5 0 3 TOPIS4 0 4 TOPIS3 0 6 TOPIS1 0 b7 TOPIS0 0 b 0, 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." TOPIS5 (TOP5 interrupt request status bit) TOPIS4 (TOP4 interrupt request status bit) TOPIS3 (TOP3 interrupt request status bit) TOPIS2 (TOP2 interrupt request status bit) TOPIS1 (TOP1 interrupt request status bit) TOPIS0 (TOP0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP Interrupt Control Register 1 (TOPIR1) b8 0 13 TOPIM2 0 9 0 10 TOPIM5 0 11 TOPIM4 0 12 TOPIM3 0 14 TOPIM1 0 b15 TOPIM0 0 b 8, 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TOPIM5 (TOP5 interrupt request mask bit) TOPIM4 (TOP4 interrupt request mask bit) TOPIM3 (TOP3 interrupt request mask bit) TOPIM2 (TOP2 interrupt request mask bit) TOPIM1 (TOP1 interrupt request mask bit) TOPIM0 (TOP0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-38 10 TOPIR0 TOP5udf Data bus b2 b10 TOP4udf b3 b11 TOP3udf b4 b12 TOP2udf b5 b13 TOP1udf b6 b14 TOP0udf b7 b15 TOPIS0 F/F TOPIM0 F/F TOPIS1 F/F TOPIM1 F/F TOPIS2 F/F TOPIM2 F/F TOPIS3 F/F TOPIM3 F/F TOPIS4 F/F TOPIM4 F/F TOPIS5 F/F TOPIM5 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 6-source inputs MJT output interrupt request 2 IRQ2 (Level) Figure 10.2.6 Block Diagram of MJT Output Interrupt Request 2 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-39 10 TOP Interrupt Control Register 2 (TOPIR2) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 0 1 0 2 TOPIS7 0 3 TOPIS6 0 4 0 6 TOPIM7 0 b7 TOPIM6 0 b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0." TOPIS7 (TOP7 interrupt request status bit) TOPIS6 (TOP6 interrupt request status bit) No function assigned. Fix to "0." TOPIM7 (TOP7 interrupt request mask bit) TOPIM6 (TOP6 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOPIR2 TOP9udf Data bus TOPIS9 b10 b14 TOP8udf 2-source inputs MJT output interrupt request 6 IRQ6 F/F TOPIM9 F/F (Level) b11 b15 TOPIS8 F/F TOPIM8 F/F Figure 10.2.8 Block Diagram of MJT Output Interrupt Request 6 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-41 10 TIO Interrupt Control Register 0 (TIOIR0) b0 TIOIS3 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 TIOIM3 0 1 TIOIS2 0 2 TIOIS1 0 3 TIOIS0 0 5 TIOIM2 0 6 TIOIM1 0 b7 TIOIM0 0 b 0 1 2 3 4 5 6 7 Bit Name TIOIS3 (TIO3 interrupt request status bit) TIOIS2 (TIO2 interrupt request status bit) TIOIS1 (TIO1 interrupt request status bit) TIOIS0 (TIO0 interrupt request status bit) TIOIM3 (TIO3 interrupt request mask bit) TIOIM2 (TIO2 interrupt request mask bit) TIOIM1 (TIO1 interrupt request mask bit) TIOIM0 (TIO0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIOIR0 TIO7udf Data bus b8 b12 TIO6udf b9 b13 TIO5udf b10 b14 TIO4udf b11 b15 TIOIS4 F/F TIOIM4 F/F TIOIS5 F/F TIOIM5 F/F TIOIS6 F/F TIOIM6 F/F TIOIS7 F/F TIOIM7 F/F 4-source inputs MJT output interrupt request 4 IRQ4 (Level) Figure 10.2.10 Block Diagram of MJT Output Interrupt Request 4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-43 10 TIO Interrupt Control Register 2 (TIOIR2) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 0 1 0 2 TIOIS9 0 3 TIOIS8 0 5 0 6 TIOIM9 0 b7 TIOIM8 0 b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0." TIOIS9 (TIO9 interrupt request status bit) TIOIS8 (TIO8 interrupt request status bit) No function assigned. Fix to "0." TIOIM9 (TIO9 interrupt request mask bit) TIOIM8 (TIO8 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIOIR2 TMS1ovf Data bus b10 b14 TMS0ovf TMSIS0 b11 b15 F/F TMSIM0 F/F TMSIS1 F/F TMSIM1 F/F (Level) 2-source inputs MJT output interrupt request 7 IRQ7 Figure 10.2.12 Block Diagram of MJT Output Interrupt Request 7 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-45 10 TIN Interrupt Control Register 0 (TINIR0) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 0 1 TINIS2 0 2 TINIS1 0 3 TINIS0 0 5 TINIM2 0 6 TINIM1 0 b7 TINIM0 0 b 0 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." TINIS2 (Reserved bit) TINIS1 (Reserved bit) TINIS0 (TIN0 interrupt request status bit) No function assigned. Fix to "0." TINIM2 (Reserved bit) TINIM1 (Reserved bit) TINIM0 (TIN0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. R W Fix to "0" 0: Interrupt not requested 1: Interrupt requested R (Note 1) 0 0 0 0 Fix to "0" Function R 0 0 W 0 0 TINIR0 TIN6edge Data bus b8 b12 TIN5edge TINIS6 F/F TINIM6 F/F 4-source inputs (Level) MJT input interrupt request 4 IRQ12 TINIS5 b9 b13 TIN4edge F/F TINIM5 F/F b10 b14 TIN3edge TINIS4 F/F TINIM4 F/F b11 b15 TINIS3 F/F TINIM3 F/F Figure 10.2.14 Block Diagram of MJT Input Interrupt Request 4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-47 10 TIN Interrupt Control Register 2 (TINIR2) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 TINIS10 0 1 0 2 0 3 TINIS11 0 5 TINIS9 0 6 TINIS8 0 b7 TINIS7 0 b 0–2 3 4 5 6 7 Bit Name No function assigned. Fix to "0." TINIS11 (TIN11 interrupt request status bit) TINIS10 (TIN10 interrupt request status bit) TINIS9 (TIN9 interrupt request status bit) TINIS8 (TIN8 interrupt request status bit) TINIS7 (TIN7 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN Interrupt Control Register 3 (TINIR3) b8 0 12 13 TINIM9 0 9 0 10 0 11 TINIM11 0 14 TINIM8 0 b15 TINIM7 0 TINIM10 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TINIM11 (TIN11 interrupt request mask bit) TINIM10 (TIN10 interrupt request mask bit) TINIM9 (TIN9 interrupt request mask bit) TINIM8 (TIN8 interrupt request mask bit) TINIM7 (TIN7 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-48 10 TINIR2 TIN11edge Data bus b3 b11 TIN10edge b4 b12 TIN9edge b5 b13 TIN8edge b6 b14 TIN7edge b7 b15 TINIS7 F/F TINIM7 F/F TINIS8 F/F TINIM8 F/F TINIS9 F/F TINIM9 F/F TINIS10 F/F TINIM10 F/F TINIS11 F/F TINIM11 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5-source inputs MJT input interrupt request 0 IRQ8 (Level) Figure 10.2.15 Block Diagram of MJT Input Interrupt Request 0 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-49 10 TIN Interrupt Control Register 4 (TINIR4) b0 TINIS19 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 TINIS15 0 1 TINIS18 0 2 TINIS17 0 3 TINIS16 0 5 TINIS14 0 6 TINIS13 0 b7 TINIS12 0 b 0 1 2 3 4 5 6 7 Bit Name TINIS19 (TIN19 interrupt request status bit) TINIS18 (TIN18 interrupt request status bit) TINIS17 (TIN17 interrupt request status bit) TINIS16 (TIN16 interrupt request status bit) TINIS15 (Reserved bit) TINIS14 (Reserved bit) TINIS13 (Reserved bit) TINIS12 (Reserved bit) Fix to "0" 0 0 Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN Interrupt Control Register 5 (TINIR5) b8 TINIM19 0 12 13 TINIM14 0 9 TINIM18 0 10 TINIM17 0 11 TINIM16 0 14 TINIM13 0 b15 TINIM12 0 TINIM15 0 b 8 9 10 11 12 13 14 15 Bit Name TINIM19 (TIN19 interrupt request mask bit) TINIM18 (TIN18 interrupt request mask bit) TINIM17 (TIN17 interrupt request mask bit) TINIM16 (TIN16 interrupt request mask bit) TINIM15 (Reserved bit) TINIM14 (Reserved bit) TINIM13 (Reserved bit) TINIM12 (Reserved bit) Fix to "0" 0 0 Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-50 10 TINIR4 TIN19edge Data bus b0 b8 TIN18edge TINIS18 b1 b9 TIN17edge b2 b10 TIN16edge b3 b11 TINIS16 F/F TINIM16 F/F TINIS17 F/F TINIM17 F/F F/F TINIM18 F/F TINIS19 F/F TINIM19 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4-source inputs (Level) MJT input interrupt request 2 IRQ10 Figure 10.2.16 Block Diagram of MJT Input Interrupt Request 2 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-51 10 TIN Interrupt Control Register 6 (TINIR6) b0 TINIS23 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 4 TINIM23 0 1 TINIS22 0 2 TINIS21 0 3 TINIS20 0 5 TINIM22 0 6 TINIM21 0 b7 TINIM20 0 b 0 1 2 3 4 5 6 7 Bit Name TINIS23 (TIN23 interrupt request status bit) TINIS22 (TIN22 interrupt request status bit) TINIS21 (TIN21 interrupt request status bit) TINIS20 (TIN20 interrupt request status bit) TINIM23 (TIN23 interrupt request mask bit) TINIM22 (TIN22 interrupt request mask bit) TINIM21 (TIN21 interrupt request mask bit) TINIM20 (TIN20 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN24,25 Interrupt Request Mask Register (TIN2425IMA) b0 0 6 TINIM24 0 1 0 2 0 3 0 4 0 5 0 b7 TINIM25 0 b 0–5 6 7 Bit Name No function assigned. Fix to "0." TINIM24 (TIN24 interrupt request mask bit) TINIM25 (TIN25 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W TIN24,25 Interrupt Request Status Register (TIN2425IST) b8 0 14 TINIS24 0 9 0 10 0 11 0 12 0 13 0 b15 TINIS25 0 b 8–13 14 15 Bit Name No function assigned. Fix to "0." TINIS24 (TIN24 interrupt request status bit) TINIS25 (TIN25 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-52 10 TIN26,27 Interrupt Request Mask Register (TIN2627IMA) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 6 TINIM26 0 1 0 2 0 3 0 4 0 5 0 b7 TINIM27 0 b 0–5 6 7 Bit Name No function assigned. Fix to "0." TINIM26 (TIN26 interrupt request mask bit) TINIM27 (TIN27 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W TIN26,27 Interrupt Request Status Register (TIN2627IST) b8 0 14 TINIS26 0 9 0 10 0 11 0 12 0 13 0 b15 TINIS27 0 b 8–13 14 15 Bit Name No function assigned. Fix to "0." TINIS26 (TIN26 interrupt request status bit) TINIS27 (TIN27 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-53 10 TIN2425IST TIN2627IST TINIR6 TIN33edge Data bus b8 b12 TIN32edge TINIS33 F/F TINIM33 F/F 4-source inputs (Level) TML1 input interrupt request IRQ18 TINIS32 b9 b13 TIN31edge F/F TINIM32 F/F b10 b14 TIN30edge TINIS31 F/F TINIM31 F/F b11 b15 TINIS30 F/F TINIM30 F/F Figure 10.2.18 Block Diagram of TML1 Input Interrupt Request 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-55 10 TOU0 Interrupt Request Mask Register (TOU0IMA) b0 TOU0IM7 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 TOU0IM2 0 1 TOU0IM6 0 2 TOU0IM5 0 3 TOU0IM4 0 4 TOU0IM3 0 6 TOU0IM1 0 b7 TOU0IM0 0 b 0 1 2 3 4 5 6 7 Bit Name TOU0IM7 (TOU0_7 interrupt request mask bit) TOU0IM6 (TOU0_6 interrupt request mask bit) TOU0IM5 (TOU0_5 interrupt request mask bit) TOU0IM4 (TOU0_4 interrupt request mask bit) TOU0IM3 (TOU0_3 interrupt request mask bit) TOU0IM2 (TOU0_2 interrupt request mask bit) TOU0IM1 (TOU0_1 interrupt request mask bit) TOU0IM0 (TOU0_0 interrupt request mask bit) Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W TOU0 Interrupt Request Status Register (TOU0IST) b8 TOU0IS7 0 14 TOU0IS1 0 9 TOU0IS6 0 10 TOU0IS5 0 11 TOU0IS4 0 12 TOU0IS3 0 13 TOU0IS2 0 b15 TOU0IS0 0 b 8 9 10 11 12 13 14 15 Bit Name TOU0IS7 (TOU0_7 interrupt request status bit) TOU0IS6 (TOU0_6 interrupt request status bit) TOU0IS5 (TOU0_5 interrupt request status bit) TOU0IS4 (TOU0_4 interrupt request status bit) TOU0IS3 (TOU0_3 interrupt request status bit) TOU0IS2 (TOU0_2 interrupt request status bit) TOU0IS1 (TOU0_1 interrupt request status bit) TOU0IS0 (TOU0_0 interrupt request status bit) Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-56 10 TOU0IMA TOU07udf MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Data bus b8 b0 TOU06udf TOU0IS7 F/F TOU0IM7 F/F 8-source inputs (Level) TOU0 output interrupt request IRQ13 b9 b1 TOU05udf TOU0IS6 F/F TOU0IM6 F/F b10 b2 TOU04udf TOU0IS5 F/F TOU0IM5 F/F b11 b3 TOU03udf TOU0IS4 F/F TOU0IM4 F/F b12 b4 TOU02udf TOU0IS3 F/F TOU0IM3 F/F b13 b5 TOU01udf TOU0IS2 F/F TOU0IM2 F/F b14 b6 TOU00udf TOU0IS1 F/F TOU0IM1 F/F b15 b7 TOU0IS0 F/F TOU0IM0 F/F Figure 10.2.19 Block Diagram of TOU0 Output Interrupt Request 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-57 10 TOU1 Interrupt Request Mask Register (TOU1IMA) b0 TOU1IM7 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 TOU1IM2 0 1 TOU1IM6 0 2 TOU1IM5 0 3 TOU1IM4 0 4 TOU1IM3 0 6 TOU1IM1 0 b7 TOU1IM0 0 b 0 1 2 3 4 5 6 7 Bit Name TOU1IM7 (TOU1_7 interrupt request mask bit) TOU1IM6 (TOU1_6 interrupt request mask bit) TOU1IM5 (TOU1_5 interrupt request mask bit) TOU1IM4 (TOU1_4 interrupt request mask bit) TOU1IM3 (TOU1_3 interrupt request mask bit) TOU1IM2 (TOU1_2 interrupt request mask bit) TOU1IM1 (TOU1_1 interrupt request mask bit) TOU1IM0 (TOU1_0 interrupt request mask bit) Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W TOU1 Interrupt Request Status Register (TOU1IST) b8 TOU1IS7 0 14 TOU1IS1 0 9 TOU1IS6 0 10 TOU1IS5 0 11 TOU1IS4 0 12 TOU1IS3 0 13 TOU1IS2 0 b15 TOU1IS0 0 b 8 9 10 11 12 13 14 15 Bit Name TOU1IS7 (TOU1_7 interrupt request status bit) TOU1IS6 (TOU1_6 interrupt request status bit) TOU1IS5 (TOU1_5 interrupt request status bit) TOU1IS4 (TOU1_4 interrupt request status bit) TOU1IS3 (TOU1_3 interrupt request status bit) TOU1IS2 (TOU1_2 interrupt request status bit) TOU1IS1 (TOU1_1 interrupt request status bit) TOU1IS0 (TOU1_0 interrupt request status bit) Function 0: Interrupt not requested 1: Interrupt requested R W R (Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-58 10 TOU1IMA TOU17udf Data bus b8 b0 TOU16udf TOU1IS6 b9 b1 TOU15udf b10 b2 TOU14udf b11 b3 TOU13udf b12 b4 TOU12udf b13 b5 TOU11udf b14 b6 TOU10udf b15 b7 TOU1IS0 F/F TOU1IM0 F/F TOU1IS1 F/F TOU1IM1 F/F TOU1IS2 F/F TOU1IM2 F/F TOU1IS3 F/F TOU1IM3 F/F TOU1IS4 F/F TOU1IM4 F/F TOU1IS5 F/F TOU1IM5 F/F F/F TOU1IM6 F/F TOU1IS7 F/F TOU1IM7 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 8-source inputs TOU1 output interrupt request IRQ16 (Level) Figure 10.2.20 Block Diagram of TOU1 Output Interrupt Request 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-59 10 10.3 TOP (Output-Related 16-Bit Timer) 10.3.1 Outline of TOP MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Single-shot output mode • Delayed single-shot output mode • Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TOP, respectively. Table 10.3.1 Specifications of TOP (Output-Related 16-Bit Timer) Item Number of channels Counter Reload register Correction register Timer startup Operation mode Specification 11 channels 16-bit down-counter 16-bit reload register 16-bit correction register Started by writing to the enable bit in software or enabled by external input (rising or falling edge or both) • Single-shot output mode • Delayed single-shot output mode • Continuous output mode Interrupt request generation Can be generated by a counter underflow 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-60 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) Output event bus 0123 TOP 0 Reload register clk Down-counter udf IRQ2 F/F0 TO 0 (P110) S Correction register (16-bit) en IRQ2 TCLK0 (P124) TCLK0S IRQ9 clk clk S clk clk clk clk en en en en en en TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 udf IRQ2 F/F1 F/F2 IRQ2 TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) udf udf IRQ2 TIN0 (P150) TIN0S DMA3, DMA common F/F3 F/F4 IRQ2 udf udf IRQ1 F/F5 S IRQ1 S S S S S udf F/F6 clk en TOP 7 udf IRQ6 S F/F7 TO 7 (P117) clk clk clk en en en TOP 8 TOP 9 TOP 10 udf IRQ6 S S IRQ5 F/F8 F/F9 F/F10 TO 8 (P100) TO 9 (P101) TO 10 (P102) udf udf S 3210 3210 0123 F/F : Output flip-flop S : Selector Figure 10.3.1 Block Diagram of TOP (Output-Related 16-Bit Timer) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-61 10 10.3.2 Outline of Each Mode of TOP (1) Single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, the counter is loaded with the content of “the reload register -1” and starts counting synchronously with the count clock at the next circle. The counter counts down and stops. The F/F output waveform in single-shot output mode is inverted at enable and upon underflow (F/F output level is changed “L” to “H,” or vice versa), generating a single-shot pulse waveform in width of “reload register set value + 1” only once. And also an interrupt request can be generated when the counter underflows. The counter value is “setting value of reload register +1.” (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of “reload register set value + 1” after a finite time equal to “counter set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after first counter underflow, it is loaded with “the reload register value -1” and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level is changed “L” to “H,” or vice versa), when the counter underflows first time and next, generating a single-shot pulse waveform in width of “reload register set value + 1” after a finite time equal to “first set value of counter + 1” only once. And also an interrupt request can be generated when the counter underflows first time and next. The effective counter value is “counter set value +1” or “reload register set value +1.” (3) Continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle after the counter underflows, it is loaded with the value that “ the reload register -1.” Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of “ reload register set value + 1.” When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow, the counter to be loaded with the content of “ the reload register -1” and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level is changed “L” to “H,” or vice versa), at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The effective counter value is “counter set value +1” and “reload register set value +1.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-62 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. Write to the enable bit BCLK Count clock period Count clock Enable F/F operation (Note 1) Count clock-dependent delay Inverted Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Figure 10.3.2 Count Clock Dependent Delay 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-63 10 10.3.3 TOP Related Register Map Shown below is a TOP related register map. TOP Related Register Map (1/2) Address b0 H'0080 0240 H'0080 0242 H'0080 0244 H'0080 0246 +0 address MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) +1 address b7 b8 TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) (Use inhibited area) TOP0 Correction Register (TOP0CC) (Use inhibited area) TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) (Use inhibited area) TOP1 Correction Register (TOP1CC) (Use inhibited area) TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) (Use inhibited area) TOP2 Correction Register (TOP2CC) (Use inhibited area) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) (Use inhibited area) TOP3 Correction Register (TOP3CC) (Use inhibited area) TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) (Use inhibited area) TOP4 Correction Register (TOP4CC) (Use inhibited area) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) (Use inhibited area) TOP5 Correction Register (TOP5CC) (Use inhibited area) b15 See pages 10-71 10-72 10-73 | H'0080 0250 H'0080 0252 H'0080 0254 H'0080 0256 10-71 10-72 10-73 | H'0080 0260 H'0080 0262 H'0080 0264 H'0080 0266 10-71 10-72 10-73 | H'0080 0270 H'0080 0272 H'0080 0274 H'0080 0276 10-71 10-72 10-73 | H'0080 0280 H'0080 0282 H'0080 0284 H'0080 0286 10-71 10-72 10-73 | H'0080 0290 H'0080 0292 H'0080 0294 H'0080 0296 H'0080 0298 10-71 10-72 10-73 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-64 10 TOP Related Register Map (2/2) Address b0 H'0080 029A H'0080 029C (Use inhibited area) +0 address MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) +1 address b7 b8 TOP0–5 Control Register 0 (TOP05CR0) TOP0–5 Control Register 1 (TOP05CR1) (Use inhibited area) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) (Use inhibited area) TOP6 Correction Register (TOP6CC) (Use inhibited area) TOP6,7 Control Register (TOP67CR) (Use inhibited area) TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) (Use inhibited area) TOP7 Correction Register (TOP7CC) (Use inhibited area) TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) (Use inhibited area) TOP8 Correction Register (TOP8CC) (Use inhibited area) TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) (Use inhibited area) TOP9 Correction Register (TOP9CC) (Use inhibited area) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) (Use inhibited area) TOP10 Correction Register (TOP10CC) (Use inhibited area) TOP8–10 Control Register (TOP810CR) (Use inhibited area) TOP0–10 External Enable Permit Register (TOPEEN) TOP0–10 Enable Protect Register (TOPPRO) TOP0–10 Count Enable Register (TOPCEN) b15 See pages 10-67 10-67 | H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA 10-71 10-72 10-73 10-69 | H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6 10-71 10-72 10-73 | H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 02C6 10-71 10-72 10-73 | H'0080 02D0 H'0080 02D2 H'0080 02D4 H'0080 02D6 10-71 10-72 10-73 | H'0080 02E0 H'0080 02E2 H'0080 02E4 H'0080 02E6 H'0080 02E8 H'0080 02EA 10-71 10-72 10-73 10-70 | H'0080 02FA H'0080 02FC H'0080 02FE 10-74 10-74 10-75 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-65 10 10.3.4 TOP Control Registers MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed singleshot output or continuous output mode), as well as select the count enable and count clock sources. Following four TOP control registers are provided for each timer group. • TOP0–5 Control Register 0 (TOP05CR0) • TOP0–5 Control Register 1 (TOP05CR1) • TOP6,7 Control Register (TOP67CR) • TOP8–10 Control Register (TOP810CR) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-66 10 TOP0–5 Control Register 0 (TOP05CR0) b0 0 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS b 0, 1 2, 3 4, 5 6, 7 8 9–11 Bit Name TOP3M (TOP3 operation mode select bit) TOP2M (TOP2 operation mode select bit) TOP1M (TOP1 operation mode select bit) TOP0M (TOP0 operation mode select bit) No function assigned. Fix to "0." TOP05ENS TOP0–5 enable source select bit 000: External TIN0 input 001: External TIN0 input 010: External TIN0 input 011: External TIN0 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 14, 15 No function assigned. Fix to "0." TOP05CKS TOP0–5 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. 0 R 0 W Function 00: Single-shot output mode 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 0 R 0 W R R W W TOP0–5 Control Register 1 (TOP05CR1) b8 0 12 TOP5M 0 9 0 10 0 11 0 13 0 14 TOP4M 0 b15 0 b 8–11 12, 13 14, 15 Bit Name No function assigned. Fix to "0." TOP5M (TOP5 operation mode select bit) TOP4M (TOP4 operation mode select bit) 00: Single-shot output mode 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode Note: • Operation mode can only be set or changed while the counter is inactive. Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-67 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) Input event bus 3210 S clk en TOP 0 TOP 1 clk en clk en TOP 2 clk en TOP 3 clk en TOP 4 clk TIN0 (P150) TIN0S en TOP 5 S S : Selector Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-68 10 TOP6,7 Control Register (TOP67CR) b0 0 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 7 0 1 TOP7ENS 2 0 3 0 4 0 5 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TOP7M TOP6M TOP67ENS TOP67CKS 0 b 0 1 2, 3 Bit Name No function assigned. Fix to "0." TOP7ENS TOP7 enable source select bit TOP7M TOP7 operation mode select bit 0: Result selected by TOP67ENS bit 1: TOP6 output 00: Single-shot output mode 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 4, 5 6, 7 No function assigned. Fix to "0." TOP6M TOP6 operation mode select bit 00: Single-shot output mode 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 8 9–11 No function assigned. Fix to "0." TOP67ENS TOP6, TOP7 enable source select bit 000: Does not select the enable source 001: Does not select the enable source 010: Does not select the enable source 011: Does not select the enable source 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 14, 15 No function assigned. Fix to "0." TOP67CKS TOP6, TOP7 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. 0 R 0 W 0 R 0 W 0 R 0 W R W Function R 0 R W 0 W Clock bus Input event bus 3210 3210 S clk en TOP 6 udf clk S S en TOP 7 udf S : Selector Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-69 10 TOP8–10 Control Register (TOP810CR) b0 0 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 9 0 10 0 11 TOP810 ENS 12 0 13 0 14 0 b15 0 TOP10M TOP9M TOP8M TOP810CKS 0 b 0, 1 2, 3 4, 5 6, 7 8–10 11 12, 13 14, 15 Bit Name No function assigned. Fix to "0." TOP10M (TOP10 operation mode select bit) TOP9M (TOP9 operation mode select bit) TOP8M (TOP8 operation mode select bit) No function assigned. Fix to "0." TOP810ENS TOP8–10 enable source select bit No function assigned. Fix to "0." TOP810CKS TOP8–10 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. 0: Does not select the enable source 1: Input event bus 3 0 R 0 W 00: Single-shot output mode 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 0 R 0 W Function R 0 R W 0 W Clock bus 3210 Input event bus 3210 S clk en TOP 8 clk en TOP 9 clk S en TOP 10 S : Selector Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.5 Outline Diagram of TOP8–10 Clock and Enable Inputs 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-70 10 10.3.5 TOP Counters (TOP0CT–TOP10CT) TOP0 Counter (TOP0CT) TOP1 Counter (TOP1CT) TOP2 Counter (TOP2CT) TOP3 Counter (TOP3CT) TOP4 Counter (TOP4CT) TOP5 Counter (TOP5CT) TOP6 Counter (TOP6CT) TOP7 Counter (TOP7CT) TOP8 Counter (TOP8CT) TOP9 Counter (TOP9CT) TOP10 Counter (TOP10CT) b0 ? MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 5 ? 1 ? 2 ? 3 ? 4 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOP0CT–TOP10CT b 0–15 Bit Name TOP0CT–TOP10CT Function 16-bit counter value R R W W Note: • These registers must always be accessed in halfwords. The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-71 10 TOP0 Reload Register (TOP0RL) TOP1 Reload Register (TOP1RL) TOP2 Reload Register (TOP2RL) TOP3 Reload Register (TOP3RL) TOP4 Reload Register (TOP4RL) TOP5 Reload Register (TOP5RL) TOP6 Reload Register (TOP6RL) TOP7 Reload Register (TOP7RL) TOP8 Reload Register (TOP8RL) TOP9 Reload Register (TOP9RL) TOP10 Reload Register (TOP10RL) b0 ? MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) 7 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOP0RL–TOP10RL b 0–15 Bit Name TOP0RL–TOP10RL Function 16-bit reload register value R R W W Note: • This register must always be accessed in halfwords. The TOP reload registers are used to load data into the TOP counters (TOP0CT–TOP10CT). The content of " the reload register -1" is loaded into the counter synchronously with the count clock at the following timing: • At the next cycle when the counter is enabled in single-shot output mode • At the next cycle when the counter underflowed in delayed single-shot or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. Note that reloading of data after an underflow is performed synchronously with a clock pulse at which the counter underflowed. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-72 10 TOP0 Correction Register (TOP0CC) TOP1 Correction Register (TOP1CC) TOP2 Correction Register (TOP2CC) TOP3 Correction Register (TOP3CC) TOP4 Correction Register (TOP4CC) TOP5 Correction Register (TOP5CC) TOP6 Correction Register (TOP6CC) TOP7 Correction Register (TOP7CC) TOP8 Correction Register (TOP8CC) TOP9 Correction Register (TOP9CC) TOP10 Correction Register (TOP10CC) b0 ? MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) 7 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOP0CC–TOP10CC (Acceptable range of values: +32,767 to –32,768) b 0–15 Bit Name TOP0CC–TOP10CC Function 16-bit correction register value R R W W Note: • These registers must always be accessed in halfwords. The TOP correction registers are used to correct the TOP counter value by adding or subtracting in the middle of operation. To increase or reduce the counter value, write to this correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the initial counter value is 10 and the value 3 is written to the correction register when the counter has counted down to 5, then the counter counts a total of 15 before it underflows. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-73 10 10.3.8 TOP Enable Control Registers TOP0–10 External Enable Permit Register (TOPEEN) b0 0 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10 TOP5 EEN 1 0 2 0 3 0 4 0 5 0 6 0 7 TOP8 EEN 8 TOP7 EEN 9 TOP6 EEN 11 TOP4 EEN 12 TOP3 EEN 13 TOP2 EEN 14 TOP1 EEN b15 TOP0 EEN TOP10 TOP9 EEN EEN 0 0 0 0 0 0 0 0 0 b 0–4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TOP10EEN (TOP10 external enable permit bit) TOP9EEN (TOP9 external enable permit bit) TOP8EEN (TOP8 external enable permit bit) TOP7EEN (TOP7 external enable permit bit) TOP6EEN (TOP6 external enable permit bit) TOP5EEN (TOP5 external enable permit bit) TOP4EEN (TOP4 external enable permit bit) TOP3EEN (TOP3 external enable permit bit) TOP2EEN (TOP2 external enable permit bit) TOP1EEN (TOP1 external enable permit bit) TOP0EEN (TOP0 external enable permit bit) 0: Disable external enable 1: Enable external enable Function R 0 R W 0 W Note: • This register must always be accessed in halfwords. The TOP0–10 External Enable Permit Register controls enable operation on TOP counters from external devices by enabling or disabling it. TOP0–10 Enable Protect Register (TOPPRO) b0 0 8 9 TOP6 PRO 1 0 2 0 3 0 4 0 5 0 6 0 7 TOP8 PRO 10 TOP5 PRO 11 TOP4 PRO 12 TOP3 PRO 13 TOP2 PRO 14 TOP1 PRO b15 TOP0 PRO TOP10 TOP9 PRO PRO TOP7 PRO 0 0 0 0 0 0 0 0 0 b 0–4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TOP10PRO (TOP10 enable protect bit) TOP9PRO (TOP9 enable protect bit) TOP8PRO (TOP8 enable protect bit) TOP7PRO (TOP7 enable protect bit) TOP6PRO (TOP6 enable protect bit) TOP5PRO (TOP5 enable protect bit) TOP4PRO (TOP4 enable protect bit) TOP3PRO (TOP3 enable protect bit) TOP2PRO (TOP2 enable protect bit) TOP1PRO (TOP1 enable protect bit) TOP0PRO (TOP0 enable protect bit) 0: Enable for rewriting 1: Protect against rewriting Function R 0 R W 0 W Note: • This register must always be accessed in halfwords. The TOP0–10 Enable Protect Register controls rewriting of the TOP count enable bit by enabling for or protecting it against rewriting. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-74 10 TOP0–10 Count Enable Register (TOPCEN) b0 0 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 8 TOP7 CEN 1 0 2 0 3 0 4 0 5 0 6 0 7 TOP8 CEN 9 TOP6 CEN 10 TOP5 CEN 11 TOP4 CEN 12 TOP3 CEN 13 TOP2 CEN 14 TOP1 CEN b15 TOP0 CEN TOP10 TOP9 CEN CEN 0 0 0 0 0 0 0 0 0 b 0–4 5 6 7 8 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TOP10CEN (TOP10 count enable bit) TOP9CEN (TOP9 count enable bit) TOP8CEN (TOP8 count enable bit) TOP7CEN (TOP7 count enable bit) TOP6CEN (TOP6 count enable bit) TOP5CEN (TOP5 count enable bit) TOP4CEN (TOP4 count enable bit) TOP3CEN (TOP3 count enable bit) TOP2CEN (TOP2 count enable bit) TOP1CEN (TOP1 count enable bit) TOP0CEN (TOP0 count enable bit) 0: Stop counting 1: Enable counting Function R 0 R W 0 W Note: • This register must always be accessed in halfwords. The TOP0–10 Count Enable Register controls operation of TOP counters. To enable any TOP counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1." To stop any TOP counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0." In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TOP0-10 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. TOPm external enable (TOPmEEN) F/F Input processing selection TINnS Event bus bn TOPm enable protect (TOPmPRO) F/F EN-ON TINn TOPm count enable (TOPmCEN) TOP enable control F/F WR WR Figure 10.3.6 Configuration of the TOP Enable Circuit 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-75 10 (1) Outline of TOP single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) In single-shot output mode, the timer generates a pulse in width of "reload register set value+1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, at the next cycle the counter is loaded with the content of " the reload register -1" and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request can be generated when the counter underflows. The count value is "reload register set value + 1." For example, if the initial reload register value is 7, then the count value is 8. Count value = 8 1 Count clock Enable H'FFFF Counter (Note 1) 6 5 2 3 4 5 6 7 8 4 3 2 1 0 (Note 3) Reload register 7 F/F output Interrupt request (Note 2) Underflow Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 7. Note 2: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 3: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-76 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined, and does not have to be specific.) When the timer starts, the value that " the reload register -1" is loaded into the counter, letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum count. Enabled (by writing to the enable bit or by external input) Disabled (by underflow) Count clock Enable bit (Note 1) H'FFFF H'FFFF Indeterminate value Starts counting down from the reload register set value H'(A000-1) Counter H'0000 (Note 2) Reload register H'A000 Correction register (Unused) F/F output Data inverted by enable Data inverted by underflow TOP interrupt request due to underflow Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-77 10 (2) Correction function of TOP single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the initial counter value is 7 and the value 3 is written to the correction register when the counter has down counted to 3, then the counter counts a total of 12 before it underflows. Count value = (7 + 1) + (3 + 1) = 12 1 Count clock Count clock dependent delay Enable H'FFFF Indeterminate value Counter (Note 1) 2 3 4 5 6 7 8 9 10 11 12 6 5 6 4 3 +3 5 4 3 2 1 (Note 2) Reload register 7 Correction register 3 0 Interrupt request Underflow Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-78 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’8000. When the timer starts, the value that " the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is written to the correction register when the counter has counted down to H’5000. As a result of this correction, the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1) before it stops. Enabled (by writing to the enable bit or by external input) Disabled (by underflow) Count clock Enable bit (Note 1) Write to the correction register H'FFFF H'FFFF Undefined value H'8000 H'5000 + H'4000 H'(8000 - 1) Counter H'5000 (Note 2) H'0000 Reload register H'8000 Correction register Undefined H'4000 F/F output Data inverted by enable Data inverted by underflow TOP interrupt request due to underflow Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-79 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (3) Precautions about using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. • If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled. • When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-80 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’FFF8. When the timer starts, the value that " the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated for an erroneous overflowed count. Enabled (by writing to the enable bit or by external input) Count clock (Note 1) Enable bit Write to the correction register Overflow occurs H'(FFF0+0014) H'FFFF H'FFFF H'FFF8 H'(FFF8-1) H'FFF0 Undefined value Counter (Note 2) Actual count after overflow H'0004 H'0000 H'FFF8 Reload register Undefined Correction register H'0014 F/F output Data inverted by enable Data inverted by underflow TOP interrupt request due to underflow Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-81 10 (1) Outline of TOP delayed single-shot output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that " the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once. An interrupt request can be generated when the counter underflows first time and next. The "counter set value + 1" and "reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Count value = (4 + 1) + (5 + 1) = 11 1 Count clock Count clock dependent delay Enable H'FFFF (Note 1) 4 Counter 3 4 2 1 0 3 H'FFFF 2 3 4 5 6 7 8 9 10 11 2 1 (Note 2) 0 Reload register F/F output 5 Interrupt request Underflow Underflow Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(underflow value), and not 5. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-82 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and at the cycle after it underflows , the counter is loaded with the content of " the reload register -1" and continues counting down. The counter stops when it underflows second time. Enabled (by writing to the enable bit or by external input) Underflow (first time) Underflow (second time) Count clock Enable bit H'FFFF H'FFFF H'F000 Count down from the counter's set value H'(F000-1) Count down from the reload register's set value H'A000 Counter (Note 1) H'0000 Reload register H'F000 Correction register (Unused) F/F output Data inverted by underflow TOP interrupt request due to underflow Data inverted by underflow Note 1: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-83 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (2) Correction function of TOP delayed single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the reload register value is 7 and the value 3 is written to the correction register when the counter has counted down to 3 after being reloaded, then the counter counts a total of 12 after being reloaded before it underflows. Count value after being reloaded = (7 + 1) + (3 + 1) = 12 1 Count clock Enable = "H" H'FFFF (Note 1) Counter 6 6 4 3 +3 H'FFFF 2 3 4 5 6 7 8 9 10 11 12 5 5 4 3 2 0 1 (Note 2) 0 Reload register 7 Correction register 3 Interrupt request Underflow Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(the underflow value), and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.14 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-84 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and at the cycle after the first underflow, the counter is loaded with the content of " the reload register -1" and continues counting down. In the diagram below, the value H’0008 is written to the correction register when the counter has counted down to H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts (H’F000 + 1 + H’0008 + 1) after the first underflow before it stops. Enabled (by writing to the enable bit or by external input) Underflow (first time) Underflow (second time) Count clock Enable bit Write to the correction register H'FFFF H'(F000+0008+1) H'F000 H'9000+H'0008 Counter H'A000 H'9000 (Note 1) H'0000 Reload register H'F000 Correction register Undefined H'0008 F/F output Data inverted by underflow TOP interrupt request due to underflow Data inverted by underflow Note 1: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-85 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (3) Precautions about using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. • If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count. • If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to " reload register value -1" at the next count clock timing after underflow. underflow The value that "reload register - 1" is reloaded by count clock next underflow Count clock Enable bit "H" Count down from the reload register value Reload cycle Counter value H'0001 H'0000 H'FFFF H'AAA9 H'(AAAA-1) H'AAA8 H'(AAAA-2) Reload register H'AAAA What is seen during underflow cycle is always H'FFFF, and not the reload register value (in this case, H'AAAA). Figure 10.3.16 Counter Value Immediately after Underflow 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-86 10 (1) Outline of TOP continuous output mode MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle after the counter underflows, it is loaded with the value that " the reload register -1." Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of " reload register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow, the counter to be loaded with the content of " the reload register -1" and count down over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The " counter set value + 1" and " reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Count value = 5 1 Count clock Count clock dependent delay Enable (Note 1) (4) 3 Counter 2 3 4 5 1 Count value = 6 2 3 4 5 6 1 Count value = 6 2 3 4 5 6 (Note 2) (Note 2) (Note 2) 4 2 1 0 3 4 2 1 0 3 2 1 0 (Note 3) (Note 3) Reload register F/F output 5 (Note 3) Interrupt request Underflow Underflow Underflow Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 4. Note 2: What actually is seen in the cycle immediately during underflow is H'FFFF (underflow value), and not 5. Note 3: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.17 Example of Counting in TOP Continuous Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-87 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of " the reload register -1" and continues counting down. However the timing for reloading is at the cycle after underflow. Enabled (by writing to the enable bit or by external input) Underflow (first time) Underflow (second time) Count clock Enable bit (Note 1) H'FFFF H'E000 H'A000 Counter Count down from the counter's set value H'FFFF H'(E000-1) Count down from the reload register's set value H'FFFF H'(E000-1) Count down from the reload register's set value (Note 2) (Note 2) H'0000 Reload register H'E000 Correction register (Unused) F/F output Data inverted by enable TOP interrupt request due to underflow Data inverted by underflow Data inverted by underflow Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.3.18 Typical Operation in TOP Continuous Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-88 10 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (2) Precautions about using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to " reload register value -1" at the next count clock timing. • Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-89 10 10.4.1 Outline of TIO MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TIO, respectively. Table 10.4.1 Specifications of TIO (Input/Output-Related 16-Bit Timer) Item Number of channels Counter Reload register Measure register Timer startup Operation mode Specification 10 channels 16-bit down-counter 16-bit reload register 16-bit capture register Started by writing to the enable bit in software or enabled by external input (rising or falling or both edges or "H" or "L" level) • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode Interrupt request generation Can be generated by a counter underflow DMA transfer request generation Can be generated by a counter underflow (TIO8, TIO9 only) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-90 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Output event bus 0123 TIO 0 Reload 0/measure register IRQ0 S clk Down-counter Reload 1 register (Note 1) udf S F/F11 TO 11 (P103) IRQ12 (16-bit) TIN3 (P153) TIN3S DMA1 IRQ12 en/cap S clk IRQ12 IRQ0 TIN4 (P30) TIN5 (P31) TIN4S TIN5S en/cap en/cap en/cap en/cap TIO 1 TIO 2 TIO 3 TIO 4 udf IRQ0 S S IRQ0 F/F12 F/F13 F/F14 TO 12 (P104) TO 13 (P105) TO 14 (P106) S clk S clk udf udf S IRQ4 IRQ12 S S clk udf S F/F15 TO 15 (P107) TIN6 (P32) TIN6S BCLK 1/2 1/4 PRS0 PRS1 PRS2 S IRQ4 TCLK1 (P125) TIN7 (P33) TCLK2 (P126) TIN8 (P44) TCLK1S TIN7S IRQ8 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 (P93) DMA4 TCLK2S TIN8S IRQ8 S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 (P94) DMA5 IRQ8 S S clk en/cap TIO 7 udf IRQ3 S F/F18 TO 18 (P95) TIN9 (P45) TIN9S IRQ8 DMA0, DMA common S S clk TIN10 (P46) TIN10S IRQ8 en/cap TIO 8 udf IRQ3 S F/F19 TO 19 (P96) S S 3210 3210 clk TIN11 (P47) TIN11S en/cap TIO 9 udf DMA common 0123 F/F20 TO 20 (P97) PRS0–2 : Prescaler F/F : Flip-flop S : Selector Note 1: The reload 1 register is used in only PWM output mode. Figure 10.4.1 Block Diagram of TIO (Input/Output-Related 16-Bit Timer) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-91 10 10.4.2 Outline of Each Mode of TIO (1) Measure clear/free-run input modes MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter starts counting until when an external capture signal is entered.And also it is possible to generate both an interrupt requested by underflow at the counter or execution of measurement operation and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H’FFFF upon underflow, from which it starts counting down.Furthermore when it underflows goes back to H’FFFF and continues down counting. In measure free-run input mode, the counter continues counting down even after capture. The counter returns to H’FFFF upon underflow, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. . (2) Noise processing input mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle when a valid-level signal is entered again, the counter is reloaded with the value that " the reload register -1" and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that “ the reload 0 register -1” and starts counting down synchronously with the count clock at the next cycle.The next cycle after the first time the counter underflows, it is loaded with the value that “ the reload 1 register -1” and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs.The effective counter value is “reload 0 register set value +1” or “reload 1 register set value +1.” The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa), when the counter starts counting and each time it underflows. Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request (for only the TIO8 and TIO9) every time the counter underflows. In addition PWM output mode of TIO does not have function of correction. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-92 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of “ reload 0 register set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the value that “ the reload 0 register -1” and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of “ reload 0 register set value + 1” only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of “reload 0 register set value + 1” after a finite time equal to “ counter set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after the first time the counter underflows, it is loaded with the value that “ the reload 0 register -1” and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of “reload 0 register set value + 1” after a finite time equal to “ first set value of counter + 1” only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon the first and next underflows of the counter. (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of “ reload 0 register set value + 1.” When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. The next cycle after this underflow causes the counter to be loaded with the content of “ the reload 0 register -1” and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) each time the counter underflows. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-93 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. Write to the enable bit BCLK Count clock period Count clock Enable F/F operation (Note 1) Count clock-dependent delay Inverted Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Figure 10.4.2 Count Clock Dependent Delay 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-94 10 10.4.3 TIO Related Register Map Shown below is a TIO related register map. TIO Related Register Map (1/2) Address b0 H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306 +0 address MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) +1 address b7 b8 TIO0 Counter (TIO0CT) (Use inhibited area) TIO0 Reload 1 Register (TIO0RL1) TIO0 Reload 0/ Measure Register (TIO0RL0) (Use inhibited area) TIO1 Counter (TIO1CT) (Use inhibited area) TIO1 Reload 1 Register (TIO1RL1) TIO1 Reload 0/ Measure Register (TIO1RL0) (Use inhibited area) TIO0–3 Control Register 0 (TIO03CR0) b15 See pages 10-105 10-107 10-106 | H'0080 0310 H'0080 0312 H'0080 0314 H'0080 0316 H'0080 0318 H'0080 031A H'0080 031C (Use inhibited area) 10-105 10-107 10-106 10-98 TIO0–3 Control Register 1 (TIO03CR1) 10-99 | H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 (Use inhibited area) TIO2 Counter (TIO2CT) (Use inhibited area) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) (Use inhibited area) TIO3 Counter (TIO3CT) (Use inhibited area) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) (Use inhibited area) TIO4 Counter (TIO4CT) (Use inhibited area) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) (Use inhibited area) TIO4 Control Register (TIO4CR) (Use inhibited area) TIO5 Control Register (TIO5CR) 10-105 10-107 10-106 | H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 10-105 10-107 10-106 | H'0080 0340 H'0080 0342 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A 10-105 10-107 10-106 10-100 10-102 | 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-95 10 TIO Related Register Map (2/2) Address b0 H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356 +0 address MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) +1 address b7 b8 TIO5 Counter (TIO5CT) (Use inhibited area) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) (Use inhibited area) TIO6 Counter (TIO6CT) (Use inhibited area) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) (Use inhibited area) b15 See pages 10-105 10-107 10-106 | H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO6 Control Register (TIO6CR) 10-105 10-107 10-106 TIO7 Control Register (TIO7CR) (Use inhibited area) TIO7 Counter (TIO7CT) (Use inhibited area) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) (Use inhibited area) TIO8 Counter (TIO8CT) (Use inhibited area) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/ Measure Register (TIO8RL0) (Use inhibited area) 10-103 10-104 | H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376 10-105 10-107 10-106 | H'0080 0380 H'0080 0382 H'0080 0384 H'0080 0386 H'0080 0388 H'0080 038A TIO8 Control Register (TIO8CR) 10-105 10-107 10-106 TIO9 Control Register (TIO9CR) (Use inhibited area) TIO9 Counter (TIO9CT) (Use inhibited area) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) (Use inhibited area) TIO0–9 Enable Protect Register (TIOPRO) TIO0–9 Count Enable Register (TIOCEN) 10-104 10-105 | H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396 10-105 10-107 10-106 | H'0080 03BC H'0080 03BE 10-108 10-109 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-96 10 10.4.4 TIO Control Registers MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the count enable and count clock sources. Following TIO control registers are provided for each timer group. • TIO0–3 Control Register 0 (TIO03CR0) • TIO0–3 Control Register 1 (TIO03CR1) • TIO4 Control Register (TIO4CR) • TIO5 Control Register (TIO5CR) • TIO6 Control Register (TIO6CR) • TIO7 Control Register (TIO7CR) • TIO8 Control Register (TIO8CR) • TIO9 Control Register (TIO9CR) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-97 10 TIO0–3 Control Register 0 (TIO03CR0) b0 TIO3EEN MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 7 0 1 0 2 TIO3M 0 3 0 4 TIO2ENS 5 0 6 TIO2M 0 8 TIO1ENS 9 0 10 TIO1M 0 11 0 12 TIO0ENS 13 0 14 TIO0M 0 b15 0 0 0 0 0 b 0 1–3 Bit Name TIO3EEN (Note 1) TIO3 external input enable bit TIO3M TIO3 operation mode select bit Function 0: Disable external input 1: Enable external input 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode 4 5–7 TIO2ENS TIO2 enable/measure input source select bit TIO2M TIO2 operation mode select bit 0: Do not use enable/measure input source 1: External input TIN5 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode 8 9–11 TIO1ENS TIO1 enable/measure input source select bit TIO1M TIO1 operation mode select bit 0: Do not use enable/measure input source 1: External input TIN4 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode 12 13–15 TIO0ENS TIO0 enable/measure input source select bit TIO0M TIO0 operation mode select bit 0: Do not use enable/measure input source 1: External input TIN3 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. • To select TIO3 enable/measure input sources, use the TIO4 Control Register TIO34ENS (TIO3, TIO4 enable/measure input source select) bits. R W R W R R W W R R W W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-98 10 Clock bus 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Input event bus S clk TIN3 (P153) TIN4 (P30) TIN5 (P31) TIN3S TIN4S TIN5S S clk S clk S clk en/cap TIO 3 en/cap TIO 2 en/cap TIO 1 en/cap TIO 0 S TIN6 (P32) TIN6S 3210 3210 clk en/cap TIO 4 S S : Selector Note: • This diagram only illustrates TIO control registers and is partly omitted. Figure 10.4.3 Outline Diagram of TIO0–4 Clock and Enable Inputs TIO0–3 Control Register 1 (TIO03CR1) b8 0 12 0 9 0 10 0 11 0 13 0 14 0 b15 0 TIO03CKS b 8–13 14, 15 Bit Name No function assigned. Fix to "0." TIO03CKS TIO0–3 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-99 10 TIO4 Control Register (TIO4CR) b0 TIO4CKS 0 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 3 4 5 0 1 2 TIO4EEN 0 6 TIO4M 0 b7 0 TIO34ENS 0 0 b 0, 1 Bit Name TIO4CKS TIO4 clock source select bit Function 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2 3, 4 TIO4EEN (Note 1) TIO4 external input enable bit TIO34ENS TIO3,4 enable/measure input source select bit 0: Disable external input 1: Enable external input 00: External input TIN6 01: External input TIN6 10: Input event bus 2 11: Input event bus 3 5–7 TIO4M TIO4 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Note: • Operation mode can only be set or changed while the counter is inactive. R W R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-100 10 Clock bus TCLK1 (P125) TIN7 (P33) TCLK1S 3210 3210 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Input event bus S TIN7S S clk en/cap TIO 5 TCLK2 (P126) TIN8 (P44) TCLK2S TIN8S S S clk en/cap TIO 6 S TIN9 (P45) TIN9S S clk en/cap TIO 7 S TIN10 (P46) TIN10S S clk en/cap TIO 8 S TIN11 (P47) TIN11S S 3210 3210 clk en/cap TIO 9 S : Selector Note: • This diagram only illustrates TIO control registers and is partly omitted. Figure 10.4.4 Outline Diagram of TIO5–9 Clock and Enable Inputs 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-101 10 TIO5 Control Register (TIO5CR) b8 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 12 0 9 TIO5CKS 0 10 0 11 TIO5ENS 0 13 0 14 TIO5M 0 b15 0 b 8–10 Bit Name TIO5CKS TIO5 clock source select bit Function 000: External input TCLK1 001: External input TCLK1 010: External input TCLK1 011: External input TCLK1 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11, 12 TIO5ENS TIO5 enable/measure input source select bit 00: Do not use enable/measure input source 01: Do not use enable/measure input source 10: External input TIN7 11: Input event bus 3 13–15 TIO5M TIO5 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: • Operation mode can only be set or changed while the counter is inactive. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-102 10 TIO6 Control Register (TIO6CR) b0 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 3 TIO6ENS 0 0 0 0 1 TIO6CKS 0 2 4 5 6 TIO6M 0 b7 0 b 0–2 Bit Name TIO6CKS TIO6 clock source select bit Function 000: External input TCLK2 001: External input TCLK2 010: External input TCLK2 011: External input TCLK2 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3, 4 TIO6ENS TIO6 enable/measure input source select bit 00: Do not use enable/measure input source 01: External input TIN8 10: Input event bus 2 11: Input event bus 3 5–7 TIO6M TIO6 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: • Operation mode can only be set or changed while the counter is inactive. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-103 10 TIO7 Control Register (TIO7CR) b8 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 12 0 9 TIO7CKS 0 10 0 11 TIO7ENS 0 13 0 14 TIO7M 0 b15 0 b 8 9, 10 Bit Name No function assigned. Fix to "0." TIO7CKS TIO7 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO7ENS TIO7 enable/measure input source select bit 00: Do not use enable/measure input source 01: External input TIN9 10: Input event bus 0 11: Input event bus 3 13–15 TIO7M TIO7 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: • Operation mode can only be set or changed while the counter is inactive. R W R W Function R 0 R W 0 W TIO8 Control Register (TIO8CR) b0 TIO8CKS 0 0 0 3 4 0 1 2 5 0 6 TIO8M 0 b7 0 TIO8ENS 0 b 0, 1 Bit Name TIO8CKS TIO8 clock source select bit Function 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 2–4 TIO8ENS TIO8 enable/measure input source select bit 000: Do not use enable/measure input source 001: Do not use enable/measure input source 010: Do not use enable/measure input source 011: Do not use enable/measure input source 100: External input TIN10 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5–7 TIO8M TIO8 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: • Operation mode can only be set or changed while the counter is inactive. R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-104 10 TIO9 Control Register (TIO9CR) b8 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 12 0 9 TIO9CKS 0 10 0 11 TIO9ENS 0 13 0 14 TIO9M 0 b15 0 b 8 9, 10 Bit Name No function assigned. Fix to "0." TIO9CKS TIO9 clock source select bit 00: Clock bus 0 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO9ENS TIO9 enable/measure input source select bit 00: Do not use enable/measure input source 01: External input TIN11 10: Input event bus 1 11: Input event bus 3 13–15 TIO9M TIO9 operation mode select bit 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: • Operation mode can only be set or changed while the counter is inactive. R W R W Function R 0 R W 0 W 10.4.5 TIO Counters (TIO0CT–TIO9CT) TIO0 Counter (TIO0CT) TIO1 Counter (TIO1CT) TIO2 Counter (TIO2CT) TIO3 Counter (TIO3CT) TIO4 Counter (TIO4CT) TIO5 Counter (TIO5CT) TIO6 Counter (TIO6CT) TIO7 Counter (TIO7CT) TIO8 Counter (TIO8CT) TIO9 Counter (TIO9CT) b0 ? 4 ? 1 ? 2 ? 3 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TIO0CT–TIO9CT b 0–15 Bit Name TIO0CT–TIO9CT Function 16-bit counter value R W R(Note 1) Note 1: Protected against write during PWM output mode. Note: • These registers must always be accessed in halfwords. The TIO counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. These counters are protected against write during PWM output mode. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-105 10 TIO0 Reload 0/ Measure Register (TIO0RL0) TIO1 Reload 0/ Measure Register (TIO1RL0) TIO2 Reload 0/ Measure Register (TIO2RL0) TIO3 Reload 0/ Measure Register (TIO3RL0) TIO4 Reload 0/ Measure Register (TIO4RL0) TIO5 Reload 0/ Measure Register (TIO5RL0) TIO6 Reload 0/ Measure Register (TIO6RL0) TIO7 Reload 0/ Measure Register (TIO7RL0) TIO8 Reload 0/ Measure Register (TIO8RL0) TIO9 Reload 0/ Measure Register (TIO9RL0) b0 ? MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) 8 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TIO0RL0–TIO9RL0 b 0–15 Bit Name TIO0RL0–TIO9RL0 Function 16-bit reload register value R W R(Note 1) Note 1: These registers are protected against write during measure input mode. Note: • These registers must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading data into the TIO Count Registers (TIO0CT-TIO9CT) and as a measure register during measure input mode. These registers are protected against write during measure input mode. The content of " the reload 0 register -1" is reloaded into the counter synchronously with the count clock at the following timing: • At the next cycle when after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows • At the next cycle when the counter is enabled in single-shot output mode • At the next cycle when the counter underflowed in delayed single-shot output or continuous output mode • At the next cycle when the counter is enabled in PWM output mode and at the next cyclewhen the counter value set by the reload 1 register underflowed Simply because data is written to the reload 0 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the register is used as a measure register, the counter value is latched into that measure register by event input. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-106 10 TIO0 Reload 1 Register (TIO0RL1) TIO1 Reload 1 Register (TIO1RL1) TIO2 Reload 1 Register (TIO2RL1) TIO3 Reload 1 Register (TIO3RL1) TIO4 Reload 1 Register (TIO4RL1) TIO5 Reload 1 Register (TIO5RL1) TIO6 Reload 1 Register (TIO6RL1) TIO7 Reload 1 Register (TIO7RL1) TIO8 Reload 1 Register (TIO8RL1) TIO9 Reload 1 Register (TIO9RL1) b0 ? MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) 7 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TIO0RL1–TIO9RL1 b 0–15 Bit Name TIO0RL1–TIO9RL1 Function 16-bit reload register value R R W W Note: • These registers must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload data into the TIO Count Registers (TIO0CT–TIO9CT). The content of " the reload 1 register -1" is reloaded into the counter counting synchronously with the count clock at the following timing: • At the next cycle when the count value set by the reload 0 register underflowed in PWM output mode Simply because data is written to the reload 1 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-107 10 10.4.8 TIO Enable Control Registers TIO0–9 Enable Protect Register (TIOPRO) b0 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 8 TIO7 PRO 1 0 2 0 3 0 4 0 5 0 6 TIO9 PRO 7 TIO8 PRO 9 TIO6 PRO 10 TIO5 PRO 11 TIO4 PRO 12 TIO3 PRO 13 TIO2 PRO 14 TIO1 PRO b15 TIO0 PRO 0 0 0 0 0 0 0 0 0 0 b 0–5 6 7 8 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TIO9PRO (TIO9 enable protect bit) TIO8PRO (TIO8 enable protect bit) TIO7PRO (TIO7 enable protect bit) TIO6PRO (TIO6 enable protect bit) TIO5PRO (TIO5 enable protect bit) TIO4PRO (TIO4 enable protect bit) TIO3PRO (TIO3 enable protect bit) TIO2PRO (TIO2 enable protect bit) TIO1PRO (TIO1 enable protect bit) TIO0PRO (TIO0 enable protect bit) 0: Enable rewrite 1: Disable rewrite Function R 0 R W 0 W Note: • This register must always be accessed in halfwords. The TIO0–9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling it. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-108 10 TIO0–9 Count Enable Register (TIOCEN) b0 0 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 8 TIO7 CEN 1 0 2 0 3 0 4 0 5 0 6 TIO9 CEN 7 TIO8 CEN 9 TIO6 CEN 10 TIO5 CEN 11 TIO4 CEN 12 TIO3 CEN 13 TIO2 CEN 14 TIO1 CEN b15 TIO0 CEN 0 0 0 0 0 0 0 0 0 0 b 0–5 6 7 8 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0." TIO9CEN (TIO9 count enable bit) TIO8CEN (TIO8 count enable bit) TIO7CEN (TIO7 count enable bit) TIO6CEN (TIO6 count enable bit) TIO5CEN (TIO5 count enable bit) TIO4CEN (TIO4 count enable bit) TIO3CEN (TIO3 count enable bit) TIO2CEN (TIO2 count enable bit) TIO1CEN (TIO1 count enable bit) TIO0CEN (TIO0 count enable bit) 0: Stop count 1: Enable count Function R 0 R W 0 W Note: • This register must always be accessed in halfwords The TIO0–9 Count Enable Register controls operation of the TIO counters. To enable any TIO counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1." To stop any TIO counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0." In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TIO0–9 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. TIOm external enable (TIOmEEN or TIOmENS) F/F Input processing selection EN-ON TINn TINnS Event bus bn TIOm enable protect (TIOmPRO) F/F WR TIOm count enable (TIOmCEN) TIO enable control F/F WR Figure 10.4.5 Configuration of the TIO Enable Circuit 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-109 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.9 Operation in TIO Measure Free-Run/Clear Input Modes (1) Outline of TIO measure free-run/clear input modes In measure free-run/clear input modes, the timer is used to measure a duration of time from when the counter starts counting until when an external capture signal is entered. It is possible to generate an interrupt request upon underflow of the counter or execution of measurement operation and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H’FFFF upon underflow, from which it starts counting down. In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H’FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Enabled (by writing to the enable bit) Measure event (capture) occurs Measure event (capture) Count clock Enable bit H'FFFF Undefined value H'9000 Counter H'7000 H'0000 Measure register Undefined H'7000 H'9000 TIN interrupt request TIN interrupt request due to external event input TIO interrupt request TIO interrupt request due to underflow DMA transfer request (Note 1) DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note: • This diagram does not show detailed timing information. TIN interrupt request due to external event input Figure 10.4.6 Typical Operation in Measure Free-Run Input Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-110 10 Enabled (by writing to the enable bit) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Measure event (capture) occurs Count clock Enable bit H'FFFF Undefined value Counter H'7000 H'0000 Measure register Undefined H'7000 TIN interrupt request TIN interrupt request due to external event input TIO interrupt request TIO interrupt request due to underflow DMA transfer request (Note 1) DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note: • This diagram does not show detailed timing information. Figure 10.4.7 Typical Operation in Measure Clear Input Mode (2) Precautions about using TIO measure free-run/ clear input modes The following describes precautions to be observed when using TIO measure free-run/ clear input modes. • If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-111 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.10 Operation in TIO Noise Processing Input Mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle after a valid-level signal is entered again, the counter is reloaded with the value that "reload register -1" and restarts counting. The effective count width is " reload 0 register set value + 1." The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. Enabled (by writing to the enable bit) Count clock Disabled by underflow Enable bit External input (noise processing) Invalid Invalid H'FFFF Undefined value Effective signal width H'A000 Counter (Note 2) (Note 2) (Note 2) H'0000 Reload 0 register H'A000 TIO interrupt request TIO interrupt request due to underflow DMA transfer request (Note 1) DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.4.8 Typical Operation in Noise Processing Input Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-112 10 (1) Outline of TIO PWM output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.11 Operation in TIO PWM Output Mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled " by writing to the enable bit in software or by external input" after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that " the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. At the cycle after the first time the counter underflows, it is loaded with the value that " the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The " reload 0 register set value + 1" and " reload 1 register set value + 1" respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit " and not in synchronism with PWM output period." The F/F output waveform in PWM output mode is inverted " F/F output level changes from "L" to "H" or vice versa" when the counter starts counting and each time it underflows. Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request " for only the TIO8 and TIO9" every time the counter underflows. Note that TIO’s PWM output mode does not have the count correction function. Enabled (by writing to the enable bit or by external input) Count clock Underflow (first time) Underflow (second time) Enable bit Count down from the reload 0 register set value Count down from the reload 1 register set value Count down from the reload 0 register set value H'FFFF Undefined value H'A000 Counter H'C000 (Note 3) (Note 2) (Note 2) H'A000 H'A000 H'0000 Reload 0 register H'A000 H'A000 Reload 1 register H'C000 H'C000 (Note 4) (Note 4) Reload 1 buffer F/F output (Note 5) Data inverted by enable TIO interrupt request PWM output period TIO interrupt request due to even-numbered occurrences of underflow Data inverted by underflow Data inverted by underflow DMA transfer request (Note 1) DMA transfer request due to underflow DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note 3: The value that "reload 1 buffer - 1" is reloaded. Note 4: When reload0 is reloaded after updating reload0 register, reload 1 buffer is tranferd. Note 5: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Note: • This diagram does not show detailed timing information. Figure 10.4.9 Typical Operation in PWM Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-113 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. Internal bus Reload 1 TIOnRL1 Reload 1 WR Reload 0 WR Reload 1 Buffer (Note1) Reload 0 TIOnRL0 PWM mode control Prescaler output 16-bit counter F/F TO Note1: It is transferd from reload 1 register to reload 1 buffer when reload 0 register is reloaded after updating reload 0 register during counter operation. Figure 10.4.10 PWM Circuit Diagram To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchronously with PWM period, from which the timer starts operating. This operation can normally be performed collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are automatically written to the reload 1 and then the reload 0 registers in succession.) If the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. When operating in the PWM output mode, writing the reload 0 register and reloard 1 register more than twice within the PWM period and meet the following conditions at the same time, the PWM waveform is output with the value that the last time written reload 0 register and finally written reload 1 register. Condition 1: Start writing reload 0 register after latching the reload 0 register PWM period of the old PWM output period. Condition 2: Rewrite reload 1 register before latching PWM period of the new PWM output period and start writing reload 0 register after latching PWM period. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-114 10 Reloading "reload 0 register" (Loading PWM period) Underflow (2nd time) Underflow (1st time) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Reloading "reload 0 register" (Loading PWM period) Underflow (2nd time) Count clock H'FFFF (Note 2) (Note 1) (Note 1) Counter H'0000 Old PWM output period F/F output New PWM putput period Condition 1 Reload 0 register Condition 2 Reload 1 register Reload 1 buffer PWM period Note 1: The value that "the reload 0 register -1" is reloaded. Note 2: The value that "the reload 1 buffer -1" is reloaded. : Indicate sampling points. Notes: . . This diagram does not show detailed timing information. Figure 10.4.11 Update timing of PWM period To update PWM period correctly, take either one of the following measures. • Identify the completion timing of PWM period by reading counter value at writing reload 1 register and reload 0 register, and then start writing reload 1 register and reload 0 register without crossing PWM period. • When writing to reload 1 register and reload 0 register by using interruption, set the prescaler value of counter as small as possible. By doing this, write to reload 1 register and reload 0 register later than the counter to be H'FFFF in the PWM period. • Writing reload 1 register and reload 0 register is performed under the period, less than one time per PWM period. (Extend the reload register's rewrite period against PWM period.) (3) Notes on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload register value -1" at the next count clock timing. • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-115 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 1 Write to reload 0 (Reload 1 data latched) Reload 0 register Reload 1 register H'1000 H'2000 Old PWM output period H'8000 H'9000 New PWM output period F/F output Operation by new reload value written Enlarged view Count clock Counter Interrupt due to underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output Timing at which reload 0 is updated Timing at which PWM period latched and reload 1 buffer is updated. H'1000 H'2000 H'2000 H'8000 H'9000 H'9000 H'9000 H'8000 H'0001 H'0000 H'FFFF H'7FFF H'FFFF H'7FFE H'7FFF New PWM output period (b) When reload register updates take effect in the next period (reflected one period later) Write to reload 1 Write to reload 0 (Reload 1 data latched) Reload 0 register Reload 1 register H'1000 H'2000 Old PWM output period H'9000 H'8000 Old PWM output period Operation by old reload value F/F output Enlarged view Count clock Old PWM output period Counter Interrupt due to underflow Reload 0 register Reload 1 register Reload 1 buffer F/F output H'0001 H'0000 H'FFFF H'0FFF H'0FFF H'0FFE H'0FFE H'1000 H'1000 H'2000 H'2000 H'2000 H'9000 H'9000 H'8000 H'8000 H'9000 PWM period latched Timing at which reload 0 is updated Note: • This diagram does not show detailed timing information. Figure 10.4.12 Reload 0 and Reload 1 Register Updates in PWM Output Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-116 10 (1) Outline of TIO single-shot output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) In single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" only once and then stops. When the timer is enabled " by writing to the enable bit in software or by external input "after setting the reload 0 register, the counter is loaded with the content of the "reload 0 register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted " F/F output level changes from "L" to "H" or vice versa" at startup and upon underflow, generating a single-shot pulse waveform in width of " reload 0 register set value + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. The count value is " reload 0 register set value + 1." (For counting operation, see also Section 10.3.9, “Operation of TOP Single-shot Output Mode.” ) (2) Precautions about using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. • If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-117 10 Count clock MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Enabled (by writing to the enable bit or by external input) Disabled (by underflow) Enable bit H'FFFF Undefined value H'A000 Counter (Note 2) H'0000 Reload 0 register H'A000 Reload 1 register (Unused) F/F output Data inverted by enable TIO interrupt request Data inverted by underflow TIO interrupt request due to underflow DMA transfer request (Note 1) DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.4.13 Typical Operation in TIO Single-shot Output Mode (without Correction Function) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-118 10 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of " reload 0 register set value + 1" after a finite time equal to " counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first counter underflow, it is loaded with "the reload 0 register value -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of " reload 0 register set value + 1" after a finite time equal to " first set value of counter + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon the first and next underflows of the counter. The " counter set value + 1" and " reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Precautions about using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. • If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • If the counter is accessed for read ar the cycle of underflow, the counter value is read out as H’FFFF but changes to "reload register value -1" at the next count clock timing. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-119 10 Enabled (by writing to the enable bit or by external input) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Underflow (first time) Underflow (second time) Count clock Enable bit H'FFFF H'F000 Count down from the counter set value (Note 2) Count down from the reload 0 register set value H'A000 Counter H'0000 Reload 0 register H'F000 Reload 1 register (Unused) F/F output Data inverted by underflow TIO interrupt request TIO interrupt request due to underflow TIO interrupt request due to underflow Data inverted by underflow DMA transfer request (Note 1) DMA transfer request due to underflow DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.4.14 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-120 10 (1) Outline of TIO continuous output mode MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) In continuous output mode, the timer counts down starting from the set value of the counter and the next cycle when the counter underflows, it is loaded with the value that " the reload 0 register -1." Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of " reload 0 register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. The cycle after this underflow causes the counter to be loaded with the content of " the reload 0 register -1" and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) each time the counter underflows. The " counter set value + 1" and " reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Precautions about using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. • If the counter is accessed for read at the cycle of underflow, the counter value is read out as H’FFFF but changes to "reload register value -1" at the next count clock timing. • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-121 10 Enabled (by writing to the enable bit or by external input) MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Underflow (first time) Underflow (second time) Count clock Enable bit H'FFFF H'E000 Count down from the counter set value H'DFFF (Note 2) H'DFFF (Note 2) H'A000 Counter H'0000 Reload 0 register H'E000 Reload 1 register (Unused) F/F output Data inverted by enable TIO interrupt request TIO interrupt request due to underflow TIO interrupt request due to underflow Data inverted by underflow Data inverted by underflow DMA transfer request (Note 1) DMA transfer request due to underflow DMA transfer request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.4.15 Typical Operation in TIO Continuous Output Mode (without Correction Function) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-122 10 10.5 TMS (Input-Related 16-Bit Timer) 10.5.1 Outline of TMS MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below and the diagram in the next page show specifications and a block diagram of TMS, respectively. Table 10.5.1 Specifications of TMS (Input-Related 16-Bit Timer) Item Number of channels Counter Measure register Timer startup Interrupt request generation Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) 16-bit up-counter × 2 16-bit measure register × 8 Started by writing to the enable bit in software Can be generated by a counter overflow 10.5.2 Outline of TMS Operation In TMS, when the timer is enabled (by writing to the enable bit in software), the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. TIN and TMS interrupt requests can be generated by external measure signal input and counter overflow, respectively. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-123 10 Clock bus 3210 MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) Input event bus 3210 Output event bus 0123 TMS 0 ovf TCLK3 (P127) TCLK3S S clk Counter (16-bit) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ7 cap3 S cap2 cap1 cap0 S S S TMS 1 ovf S clk Counter (16-bit) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ7 IRQ10 cap3 S cap2 cap1 cap0 TIN16 (P130) TIN16S IRQ10 TIN17 (P131) TIN17S IRQ10 S TIN18 (P132) TIN18S DMA2 IRQ10 S TIN19 (P133) TIN19S DMA4 S 3210 3210 0123 S : Selector Figure 10.5.1 Block Diagram of TMS (Input-Related 16-Bit Timer) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-124 10 MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) • Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. Write to the enable bit BCLK Count clock period Count clock Enable Count clock-dependent delay Figure 10.5.2 Count Clock-Dependent Delay 10.5.3 TMS Related Register Map Shown below is a TMS related register map. TMS Related Register Map Address b0 H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA TMS0 Control Register (TMS0CR) (Use inhibited area) TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) 10-127 10-127 10-127 10-127 10-127 +0 address b7 b8 TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS1 Control Register (TMS1CR) +1 address b15 10-127 10-127 10-127 10-127 10-127 10-126 See pages | H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-125 10 10.5.4 TMS Control Registers MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control count enable. Following two TMS control registers are included: • TMS0 Control Register (TMS0CR) • TMS1 Control Register (TMS1CR) TMS0 Control Register (TMS0CR) b0 1 2 TMS0SS2 0 4 TMS0CKS 0 0 0 3 TMS0SS3 0 5 6 b7 TMS0CEN 0 TMS0SS0 TMS0SS1 0 0 b 0 1 2 3 4, 5 Bit Name TMS0SS0 TMS0 measure 0 source select bit TMS0SS1 TMS0 measure 1 source select bit TMS0SS2 TMS0 measure 2 source select bit TMS0SS3 TMS0 measure 3 source select bit TMS0CKS TMS0 clock source select bit Function 0: Does not use measure input source 1: Input event bus 0 0: Does not use measure input source 1: Input event bus 1 0: Does not use measure input source 1: Input event bus 2 0: Does not use measure input source 1: Input event bus 3 00: External input TCLK3 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 7 No function assigned. Fix to "0." TMS0CEN TMS0 count enable bit 0: Stop count 1: Start count 0 R 0 W R W R W R R R R W W W W TMS1 Control Register (TMS1CR) b8 9 10 TMS1SS2 0 12 0 11 TMS1SS3 0 13 TMS1CKS 0 14 0 b15 TMS1CEN 0 TMS1SS0 TMS1SS1 0 0 b 8 9 10 11 12 13 14 15 Bit Name TMS1SS0 TMS1 measure 0 source select bit TMS1SS1 TMS1 measure 1 source select bit TMS1SS2 TMS1 measure 2 source select bit TMS1SS3 TMS1 measure 3 source select bit No function assigned. Fix to "0." TMS1CKS TMS1 clock source select bit No function assigned. Fix to "0." TMS1CEN TMS1 count enable bit 0: Stop count 1: Start count 0: Clock bus 0 1: Clock bus 3 0 R 0 W Function 0: External input TIN19 1: Input event bus 0 0: External input TIN18 1: Input event bus 1 0: External input TIN17 1: Input event bus 2 0: External input TIN16 1: Input event bus 3 0 R 0 W R W R W R W R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-126 10 10.5.5 TMS Counters (TMS0CT, TMS1CT) TMS0 Counter (TMS0CT) TMS1 Counter (TMS1CT) b0 ? MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) 5 ? 1 ? 2 ? 3 ? 4 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TMS0CT, TMS1CT b 0–15 Bit Name TMS0CT, TMS1CT Function 16-bit counter value R R W W Note: • These registers must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counters can be read on-the-fly. 10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) b0 ? 7 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TMS0MR3–TMS0MR0 , TMS1MR3–TMS1MR0 b 0–15 Bit Name TMS0MR3-TMS0MR0 TMS1MR3-TMS1MR0 Notes: • These registers are a read-only register. • These registers can be accessed in either byte or halfword. Function 16-bit measured value R R W – The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-127 10 10.5.7 Operation of TMS Measure Input (1) Outline of TMS measure input MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting up synchronously with the count clock. Then when event input to TMS is detected while the timer is operating, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count is disabled by writing to the enable bit. A TIN interrupt request can be generated by measure signal input from an external device. A TMS interrupt request can be generated when the counter overflows. Enabled (by writing to the enable bit) Measure event 0 occurs Measure event 1 Overflow occurs occurs Measure event 0 occurs Measure event 1 occurs Count clock Enable bit H'FFFF H'D000 H'C000 Counter Undefined value H'0000 Measure 0 register TIN19 interrupt request Undefined H'8000 H'6000 H'8000 H'6000 Measure 1 register TIN18 interrupt request Undefined H'C000 H'D000 TMS interrupt request due to overflow Note: • This diagram does not show detailed timing information. Figure 10.5.3 Typical Operation of TMS Measure Input (2) Precautions about using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-128 10 10.6 TML (Input-Related 32-Bit Timer) 10.6.1 Outline of TML MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table and diagram below show specifications and a block diagram of TML, respectively. Table 10.6.1 Specifications of TML (Input-Related 32-Bit Timer) Item Number of channels Input clock Counter Measure register Timer startup Specification 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) BCLK/4 (5.0 MHz when f(BCLK) = 20 MHz), BCLK/2 (10.0 MHz when f(BCLK) = 20 MHz) or clock bus 1 input 32-bit up-counter × 2 32-bit measure register × 8 Start counting after exiting the reset state Clock bus Input event bus TML0 Output event bus 0123 3210 3210 BCLK 1/2 1/4 S clk Counter (32-bit) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ11 cap3 S S S cap2 cap1 cap0 TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) TIN20S TIN21S DMA5 IRQ11 IRQ11 TIN22S IRQ11 TIN23S AD0TRG S TML1 S clk Counter (32-bit) Measure register 3 Measure register 2 Measure register 1 Measure register 0 IRQ18 cap3 S S S cap2 cap1 cap0 TIN30 (P34) TIN31 (P35) TIN32 (P36) TIN33 (P37) TIN30S TIN31S TIN32S TIN33S DMA common IRQ18 IRQ18 IRQ18 S 3210 3210 0123 S : Selector Figure 10.6.1 Block Diagram of TML (Input-Related 32-Bit Timer) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-129 10 10.6.2 Outline of TML Operation MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When the reset input signal is deasserted, the counter starts operating with a BCLK/4 clock, and cannot be stopped once it has started. The counter is idle only when the microcomputer remains reset. A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow interrupts are available. 10.6.3 TML Related Register Map Shown below is a TML related register map. TML Related Register Map Address b0 H'0080 03E0 H'0080 03E2 +0 address b7 b8 TML0 Counter (TML0CT) +1 address b15 (Upper) (TML0CTH) (Lower) (TML0CTL) 10-132 See pages | H'0080 03EA (Use inhibited area) (Use inhibited area) TML0 Control Register (TML0CR) (Use inhibited area) TML0 Measure 3 Register (TML0MR3) (Upper) (TML0MR3H) (Lower) (TML0MR3L) (Upper) (TML0MR2H) (Lower) (TML0MR2L) (Upper) (TML0MR1H) (Lower) (TML0MR1L) (Upper) (TML0MR0H) (Lower) (TML0MR0L) 10-132 10-131 | H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA H'0080 03FC H'0080 03FE TML0 Measure 2 Register (TML0MR2) 10-132 TML0 Measure 1 Register (TML0MR1) 10-132 TML0 Measure 0 Register (TML0MR0) 10-132 | H'0080 0FE0 H'0080 0FE2 TML1 Counter (TML1CT) (Upper) (TML1CTH) (Lower) (TML1CTL) 10-132 | H'0080 0FEA (Use inhibited area) (Use inhibited area) TML1 Control Register (TML1CR) (Use inhibited area) TML1 Measure 3 Register (TML1MR3) (Upper) (TML1MR3H) (Lower) (TML1MR3L) (Upper) (TML1MR2H) (Lower) (TML1MR2L) (Upper) (TML1MR1H) (Lower) (TML1MR1L) (Upper) (TML1MR0H) (Lower) (TML1MR0L) 10-132 10-131 | H'0080 0FF0 H'0080 0FF2 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA H'0080 0FFC H'0080 0FFE TML1 Measure 2 Register (TML1MR2) 10-132 TML1 Measure 1 Register (TML1MR1) 10-132 TML1 Measure 0 Register (TML1MR0) 10-132 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-130 10 10.6.4 TML Control Registers TML0 Control Register (TML0CR) b8 TML0SS0 0 MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 12 0 9 TML0SS1 0 10 TML0SS2 0 11 TML0SS3 0 13 0 14 0 b15 TML0CKS 0 b 8 9 10 11 12–14 15 Bit Name TML0SS0 TML0 measure 0 source select bit TML0SS1 TML0 measure 1 source select bit TML0SS2 TML0 measure 2 source select bit TML0SS3 TML0 measure 3 source select bit No function assigned. Fix to "0." TML0CKS TML0 clock source select bit Section 10.2.2, “Common Count Clock Select Function.” 0: BCLK/2 or BCLK/4 (Note 1) 1: Clock bus 1 Function 0: External input TIN23 1: Input event bus 0 0: External input TIN22 1: Input event bus 1 0: External input TIN21 1: Input event bus 2 0: External input TIN20 1: Input event bus 3 0 R 0 W R W R W R W R R W W Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to TML1 Control Register (TML1CR) b8 TML1SS0 0 12 0 9 TML1SS1 0 10 TML1SS2 0 11 TML1SS3 0 13 0 14 0 b15 TML1CKS 0 b 8 9 10 11 12–14 15 Bit Name TML1SS0 TML1 measure 0 source select bit TML1SS1 TML1 measure 1 source select bit TML1SS2 TML1 measure 2 source select bit TML1SS3 TML1 measure 3 source select bit No function assigned. Fix to "0." TML1CKS TML1 clock source select bit Section 10.2.2, “Common Count Clock Select Function.” 0: BCLK/2 or BCLK/4 (Note 1) 1: Clock bus 1 Function 0: External input TIN33 1: Input event bus 0 0: External input TIN32 1: Input event bus 1 0: External input TIN31 1: Input event bus 2 0: External input TIN30 1: Input event bus 3 0 R 0 W R W R R R R W W W W Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to The TML control register is used to select TML input event and count clock. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-131 10 10.6.5 TML Counters TML0 Counter (TML0CT) TML1 Counter (TML1CT) MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TML0CT, TML1CT (16 high-order bits) b16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 ? b31 ? (16 low-order bits) b 0–31 Bit Name TML0CT Function 32-bit counter value R R W W Note: • These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary(The lower address B’00). The TML counters are a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The counters can be read during operation. 10.6.6 TML Measure Registers TML0 Measure 3 Register (TML0MR3) TML0 Measure 2 Register (TML0MR2) TML0 Measure 1 Register (TML0MR1) TML0 Measure 0 Register (TML0MR0) TML1 Measure 3 Register (TML1MR3) TML1 Measure 2 Register (TML1MR2) TML1 Measure 1 Register (TML1MR1) TML1 Measure 0 Register (TML1MR0) b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TML0MR3-TML0MR0,TML1MR3-TML1MR0 (16 high-order bits) b16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 ? b31 ? (16 low-order bits) b 0–31 Bit Name TML0MR3–TML0MR0, TML1MR3–TML1MR0 Function 32-bit measure register value R R W – Notes: • These registers are a read-only register. • These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary(The lower address B’00). The TML measure registers are a 32-bit register, which is used to latch the counter content upon event input. The TML measure registers can only be read, and cannot be written to. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-132 10 10.6.7 Operation of TML Measure Input (1) Outline of TML measure input MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchronously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each measure register. A TIN interrupt request can be generated by measure signal input from an external device. However, no TML counter overflow interrupts are available. Measure Enabled (by deassertion event 0 occurs of reset) Measure event 1 Overflow occurs occurs Measure event 0 occurs Measure event 1 occurs Count clock Reset H'FFFF FFFF H'C000 0000 Counter (32-bit) H'8000 0000 H'6000 0000 Undefined value H'D000 0000 H'0000 0000 Measure 0 register TIN23 interrupt request Undefined H'8000 0000 H'6000 0000 Measure 1 register TIN22 interrupt request Undefined H'C000 0000 H'D000 0000 Note: • This diagram does not show detailed timing information. Figure 10.6.2 Typical Operation of TML Measure Input 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-133 10 (2) Precautions about using TML measure input MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register. • If clock bus 1 is selected and any clock other than BCLK/2 or BCLK/4 (Note 1) is used for the timer by divided by internal prescaler PRS1, the value captured into the measure register is one count larger the counter value. During the count clock to BCLK/2 or BCLK/4 (Note 1) period interval, however, the captured value is exactly the counter value. The diagram below shows the relationship between counter operation and the valid data that can be captured. Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, “Common Count Clock Select Function.” • When BCLK/2 or BCLK/4 is selected (Note 1) BCLK/2 or BCLK/4 Counter A B C D E F Captured A B C D E F • When clock bus 1 is selected BCLK/2 or BCLK/4 Count clock Counter A B C Captured B C D Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, "Common Count Clock Select Function." Figure 10.6.3 Mistimed Counter Value and the Captured Value 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-134 10 10.7 TID (Input-Related 16-Bit Timer) 10.7.1 Outline of TID MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: • Fixed period count mode • Event count mode • Multiply-by-4 event count mode • Up/down event count mode The table below and the diagram in the next page show specifications and a block diagram of TID, respectively. Table 10.7.1 Specifications of TID (Input-Related 16-Bit Timer) Item Number of channels Counter Reload register Timer startup Operation mode Specification 2 channels 16-bit up/down-counter 16-bit reload register Started by writing to the enable bit in software • Fixed period count mode • Event count mode • Multiply-by-4 event count mode • Up/down event count mode Interrupt request generation DMA transfer request generation Can be generated by counter underflow and overflow Can be generated by counter underflow and overflow 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-135 10 TID 0 BCLK 1/4 PRS3 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) Output event bus 0 Reload register clk IRQ11 Clock control (Note 1) Up/down-counter ovf udf TIN24S TIN24(P103) TIN25(P104) TIN25S IRQ14 DMA0 CLK1 CLK2 S TOU0_0-7en IRQ11 TOU0_7udf TID 1 BCLK 1/4 PRS4 Reload register clk IRQ11 Clock control (Note 1) Up/down-counter ovf udf TIN26S TIN26(P73) TIN27(P72) TIN27S IRQ15 DMA1 CLK1 CLK2 S TOU1_0-7en IRQ11 TOU1_7udf Note 1: The clock source to be used depends on the operation mode. Figure 10.7.1 Block Diagram of TID (Input-Related 16-Bit Timer) • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. Write to the enable bit BCLK Count clock period Count clock Enable Count clock-dependent delay Figure 10.7.2 Count Clock Dependent Delay 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-136 10 10.7.2 TID Related Register Map Shown below is a TID related register map. TID Related Register Map Address b0 H'0080 078C H'0080 078E +0 address MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) +1 address b7 b8 TID0 Counter (TID0CT) TID0 Reload Register (TID0RL) b15 See pages 10-140 10-140 | H'0080 07D0 TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) 10-138 | H'0080 0B8C H'0080 0B8E TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) 10-140 10-140 | H'0080 0BD0 TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) 10-139 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-137 10 10.7.3 TID Control & Prescaler Enable Registers TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) b8 0 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 14 0 9 TID0M 0 10 0 11 TID0CEN 0 12 0 13 TOU0ENS 0 b15 PRS3EN 0 b 8–10 Bit Name TID0M TID0 operation mode select bit Function 000: Fixed period count mode 001: Fixed period count mode 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: Fixed period count mode 110: Multiply-by-4 event count mode 111: Up/down event count mode 11 12–14 TID0CEN TID0 count enable bit TOU0ENS TOU0 enable source select bit 0: Stop TID0 count 1: Start TID0 count 000: Disable event enable 001: Disable event enable 010: TID0 underflow/overflow 011: TOU0_7 underflow 100: Disable event enable 101: Disable event enable 110: Output event bus 0 111: External input TIN25 signal 15 PRS3EN Prescaler 3 enable bit 0: Stop prescaler 3 count 1: Start prescaler 3 count R W R W R W R R W W Note: • Operation mode can only be set or changed while the counter is inactive. The TID0 Control & Prescaler 3 Enable Register is used to select TID0 operation mode (Fixed period count, Event count, Multiply-by-4 event count or up/down event count mode), as well as select TOU0_0–7 timer enable sources and control prescaler 3 startup. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-138 10 TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) b8 0 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 14 0 9 TID1M 0 10 0 11 TID1CEN 0 12 0 13 T0U1ENS 0 b15 PRS4EN 0 b 8–10 Bit Name TID1M TID1 operation mode select bit Function 000: Fixed period count mode 001: Fixed period count mode 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: Fixed period count mode 110: Multiply-by-4 event count mode 111: Up/down event count mode 11 12–14 TID1CEN TID1 count enable bit TOU1ENS TOU1 enable source select bit 0: Stop TID1 count 1: Start TID1 count 000: Disable event enable 001: Disable event enable 010: TID1 underflow/overflow 011: TOU1_7 underflow 100: Disable event enable 101: Disable event enable 110: TOU0 startup source (Note 1) (The enable source selected by TOU0ENS) 111: External input TIN27 signal 15 PRS4EN Prescaler 4 enable bit 0: Stop prescaler 4 count 1: Start prescaler 4 count R W R R W W R R W W Note 1: Any event must be selected using the TOU0 enable source select bit. Note: • Operation mode can only be set or changed while the counter is inactive. The TID1 Control & Prescaler 4 Enable Register is used to select TID1 operation mode (Fixed period count, Event count, Multiply-by-4 event count or up/down event count mode), as well as select TOU1_0–7 timer enable sources and control prescaler 4 startup. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-139 10 10.7.4 TID Counters (TID0CT and TID1CT) TID0 Counter (TID0CT) TID1 Counter (TID1CT) b0 ? MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 4 ? 1 ? 2 ? 3 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TID0CT, TID1CT b 0–15 Bit Name TID0CT, TID1CT Function 16-bit counter value R R W W Note: • These registers must always be accessed in halfwords. The TID counters are a 16-bit up/down-counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting synchronously with the count clock. 10.7.5 TID Reload Registers (TID0RL and TID1RL) TID0 Reload Register (TID0RL) TID1 Reload Register (TID1RL) b0 ? 6 ? 1 ? 2 ? 3 ? 4 ? 5 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TID0RL, TID1RL b 0–15 Bit Name TID0RL,TID1RL Function 16-bit reload register value R R W W Note: • These registers must always be accessed in halfwords. The TID reload registers are used to reload data into the TID counter registers (TID0CT and TID1CT). The content of " the reload register -1" is loaded into the counter synchronously with the count clock in the following timing: • At the next cycle when the counter is enabled in fixed period count mode • At the next cycle when the counter has underflowed in fixed period count mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-140 10 10.7.6 Outline of Each Mode of TID (1) Fixed period count mode MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time. In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of " reload register set value + 1." Note: • TINn cannot be used as a clock source. When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initial value being undefined), the counter is loaded with the content of " the reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when it underflows after reaching the minimum count, the counter is loaded with the content of " the reload register -1" and continues counting. To stop the counter, disable count by writing to the enable bit in software. An interrupt request and a DMA transfer request can be generated each time the counter underflows. The " reload register set value + 1" is effective as count value. Enabled (by writing to the enable bit) Underflow (first time) Underflow (second time) Count clock Enable bit H'FFFF H'E000 H'(E000-1) (Note 1) H'E000 H'(E000-1) (Note 1) H'(E000-1) (Note 1) Counter Undefined value H'0000 Reload register H'E000 TID0 interrupt request due to underflow DMA transfer request due to underflow Note 1: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-141 10 (2) Event count mode MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) In event count mode, the timer uses an external input signal (TIN24 or TIN26) as the clock source for the counter. Note: • TIN25 and TIN27 cannot be used as the clock source for the counter. By detecting the rising and falling edges of the external input signal (TIN24 or TIN26), the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting up from the set count value synchronously with the generated clock. An interrupt request and a DMA transfer request can be generated by a counter overflow. To stop the counter, disable count by writing to the enable bit in software or fix the external input signal either "H" or "L." TIN24 (TIN26) Counter value 7FFF 8000 8001 8002 8003 8004 Figure 10.7.4 Typical Operation in TID Event Count Mode (Basic Operation) TIN24 (TIN26) Counter value FFFD FFFE FFFF 0000 0001 0002 0003 TID interrupt request due to overflow DMA transfer request due to overflow Figure 10.7.5 Typical Operation in TID Event Count Mode (when Overflow Occurs) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-142 10 (3) Multiply-by-4 event count mode MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25 or TIN26 and TIN27) as the clock sources for the counter. The count direction is switched between up-count and down-count depending on the status of the two input signals. By detecting the rising and falling edges on both of the two external input signals, the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting synchronously with the generated clock. To know whether the counter counts up or counts down, see Table 10.7.2 below. An interrupt request and a DMA transfer request can be generated when the counter underflows or overflows. To stop the counter, disable count by writing to the enable bit in software or fix the external input signals either "H" or "L." Table 10.7.2 Count Direction during Multiply-by-4 Event Count Mode Input TIN24 (TIN26) TIN25 (TIN27) Count Direction Up-count H H Down-count L L H L L H 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-143 10 TIN24 (TIN26) TIN25 (TIN27) Counter value 7FFE 7FFF 8000 8001 8002 8003 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 8002 8001 8000 7FFF 7FFE Switched over 8003 Counter 7FFE Up-count Down-count Figure 10.7.6 Multiply-by-4 Count Operation (Switchover Timing) TIN24 (TIN26) TIN25 (TIN27) Counter value Timer count enable Enabled Disabled Enabled 7FFE 7FFF 8000 8001 8000 7FFF Switched over Disabled Enabled Disabled 8001 Counter 7FFE Up-count Down-count Figure 10.7.7 Multiply-by-4 Count Operation (Count Enabled/Disabled) TIN24 (TIN26) TIN25 (TIN27) Counter value FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF FFFE FFFD Switched over FFFF Counter 0000 TID output interrupt request Up-count DMA transfer interrupt request Down-count Figure 10.7.8 Multiply-by-4 Count Operation (Interrupt Request Timing) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-144 10 (4) Up/down event count mode MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) In up/down event count mode, the timer uses one of two-channel external input signals (TIN24 or TIN26) as the clock source for the counter and the other (TIN25 or TIN27) as an up/down select signal. The counter is switched between up-count and down-count depending on the status of the up/down select input signal. By detecting the rising and falling edges of the external input signal selected as the clock source, the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is enabled, the counter starts counting up or down synchronously with the generated clock. The count direction is determined by the level of the up/down select input signal (see Table 10.7.3). An interrupt request and a DMA transfer request can be generated when the counter underflows or overflows. To stop the counter, disable count by writing to the enable bit in software or fix the external input signal selected as the clock source either "H" or "L." Note that TIN25 and TIN27 cannot be used as the clock source. Table 10.7.3 Count Direction during Up/Down Event Count Mode Input TIN24 (TIN26) TIN25 (TIN27) Count Direction Up-count Down-count "L" level "H" level TIN24 (TIN26) TIN25 (TIN27) Counter value 7FFF 8000 8001 8002 8001 8000 7FFF Up-count Down-count Figure 10.7.9 Up/Down Count Operation TIN24 (TIN26) TIN25 (TIN27) Counter value FFFD FFFE FFFF 0000 0001 0002 0003 0002 0001 0000 FFFF FFFE FFFD TID output interrupt request due to overflow or underflow DMA transfer request Figure 10.7.10 Up/Down Count Operation (Interrupt Request Timing) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-145 10 10.8 TOU (Output-Related 24-Bit Timer) 10.8.1 Outline of TOU MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU (Timer Output Unification) is an output-related 24-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time. • PWM output mode • Single-shot PWM output mode • Delayed single-shot output mode • Single-shot output mode • Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TOU, respectively. Table 10.8.1 Specifications of TOU (Output-Related 24-Bit Timer) Item Number of channels Counter Reload register Timer startup Specification 16 channels (8 channels × 2 circuit blocks) 24-bit down-counter (or 16-bit down counter when in PWM output or single-shot PWM output mode) 24-bit reload register (or 16-bit reload register when in PWM output or single-shot PWM output mode) TOU0: • Writing to the enable bit in software • TID0 underflow/overflow signal • TOU0_7 underflow signal • Output event bus 0 signal • External input TIN25 signal TOU1: • Writing to the enable bit in software • TID1 underflow/overflow signal • TOU1_7 underflow signal • TOU0 cause of start signal (Event enable must be selected by TOU0) • External input TIN27 signal Mode switching • PWM output mode • Single-shot PWM output mode • Delayed single-shot output mode • Single-shot output mode • Continuous output mode Interrupt request generation DMA transfer request generation Can be generated by a counter underflow Can be generated by a counter underflow 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-146 10 TIN16/PWMOFF0 (P130) PWMOFF0S MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Output event bus 0 IRQ13 PO0DIS clk clk clk clk clk clk clk IRQ11 en TOU0_0 (24-bit) en TOU0_1 (24-bit) en TOU0_2 (24-bit) en TOU0_3 (24-bit) en TOU0_4 (24-bit) en TOU0_5 (24-bit) en TOU0_6 (24-bit) en TOU0_7 (24-bit) CLK1 CLK2 TID 0 S udf DMA5 IRQ13 F/F21 F/F22 DMA6 IRQ13 TO21 (P00/P87) TO22 (P01/P86) TO23 (P02/P85) TO24 (P03/P84) TO25 (P04/P83) TO26 (P05/P82) TO27 (P06/P175) TO28 (P07/P174) udf udf DMA7 IRQ13 F/F23 F/F24 udf IRQ13 udf IRQ13 F/F25 F/F26 IRQ13 udf udf DMA8 IRQ13 F/F27 F/F28 DMA9 IRQ14 DMA0 TIN24S BCLK 1/4 PRS3 S clk clk udf ovf udf TIN24 (P103) TIN25 (P104) TIN25S TIN17/PWMOFF1 (P131) PWMOFF1S IRQ11 clk clk clk clk clk clk clk IRQ11 IRQ16 PO1DIS en TOU1_0 (24-bit) en TOU1_1 (24-bit) en TOU1_2 (24-bit) en TOU1_3 (24-bit) en TOU1_4 (24-bit) en TOU1_5 (24-bit) en TOU1_6 (24-bit) en TOU1_7 (24-bit) CLK1 CLK2 TID 1 S udf udf udf DMA0 IRQ16 DMA1 IRQ16 F/F29 F/F30 F/F31 F/F32 TO29 (P10/P110) TO30 (P11/P111) TO31 (P12/P112) TO32 (P13/P113) TO33 (P14/P114) TO34 (P15/P115) TO35 (P16/P116) TO36 (P17/P117) IRQ16 udf IRQ16 udf IRQ16 F/F33 F/F34 IRQ16 udf udf udf DMA4 DMA3 IRQ16 F/F35 F/F36 TIN26S BCLK 1/4 PRS4 S clk clk ovf udf TIN26 (P73) TIN27 (P72) TIN27S IRQ15 DMA1 IRQ11 Figure 10.8.1 Block Diagram of TOU (Output-Related 24-Bit Timer) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-147 10 10.8.2 Outline of Each Mode of TOU MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Each mode of TOU is outlined below. Modes on each TOU channel can be selected from the following, only one at a time. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that " the reload 0 register -1" and starts counting down synchronously with the count clock. At the cycle after first time the counter underflows, it is loaded with the contents that " the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs.The " reload 0 register set value + 1" and " reload 1 register set value + 1" respectively are effective as count values. Stopping timer and count disable writing to enable bit occur at same time. (Stopping time is not synchronized with PWM output period.) The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter starts counting and each time it underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt request and DMA transfer request can be generated at even-numbered occurrences of underflow after the counter is enabled. (2) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that " the reload 1 register -1" and continues counting. The counter stops when it underflows next time. The " reload 0 register set value + 1" and " reload 1 register set value + 1" respectively are effective as count values. The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated when the counter underflows second time after being enabled. (3) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of " reload register set value + 1" after a finite time equal to " counter set value + 1" only once and then stops. When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that " the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of " reload register set value + 1" after a finite time equal to " first set value of counter + 1" only once. An interrupt request and DMA transfer request can be generated when the counter underflows first time and next. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-148 10 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of " reload register set value + 1" only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of " the reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of " reload register set value + 1" only once. An interrupt request and DMA transfer request can be generated when the counter underflows. (5) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the value that the reload register. Thereafter, this operation is repeated each time the counter underflows, thus generating inverted consecutive pulses in width of " reload register set value + 1." When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow causes the counter to be loaded with the content of " the reload register -1" and start counting over again at the next cycle. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request and DMA transfer request can be generated each time the counter underflows. • Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. Write to the enable bit BCLK Count clock period Count clock Enable F/F operation (Note 1) Count clock-dependent delay Inverted Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Figure 10.8.2 Count Clock Dependent Delay 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-149 10 10.8.3 TOU Related Register Map Shown below is a TOU related register map. TOU Related Register Map (1/3) Address b0 H'0080 0520 H'0080 0522 H'0080 0524 H'0080 0526 +0 address b7 b8 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) +1 address See pages 10-168 10-171 10-168 10-171 b15 PWM Output 0 Disable Control Register GA PWM Output 0 Disable Level Control Register GA (PO0DISGACR) (PO0LVGACR) PWM Output 1 Disable Control Register GA PWM Output 1 Disable Level Control Register GA (PO1DISGACR) (PO1LVGACR) (Use inhibited area) PWMOFF 0 Function Enable Register (PWMOFF0EN) PWMOFF 1 Function Enable Register (PWMOFF1EN) 10-173 | H'0080 0780 H'0080 0782 PWM Output 0 Disable Control Register GB (PO0DISGBCR) PWM Output 1 Disable Control Register GB (PO1DISGBCR) PWM Output 0 Disable Level Control Register GB (PO0LVGBCR) PWM Output 1 Disable Level Control Register GB (PO1LVGBCR) 10-168 10-171 10-169 10-171 | H'0080 0790 H'0080 0792 H'0080 0794 H'0080 0796 H'0080 0798 H'0080 079A H'0080 079C H'0080 079E H'0080 07A0 H'0080 07A2 H'0080 07A4 H'0080 07A6 H'0080 07A8 H'0080 07AA H'0080 07AC H'0080 07AE H'0080 07B0 H'0080 07B2 H'0080 07B4 H'0080 07B6 TOU0_4 Reload Register (TOU04RLW) TOU0_4 Counter (TOU04CTW) TOU0_3 Reload Register (TOU03RLW) TOU0_3 Counter (TOU03CTW) TOU0_2 Reload Register (TOU02RLW) TOU0_2 Counter (TOU02CTW) TOU0_1 Reload Register (TOU01RLW) TOU0_1 Counter (TOU01CTW) TOU0_0 Reload Register (TOU00RLW) TOU0_0 Counter (TOU00CTW) (Upper) (TOU00CTH) (Lower) (TOU00CT) TOU0_0 Reload 1 Register (TOU00RL1) TOU0_0 Reload 0 Register (TOU00RL0) (Upper) (TOU01CTH) (Lower) (TOU01CT) TOU0_1 Reload 1 Register (TOU01RL1) TOU0_1 Reload 0 Register (TOU01RL0) (Upper) (TOU02CTH) (Lower) (TOU02CT) TOU0_2 Reload 1 Register (TOU02RL1) TOU0_2 Reload 0 Register (TOU02RL0) (Upper) (TOU03CTH) (Lower) (TOU03CT) TOU0_3 Reload 1 Register (TOU03RL1) TOU0_3 Reload 0 Register (TOU03RL0) (Upper) (TOU04CTH) (Lower) (TOU04CT) TOU0_4 Reload 1 Register (TOU04RL1) TOU0_4 Reload 0 Register (TOU04RL0) 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-150 10 TOU Related Register Map (2/3) Address b0 H'0080 07B8 H'0080 07BA H'0080 07BC H'0080 07BE H'0080 07C0 H'0080 07C2 H'0080 07C4 H'0080 07C6 H'0080 07C8 H'0080 07CA H'0080 07CC H'0080 07CE +0 address MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) +1 address b7 b8 TOU0_5 Counter (TOU05CTW) b15 (Upper) (TOU05CTH) (Lower) (TOU05CT) TOU0_5 Reload 1 Register (TOU05RL1) TOU0_5 Reload 0 Register (TOU05RL0) (Upper) (TOU06CTH) (Lower) (TOU06CT) TOU0_6 Reload 1 Register (TOU06RL1) TOU0_6 Reload 0 Register (TOU06RL0) (Upper) (TOU07CTH) (Lower) (TOU07CT) TOU0_7 Reload 1 Register (TOU07RL1) TOU0_7 Reload 0 Register (TOU07RL0) See pages 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 TOU0_5 Reload Register (TOU05RLW) TOU0_6 Counter (TOU06CTW) TOU0_6 Reload Register (TOU06RLW) TOU0_7 Counter (TOU07CTW) TOU0_7 Reload Register (TOU07RLW) | H'0080 07D4 H'0080 07D6 H'0080 07D8 H'0080 07DA H'0080 07DC H'0080 07DE H'0080 07E0 Shorting Prevention Function F/F21–26 Protect Register (SHFF2126P) Shorting Prevention Function F/F21–26 Data Register (SHFF2126D) TOU0 Control Register 1 (TOU0CR1) TOU0 Control Register 0 (TOU0CR0) (Use inhibited area) TOU0 Enable Protect Register (TOU0PRO) (Use inhibited area) TOU0 Count Enable Register (TOU0CEN) PWMOFF0 Input Processing Control Register (PWMOFF0CR) 10-155 10-156 10-153 10-153 10-163 10-164 10-166 | H'0080 0B90 H'0080 0B92 H'0080 0B94 H'0080 0B96 H'0080 0B98 H'0080 0B9A H'0080 0B9C H'0080 0B9E TOU1_1 Reload Register (TOU11RLW) TOU1_1 Counter (TOU11CTW) TOU1_0 Reload Register (TOU10RLW) TOU1_0 Counter (TOU10CTW) (Upper) (TOU10CTH) (Lower) (TOU10CT) TOU1_0 Reload 1 Register (TOU10RL1) TOU1_0 Reload 0 Register (TOU10RL0) (Upper) (TOU11CTH) (Lower) (TOU11CT) TOU1_1 Reload 1 Register (TOU11RL1) TOU1_1 Reload 0 Register (TOU11RL0) 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-151 10 TOU Related Register Map (3/3) Address b0 H'0080 0BA0 H'0080 0BA2 H'0080 0BA4 H'0080 0BA6 H'0080 0BA8 H'0080 0BAA H'0080 0BAC H'0080 0BAE H'0080 0BB0 H'0080 0BB2 H'0080 0BB4 H'0080 0BB6 H'0080 0BB8 H'0080 0BBA H'0080 0BBC H'0080 0BBE H'0080 0BC0 H'0080 0BC2 H'0080 0BC4 H'0080 0BC6 H'0080 0BC8 H'0080 0BCA H'0080 0BCC H'0080 0BCE +0 address MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) +1 address b7 b8 TOU1_2 Counter (TOU12CTW) b15 (Upper) (TOU12CTH) (Lower) (TOU12CT) TOU1_2 Reload 1 Register (TOU12RL1) TOU1_2 Reload 0 Register (TOU12RL0) (Upper) (TOU13CTH) (Lower) (TOU13CT) TOU1_3 Reload 1 Register (TOU13RL1) TOU1_3 Reload 0 Register (TOU13RL0) (Upper) (TOU14CTH) (Lower) (TOU14CT) TOU1_4 Reload 1 Register (TOU14RL1) TOU1_4 Reload 0 Register (TOU14RL0) (Upper) (TOU15CTH) (Lower) (TOU15CT) TOU1_5 Reload 1 Register (TOU15RL1) TOU1_5 Reload 0 Register (TOU15RL0) (Upper) (TOU16CTH) (Lower) (TOU16CT) TOU1_6 Reload 1 Register (TOU16RL1) TOU1_6 Reload 0 Register (TOU16RL0) (Upper) (TOU17CTH) (Lower) (TOU17CT) TOU1_7 Reload 1 Register (TOU17RL1) TOU1_7 Reload 0 Register (TOU17RL0) See pages 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 10-157 10-159 10-160 10-162 10-161 TOU1_2 Reload Register (TOU12RLW) TOU1_3 Counter (TOU13CTW) TOU1_3 Reload Register (TOU13RLW) TOU1_4 Counter (TOU14CTW) TOU1_4 Reload Register (TOU14RLW) TOU1_5 Counter (TOU15CTW) TOU1_5 Reload Register (TOU15RLW) TOU1_6 Counter (TOU16CTW) TOU1_6 Reload Register (TOU16RLW) TOU1_7 Counter (TOU17CTW) TOU1_7 Reload Register (TOU17RLW) | Shorting Prevention Function F/F29–34 Protect Register (SHFF2934P) H'0080 0BD6 Shorting Prevention Function F/F29–34 Data Register (SHFF2934D) H'0080 0BD8 TOU1 Control Register 1 (TOU1CR1) H'0080 0BDA TOU1 Control Register 0 (TOU1CR0) H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register (TOU1PRO) H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register (TOU1CEN) H'0080 0BE0 PWMOFF1 Input Processing Control Register (PWMOFF1CR) H'0080 0BD4 10-155 10-156 10-154 10-154 10-163 10-164 10-166 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-152 10 10.8.4 TOU Control Registers TOU0 Control Register 0 (TOU0CR0) b0 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 7 0 1 0 2 0 3 0 4 0 5 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TOU00M0 TOU01M0 TOU02M0 TOU03M0 TOU04M0 TOU05M0 TOU06M0 TOU07M0 b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TOU00M0 (TOU0_0 operation mode select 0 bit) TOU01M0 (TOU0_1 operation mode select 0 bit) TOU02M0 (TOU0_2 operation mode select 0 bit) TOU03M0 (TOU0_3 operation mode select 0 bit) TOU04M0 (TOU0_4 operation mode select 0 bit) TOU05M0 (TOU0_5 operation mode select 0 bit) TOU06M0 (TOU0_6 operation mode select 0 bit) TOU07M0 (TOU0_7 operation mode select 0 bit) Function 00: Single-shot output mode 01: Single-shot PWM output mode or delayed single-shot output mode (Note 1) 10: Continuous output mode 11: PWM output mode R R W W Note 1: Use TOU0 Control Register 1 to select between these two modes. Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. TOU0 Control Register 1 (TOU0CR1) b0 TOU0 CKS 0 7 8 9 10 11 12 13 14 b15 1 PRS3 CKS 0 2 0 3 0 4 0 5 0 6 0 TOU0 TOU00 TOU01 TOU02 TOU03 TOU04 TOU05 TOU06 TOU07 SHEN M1 M1 M1 M1 M1 M1 M1 M1 0 0 0 0 0 0 0 0 0 b 0 1 2–6 7 8 9 10 11 12 13 14 15 Bit Name TOU0CKS TOU0 clock source select bit PRS3CKS Prescaler 3 supplied clock select bit No function assigned. Fix to "0." TOU0SHEN TOU0 shorting prevention function enable bit TOU00M1 (TOU0_0 operation mode select 1 bit) TOU01M1 (TOU0_1 operation mode select 1 bit) TOU02M1 (TOU0_2 operation mode select 1 bit) TOU03M1 (TOU0_3 operation mode select 1 bit) TOU04M1 (TOU0_4 operation mode select 1 bit) TOU05M1 (TOU0_5 operation mode select 1 bit) TOU06M1 (TOU0_6 operation mode select 1 bit) TOU07M1 (TOU0_7 operation mode select 1 bit) • Operation mode and the short preventiion function can only be set or changed while the counter is inactive. 0: Disable shorting prevention function 1: Enable shorting prevention function 0: Single-shot PWM output mode 1: Delayed single-shot output mode Function 0: Use prescaler 3 1: Use external clock (TIN24) 0: BCLK/4 1: BCLK 0 R R – W W R W R R W W Notes: • This register must always be accessed in halfwords. TOU0 Control Registers 0 and 1 are used to select operation modes of TOU0_0–7. To select prescaler 3 as the clock source for TOU0, make sure the TID0 Control & Prescaler 3 Enable Register’s prescaler 3 enable bit is set to "1." For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.” Note: • Before setting up or modifying the TOU control register, be sure to stop the relevant timer by writing "0" to its count enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-153 10 TOU1 Control Register 0 (TOU1CR0) b0 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 7 0 1 0 2 0 3 0 4 0 5 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TOU10M0 TOU11M0 TOU12M0 TOU13M0 TOU14M0 TOU15M0 TOU16M0 TOU17M0 b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TOU10M0 (TOU1_0 operation mode select 0 bit) TOU11M0 (TOU1_1 operation mode select 0 bit) TOU12M0 (TOU1_2 operation mode select 0 bit) TOU13M0 (TOU1_3 operation mode select 0 bit) TOU14M0 (TOU1_4 operation mode select 0 bit) TOU15M0 (TOU1_5 operation mode select 0 bit) TOU16M0 (TOU1_6 operation mode select 0 bit) TOU17M0 (TOU1_7 operation mode select 0 bit) Function 00: Single-shot output mode 01: Single-shot PWM output mode or delayed single-shot output mode (Note 1) 10: Continuous output mode 11: PWM output mode R R W W Note 1: Use TOU1 Control Register 1 to select between these two modes. Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. TOU1 Control Register 1 (TOU1CR1) b0 TOU1 CKS 0 7 8 9 10 11 12 13 14 b15 1 PRS4 CKS 0 2 0 3 0 4 0 5 0 6 0 TOU1 TOU10 TOU11 TOU12 TOU13 TOU14 TOU15 TOU16 TOU17 SHEN M1 M1 M1 M1 M1 M1 M1 M1 0 0 0 0 0 0 0 0 0 b 0 1 2–6 7 8 9 10 11 12 13 14 15 Bit Name TOU1CKS TOU1 clock source select bit PRS4CKS Prescaler 4 supplied clock select bit No function assigned. Fix to "0." TOU1SHEN TOU1 shorting prevention function enable bit TOU10M1 (TOU1_0 operation mode select 1 bit) TOU11M1 (TOU1_1 operation mode select 1 bit) TOU12M1 (TOU1_2 operation mode select 1 bit) TOU13M1 (TOU1_3 operation mode select 1 bit) TOU14M1 (TOU1_4 operation mode select 1 bit) TOU15M1 (TOU1_5 operation mode select 1 bit) TOU16M1 (TOU1_6 operation mode select 1 bit) TOU17M1 (TOU1_7 operation mode select 1 bit) • Operation mode and the short preventiion function can only be set or changed while the counter is inactive. 0: Disable shorting prevention function 1: Enable shorting prevention function 0: Single-shot PWM output mode 1: Delayed single-shot output mode R W Function 0: Use prescaler 4 1: Use external clock (TIN26) 0: BCLK/4 1: BCLK 0 R – W R W R R W W Notes: • This register must always be accessed in halfwords. TOU1 Control Registers 0 and 1 are used to select operation modes of TOU1_0–7. To select prescaler 4 as the clock source for TOU1, make sure the TID1 Control & Prescaler 4 Enable Register’s prescaler 4 enable bit is set to "1." For details, see Section 10.7.3, "TID Control & Prescaler Enable Registers." Note: • Before setting up or modifying the TOU control register, be sure to stop the relevant timer by writing "0" to its count enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-154 10 10.8.5 Shorting Prevention Function Registers b0 SHFP21 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Shorting Prevention Function F/F21-26 Protect Register (SHFF2126P) 1 SHFP22 0 2 SHFP23 0 3 SHFP24 0 4 SHFP25 0 5 SHFP26 0 6 0 b7 0 b 0 1 2 3 4 5 6, 7 Bit Name SHFP21 Shorting prevention function F/F21 protect bit SHFP22 Shorting prevention function F/F22 protect bit SHFP23 Shorting prevention function F/F23 protect bit SHFP24 Shorting prevention function F/F24 protect bit SHFP25 Shorting prevention function F/F25 protect bit SHFP26 Shorting prevention function F/F26 protect bit No function assigned. Fix to "0." 0 0 Function 0: Enable write to shorting prevention function F/F output bit 1: Disable write to shorting prevention function F/F output bit R R W W Shorting Prevention Function F/F29–34 Protect Register (SHFF2934P) b0 SHFP29 0 1 SHFP30 0 2 SHFP31 0 3 SHFP32 0 4 SHFP33 0 5 SHFP34 0 6 0 b7 0 b 0 1 2 3 4 5 6, 7 Bit Name SHFP29 Shorting prevention function F/F29 protect bit SHFP30 Shorting prevention function F/F30 protect bit SHFP31 Shorting prevention function F/F31 protect bit SHFP32 Shorting prevention function F/F32 protect bit SHFP33 Shorting prevention function F/F33 protect bit SHFP34 Shorting prevention function F/F34 protect bit No function assigned. Fix to "0." 0 0 Function 0: Enable write to shorting prevention function F/F output bit 1: Disable write to shorting prevention function F/F output bit R R W W These registers control write to each shorting prevention function F/F (flip-flop) by enabling or disabling. If write to any F/F is disabled, writing to the shorting prevention F/F data register has no efect. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-155 10 b0 SHFD21 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) b7 0 Shorting Prevention Function F/F21-26 Data Register (SHFF2126D) 1 SHFD22 0 2 SHFD23 0 3 SHFD24 0 4 SHFD25 0 5 SHFD26 0 6 0 b 0 1 2 3 4 5 6, 7 Bit Name SHFD21 Shorting prevention function F/F21 data bit SHFD22 Shorting prevention function F/F22 data bit SHFD23 Shorting prevention function F/F23 data bit SHFD24 Shorting prevention function F/F24 data bit SHFD25 Shorting prevention function F/F25 data bit SHFD26 Shorting prevention function F/F26 data bit No function assigned. Fix to "0." 0 0 Function 0: Shorting prevention function F/F output data = 0 1: Shorting prevention function F/F output data = 1 R R W W Shorting Prevention Function F/F29–34 Data Register (SHFF2934D) b0 SHFD29 0 b7 0 1 SHFD30 0 2 SHFD31 0 3 SHFD32 0 4 SHFD33 0 5 SHFD34 0 6 0 b 0 1 2 3 4 5 6, 7 Bit Name SHFD29 Shorting prevention function F/F29 data bit SHFD30 Shorting prevention function F/F30 data bit SHFD31 Shorting prevention function F/F31 data bit SHFD32 Shorting prevention function F/F32 data bit SHFD33 Shorting prevention function F/F33 data bit SHFD34 Shorting prevention function F/F34 data bit No function assigned. Fix to "0." 0 0 Function 0: Shorting prevention function F/F output data = 0 1: Shorting prevention function F/F output data = 1 R R W W These registers are used to set output in each shorting prevention function F/F (flip-flop). The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-156 10 10.8.6 TOU Counters MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) The TOU counters are functionally different depending on the timer’s operation mode. (1) TOU counters during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Counter (TOU00CTW) TOU0_1 Counter (TOU01CTW) TOU0_2 Counter (TOU02CTW) TOU0_3 Counter (TOU03CTW) TOU0_4 Counter (TOU04CTW) TOU0_5 Counter (TOU05CTW) TOU0_6 Counter (TOU06CTW) TOU0_7 Counter (TOU07CTW) TOU1_0 Counter (TOU10CTW) TOU1_1 Counter (TOU11CTW) TOU1_2 Counter (TOU12CTW) TOU1_3 Counter (TOU13CTW) TOU1_4 Counter (TOU14CTW) TOU1_5 Counter (TOU15CTW) TOU1_6 Counter (TOU16CTW) TOU1_7 Counter (TOU17CTW) b0 ? 6 ? 1 ? 2 ? 3 ? 4 ? 5 ? 7 ? 8 9 10 11 12 13 14 b15 TOU00CTW-TOU07CTW, TOU10CTW-TOU17CTW ? ? ? ? ? ? ? ? b16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 ? b31 ? b 0–7 8–31 Bit Name No function assigned. Fix to "0" TOU00CTW-TOU07CTW, TOU10CTW-TOU17CTW Note: • This register has to be accessed in word (32 bit) from word boundary(the low address B'00). 24-bit counter value Function R 0 R W 0 W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-157 10 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively. Bits 0–7 are ignored. When writing to the counter separately in high and low-order bits, rewrite the 8 high-order bits first and then the 16 low-order bits. The 8 high-order bits become effective when the 16 low-order bits are rewritten. If the counter is rewritten in the reverse order beginning with the 16 low-order bits, the value of the 8 high-order bits is not reflected until the next time the 16 low-order bits are rewritten. If the 8 high-order bits are read before the CPU has finished rewriting the 16 low-order bits after rewriting the 8 high-order bits. The read value shows the previous data (when not counting) or the current count of the previous data (when count is in progress), and not the new rewritten data. If the counter is written to in 32-bit units, it is rewritten successively in order of the 8 high-order bits and then the 16 low-order bits automatically. During PWM output or single-shot PWM output mode, the TOU counters operate as a 16-bit down-counter where only the 16 low-order bits are effective. For details, see Section 10.8.6, Paragraph (2), “TOU counters during PWM output and single-shot PWM output modes.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-158 10 TOU0_0 Counter (TOU00CT) TOU0_1 Counter (TOU01CT) TOU0_2 Counter (TOU02CT) TOU0_3 Counter (TOU03CT) TOU0_4 Counter (TOU04CT) TOU0_5 Counter (TOU05CT) TOU0_6 Counter (TOU06CT) TOU0_7 Counter (TOU07CT) TOU1_0 Counter (TOU10CT) TOU1_1 Counter (TOU11CT) TOU1_2 Counter (TOU12CT) TOU1_3 Counter (TOU13CT) TOU1_4 Counter (TOU14CT) TOU1_5 Counter (TOU15CT) TOU1_6 Counter (TOU16CT) TOU1_7 Counter (TOU17CT) MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (2) TOU counters during PWM output and single-shot PWM output modes b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOU00CT–TOU07CT, TOU10CT–TOU17CT b 0–15 Bit Name TOU00CT–TOU07CT, TOU10CT–TOU17CT Note: • These registers must always be accessed in halfwords. Function 16-bit counter value R R W W The TOU counters operate as a 16-bit down-counter when in PWM output or single-shot PWM output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. During single-shot output, delayed single-shot output and continuous output modes, the TOU counters operate as a 24-bit down-counter, with the 8 high-order bits added. For details, see Section 10.8.6, Paragraph (1), “TOU counters during single-shot output, delayed single-shot output and continuous output modes.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-159 10 10.8.7 TOU Reload Registers MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) The TOU reload registers are used to load data into the TOU counters. These registers are functionally different depending on the timer’s operation mode. (1) TOU reload registers during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Reload Register (TOU00RLW) TOU0_1 Reload Register (TOU01RLW) TOU0_2 Reload Register (TOU02RLW) TOU0_3 Reload Register (TOU03RLW) TOU0_4 Reload Register (TOU04RLW) TOU0_5 Reload Register (TOU05RLW) TOU0_6 Reload Register (TOU06RLW) TOU0_7 Reload Register (TOU07RLW) TOU1_0 Reload Register (TOU10RLW) TOU1_1 Reload Register (TOU11RLW) TOU1_2 Reload Register (TOU12RLW) TOU1_3 Reload Register (TOU13RLW) TOU1_4 Reload Register (TOU14RLW) TOU1_5 Reload Register (TOU15RLW) TOU1_6 Reload Register (TOU16RLW) TOU1_7 Reload Register (TOU17RLW) b0 ? 7 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 8 9 10 11 12 13 14 b15 TOU00RLW-TOU07RLW, TOU10RLW-TOU17RLW ? ? ? ? ? ? ? ? b16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 ? b31 ? b 0–7 8–31 Bit Name No function assigned. Fix to "0." TOU00RLW–TOU07RLW, TOU10RLW–TOU17RLW Note: • This register has to be accessed in word (32 bit) from word boundary(The lower address B’00). 24-bit reload register value Function R 0 R W 0 W During single-shot output, delayed single-shot output and continuous output modes, TOU operates as a 24-bit timer. The value set in the 24 low-order bits of the reload register is loaded into the counter. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively. Bits 0–7 are ignored. The content of " the reload register -1" is loaded into the counter synchronously with the count clock at the following timing: • At the next cycle when the counter is enabled in single-shot output mode • At the next cycle when the counter has underflowed in delayed single-shot output or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. During PWM output and single-shot PWM output modes, the TOU reload register operates as 16-bit reload 0 and reload 1 registers. For details, see Section 10.8.7, Paragraph (2), “TOU reload registers during PWM output and single-shot PWM output modes.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-160 10 TOU0_0 Reload 0 Register (TOU00RL0) TOU0_1 Reload 0 Register (TOU01RL0) TOU0_2 Reload 0 Register (TOU02RL0) TOU0_3 Reload 0 Register (TOU03RL0) TOU0_4 Reload 0 Register (TOU04RL0) TOU0_5 Reload 0 Register (TOU05RL0) TOU0_6 Reload 0 Register (TOU06RL0) TOU0_7 Reload 0 Register (TOU07RL0) TOU1_0 Reload 0 Register (TOU10RL0) TOU1_1 Reload 0 Register (TOU11RL0) TOU1_2 Reload 0 Register (TOU12RL0) TOU1_3 Reload 0 Register (TOU13RL0) TOU1_4 Reload 0 Register (TOU14RL0) TOU1_5 Reload 0 Register (TOU15RL0) TOU1_6 Reload 0 Register (TOU16RL0) TOU1_7 Reload 0 Register (TOU17RL0) b0 ? MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (2) TOU reload registers during PWM output and single-shot PWM output modes 8 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOU00RL0–TOU07RL0, TOU10RL0–TOU17RL0 b 0–15 Bit Name TOU00RL0–TOU07RL0, TOU10RL0–TOU17RL0 Note: • These registers must always be accessed in halfwords. Function 16-bit reload register value R R W W During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 0 register to set the 16-bit value to be loaded into the counter when it is enabled. The content of " the reload 0 register -1" is loaded into the counter synchronously with the count clock at the following timing: • At the next cycle when the counter is enabled • At the next cycle when the count value set in the reload 1 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value ‘H'FFFF’ is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-161 10 TOU0_0 Reload 1 Register (TOU00RL1) TOU0_1 Reload 1 Register (TOU01RL1) TOU0_2 Reload 1 Register (TOU02RL1) TOU0_3 Reload 1 Register (TOU03RL1) TOU0_4 Reload 1 Register (TOU04RL1) TOU0_5 Reload 1 Register (TOU05RL1) TOU0_6 Reload 1 Register (TOU06RL1) TOU0_7 Reload 1 Register (TOU07RL1) TOU1_0 Reload 1 Register (TOU10RL1) TOU1_1 Reload 1 Register (TOU11RL1) TOU1_2 Reload 1 Register (TOU12RL1) TOU1_3 Reload 1 Register (TOU13RL1) TOU1_4 Reload 1 Register (TOU14RL1) TOU1_5 Reload 1 Register (TOU15RL1) TOU1_6 Reload 1 Register (TOU16RL1) TOU1_7 Reload 1 Register (TOU17RL1) b0 ? MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 8 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? TOU00RL1–TOU07RL1, TOU10RL1–TOU17RL1 b 0–15 Bit Name TOU00RL1–TOU07RL1, TOU10RL1–TOU17RL1 Function 16-bit reload register value R R W W Note: • These registers must always be accessed in halfwords. During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 1 register to set the 16-bit value to be loaded into the counter when the count value set in the reload 1 register has underflowed. The content of " the reload 1 register -1" is loaded into the counter synchronously with the count clock at the following timing: • At the next cycle when the count value set in the reload 0 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value ‘H'FFFF’ is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.” 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-162 10 10.8.8 TOU Enable Protect Registers TOU0 Enable Protect Register (TOU0PRO) TOU1 Enable Protect Register (TOU1PRO) b8 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 13 0 9 0 10 0 11 0 12 0 14 0 b15 0 TOUn0PRO TOUn1PRO TOUn2PRO TOUn3PRO TOUn4PRO TOUn5PRO TOUn6PRO TOUn7PRO b 8 9 10 11 12 13 14 15 Bit Name TOUn0PRO TOUn_0 enable protect bit TOUn1PRO TOUn_1 enable protect bit TOUn2PRO TOUn_2 enable protect bit TOUn3PRO TOUn_3 enable protect bit TOUn4PRO TOUn_4 enable protect bit TOUn5PRO TOUn_5 enable protect bit TOUn6PRO TOUn_6 enable protect bit TOUn7PRO TOUn_7 enable protect bit Function 0: Enable rewrite 1: Disable rewrite R R W W The TOU enable protect registers control rewriting of the TOU count enable bit described in Section 10.8.9, “TOU Count Enable Registers,” by enabling or disabling rewrite. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-163 10 10.8.9 TOU Count Enable Registers TOU0 Count Enable Register (TOU0CEN) TOU1 Count Enable Register (TOU1CEN) b8 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) b7 0 1 0 2 0 3 0 4 PWMOFF0SP 5 0 6 PWMOFF0S 0 0 b 0–3 4 5–7 Bit Name No function assigned. Fix to "0." PWMOFF0SP PWMOFF0S write control bit PWMOFF0S PWMOFF0 input processing control bit 000: Input has no effect 001: Rising edge 010: Falling edge 011: Both edges 10X: "L" level 11X: "H" level R W – Function R 0 0 W 0 W PWMOFF1 Input Processing Control Register (PWMOFF1CR) b0 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 PO1DISGAP PO1DISGA R 0 W 0 W W b 0–5 6 7 Bit Name No function assigned. Fix to "0." PO1DISGAP PO1DISGA write control bit PO1DISGA P110/TO29–P115/TO34 output disable select bit Function – 0: Enable output 1: Disable output 0 R PWM Output 0 Disable Control Register GB (PO0DISGBCR) b0 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 PO0DISGBP PO0DISGB R 0 W 0 W W b 0–5 6 7 Bit Name No function assigned. Fix to "0." PO0DISGBP PO0DISGB write control bit PO0DISGB P00/TO21–P05/TO26 output disable select bit Function – 0: Enable output 1: Disable output 0 R PWM output disable control register is a register which performs disable control of the PWM output from TO 21–26 and TO29–TO34 terminal. Refer to the "10.8.20 PWM Output Disable Function" for the details of PWM Output Disable Function. The procedure of setting up a POnDISGm bit is described blow. 1. Set POnDISGmP Bit of POnDISGmCR as "1" and write it. 2. Write "0" in POnDISGmP Bit and write setting value in POnDISGm Bit. Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 10-168 10 PWM Output 1 Disable Control Register GB (PO1DISGBCR) b0 0 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) b15 0 10 0 11 0 12 0 13 0 14 0 PO0LVSELGA PO0LVENGA b 8–13 14 15 Bit Name No function assigned. Fix to "0." PO0LVSELGA P87/TO21–P82/TO26 output disable level select bit PO0LVENGA Output disable level enable/disable select bit 0: Select "L" output disable level 1: Select "H" output disable level 0: Disable selected output disable level 1: Enable selected output disable level Function R 0 R R W 0 W W PWM Output 1 Disable Level Control Register GA (PO1LVGACR) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 PO0LVSELGB PO0LVENGB b 8–13 14 15 Bit Name No function assigned. Fix to "0." PO0LVSELGB P00/TO21–P05/TO26 output disable level select bit PO0LVENGB Output disable level enable/disable select bit 0: Select "L" output disable level 1: Select "H" output disable level 0: Disable selected output disable level 1: Enable selected output disable level Function R 0 R R W 0 W W PWM Output 1 Disable Level Control Register GB (PO1LVGBCR) b8 0 6 0 1 PWMOFF0 GAEN 2 0 3 0 4 0 5 0 b7 0 0 0 b 0 1 2–7 Bit Name PWMOFF0GBEN P00–P05PWMOFF function select bit PWMOFF0GAEN P87–P82PWMOFF function select bit No function assigned. Fix to "0." Function 0: Disable PWMOFF0 function 1: Enable PWMOFF0 function 0: Disable PWMOFF0 function 1: Enable PWMOFF0 function 0 0 R W R R W W PWMOFF1 Function Enable Register (PWMOFF1EN) b8 PWMOFF1 GBEN 0 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 13-107 13 CAN1 Message Slot 16 Data 5 (C1MSL16DT5) CAN1 Message Slot 17 Data 5 (C1MSL17DT5) CAN1 Message Slot 18 Data 5 (C1MSL18DT5) CAN1 Message Slot 19 Data 5 (C1MSL19DT5) CAN1 Message Slot 20 Data 5 (C1MSL20DT5) CAN1 Message Slot 21 Data 5 (C1MSL21DT5) CAN1 Message Slot 22 Data 5 (C1MSL22DT5) CAN1 Message Slot 23 Data 5 (C1MSL23DT5) CAN1 Message Slot 24 Data 5 (C1MSL24DT5) CAN1 Message Slot 25 Data 5 (C1MSL25DT5) CAN1 Message Slot 26 Data 5 (C1MSL26DT5) CAN1 Message Slot 27 Data 5 (C1MSL27DT5) CAN1 Message Slot 28 Data 5 (C1MSL28DT5) CAN1 Message Slot 29 Data 5 (C1MSL29DT5) CAN1 Message Slot 30 Data 5 (C1MSL30DT5) CAN1 Message Slot 31 Data 5 (C1MSL31DT5) b8 ? CAN MODULE 13.2 CAN Module Related Registers 14 0 9 0 10 0 11 0 12 0 13 0 b15 DD03SEL 0 b 0 1 2 3 4 5 6, 7 Bit Name DIN0IS DIN0 interrupt request status bit DIN1IS DIN1 interrupt request status bit DIN2IS DIN2 interrupt request status bit DIN3IS DIN3 interrupt request status bit DIN4IS DIN4 interrupt request status bit DIN5IS DIN5 interrupt request status bit No function assigned. Fix to "0." 0 0 Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value. Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) If a DINn event is detected according to settings of the DIN Input Processing Control Register, the status bit corresponding to that DINn is set to "1" in hardware. Note: • If the status is cleared in software at the same time it is set for an interrupt request generated, the latter has priority, so that the status is set. DIN Interrupt Request Enable Register (DRIDINIEN) b8 0 b 8 9 10 11 12 13 14, 15 Bit Name DIN0IEN (DIN0 interrupt request enable bit) DIN1IEN (DIN1 interrupt request enable bit) DIN2IEN (DIN2 interrupt request enable bit) DIN3IEN (DIN3 interrupt request enable bit) DIN4IEN (DIN4 interrupt request enable bit) DIN5IEN (DIN5 interrupt request enable bit) No function assigned. Fix to "0." 0 0 Function 0: Mask (disable) interrupt request 1: Enable interrupt request R R W W This register disables or prohibit the interrupt requests that will be generated for DINn event detection. Setting each bit in this register to "1" enables the corresponding DINn event detection interrupt request. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-9 14 DEC Interrupt Request Status Register (DRIDECIST) b0 DEC0IS 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0 1 2 3 4 5–7 Bit Name DEC0IS (DEC0 interrupt request stabus bit) DEC1IS (DEC1 interrupt request stabus bit) DEC2IS (DEC2 interrupt request stabus bit) DEC3IS (DEC3 interrupt request stabus bit) DEC4IS (DEC4 interrupt request stabus bit) No function assigned. Fix to "0." 0 0 Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value. If one of five event counters (DEC0–DEC4) included in the DRI underflows upon reaching the terminal count, the corresponding status bit in this register is set to "1" in hardware. Note: • If the status is cleared in software at the same time it is set for an interrupt request generated, the latter has priority, so that the status is set. DEC Interrupt Request Enable Register (DRIDECIEN) b8 0 b 8 9 10 11 12 13–15 Bit Name DEC0IEN (DEC0 interrupt request enable bit) DEC1IEN (DEC1 interrupt request enable bit) DEC2IEN (DEC2 interrupt request enable bit) DEC3IEN (DEC3 interrupt request enable bit) DEC4IEN (DEC4 interrupt request enable bit) No function assigned. Fix to "0." 0 0 Function 0: Mask (disable) interrupt request 1: Enable interrupt request R R W W This register enables or prohibit the interrupt requests that will be generated when one of the internal event counters underflows. Setting each bit in this register to "1" enables the interrupt request by the corresponding event counter underflow. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-10 14 DRI Transfer Interrupt Request Status Register (DRITRMIST) b0 ADR0IS 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0 1 2 3 4 5–7 Bit Name ADR0IS DRI address counter 0 interrupt request status bit ADR1IS DRI address counter 1 interrupt request status bit OVREIS Overrun error interrupt request status bit DCPEIS Capture enable error interrupt request status bit DTRFIS DRI transfer counter interrupt request status bit No function assigned. Fix to "0." 0 0 Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value. Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) (1) ADR0IS (DRI Address Counter 0 Interrupt Request Status) bit (Bit 0) If while DRI address counter 0 (DRIADR0CT) is enabled as the destination of transfer for the captured data the DRI transfer counter (DRITRMCT) underflows (H'0000 0000: count stop) upon reaching the terminal count, this bit is set to "1" in hardware. (2) ADR1IS (DRI Address Counter 1 Interrupt Request Status) bit (Bit 1) If while DRI address counter 1 (DRIADR1CT) is enabled as the destination of transfer for the captured data the DRI transfer counter (DRITRMCT) underflows (H'0000 0000: count stop) upon reaching the terminal count, this bit is set to "1" in hardware. (3) OVREIS (Overrun Error Interrupt Request Status) bit (Bit 2) The DRI contains four 32-bit intermediate buffers to avoid losses of captured data arising from bus contention for RAM access with other bus masters. If a data capture event is detected while all of the buffers are full, this bit is set to "1" in hardware. In this case, the detected data capture event is ignored. (4) DCPEIS (Capture Enable Error Interrupt Request Status) bit (Bit 3) If the DCPEN (capture enable) bit in the DRI Data Capture Control Register (DRIDCAPCNT) changes state from "0" to "1" or the external event is detected before the DRI capture event counter (DRIDCAPCT) or the DRI transfer counter (DRITRMCT) underflows(H'0000 0000: count stop), this bit is set to "1." [Set condition] 1. If any capture enable external event is selected by DEXSL(capture enable external source select) bit in the DRI Data Capture Control Register (DRIDCAPCNT); and 1) when the selected external event is detected while DCPEN(capture enable) bit is enabled for data capture 2) when the selected external event is detected before the DRI transfer counter (DRITRMCT) underflows(H'0000 0000: count stop) 2. If DCPEN (capture enable) bit is set to "1" from "0" in software before the DRI transfer counter (DRITRMCT) underflows(H'0000 0000: count stop) Notes: • In case of 1, the capture enable event is ignored. • In case of 2, the DRI control unit should be initialized by clearing the DRI Transfer Control Register(DRITRMCNT) and DRI Data Capture Control Register (DRIDCAPCNT) to "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-11 14 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers (5) DTRFIS (DRI Transfer Counter Interrupt Request Status) bit (Bit 4) This bit is set when DRI transfer counter(DRITRMCT) is underflown (H'0000 0000: stop counting). Note: • If the status is cleared in software at the same time it is set for an interrupt request generated, the latter has priority, so that the status is set. DRI Transfer Interrupt Request Enable Register (DRITRMIEN) b8 0 b 8 9 10 11 12 13–15 Bit Name ADR0IEN DRI address counter 0 interrupt request enable bit ADR1IEN DRI address counter 1 interrupt request enable bit OVREIEN Overrun error interrupt request enable bit DCPEIEN Capture enable error interrupt request enable bit DTRFIEN DRI transfer counter interrupt request enable bit No function assigned. Fix to "0." 0 0 Function 0: Mask (disable) interrupt request 1: Enable interrupt request R R W W This register enables or prohibit the interrupt requests that will be generated by the DRI transfer related interrupt status register. Setting any bit in this register to "1" enables the corresponding interrupt request. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-12 14 14.2.3 DRI Transfer Control Register DRI Transfer Control Register (DRITRMCNT) b0 DRST 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers 1 DBST 0 2 ADST 0 3 ADMD 0 4 ADSL 0 5 0 6 0 b7 ADEV 0 b 0 1 2 3 4, 5 Bit Name DRST DRI reset bit DBST DRI buffer status bit ADST Address counter status bit ADMD Address counter operation mode select bit ADSL Address counter select bit Function 0: Reset DRI 1: Enable operation 0: No data exists that has not been DRI transferred yet R 1: Data exists that has not been DRI transferred yet 0: DRI address counter 0 is active 1: DRI address counter 1 is active 0: Continuous mode 1: Reload mode 00: Select DRI address counter 0 01: Select DRI address counter 1 10: Toggle between DRI address counters 0 and 1 11: Settings inhibited 6 7 No function assigned. Fix to "0." ADEV Address counter switchover select bit 0: DRI transfer counter underflow 1: DEC4 underflow 0 R 0 W R W R W R – – R R W W (1) DRST (DRI Reset) bit (Bit 0) This is a software reset bit of the DRI control unit. No data captures nor DRI transfers are performed while this bit = "0." This bit should be set to "1" to enable operation of the DRI. If this bit is cleared to "0" while the DRI is operating, the DRI capture control unit and the DRI transfer control unit both are initialized. Therefore, if any data exists in the DRI that has not been DRI transferred yet, all transfers for that data are canceled, and data captures are not performed either. The following lists the registers and bits that are affected by this bit: 1) ADST(Address counter status) bit If the DRST bit is cleared to "0" while ADSL(address counter select) bits = "10" (DRI address counters 0/1 toggled), the DRI address counter 0(DRIADR0CT) is activated and ADST bit is cleared to "0." 2) DRST(DRI buffer status) bit If the DRST bit is cleared to "0," this status bit is initialized to "0." 3) DRI transfer counter(DRITRMCT) If the DRST bit is cleared to "0," the DRI transfer counter(DRITRMCT) is initialized to "0." Notes: • DIN input processing control and DEC0–4 operations are not affected by setting or clearing the DRST bit. • If the DRST bit changes state from "0" to "1" or vice versa, a finite time of 4 BCLKs is required before the new state takes effect. Changing the DRST bit again during that time is prohibited. • If the DRST bit is set or cleared, a finite time of 1 BCLK is required before ADST bit and DBST bit are initialized. • Changing any of ADMD(address counter operation mode select) bit, ADSL (address counter select) bit or ADVEN(address counter switchover select) bit while the DRST bit = "1" is prohibited. (2) DBST (DRI Buffer Status) bit (Bit 1) This bit indicates whether the internal DRI buffer contains any data that has not been DRI transferred yet. In order to avoid the data loss of Data transfer, middle buffer for 32 bits × 4 row is embedded in the inside of DRI. If the data is in this middle buffer, DBST bit shows “1.” If it is not DBST bit shows “0” Also, when DRST bit is “0” cleared DBST bit is cleared as well. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-13 14 (3) ADST (Address Counter Status) bit (Bit 2) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers This bit indicates which DRI address counter, 0 or 1, is currently selected to specify the destination address of DRI transfer. (4) ADMD (Address Counter Operation Mode Select) bit (Bit 3) This bit selects operation modes of DRI address counter 0(DRIADR0CT) and DRI address counter 1(DRIADR1CT). Both DRI address counters operate in the same mode. • When continuous mode is selected The active DRI address counter is incremented by 4 each time a DRI transfer is completed after DRI transfer is enabled. In continuous mode, no DRI address reload register values are used. • When reload mode is selected When the DCPEN (capture enable) bit in the DRI Data Capture Control Register(DRIDCAPCNT) changes state from "0" to "1" (= enabled) after DRI transfer is enabled, the DRI address counter is reloaded with a count value from the corresponding DRI address reload register. Thereafter, the active DRI address counter is incremented by 4 each time a DRI transfer is completed. Note: • If the bus width for the input data from external devices is chosen to be 8 bits, a DRI transfer is executed every four data capture events detected. Similarly, a DRI transfer is executed every two data capture events detected if the selected bus width is 16 bits or every data capture event detected if the selected bus width is 32 bits. (5) ADSL (Address Counter Select) bits (Bits 4, 5) The DRI contains two address counters to specify the internal RAM address to which data is transferred. These bits are used to select one of the two address counters. 1) When DRI address counter 0 selected Data is transferred to the internal RAM address specified by DRI address counter 0(DRIADR0CT). 2) When DRI address counter 1 selected Data is transferred to the internal RAM address specified by DRI address counter 1(DRIADR1CT). 3) When DRI address counters 0 and 1 toggled The DRI address counters are switched over in hardware by an event selected by the ADEV (address counter switchover select) bit. After a mycrocomputer reset, DRI address counter 0 (DRIADR0CT) is active. When the DRST (DRI reset) bit is cleared to "0," the active DRI address counter is initialized to DRI address counter 0(DRIADR0CT). (6) ADEV (Address Counter Switchover Select) bit (Bit 7) This bit is effective only when the ADSL(address counter select) bit are set to "10" (DRI address counters 0/1 toggled). This bit selects an event that causes the DRI address counter 0(DRIADR0CT) and 1(DRIADR1CT) that specify the destination address on the internal RAM of transfer to switch over. Note: • If a DEC4 underflow is selected as the address counter switchover event, it is prohibited to select DIN4 event detection/capture event as the DEC4 count event. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-14 14 14.2.4 DRI Special Mode Control Register DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers Selecting the special mode allows the DRI to be interfaced with external devices at still higher speed. The width of input data bus during special mode is 8 or 16 bits. And data capturing timing(shown in Figure 14.2.6) can be selected when default timing. DI3 can only be selected for data synchronous signal. Also, the event detection unit and data capture unit of the DRI are clocked by a signal whose transfer rate has been halved as shown in Figure 14.2.5. DRI Special Mode Register (DRISPMOD) b8 SPSSL 0 0 b 8 9 10 11 12–15 Bit Name SPSSL DIN3 sampling edge select bit No function assigned. Fix to "0." SPISL SPMEN Special mode enable bit No function assigned. Fix to "0." 0: "L" level 0: Special mode off 1: Special mode on 0 0 Special mode control unit initialization DIN1 level select bit 1: "H" level R W Function 0: Rising edge 1: Falling edge 0 R 0 W R R W W (1) SPSSL (DIN3 Sampling Edge Select) bit (Bit 8) Select the falling edge as the sampling edge for the transfer method shown in Figure 14.2.4, or the rising edge for the transfer method shown in Figure 14.2.3. This bit can only be changed while the DRST(DRI reset) bit in DRI transfer control register(DRITRMCNT) is "0." Note that the data synchronous signal during special mode is fixed to DIN3, and cannot be changed. In special mode, furthermore, the signal controlled by DIN3ED (DIN3 event detection control) bit in the DIN Input Processing Control Register(DINCNT) is the “output signal to the event detection unit” shown in Figure 14.2.5, and not the input signal from the DIN3 pin. (2) SPISL (Special Mode Control Unit Initialization DIN1 Level Select) bit (Bit 10) The special mode control circuit block can be initialized using the input signal supplied from DIN1. This bit selects the active level of the DIN1 signal by which said circuit is initialized. When DIN1 is driven to the initialization level, the output signals to the event detection unit and data capture unit all go "L," causing data sampling to stop. Conversely, when DIN1 is not at the initialization level, data sampling is performed at given internals and the signal shown in Figure 14.2.5 is passed to the event detection unit/data capture unit. Note that initialization function of the special mode control circuit block by DIN1 is not affected by setting of the DIN1ED bit in the DIN Input Processing Register (DINCNT). Note also that this bit can only be changed when the DRST (DRI reset) bit in the DRI Transfer Control Register (DRITRMCNT) = "0." Note: • If DIN1 changes to the initialization level while the DCPEN (capture enable) bit in the DRI Data Capture Control Register (DRIDCAPCNT) = "1," the following problems may occur: 1) Erroneous data is taken in by the DRI. 2) Eight data prior to a change to the reset state are not taken in. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-15 14 (3) SPMEN (Special Mode Enable) bit (Bit 11) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers This bit selects whether to operate in special mode. If operation is special mode is selected, the following limitations apply. A) DRI Data Capture Control Register (DRIDCAPCNT) 1) DWDSL (Input data bus width select) bit The data width that can be handled in special mode is limited to 8 or 16 bits. According to the handled data width, set the DWDSL bits as follows: • If the input data is 8 bits wide, set the DWDSL bits to "01" (= 16 bits). • If the input data is 16 bits wide, set the DWDSL bits to "10" (= 32 bits). 2) DCPSL (Capture event select) bit Select DIN3. 3) DTMSL (Capture timing select) bit Select the default timing. B) DIN Input Processing Control Register (DINCNT) 1) DIN3ED(DIN3 event detection control) bit Select falling detection. Note: • This register can only be set while the DRST (DRI reset) bit in the DRI Transfer Control Register (DRITRMCNT) = "0," i.e., while the DRI is reset. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-16 14 Data synchronous signal Data DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers Figure 14.2.3 Data Transfer Method 1 Data synchronous signal Data Figure 14.2.4 Data Transfer Method 2 DIN1(Note 1) Data synchronous signal (DIN3) Data Output signal to the event detection unit (Note 2) Output signal to the data capture unit DATA0, DATA1 DATA2, DATA3 DATA4, ... DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 Note1: When "L" level is selected in SPISL bit of DRI special mode register (DRISPMOD) Note2: Select falling detection to DIN3ED(DIN3 event detection control) bit of DIN input processing control register (DINCNT). Figure 14.2.5 Timing Chart when Special Mode is On (DIN3 Sampling Edge: Rise) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-17 14 14.2.5 DRI Data Capture Control Register DRI Data Capture Control Register (DRIDCAPCNT) b0 DCPEN 0 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0 1–3 Bit Name DCPEN Capture enable bit DEXSL Capture enable external source select bit Function 0: Disable capturing data 1: Enable capturing data 0XX: No external source selected 100: DIN0 event detection 101: DIN1 event detection 110: DIN2 event detection 111: DEC0 underflow 4, 5 DDSSL Capture external control disable souce select bit 00: No disable source selected 01: DRI capture event counter underflow 10: DEC3 underflow 11: DEC4 underflow 6, 7 DWDSL Input data bus width select bit 00: 8 bits 01: 16 bits 10: 32 bits 11: Settings inhibited 8, 9 DCPSL Capture event select bit 00: DIN2 event detection 01: DIN3 event detection 10: DIN4 event detection 11: DIN5 event detection 10 11 12–15 DDSL DD input 16-high order bit pin select bit DWRPR Capture control WR protect bit DTMSL Capture timing select bit 0: Select pin group A 1: Select pin group B 0: Enable WR 1: Disable WR 0000: Default 0001: 1 BCLK later 0010: 2 BCLK later 0011: 3 BCLK later 0100: 4 BCLK later 0101: 5 BCLK later 0110: 6 BCLK later 0111: 7 BCLK later 1000: 8 BCLK later 1001: 9 BCLK later 1010: 10 BCLK later 1011: 11 BCLK later 1100: 12 BCLK later 1101: 13 BCLK later 1110: 14 BCLK later 1111: 15 BCLK later Note: • This register must always be accessed halfword (in 16 bits) units from the halfword boundary. R W 0 W R W R W R W R W R W R R W W This register is used to make settings necessary to capture the input data that is fed in synchronously with an external clock signal. Before setting up this register, make sure the DRST (DRI reset) bit in the DRI Transfer Control Register (DRITRMCNT) is set to "1." Also, if the DRST bit is cleared to "0," be sure to clear this register to "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-18 14 (1) DCPEN (Capture Enable) bit (Bit 0) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers When DCPEN = "1," the DRI is enabled for “capturing” data (i.e., taking in data into the internal RAM). [Set condition] • When explicitly set by writing "1" in software • When the event selected by the DEXSL (capture enable external source select) bit is detected [Clear condition] • When explicitly cleared by writing "0" in software • When the DRI capture event counter (DRIDCAPCT) underflows (H'0000 0000: stop counting) upon reaching the terminal count Notes: • If an external source is selected by the DEXSL (capture enable external source select) bit, the bit cannot be set by writing "1" in software. • Before setting the bit by writing "1" in software, always be sure to check the DRI transfer counter (DRITRMCT) to see that the counter is in an underflow (H'0000 0000: stop counting) state. (2) DEXSL (Capture Enable External Source Select) bits (Bits 1–3) These bits select an external source that causes DCPEN (capture enable) bit to be enabled for data capture. When the event selected here is detected, the capture enable bit is set to "1." If no external sources are selected, in no case will the capture enable bit be set by any external source. The external source or event selected by these bits can be cleared to "0" by using the DDSSL (capture external control disable source select) bit. (3) DDSSL (Capture External Control Disable Source Select) bits (Bits 4, 5) These bits select the external source or event to clear the capture enable external source select bits to "0." (4) DWDSL (Input Data Bus Width Select) bits (Bits 6, 7) These bits select the bus width of the input data supplied from external devices. If the bus width is chosen to be 8 bits, a DRI transfer is executed every four data capture events detected. Similarly, a DRI transfer is executed every two data capture events detected if the selected bus width is 16 bits or every data capture event detected if the selected bus width is 32 bits. Table 14.2.1 shows the relationship between each selected bus width and the data bits that are taken in. Note: • When special mode is selected, the input data bus width select bits are subject to setting limitations. For details, refer to DRI Special Mode Control Register (DRISPMOD). (5) DCPSL (Capture Event Select) bits (Bits 8, 9) These bits select an event at which data is taken in. In cases where the DRTS (DRI reset) bit in DRI transfer control register (DRITRMCNT)is enabled for operation, the capture enable bit is enabled for data capture and the interleaving control is in use, data is taken in when the selected event is detected while capture event detection conditions are met.If a data capture event is detected at the same time the DCPEN (capture enable) bit is set, data is taken in. Note: • When special mode is selected, be sure to select DIN3 event detection. (6) DDSL (DD Input 16 High-Order Bit Pin Select) bit (Bit 10) Of the data inputs to the DRI, DDn (n = 0–31), pins for the 16 high-order bits (DD0-DD15) can be selected from two pin groups. This bit selects the pin group (the pin groupA,B) to be used. However, for the other inputs DD16-DD31 are fixed. Table 14.2.2 lists pins in each pin group. If pin group A is selected, the DD Input Pin Select Register (DDSEL) should be set to specify which pins in DD0-DD3 to be used. Note: • Port operation mode must be set separately from this register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-19 14 (7) DWRPR (Capture Control WR Protect) bit (Bit 11) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers This bit controls writing to DCPEN (capture enable) bit and DEXSL (capture enable external source select) bit by enalbing or disabling the access for write. If this bit is "0" when the register is accessed for write, the bits are write-enabled. If this bit is "1," the bits are write-protected. (8) DTMSL (Data Capture Timing Select) bit (Bits 12–15) These bits select the timing with which data is taken in after a data capture event is detected. The DRI detects an event on each falling edge of BCLK. When the default timing is selected, data is taken in synchronously with the falling edge of the same BCLK cycle in which an event is detected. With this as the starting point, data capture can be chosen to occur 1 BCLK to 15 BCLKs later. Figure 14.2.6 shows a data capture timing chart. Note: • When special mode is selected, be sure to select the default timing. Table 14.2.1 Capture Data Positions DD0–7 When 8 bits wide When 16 bits wide When 32 bits wide Captured data Captured data Captured data DD8–15 DD16–23 Don't care Don't care DD24–31 Notes: • When operating in special mode, the relationship between the actual data bus width and the register value set by the input data bus width select bits varies. For details, refer to DRI Special Mode Control Register (DRISPMOD). • DD0 is the MSB, and DD31 is the LSB. Table 14.2.2 Pins in Each Pin Group Function DD03SEL="0" DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 P127/TCLK3/CS3#/DD0 P126/TCLK2/CS2#/DD1 P125/TCLK1/A10/DD2 P124/TCLK0/A9/DD3 Pin group A DD03SEL="1" P107/TO15/RXD4/DD0 P106/TO14/TXD4/DD1 P105/TO13/SCLKI4/SCLKO4/DD2 P104/TO12/TIN25/DD3 P00/DB0/TO21/DD0 P01/DB1/TO22/DD1 P02/DB2/TO23/DD2 P03/DB3/TO24/DD3 P04/DB4/TO25/DD4 P05/DB5/TO26/DD5 P06/DB6/TO27/DD6 P07/DB7/TO28/DD7 P10/DB8/TO29/DD8 P11/DB9/TO30/DD9 P12/DB10/TO31/DD10 P13/DB11/TO32/DD11 P14/DB12/TO33/DD12 P15/DB13/TO34/DD13 P16/DB14/TO35/DD14 P17/DB15/TO36/DD15 Pin group B P117/TO7/TO36/DD4 P116/TO6/TO35/DD5 P115/TO5/TO34/DD6 P114/TO4/TO33/DD7 P113/TO3/TO32/DD8 P112/TO2/TO31/DD9 P111/TO1/TO30/DD10 P110/TO0/TO29/DD11 P97/TO20/DD12 P96/TO19/DD13 P95/TO18/RXD5/DD14 P94/TO17/TXD5/DD15 Notes: • Which pin groups (pin groups A or B) is used is selected in the DDSL bit. • When pin group A is selected which pin is used for DD0 to DD3 is selected in DD03SEL of DDSEL register. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-20 14 Event detection point DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers BCLK Capture timing Default 1 BCLK later 2 BCLK later 14 BCLK later 15 BCLK later Figure 14.2.6 Data Capture Timing 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-21 14 14.2.6 DRI Data Interleave Control Register DRI Data Interleave Control Register (DRIDSELCNT) b0 DSD0 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0 1 2 3 4 5–7 Bit Name DSD0 DEC0 data interleave control bit DSD1 DEC1 data interleave control bit DSD2 DEC2 data interleave control bit DSD3 DEC3 data interleave control bit DSD4 DEC4 data interleave control bit No function assigned. Fix to "0." Function 0: Not interleaved 1: Interleaved by DEC0CT 0: Not interleaved 1: Interleaved by DEC1CT 0: Not interleaved 1: Interleaved by DEC2CT 0: Not interleaved 1: Interleaved by DEC3CT 0: Not interleaved 1: Interleaved by DEC4CT 0 0 R W R W R W R W R R W W The five event counters included in the DRI may be used to have the input data interleaved or “thinned out” in hardware before being taken in. Use this register to make interleave control related settings. If the DECn data interleave control bit (n = 0–4) is set to "0," the input data is not interleaved using the corresponding DECn counter. If the DECn data interleave control bit is set to "1," the input data is interleaved or “thinned out” because data is not taken in unless the corresponding DECn counter is in an underflow state (count value = H'FFFF). If multiple event counters are selected for interleaving control data by this register, data is taken in for only a capture event that is input while all of the DECn counters with their interleave control bits set to "1" are in an underflow state. Note: • The next event occurring after a counter underflow and those that follow are effective as the capture event. 14.2.7 DIN Input Event Select Register DIN Input Event Select Register (DINSEL) b8 0 b 8–13 14, 15 Bit Name No function assigned. Fix to "0." DIN5SL DIN5 input event select bit 00: F/F19 (TIO8) 01: F/F8 (TOP8) 10: F/F28 (TOU0_7) 11: F/F36 (TOU1_7) Function R 0 R W 0 W The value of flip-flop, which is selected by the DIN5SL bit, is fed as an input signal to the DIN5 input processing circuit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-22 14 14.2.8 DD Input Enable Registers DD Input Enable Register 0 (DRIDDEN0) b0 DD0EN 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0 1 2 3 4 5 6 7 Bit Name DD0EN (DD0 input enable bit) DD1EN (DD1 input enable bit) DD2EN (DD2 input enable bit) DD3EN (DD3 input enable bit) DD4EN (DD4 input enable bit) DD5EN (DD5 input enable bit) DD6EN (DD6 input enable bit) DD7EN (DD7 input enable bit) Function 0: Disable input 1: Enable input R R W W DD Input Enable Register 1 (DRIDDEN1) b8 DD8EN 0 b 8 9 10 11 12 13 14 15 Bit Name DD8EN (DD8 input enable bit) DD9EN (DD9 input enable bit) DD10EN (DD10 input enable bit) DD11EN (DD11 input enable bit) DD12EN (DD12 input enable bit) DD13EN (DD13 input enable bit) DD14EN (DD14 input enable bit) DD15EN (DD15 input enable bit) Function 0: Disable input 1: Enable input R R W W DD Input Enable Register 2 (DRIDDEN2) b0 0 b 0 1 2 3 4 5 6 7 Bit Name DD16EN (DD16 input enable bit) DD17EN (DD17 input enable bit) DD18EN (DD18 input enable bit) DD19EN (DD19 input enable bit) DD20EN (DD20 input enable bit) DD21EN (DD21 input enable bit) DD22EN (DD22 input enable bit) DD23EN (DD23 input enable bit) Function 0: Disable input 1: Enable input R R W W 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-23 14 DD Input Enable Register 3 (DRIDDEN3) b8 0 DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 8 9 10 11 12 13 14 15 Bit Name DD24EN (DD24 input enable bit) DD25EN (DD25 input enable bit) DD26EN (DD26 input enable bit) DD27EN (DD27 input enable bit) DD28EN (DD28 input enable bit) DD29EN (DD29 input enable bit) DD30EN (DD30 input enable bit) DD31EN (DD31 input enable bit) Function 0: Disable input 1: Enable input R R W W The DD Input Enable Register ‘n’ (n = 0–3) controls data input to the DRI by disabling or enabling the data input. If the DDn input enable bit is set to "0," input to the DRI is always fixed to "0" irrespective of the corresponding pin input level. If the DDn input enable bit is set to "1," data input to the DRI is taken in according to the corresponding pin input level. Figure 14.2.7 schematically shows a DD input block diagram. DD0-3 input pin select bit DDSL bit DDj_A0 s DDj_A1 s DDj_B DD0-3 (To the data capture unit) DDjEN(DDj input enable)bit DDSL bit DDm DDk_A s DDk_B DD4-15 (To the data capture unit) DDkEN(DDk input enable)bit DDn DD16-31 (To the data capture unit) DDnEN(DDn input enable)bit Notes: • j=0 3, k=4 15, n=16 31 • s :Selecter Figure 14.2.7 Block Diagram of DD Input 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-24 14 DRI Data Capture Event Count Setting Register (DRIDCAPNUM) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers 14.2.9 DRI Data Capture Event Count Setting Register b 0–13 14–31 Bit Name No function assigned. Fix to "0." DCAPNUM Function R 0 R W 0 W Transfer Event Count Note: • This register must always be accessed in halfword or word units beginning with even addresses. This register is used to set the number of events, at occurrence of which data is taken in. The value set in this register is used as the reload value for the DRI capture event counter(DRIDCAPCT) and the DRI transfer counter(DRITRMCT). Since the DRI performs data transfers in 32-bit units, make sure the value set in this register satisfies the requirement given below depending on how DWDSL(input data bus width select) bits in the DRI Data Capture Control Register(DRIDCAPCNT) are set: • When selected to be 8 bits, a multiple of 4 (equal to or greater than 4) • When selected to be 16 bits, a multiple of 2 (equal to or greater than 2) • When selected to be 32 bits, any value (equal to or greater than 1) Also be careful that the total amount of captured data will not exceed the RAM area supported by the DRI. Note: • This register can only be rewritten when DCPEN(capture enable) bit in the DRI Data Capture Control Register(DRIDCAPCNT) is "0." 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-25 14 14.2.10 DRI Capture Event Counter DRI Capture Event Counter (DRIDCAPCT) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0–13 14–31 Bit Name No function assigned. Fix to "0." DCAPCT Capture event counter Note: • This register must always be accessed in word (32 bit) units from the halfword boundary(The lower address B’00). Function R 0 R W 0 – The DRI Capture Event Counter is an 18-bit counter to count data capture events. When DCPEN(capture enable) bit in the DRI Data Capture Control Register(DRIDCAPCNT) changes state from data capture disabled to enabled, this counter is reloaded with the value of the DRI Data Capture Event Count Setting Register(DRIDCAPNUM). Thereafter, the counter is decremented by one each time data is taken in. Then, when the DRI capture event counter is decremented to H’0000 0000, it stops counting. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-26 14 14.2.11 DRI Transfer Counter DRI Transfer Counter (DRITRMCT) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b 0–13 14–31 Bit Name No function assigned. Fix to "0." DRICT Function R 0 R W 0 – DRI transfer counter Note: • This register must always be accessed wordwise (32 bits) beginning with the address of the DRI Transfer Counter (Upper). The DRI Transfer Counter is an 18-bit counter to count DRI transfers. When DCPEN (capture enable) bit in DRI Data Capture Control Register(DRIDCAPCNT) changes state from data capture disabled to enabled, this counter is reloaded with one of the values shown below, depending on how the DRI Data Capture Event Count Setting Register(DRIDCAPNUM) and DWDSL(input data bus width select) bits in DRIDCAPCNT register are set. • When selected to be 8 bits, the value set in the DRI Data Capture Event Count Setting Register (DRIDCAPNUM) divided by 4 • When selected to be 16 bits, the value set in the DRI Data Capture Event Count Setting Register (DRIDCAPNUM) divided by 2 • When selected to be 32 bits, the value set in the DRI Data Capture Event Count Setting Register (DRIDCAPNUM) If the bus width for the input data from external devices is chosen to be 8 bits, a DRI transfer is executed every four data capture events detected. Similarly, a DRI transfer is executed every two data capture events detected if the selected bus width is 16 bits or every data capture event detected if the selected bus width is 32 bits. The counter is decremented by one each time a DRI transfer finishes. Then, when the counter underflows(H’0000 0000), it stops counting. And Underflow of DRI transfer counter indicates H'0000 0000(counter stop). 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 14-27 14 14.2.12 DRI Address Counters DRI Address Counter 0 (DRIADR0CT) DRI Address Counter 1 (DRIADR1CT) DIRECT RAM INTERFACE (DRI) 14.2 DRI Related Registers b0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 DRIADn 0 b16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 DRIADn 24 0 25 0 26 0 27 0 28 0 29 0 30 0 b31 0 0 b0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DRIADnRLD b16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 0 30 0 b31 0 DRIADnRLD 7 8 DIN4ED 1 DIN0ED 2 DIN1ED 3 0 4 DIN2ED 5 0 6 0 9 0 10 0 11 DIN5ED 12 0 13 0 14 0 b15 0 DIN3ED 0 0 0 0 0 0 5 0 1 2 DEC0EXT 0 3 0 4 0 6 0 b7 DEC0MOD 0 DEC0CS 5 0 1 2 DEC1EXT 0 3 0 4 0 6 0 b7 DEC1MOD 0 DEC1CS 5 0 1 2 DEC2EXT 0 3 0 4 0 6 0 b7 DEC2MOD 0 DEC2CS 5 0 1 2 DEC3EXT 0 3 0 4 0 6 0 b7 DEC3MOD 0 DEC3CS 5 0 1 2 DEC4EXT 0 3 0 4 0 6 0 b7 DEC4MOD 0 DEC4CS 4 0 1 0 2 0 3 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DECnCT 5 0 1 0 2 0 3 0 4 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DECnRL b 8–14 15 Bit Name No function assigned. Fix to "0." RTDWRDIS RTD RAM write function disable bit 0: Enable RTD RAM write function 1: Disable RTD RAM write function Function R 0 R W 0 W This register selects whether to enable or disable the RTD function for writing to RAM. Setting the RTDWRDIS bit to "1" disables the RTD function for writing to RAM, so that even when the RTD receives a command for write to RAM, the command is ignored and no data is written to RAM. Note: • Settings of this register cannot be altered while the RTD is in use. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-3 15 15.4 Functional Description of RTD 15.4.1 Outline of RTD Operation REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD Operation of the RTD is specified by a command entered from devices external to the chip. A command is indicated by bits 16–19 (Note 1) of the RTD received data. Table 15.4.1 RTD Commands RTD Received Data b19 0 0 0 0 0 0 1 0 b18 0 1 1 1 0 0 1 0 b17 0 0 0 1 1 1 1 0 b16 0 0 1 0 0 1 1 1 Command Mnemonic VER (VERify) RTD Function Continuous monitor VEI (VErify Interrupt request) RDR (ReaD RAM) WRR (WRite RAM) RCV (ReCoVer) System reserved (use inhibited) RTD interrupt request Real-time RAM content output RAM content forcible rewrite (with verify) Recover from runaway condition (Note 2), (Note 3) ↑ (Note 1) Note 1: The RTD received data bit 19 actually is not stored in the command register, and except for the RCV command, handled as a “Don’t care” bit. (Bits 16–18 are effective for the command specified.) Note 2: The RCV command must always be transmitted twice in succession. Note 3: For the RCV command, all bits, not just 16–19, (i.e., bits 0–15 and bits 20–31) must be set to "1." 15.4.2 Operation of RDR (Real-time RAM Content Output) When the RDR (real-time RAM content output) command is issued, the RTD is enabled to transfer the contents of the internal RAM to external devices without causing the CPU’s internal bus to stop. Because the RTD reads data from the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra CPU load is incurred. Only the 32-bit word-aligned addresses(The lower address B’00) can be specified for read from the internal RAM. (The two low-order address bits specified by a command are ignored.) Data are read out and transferred from the internal RAM in 32-bit units. (LSB side) 31 RTDRXD X 20 19 18 17 16 15 14 13 12 X 0 0 1 0 A15 A14 A29 A28 (MSB side) 1 0 A17 A16 Command (RDR) Specified address Note: • X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to "1.") Figure 15.4.1 RDR Command Data Format 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-4 15 32 clock periods RTDCLK 32 clock periods REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD 32 clock periods 32 clock periods RTDRXD RDR (A1) RDR (A2) RDR (A3) RTDTXD D (A1) D (A2) RTDACK 2 clock periods Notes: • (An) = Specified address • D(An) = Data at specified address (An) Figure 15.4.2 Operation of the RDR Command (LSB side) 31 30 b31 b30 (MSB side) 10 b1 b0 RTDTXD Read data Note: • The read data is transferred LSB-first. Figure 15.4.3 Read Data Transfer Format 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-5 15 REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD 15.4.3 Operation of WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU’s internal bus to stop. Because the RTD writes data to the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra CPU load is incurred. Only the 32-bit word-aligned addresses(The lower address B’00) can be specified for read from the internal RAM. (The two low-order address bits specified by a command are ignored.) Data are written to the internal RAM in 32-bit units. The external host should transmit the command and address in the first frame and then the write data in the second frame. The RTD writes to the internal RAM in the third frame after receiving the write data. a) First frame (LSB side) 31 RTDRXD X 20 X 19 18 17 16 0 0 1 1 15 14 13 12 A15 A14 A29 A28 (MSB side) 1 0 A17 A16 Command (WRR) b) Second frame (LSB side) 31 30 RTDRXD b31 b30 Specified address (MSB side) 1 b1 0 b0 Write data Notes: • X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to "1.") • The specified address and write data are transferred LSB-first. Figure 15.4.4 WRR Command Data Format The RTD reads out data from the specified address before writing to the internal RAM and again reads out data from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD WRR(A1) (A1) Write data WRR(A2) (A2) Write data RTDTXD RTDACK D (A1) Read value before writing D (A1) Verify value after writing 3 clock periods Notes: • (An) = Specified address • D(An) = Data at specified address (An) Figure 15.4.5 Operation of the WRR Command 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-6 15 15.4.4 Operation of VER (Continuous Monitor) REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD When the VER (continuous monitor) command is issued, the RTD outputs the data from the address that has been accessed by an instruction (either read or write) immediately before receiving the VER command. (LSB side) 31 RTDRXD X 20 19 18 17 16 15 14 X 0 0 0 0 X X (MSB side) 0 X Command (VER) Note: • X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to "1.") Figure 15.4.6 VER (Continuous Monitor) Command Data Format 32 clock periods RTDCLK 32 clock periods 32 clock periods 32 clock periods RTDRXD RDR(A1) (Note 1) VER VER RTDTXD RTDACK D (A1) Read value D (A1) Latest read value 2 clock periods Note 1: WRR command can also be used. Notes: • (An) = Specified address • D(An) = Data at specified address (An) Figure 15.4.7 Operation of the VER (Continuous Monitor) Command 15.4.5 Operation of VEI (Interrupt Request) When the VEI (interrupt request) command is issued, the RTD generates an interrupt request. Furthermore, the RTD outputs the data from the address that has been accessed by an instruction (either read or write) immediately before receiving the VEI command. (LSB side) 31 RTDRXD X 20 19 18 17 16 15 14 X 0 1 1 0 X X (MSB side) 0 X VEI (interrupt request generation) command Note: • X = Don't care. (However, if issued immediately after the RVC command, bits 20-31 must all be set to "1.") Figure 15.4.8 VEI (Interrupt Request) Command Data Format 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-7 15 32 clock periods RTDCLK 32 clock periods REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD 32 clock periods 32 clock periods RTDRXD RDR(A1) (Note 1) VEI RTDTXD RTDACK D (A1) Read value 2 clock periods RTD interrupt request D (A1) Read value RTD interrupt Note 1: WRR command can also be used. Notes: • (An) = Specified address • D(An) = Data at specified address (An) Figure 15.4.9 Operation of the VEI (Interrupt Request) Command 15.4.6 Operation of RCV (Recover from Runaway) If the RTD runs out of control, the RCV (recover from runaway) command may be issued to recover from the runaway condition without the need to reset the system. The RCV command must always be issued twice in succession. Also, any command issued immediately following the RCV command must have all of its bits 20–31 set to "1." (LSB side) 31 RTDRXD 1 20 19 18 17 16 15 1 1 1 1 1 1 (MSB side) 0 1 Command (RCV) Notes: • All of 32 data bits are "1." • The RCV command must always be issued twice in succession. Figure 15.4.10 RCV Command Data Format 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-8 15 32 clock periods RTDCLK Bits 20-31 REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD 32 clock periods 32 clock periods 32 clock periods RTDRXD RCV RCV 1 • • • 1 RDR(A1) Next command following RCV command RTDTXD Indeterminate data during runaway condition D(A1) RTDACK Indeterminate value during runaway condition 2 clock periods RCV command stored 2 clock periods Note: • The next command following the RCV command must have all of its bits 20-31 set to "1." Figure 15.4.11 Operation of the RCV Command 15.4.7 Method for Setting Specified Address when Using RTD In the Real-Time Debugger (RTD), the low-order 18-bit addresses of the internal RAM(H'0 0000 to H'3 FFFF) can be specified. However, it is inhibited to access any location other than the area in which the RAM is located (for 32185: H'0080 4000 to H'0080 BFFF, for 32186: H'0080 4000 to H'0081 3FFF). Note also that two least significant address bits, A31 and A30, are always "0" because data are read and written to and from the internal RAM in a fixed length of 32 bits. Memory map (Note 1) X ... X A15 A14 A29 - A16 H'0080 0000 SFR 16KB H'0080 4000 RAM area can only be specified RAM area (Note 2) Note 1: Because the address bits A29-A16 and the address bits A15 and A14 are not contiguously located, care must be taken when setting the RAM addresses. Note 2: For 32185: H'0080 4000 to H'0080 BFFF, for 32186: H'0080 4000 to H'0081 3FFF Figure 15.4.12 Setting Addresses in the Real-Time Debugger 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-9 15 15.4.8 Resetting RTD REAL TIME DEBUGGER (RTD) 15.4 Functional Description of RTD The RTD is reset by applying a system reset (i.e., RESET# signal input). The status of the RTD related output pins upon exiting system reset are shown below. Table 15.4.2 RTD Pin Status Upon Exiting System Reset Pin Name RTDACK RTDTXD Status “H” level output “H” level output The first command transfer to the RTD after being reset is initiated by transferring data to the RTDRXD pin synchronously with the falling edge of RTDCLK. 32 clock periods RTDCLK System reset 32 clock periods 32 clock periods 32 clock periods RESET# RTDRXD Don't Care RDR(A1) RDR(A2) RTDTXD "H" FFFF FFFF FFFF FFFF D(A1) D(A2) RTDACK "H" Notes: • (An) = Specified address • D(An) = Data at specified address (An) Figure 15.4.13 Command Transfer to the RTD after System Reset 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-10 15 15.5 Typical Connection with Host REAL TIME DEBUGGER (RTD) 15.5 Typical Connection with Host The host uses a serial synchronous interface to transfer data. The clock for synchronous communication should be generated by the host. An example for connecting the RTD and host is shown below. M32R/ECU Host microprocessor RTDCLK RTDRXD RTDTXD RTDACK (Note 1) SCLK RXD TXD PORT Note 1: This applies to the case where the RTDACK level is checked between transfer frames. Figure 15.5.1 Connecting the RTD and Host The RTD communication is performed in a fixed length of 32 bits per frame. Because serial interfaces generally handle data in 8-bit units, data is transferred separately in four operations, 8 bits at a time. The RTDACK signal is used to verify that communication is performed normally. The RTDACK signal goes 0 “L” after a command is sent, providing a means of verifying the communication status. When issuing the VER command, the RTDACK signal is pulled “L” for only one clock period. Therefore, after sending 32 bits in one frame via a serial interface, turn off RTDCLK output and check that RTDACK is “L.” That way, it is possible to know whether the RTD is communicating normally. If it is desirable to identify the type of transmitted command by the width of RTDACK, use the microcomputer’s internal measurement timer (to count RTDCLK pulses while RTDACK is “L”), or design a dedicated circuit. Transfer of the next frame Transfer of one frame (32 bits) 1 2 RTDCLK RTDRXD (8 bits) (8 bits) (8 bits) RTDTXD RTDACK Check that the RTDACK signal is "L." Figure 15.5.2 Example of Communication with the Host (when Using VER Command) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-11 15 REAL TIME DEBUGGER (RTD) 15.5 Typical Connection with Host This page is blank for reasons of layout. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 15-12 CHAPTER 16 NON-BREAK DEBUG (NBD) 16.1 16.2 16.3 16.4 16.5 16.6 Outline of Non-Break Debug (NBD) Pin Functions of NBD NBD Related Registers Communication Protocol RAM Monitor Function Event Detection Function 16 16.1 Outline of Non-Break Debug (NBD) NON-BREAK DEBUG (NBD) 16.1 Outline of Non-Break Debug (NBD) Non-Break Debug (NBD) has the RAM monitor and event output functions. A dedicated DMA is incorporated in NBD, so that accesses to the internal RAM, etc. are accomplished using this DMA. (1) RAM monitor function This function is provided for reading and writing to and from all resources connected to the internal/ external buses mapped in the address space. It allows the RAM data, etc. to be referenced and altered. Furthermore, accesses to the address space used exclusively for NBD (i.e., NBD space) are accomplished using this function. (2) Event output function Upon detecting access to a preset address, this function outputs "L" level signal from the NBDEVNT# pin. A specific address and read/write access can be specified as the event occurrence condition. Table 16.1.1 Outline of the Non-Break Debug (NBD) Item Transfer method Transfer clock generation Access area Access size Maximum transfer rate Input/output pins Functions Number of events set Content Clock-synchronous parallel interface (4 bits) Generated by external host All areas in the address map and NBD space 8, 16 or 32 bits (for NBD space, fixed to 8 bits) 12.5MHz 7 pins (NBDD3–NBDD0, NBDCLK, NBDSYNC#, NBDEVNT#) • RAM monitor function (Note 1) • Event output function 1 event Note 1: Accessible to all resources connected to the internal/external buses as well as RAM. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-2 16 NBD M32R-FPU core DMA for NBD NON-BREAK DEBUG (NBD) 16.1 Outline of Non-Break Debug (NBD) NBDD0(P74/RTDTXD/TXD3) NBDD1(P75/RTDRXD/RXD3) NBDD2(P76/RTDACK/CTX1) Event detection block Internal Flash Memory Internal 32-bit bus NBDD3(P77/RXDCLK/CRX1) NBDCLK(JTCLK) NBDSYNC#(JTDI) NBD register NBDEVNT#(JTDO) Internal RAM Internal bus interface Internal 16-bit bus SFR area External bus Figure 16.1.1 Block Diagram of the Non-Break Debug (NBD) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-3 16 16.2 Pin Functions of NBD The following describes pin functions of NBD. Table 16.2.1 NBD Pin Functions Pin name NBDD3–NBDD0 NBDCLK NBDSYNC# NBDEVNT# Type Input/output Input Input Output Function NON-BREAK DEBUG (NBD) 16.2 Pin Functions of NBD Command and address/data input/output Synchronous clock input Top of data position recognition signal input Event otuput (asserted "L" for 2BCLKs when an event occurs) Note: • The NBD pins are shared with RTD, JTAG and other function. Before NBD can be used, the functions of the NBD pins must be set using the NBD Pin Control Register (NBDCNT). 16.2.1 NBD Pin Control Register NBD Pin Control Register (NBDCNT) b0 0 b 0–5 6 7 Bit Name No function assigned. Fix to "0." NBDSETP NBDSET NBD-related pins select bit JTRST (JTAG reset) pin should be pulled "L." NBDSET write control bit 0: Set NBD-related pins for other than the NBD function 1: Set NBD-related pins for the NBD function Function R 0 0 R W 0 W W Note: • The NBD function cannot be used while the system is reset (because NBDSET = 0). For the NBD function to be used, the The NBDSET bit selects the functions of the NBD-related pins. To use the NBD function, set this bit to "1," so that the NBD-related pins will be set for the NBD pin functions shown in Table 16.2.1. To set the register, follow the procedure described below. 1. Write a "1" to NBDSETP bit. 2. Subsequent to 1 above, write a "0" to NBDSETP bit and a "0" or "1" to NBDSET bit. Notes: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. • In NBDCNT register, indefined value is outputted until EVTU_A register and EVTU_C register are set after exiting reset, when set NBD related pin to NBD function. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-4 16 • Example of correct settings NON-BREAK DEBUG (NBD) 16.2 Pin Functions of NBD NBDSETP "1" If a write cycle to any other area occurs during this interval, the value that was set in the NBDSET bit is not reflected. (Note 1) NBDSETP NBDSET "0" Set value • Cases where settings have no effect (1) NBDSETP "1" Write to other area Because a write cycle to other area exists, the set value is not reflected. (Note 1) NBDSETP NBDSET "0" Set value (2) NBDSETP "1" Because these two consecutive writes comprise a pair, the next set value is not reflected. NBDSETP "1" NBDSETP NBDSET "0" Set value Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, SDI (tool), NBD to any other area. The writing cycle from RTD and DRI do not effect. Figure 16.2.1 NBDSET Bit Setting Procedure 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-5 16 16.3 NBD Related Registers NON-BREAK DEBUG (NBD) 16.3 NBD Related Registers The following shows an NBD related register map. Some NBD-related registers are located in the address map (CPU space), and others are located in another area that is used exclusively for NBD (i.e., NBD space). The NBD space is addressed by 12 bits, and is accessed in a fixed size of 8 bits. Furthermore, the NBD space is constructed to be accessible from only the dedicated NBD interface, and cannot be accessed from the CPU. Table 16.3.1 NBD Related Register Map Space CPU Address H'E000 0000 H'E000 0004 H'E000 0008 NBD H'800 H'801 H'802 H'803 H'820 Event condition setting register (EVTU_C) R/W Indefined Register Name NBD enable register (NBDENB) NBD pin control register (NBDCNT) Event generation register (NEVNTGEN) Event address setting register (EVTU_A) R/W R/W R/W W R/W Upon exiting reset H'00 H'00 Indefined Indefined 16.3.1 NBD Enable Register NBD Enable Register (NBDENB) b0 0 b 0–5 6 7 Bit Name No function assigned. Fix to "0." NBDENP NBDEN write control bit NBDEN 0: Disable NBD operation R W NBD operation enable bit 1: Enable NBD operation Notes: • Allow for an interval time of 20 CPUCLK cycles or more before altering the value of the NBDEN bit. • If the NBDEN bit is reenabled after being disabled, a finite time of 20 CPUCLK cycles is required before the NBD becomes operational. • The value of the NBDEN bit can only be altered when the NBDSET bit in the NBD Pin Control Register = "0" (NBD-related pins set for other than the NBD function). Function R 0 0 W 0 W The NBDEN bit selects to enable or disable the NBD functions. When NBDEN = "0," the NBD is in a reset state, so that the content of each register is reset to the initial value. To use the NBD functions, this bit should be set to "1" before setting other NBD registers. When the NBDEN bit = "0," accessing not just the NBDENB register, but any other NBD registers (in either the CPU or the NBD space) is prohibited. To set the register, follow the procedure described below. 1. Write a "1" to NBDENP bit. 2. Subsequent to 1 above, write a "0" to NBDENP bit and a "0" or "1" to NBDEN bit. Notes: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. • The setting procedure of NBDEN bit is same as that of NBDSET bit shown in Figure 16.2.1. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-6 16 16.4 Communication Protocol NON-BREAK DEBUG (NBD) 16.4 Communication Protocol When NBDSYNC# is asserted, the NBD starts latching NBDD3–NBDD0 into the internal circuit synchronously with NBDCLK. Make sure NBDD3–NBDD0 are input in the format shown below. When data input from NBDD3–NBDD0 shown in Figure 16.4.1 finishes, the data bus is temporarily placed in the high-impedance (Hi-Z) state for 1 NBDCLK cycle and then data is output from NBDD3–NBDD0 synchronously with NBDCLK in the format shown in Figure 16.4.2. NBDCLK NBDSYNC# NBDD3–NBDD0 NBDD3–NBDD0 Hi-Z 0000 SIZ1, SIZ0, A28–A31 R/W, I/T Control field A0–A3 Dn-3–Dn D0–D3 Hi-Z Extension field Address field Write field (Only when writing) n = 7,15 or 31 Command packet Note: • :Sampling Point Figure 16.4.1 NBDD3–NBDD0 Input Format NBDCLK NBDSYNC# NBDD3–NBDD0 Hi-Z 0000 Not Ready 0001 Ready 0001 Ready 0001 Ready Dn-3–Dn D0–D3 Hi-Z Flag sense Read data packet (Only when reading) n = 7,15 or 31 Note: • :Sampling Point Figure 16.4.2 NBDD3–NBDD0 Output Format 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-7 16 16.5 RAM Monitor Function 16.5.1 Description of NBD Operation NON-BREAK DEBUG (NBD) 16.5 RAM Monitor Function Figure 16.5.1 shows an example of read operation of the NBD. Figure 16.5.2 shows an example of write operation of the NBD. When input to the NBDSYNC# pin is pulled "L," the NBD starts taking in a command packet from NBDD3–NBDD0 in the format shown in Figure 16.4.1. When the command packet input finishes, the NBD starts reading/writing to or from the address specified in the address field. When the NBD finishes receiving a command packet, it starts outputting data from NBDD3–NBDD0 in the format shown in Figure 16.4.2 after the data bus is temporarily placed in the high-impedance (Hi-Z) state for 1 NBDCLK cycle. While input to the NBDSYNC# pin is held "L," NBDD3–NBDD0 are in a flag sense state, in which they output Not Ready (0000) during a read/write operation or Ready (0001) when the operation has finished. During a read, when input to the NBDSYNC# pin is released back high after detecting Ready, the read data (read data packet) is output (Figure 16.5.1).Also, during writing when input "H" level to NBDSYNC# pin after Ready detection, it is changed to high impedance status by next NBDCLK rising after "H" level detection by rising NBDCLK. (Figure 16.5.2) Before a next command packet can be transmitted, input to the NBDSYNC# pin must be held "H" for at least 2 NBDCLK cycles. NBDCLK NBDSYNC# (Note 1) NBDD3–NBDD0 Hi-Z 0000 SIZ1, SIZ0, R/W, I/T (Note 2) Hi-Z 0001 Ready Ready 0001 Ready 0001 Ready D4–D7 D0–D3 A28–A31 A0–A3 Hi-Z Not Ready 0000 Not Ready Input Output Note 1: When input adress from NBDD0 – NBDD3 is completed, plug sence packet is outputted though high impedance period of 1NBDCLK. Note 2: After "H" level detection by rising NBDCLK, read out data (read data packet)is outputted from next NBDCLK rising. Note: • : Sampling point Figure 16.5.1 Example of Read Operation (for 8-Bit Read from the CPU Space) NBDCLK NBDSYNC# Hi-Z 0000 Hi-Z A28–A31 A0–A3 D28–D31 D0–D3 (Note 1) 0000 Not Ready 0001 Ready 0001 Ready 0001 Ready (Note 2) Hi-Z NBDD3–NBDD0 SIZ1, SIZ0, R/W, I/T Input Output Note 1: When input adress from NBDD0 – NBDD3 is completed, plug sence packet is outputted though high impedance period of 1NBDCLK. Note 2: After "H" level detection by rising NBDCLK, read out data (read data packet)is outputted from next NBDCLK rising. Note: • :Sampling point Figure 16.5.2 Example of Write Operation (for 32-Bit Write to the CPU Space) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-8 16 16.5.2 NBDD Data Format (1) Command packet (input) Table 16.5.1 Bit Assignments of a Command Packet Bit arrangement Input order Field name NBDD3 NBDD2 NBDD1 NBDD0 Extension field Control field aux3 SIZ1 A28 A24 A20 A16 A12 A8 A4 A0 D28 D24 D20 D16 D12 D8 D4 D0 aux2 SIZ0 A29 A25 A21 A17 A13 A9 A5 A1 D29 D25 D21 D17 D13 D9 D5 D1 aux1 R/W A30 A26 A22 A18 A14 A10 A6 A2 D30 D26 D22 D18 D14 D10 D6 D2 aux0 I/T A31 A27 A23 A19 A15 A11 A7 A3 D31 D27 D23 D19 D15 D11 D7 D3 NON-BREAK DEBUG (NBD) 16.5 RAM Monitor Function The following describes the content of each packet/field which are input to or output from the NBDD3–NBDD0 pins. √ : Necessary, -: Unnecessary When accesing NBD space During read √ √ When accesing CPU space During During During 8-bit write 16-bit write 32-bit write √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ During write During read √ √ √ √ √ √ √ √ √ √ √ √ First Address field √ √ √ √ √ √ Write data field Last - √ √ - √ √ √ √ √ √ 1) Extension field Bit Name aux3 aux2 aux1 aux0 Function Reserved for future extension Reserved for future extension Reserved for future extension Reserved for future extension Content Set to "0" Set to "0" Set to "0" Set to "0" Note 1: If these bits are set otherwise, device operation cannot be guaranteed. 2) Control field Bit Name SIZ1, SIZ0 Function Specify access size Content SIZ1 SIZ0 0 0 0 1 1 0 1 1 0: Read 1: Write 0: Access NBD space 1: Access CPU space 8-bit (Note 1) 16-bit 32-bit Settings inhibited R/W I/T Specify read/write Specify access space Note 1: When the NBD space access is selected (I/T = "0"), only 8-bit access is accepted. If these bits are set otherwise, device operation cannot be guaranteed. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-9 16 3) Address field Bit Name A0–A31 Function Specify address Content NON-BREAK DEBUG (NBD) 16.5 RAM Monitor Function A0–A31 should be specified in big endian format (A0 = MSB). When accessing NBD space: specify with 12 bits of A0–A11 When accessing CPU space: specify with 32 bits of A0–A31 4) Write data field Bit Name D0–D31 Function Specify write data Content D0–D31 should be specified in big endian format (D0 = MSB). The necessary number of bits varies depending on how the R/W bit and SIZ1–SIZ0 bits in the control field are set. (See Table 16.5.1 Bit Assignments of a Command Packet) (2) Flag sense packet (output) Table 16.5.2 Bit Assignments of a Flag Sense Packet NBDD3 0 Bit arrangement NBDD2 NBDD1 0 0 NBDD0 RFLG Bit Name RFLG Function Indicates that the internal operation of NBD is completed Content 0: Not Ready 1: Ready (3) Read data packet (output) Table 16.5.3 Bit Assignments of a Read Data Packet Output order First NBDD3 D28 D24 D20 D16 D12 D8 D4 D0 Bit arrangement NBDD2 D29 D25 D21 D17 D13 D9 D5 D1 NBDD1 D30 D26 D22 D18 D14 D10 D6 D2 NBDD0 D31 D27 D23 D19 D15 D11 D7 D3 During read (Note 1) √ : Necessary, -: Unnecessary When accesing NBD space During write When accesing CPU space During During During During 8-bit write 16-bit write 32-bit write write √ √ Last - √ √ √ √ √ √ √ √ √ √ √ √ √ √ - Note 1: When the NBD space access is selected, only 8-bit access is accepted. Bit Name D0–D31 Function Output read data Content D0–D31 should be specified in big endian format (D0 = MSB). The number of bits to be output varies depending on how the R/W bit and SIZ1–SIZ0 bits in the control field are set. (See Table 16.5.3 Bit Assignments of a Read Data Packet) 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-10 16 16.6 Event Detection Function NON-BREAK DEBUG (NBD) 16.6 Event Detection Function The NBD has the function to output an event occurrence when there is a matching address accessed for read/write in the CPU space. The event output is active "L," and is asserted synchronously with BCLK for a period of 2 BCLK cycles. The NBDEVNT# pin also can output "L" level signal for 2 BCLK cycles when the NEVNTGEN register located in the CPU space is accessed for write. Output from the NBDEVNT# pin is generated by matching the abovementioned address or a write access to the NEVNTGEN register Figure 16.6.1 shows the structure of the NBDEVNT# pin. Address bus, R/W signal information EVTU_A, EVTU_C information Comparate circuit Output "L" when a match is detected NBDEVNT# pin Output "L" for 2BCLK NEVNTGEN Register Also output "L" by writing any data Figure 16.6.1 NBDEVNT# Pin Configuration 16.6.1 Event Address Setting Register Event Address Setting Register (EVTU_A) b0 ? 6 ? 1 ? 2 ? 3 ? 4 ? 5 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? EVTU_A b16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 0 b31 0 EVTU_A b 0–29 30, 31 Bit Name EVTU_A No function assigned. Fix to "0." NBD operation) to "1"(enable NBD operation). • After enabling NBD operation(after setting "1"in NBDEN bit of NBDENB register), an indefinite value is outputted from NBDEVENT# pin in NBD pin control register(NBDCNT) during the period of time from setting NBD-related pins to NBD function to setting value of EVTU_A and EVTU_C are effective(period of time from Ready status to after 3NBDCLK). • During event detection function is used, when the setting value of EVTU_A register or EVTU_C register is changed, the event detection result by the changed setting conditions becomes effective after 3NBDCLK from setting EVTU_A register or EVTU_C register (at the time of being Ready state in flag sense period). Function Specify the target address A0–A29 for event detection R R 0 W W 0 Notes: • In the NBDEN bit of NBD enable register (NBDENB), AVTU_A bit value becomes indefinite after setting from "0" (disable 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 16-11 16 16.6.2 Event Condition Setting Register Event Condition Setting Register (EVTU_C) b0 0 NON-BREAK DEBUG (NBD) 16.6 Event Detection Function 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 CLKOSELP CLKOSEL 6 0 1 0 2 0 3 0 4 0 5 0 b7 FEWWAIT 0 6 0 1 0 2 0 3 0 4 0 5 0 b7 0 CLKOSELP CLKOSEL C2 {10 × 2× × i -1} i=0 2 Eq. A-3 Eq. A-4 Thus, for a 10-bit resolution A/D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for reference when setting up C1. (b) Maximum value of the output impedance R1 when C1 is not added If the external capacitor C1 in Appendix Figure 4.10.1 is not used, examination must be made to see if the analog output device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Appendix Figure 4.10.1 does not exist is shown below. i2 = C2(E - V2) Cin × R1+C2(R1+R2) × exp { -t } --------------------- Eq. B-1 Cin × R1+C2(R1+R2) When sample-and-hold is disabled Conversion time for the first bit Second bit ADiINn Sampling time Comparison Sampling time time Repeated (10 times) for 10 bits * When sample-and-hold is enabled, the analog input is sampled for only the first bit. Appendix Figure 4.10.2 A/D Conversion Timing Diagram Appendix Figure 4.10.2 shows an A/D conversion timing diagram. C2 must be charged up within the sampling time shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and subsequent bits is about half that of the first bit. The sampling times at the respective conversion speeds are listed in the Appendix Table 4.10.1. Note that when the sample-and-hold function is enabled, the analog input is sampled for only the first bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-23 Appendix 4 Conversion start method Conversion speed SUMMARY OF PRECAUTIONS Appendix 4.10 Notes on A/D Converter Appendix Table 4.10.1 Sampling Time (in Which C2 Needs to Be Charged) Sampling time for the first bit Sampling time for the 2nd and subsequent bits 2BCLK mode Single mode (when sample-and-hold disabled or normal sample-and-hod enabled Single mode (when fast sampleand-hold enabled) Comparator mode Slow mode Fast mode Slow mode Fast mode Slow mode Fast mode Normal speed Double speed Normal speed Double speed Normal speed Double speed Normal speed Double speed Normal speed Double speed Normal speed Double speed Normal speed Double speed Normal speed Double speed 55BCLK 31BCLK 23BCLK 15BCLK 55BCLK 31BCLK 23BCLK 15BCLK 55BCLK 31BCLK 23BCLK 15BCLK 55BCLK 31BCLK 23BCLK 15BCLK 27BCLK 15BCLK 11BCLK 7BCLK – – – – – – – – – – – – Simultaneous sampling Slow mode Fast mode Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows: Sampling time (in which C2 needs to be charged) > Cin × R1 + C2(R1 + R2) ----Eq. B-2 Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2 charging time) must be applied. C2 charging time - C2 × R 2 Cin + C2 R1 < 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-24 Appendix 4 Appendix 4.11 Notes on Serial Interface Appendix 4.11.1 Notes on Using CSIO Mode SUMMARY OF PRECAUTIONS Appendix 4.11 Notes on Serial Interface • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register, SIO Special Mode Register and SIOn Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set when the serial interface is not operating. If a transmit or receive operation is in progress, wait until the transmit and receive operations are finished and then clear the transmit and receive enable bits before making changes. • Settings of SIOn Baud Rate Register Use caution when setting SIOn Baud Rate Register so that the transfer rate will not exceed f(BCLK)/8. • About successive transmission To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register before the current data transmission finishes. • About reception Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit operation must always be executed (by sending dummy data) even when the serial interface is used for only receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation mode register to "1"), dummy data may actually be output from the pin. • About successive reception To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts. • Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts. • About reception finished bit If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive enable bit, and cannot be cleared by reading out the receive buffer register. • About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Although a receive operation continues thereafter, the subsequent received data is not stored in the receive buffer register (receive status bit = "1"). Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0." And this is the only way that the overrun error flag can be cleared. • About DMA transfer request generation during SIO transmission If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated. • About DMA transfer request generation during SIO reception If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer request is not generated. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-25 Appendix 4 • Switching from general-purpose to serial interface pin SUMMARY OF PRECAUTIONS Appendix 4.11 Notes on Serial Interface When switching general-purpose to serial interface pin, SCLKOn pin outputs "H" level (For the case of selecting internal clock and setting CKPOL bit to "0." When setting CKPOL bit to "1," it outputs "L" level.), and TXDn pin outputs undefined value. However, when switching general-purpose to serial interface pin with setting TEN bit of the SIOn transmit control register to "1" (transmit enable), TXDn pin outputs the last bit level of the previously output serial data. Appendix 4.11.2 Notes on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register, SIO Special Mode Register and SIOn Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set when the serial interface is not operating. If a transmit or receive operation is in progress, wait until the transmit and receive operations are finished and then clear the transmit and receive enable bits before making changes. • Settings of SIOn Baud Rate Register Writes to the SIOn Baud Rate Register take effect in the next cycle after the BRG counter has finished counting. However, if the register is accessed for write while transmission and reception are disabled, the written value takes effect at the same time it is written. • Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts. • About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Once an overrun error occurs, although a receive operation continues, the subsequent received data is not stored in the receive buffer register. Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared. And this is the only way that the overrun error flag can be cleared. • Flags showing the status of UART receive operation There are following flags that indicate the status of receive operation during UART mode: • SIO Receive Control Register receive status bit • SIO Receive Control Register reception finished bit • SIO Receive Control Register receive error sum bit • SIO Receive Control Register overrun error bit • SIO Receive Control Register parity error bit • SIO Receive Control Register framing error bit The manner in which the reception finished bit and various error flags are cleared differs depending on whether an overrun error occurred, as described below. [When an overrun error did not occur] Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit. [When an overrun error occurred] Cleared by only clearing the receive enable bit. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-26 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.11 Notes on Serial Interface • Switching from general-purpose to serial interface pin When switching from general-purpose port to the serial interface pin by the port operation mode register, the terminal TXDn pin outputs "H" level. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-27 Appendix 4 Appendix 4.12 Notes on CAN Module SUMMARY OF PRECAUTIONS Appendix 4.12 Notes on CAN Module • Note for cancelation of transmit and receive CAN remote frame When aborting remote frame transmission or canceling remote frame receiving, make sure that the RA (Remote Active) bit is cleared to "0" after writing "H'00" or "H'0F" to the CAN Message Slot Control Register. (1) When aborting remote frame transmission Start transmission abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register No RA (Remote Active) bit = "0" Yes Complete transmission abort Note 1: H'00 or H'0F can be used. Appendix Figure 4.12.1 Opertion Flow when Aborting Remote Frame Transmission (2) When canceling remote frame receiving Start receiving abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register No RA (Remote Active) bit = "0" Yes Complete receiving abort Note 1: H'00 or H'0F can be used. Appendix Figure 4.12.2 Opertion Flow when Canceling Remote Frame Receiving 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-28 Appendix 4 Appendix 4.13 Notes on DRI Precautions about the DRI is shown below. SUMMARY OF PRECAUTIONS Appendix 4.13 Notes on DRI • In order that the data writing from DRI and RTD to internal RAM use the exclusive bus prepared apart from M32 RFPU, do not usually generate the competition with access from other bus masters (CPU, DMA, NBD, SDI). However DRI transfer, RTD transfer and the access (read-out/writing) from other bus master occur at the same time for areas of the 16-K byte unit of internal RAM, access competition occurs. When access competition occurs, mediation is operated according to the following priority. NBD/SDI > DMA > CPU > DRI > RTD Appendix 4.14 Notes on RAM Backup Mode Appendix 4.14.1 Precautions to Be Observed at Power-On When changing portn from input mode to output mode after power-on, pay attention to the following. If port n is set for output mode while no data is set in the Portn Data Register, the port’s initial output level is instable. Therefore, before changing portn for output mode, make sure the Portn Data Register is set to output a "H." Unless this precaution is followed, port output may go "L" at the same time the port is set for output after the oscillation has stabilized, causing the microcomputer to enter RAM backup mode. Appendix 4.14.2 Power-On Limitation When powering on, make sure to meet the limitation VDDE ≥ VCCER. If VDDE is 3.0 V or more, there will be no problem even when the limitation VDDE ≥ VCCER cannot be met. When the above power-on limitation cannot be met, sufficient evaluation must be made during system design in order to ensure that no power will be applied to the microcomputer with a potential difference of 1 V or more. For potential differences 0 V to 0.6 V, there is almost no in-flow current. The amount of in-flow current begins to increase when the potential difference exceeds 0.6 V. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-29 Appendix 4 Appendix 4.15 Notes on JTAG SUMMARY OF PRECAUTIONS Appendix 4.15 Notes on JTAG Appendix 4.15.1 Notes on Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools, make sure wiring lengths of JTAG pins are matched during board design. VCCE(5V) M32R/ECU 10kΩ (Note 1) RESET# 10kΩ 33Ω JTDO 10kΩ 33Ω JTDI 10kΩ 33Ω JTMS 10kΩ 33Ω JTCK 33Ω JTRST 2kΩ 0.1µF VSS User board 33Ω SDI connector (JTAG connector) Power JTAG tool RESET (Note 2) TDO TDI TMS TCK TRST GND Make sure wiring lengths are the same, and avoid bending wires as much as possible. Be careful not to use through-holes within the wiring. Note 1: The RESET# related circuit and resistance-capacitance values must be determined depending on the user board's system design conditions and the microcomputer's operating conditions. Note 2: N-channel open-drain output is recommended for the RESET output of JTAG tools. For details, see JTAG tool specifications. Notes: • Only if the JTRST pin is firmly tied to ground, the JTDO, JTDI, JTMS and JTCLK pins can be processed by either pullup or pulldown. • Each of these pins must always be processed even when not using JTAG tools. The same pullup/pulldown resistance values as when using JTAG tools may be used. Appendix Figure 4.15.1 Notes on Board Design when Connecting JTAG Tools 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-30 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.15 Notes on JTAG Appendix 4.15.2 Processing Pins when Not Using JTAG The following shows how the pins on the chip should be processed when not using JTAG tools. VCCE(5V) M32R/ECU 0–100kΩ JTDO 0–100kΩ JTDI 0–100kΩ JTMS 0–100kΩ JTCK JTRST 0–100kΩ User board Note: • Only if the JTRST pin is firmly tied to ground, the JTDO, JTDI, JTMS and JTCLK pins can be processed by either pullup or pulldown. Appendix Figure 4.15.2 Processing Pins when Not Using JTAG 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-31 Appendix 4 Appendix 4.16 Notes on Noise SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system incorporating those measures be fully evaluated before it can actually be put to use. Appendix 4.16.1 Reduction of Wiring Length Wiring on the board may serve as an antenna to draw noise into the microcomputer. Shorter the total wiring length, the smaller the possibility of drawing noise into the microcomputer. (1) Wiring of the RESET# pin Reduce the length of wiring connecting to the RESET# pin. Especially when connecting a capacitor between the RESET# and VSS pins, make sure it is wired to each pin in the shortest distance possible (within 20 mm). Reset is a function to initialize the internal logic of the microcomputer. The width of a pulse applied to the RESET# pin is important and is therefore specified as part of timing requirements. If a pulse in width shorter than the specified duration (i.e., noise) is applied to the RESET# pin, the microcomputer will not be reset for a sufficient duration of time and come out of reset before its internal logic is fully initialized, causing the program to malfunction. Noise Reset circuit VSS Reset circuit VSS RESET# VSS RESET# VSS Long wiring Short wiring Appendix Figure 4.16.1 Example Wiring of the RESET# Pin 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-32 Appendix 4 (2) Wiring of clock input/output pins SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise Use as much thick and short wiring as possible for connections to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible (within 20 mm). Also, make sure the VSS pattern used for clock oscillation is a large ground plane and is connected to GND. The microcomputer operates synchronously with the clock generated by an oscillator circuit. Inclusion of noise on the clock input/output pins causes the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. Furthermore, if a noise-induced potential difference exists between the microcomputer’s VSS level and that of the oscillator, the clock fed into the microcomputer may not be an exact clock. Noise OSC-VSS XIN XOUT VSS OSC-VSS XIN XOUT VSS Thin and long wiring Thick and short wiring Appendix Figure 4.16.2 Example Wiring of Clock Input/Output Pins (3) Wiring of the operation mode setup pins When connecting the operation mode setup pins and the VCC or VSS pin, make sure they are wired in the shortest distance possible. The levels of the operation mode setup pins affect the microcomputer’s operation mode. When connecting the operation mode setup pins and the VCC or VSS pin, be careful that no noise-induced potential difference will exist between the operation mode setup pins and the VCC or VSS pin. This is because the presence of such a potential difference makes operation mode instable, which may result in the microcomputer operating erratically or getting out of control. Noise Operation mode setup pins Operation mode setup pins VSS VSS Long wiring Short wiring Appendix Figure 4.16.3 Example Wiring of the MOD0 and MOD1 Pins 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-33 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise Appendix 4.16.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between the VSS and VCC lines. At this time, make sure the requirements described below are met. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the same. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the shortest distance possible. • The VSS and VCC lines have a greater wiring width than that of all other signal lines. VCC Chip VCC VSS Chip VSS VCC VSS Appendix Figure 4.16.4 Example of a Bypass Capacitor Inserted between VSS and VCC Lines Appendix 4.16.3 Processing Analog Input Pin Wiring Insert a resistor of about 100 to 500Ω in series to the analog signal line connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible. The signal fed into the analog input pin (e.g., A/D converter input pin) normally is an output signal from a sensor. In many cases, a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted, so that wiring to the analog input pin is inevitably long. Because a long wiring serves as an antenna which draws noise into the microcomputer, the signal fed into the analog input pin tends to be noise-ridden. Furthermore, if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin, noise riding on the ground line may penetrate into the microcomputer via the capacitor. Noise Sensor Microcomputer Analog input pin AVSS Appendix Figure 4.16.5 Example of a Resistor and Capacitor Inserted for the Analog Signal Line 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-34 Appendix 4 Appendix 4.16.4 Consideration about Oscillator SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it unsusceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines that conduct a large current exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator) as possible. Also, make sure the circuit is protected with a GND pattern. Systems using a microcomputer have signal lines to control a motor, LED or thermal head, for example. When a large current flows in these signal lines, it generates noise due to mutual inductance (M). Noise is generated by mutual inductance between the microcomputer and an adjacent signal line M OSC-VSS XIN Large current GND XOUT A signal line that conducts a large current exists near the microcomputer. M OSC-VSS XIN XOUT Large current GND Locate a signal line that conducts a large current apart from the microcomputer. Appendix Figure 4.16.6 Example Wiring of a Large-Current Signal Line 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-35 Appendix 4 (2) Avoiding effects of rapidly level-changing signal lines SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure the rapidly level-changing signal lines will not intersect the clock-related signal lines and other noise-sensitive signal lines. Rapidly level-changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls. Especially if these signal lines intersect the clock-related signal lines, they will cause the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. High-speed serial interface High-speed timer input/output, etc. XIN XOUT Signal line intersecting the clock-related and other signal lines High-speed serial interface High-speed timer input/output, etc. XIN XOUT Locate the signal line away from the clock-related and other signal lines Appendix Figure 4.16.7 Example Wiring of a Rapidly Level-Changing Signal Line 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-36 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise (3) Protection against signal lines that are the source of strong noise Do not use any pin that will probably be subject to strong noise for an adjacent port near the oscillator. If the pin can be left unused, set it for input and connect to GND via a resistor, or fix it to output and leave open. If the pin needs to be used, it is recommended that it be used for input-only. For protection against a still stronger noise source, set the adjacent port for input and connect to GND via a resistor, and use those that belong to the same port group as much for input-only as possible. If greater stability is required, do not use those that belong to the same port group and set them for input and connect to GND via a resistor. If they need to be used, insert a limiting resistor for protection against noise. If the ports or pins adjacent to the oscillator operate at high speed or are exposed to strong noise from an external source, noise may affect the oscillator circuit, causing its oscillation to become instable. XIN XOUT Oscillator External noise or switching noise Noise Adjacent pin/peripheral pin (set for output) Fast switching Switching noise from an output pin applied directly to the port Adjacent pin/peripheral pin (set for input) Noise External noise from an input pin applied directly to the port Appendix Figure 4.16.8 Example Processing of a Noise-Laden Pin 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-37 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for output) Method for limiting the effect of noise in output mode Adjacent pin/peripheral pin (set for input) Noise Method for limiting noise with a resistor Noise Adjacent pin/peripheral pin (set for output) Fast switching Method for limiting switching noise with a resistor Appendix Figure 4.16.9 Example Processing of Pins Adjacent to the Oscillator 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-38 Appendix 4 Appendix 4.16.5 Processing Input/Output Ports SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100Ω or more in series to the input/output ports. Software measures • For input ports, read out data in a program two or more times to verify that the levels coincide. • For output ports, rewrite the data register at certain intervals because there is a possibility of the output data being inverted by noise. • Rewrite the direction register at certain intervals. Noise Data bus Direction register Noise Data register Input/output port Appendix Figure 4.16.10 Example Processing of Input/Output Ports 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-39 Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.16 Notes on Noise To be written at a later time. 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Appendix 4-40 3 2185/32186 Group Hardware Manual Publication Data : Rev.1.00 Dec 26, 2005 Rev.1.10 May 15, 2007 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2 007. Renesas Technology Corp., All rights reserved. Printed in Japan. 32185/32186 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan
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