3825

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES 3825 User’s Manual Group k eep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Preface This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3825 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3825 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “ SERIES 740 USER’S MANUAL.” BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer, operation of each peripheral function and electric characteristics. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer, a list of control registers, the masking confirmation forms (mask ROM version), ROM programming confirmation forms (One Time PROM version) and mark specification forms which are to be submitted when ordering. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : Bit attributes (Note 2) Bits (Note 1) Values immediately after reset release CPU mode register (CPUM) [Address:3B 16] B 0 1 2 3 4 5 6 Stack page selection bit Fix this bit to “1.” Port X C switch bit Main clock (X IN–XOUT) stop bit Main clock division ratio selection bit Internal system clock selection bit 0 : I/O port 1 : XCIN, XCOUT 0 : Oscillating 1 : Stopped 0 : f(XIN )/2 (high-speed mode) (high-speed mode) 1 : f(XIN )/8 (middle-speed mode) 0 : XIN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) b7 b6 b5 b4 b3 b2 b1 b0 1 Name Processor mode bits b1b0 Functions 00: Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 1 0 0 1 0 1 1 ! 7 : Bit in which nothing is allocated : Bit that is not used for control of the corresponding function Notes 1: Values immediately after reset release 0 …… “0” at reset release 1 …… “1” at reset release ? ……Undefined or reset release 2: Bit attributes ……The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : …… Read W …… Write R …… Write enabled …… Read enabled ! …… Read disabled ! …… Write disabled 0 …… Fixed to “0” V …… Only “0” write enabled 1 …… Fixed to “1” 0 …… Fix to “0” 1 …… Fix to “1” T able of contents Table of contents CHAPTER 1. HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ..................................................................................................................................... 1-2 APPLICATIONS .............................................................................................................................. 1-2 PIN CONFIGURATION (TOP VIEW) ........................................................................................... 1-3 FUNCTIONAL BLOCK DIAGRAM (Package: 100P6S-A) ......................................................... 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 PART NUMBERING ....................................................................................................................... 1-7 GROUP EXPANSION .................................................................................................................... 1-8 GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ..................... 1-9 FUNCTIONAL DESCRIPTION ..................................................................................................... 1-10 Central Processing Unit (CPU) ...............................................................................................1-10 CPU Mode Register ................................................................................................................1-10 MEMORY ....................................................................................................................................... 1-11 Special Function Register (SFR) Area ................................................................................... 1-11 RAM ........................................................................................................................................1-11 ROM ....................................................................................................................................... 1-11 Interrupt Vector Area .............................................................................................................. 1-11 Zero Page ...............................................................................................................................1-11 Special Page ..........................................................................................................................1-11 I/O PORTS ....................................................................................................................................1-13 Direction Registers .................................................................................................................1-13 Port P1 Output Control Register ............................................................................................. 1-13 Pull-up/Pull-down Control ....................................................................................................... 1-13 INTERRUPTS ................................................................................................................................ 1-17 Interrupt Control ......................................................................................................................1-17 Interrupt Operation .................................................................................................................1-17 Notes on Use ..........................................................................................................................1-17 Key Input Interrupt (Key-on Wake up) .................................................................................... 1-19 TIMERS .........................................................................................................................................1-20 Timer X ...................................................................................................................................1-21 Timer X Write Control ............................................................................................................. 1-21 Note on CNTR0 Interrupt Active Edge Selection .................................................................... 1-21 Real Time Port Control ...........................................................................................................1-21 Timer Y ...................................................................................................................................1-22 Note on CNTR1 Interrupt Active Edge Selection .................................................................... 1-22 Timer 1, Timer 2, Timer 3 ....................................................................................................... 1-23 Timer 2 Write Control ............................................................................................................. 1-23 Timer 2 Output Control ...........................................................................................................1-23 Note on Timer 1 to Timer 3..................................................................................................... 1-23 SERIAL I/O ...................................................................................................................................1-24 Clock Synchronous Serial I/O Mode ....................................................................................... 1-24 Asynchronous Serial I/O (UART) Mode.................................................................................. 1-25 Serial I/O Control Register (SIOCON) 001A16 ......................................................................................... 1-26 UART Control Register (UARTCON) 001B16 ........................................................................................... 1-26 Serial I/O Status Register (SIOSTS) 001916 ............................................................................................. 1-26 Transmit Buffer/Receive Buffer Register (TB/RB) 001816 ................................................................... 1-26 Baud Rate Generator (BRG) 001C16 ........................................................................................................... 1-26 i 3825 GROUP USER’S MANUAL T able of contents A-D CONVERTER ........................................................................................................................ 1-28 A-D Conversion Register (AD) 003516 ........................................................................................................ 1-28 A-D Control Register (ADCON) 003416 ...................................................................................................... 1-28 Comparison Voltage Generator .............................................................................................. 1-28 Channel Selector .................................................................................................................... 1-28 Comparator and Control Circuit .............................................................................................. 1-28 LCD DRIVE CONTROL CIRCUIT .............................................................................................. 1-29 Voltage Multiplier (3 Times) .................................................................................................... 1-31 Bias Control and Applied Voltage to LCD Power Input Pins .................................................. 1-31 Common Pin and Duty Ratio Control ..................................................................................... 1-31 LCD Display RAM ................................................................................................................... 1-32 LCD Drive Timing ................................................................................................................... 1-32 CLOCK OUTPUT FUNCTION ..................................................................................................... 1-35 Selection of Input/Output Ports and Clock Output Function ................................................... 1-35 Selection of Output Clock Frequency ..................................................................................... 1-35 RESET CIRCUIT .......................................................................................................................... 1-36 CLOCK GENERATING CIRCUIT ............................................................................................... 1-38 Frequency Control .................................................................................................................. 1-38 Oscillation Control .................................................................................................................. 1-38 NOTES ON PROGRAMMING ..................................................................................................... 1-41 Processor Status Register ...................................................................................................... 1-41 Interrupt .................................................................................................................................. 1-41 Decimal Calculations .............................................................................................................. 1-41 Timers ..................................................................................................................................... 1-41 Multiplication and Division Instructions ................................................................................... 1-41 Ports ....................................................................................................................................... 1-41 Serial I/O ................................................................................................................................. 1-41 A-D Converter ......................................................................................................................... 1-41 Instruction Execution Time ..................................................................................................... 1-41 DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-42 ROM PROGRAMMIG METHOD ............................................................................................... 1-42 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 1-43 RECOMMENDED OPERATING CONDITIONS .......................................................................... 1-43 ELECTRICAL CHARACTERISTICS ............................................................................................ 1-45 A-D CONVERTER CHARACTERISTICS ................................................................................... 1-47 TIMING REQUIREMENTS 1 ....................................................................................................... 1-48 TIMING REQUIREMENTS 2 ....................................................................................................... 1-48 SWITCHING CHARACTERISTICS 1 .......................................................................................... 1-49 SWITCHING CHARACTERISTICS 2 .......................................................................................... 1-49 ABSOLUTE MAXIMUM RATINGS (Extended Operating Temperature Version) ............... 1-50 RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version) .............................. 1-50 ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version) ............. 1-52 A-D CONVERTER CHARACTERISTICS (Extended Operating Temperature Version) ..... 1-53 TIMING REQUIREMENTS 1 (Extended Operating Temperature Version) ......................... 1-54 TIMING REQUIREMENTS 2 (Extended Operating Temperature Version) ......................... 1-54 SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version) ........... 1-55 SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version) ........... 1-55 TIMING DIAGRAM ....................................................................................................................... 1-56 CHAPTER 2. APPLICATION 2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports ........................................................................................................................... 2-2 2.1.2 Function pins ................................................................................................................... 2-7 2.1.3 Application examples ....................................................................................................... 2-8 2.1.4 Notes on use ................................................................................................................. 2-12 3825 GROUP USER’S MANUAL ii T able of contents 2.2 Interrupts ...............................................................................................................................2-15 2.2.1 Explanation of operations .............................................................................................. 2-15 2.2.2 Control ........................................................................................................................... 2-19 2.2.3 Related registers ...........................................................................................................2-22 2.2.4 INT interrupts .................................................................................................................2-28 2.2.5 Key input interrupt ......................................................................................................... 2-29 2.2.6 Notes on use .................................................................................................................2-31 2.3 Timer X and timer Y ..........................................................................................................2-32 2.3.1 Explanation of timer X operations.................................................................................. 2-32 2.3.2 Explanation of timer Y operations.................................................................................. 2-42 2.3.3 Related registers ...........................................................................................................2-50 2.3.4 Register setting example ...............................................................................................2-65 2.3.5 Application examples..................................................................................................... 2-74 2.3.6 Notes on use .................................................................................................................2-81 2.4 Timer 1, timer 2, and timer 3 .......................................................................................... 2-84 2.4.1 Explanation of operations .............................................................................................. 2-84 2.4.2 Related registers ...........................................................................................................2-89 2.4.3 Register setting example ...............................................................................................2-98 2.4.4 Application example ...................................................................................................... 2-99 2.4.5 Notes on use ............................................................................................................... 2-101 2.5 Serial I/O .............................................................................................................................2-102 2.5.1 Explanation of operations ............................................................................................ 2-102 2.5.2 Pins .............................................................................................................................. 2-119 2.5.3 Related registers ......................................................................................................... 2-120 2.5.4 Register setting example ............................................................................................. 2-128 2.5.5 Notes on use ............................................................................................................... 2-138 2.6 A-D converter ..................................................................................................................... 2-140 2.6.1 Explanation of operations ............................................................................................ 2-140 2.6.2 Conversion method ..................................................................................................... 2-141 2.6.3 Pins .............................................................................................................................. 2-145 2.6.4 Related registers ......................................................................................................... 2-146 2.6.5 Measuring various A-D converter standard characteristics ......................................... 2-154 2.6.6 Register setting example ............................................................................................. 2-156 2.6.7 Application example .................................................................................................... 2-161 2.6.8 Notes on use ............................................................................................................... 2-163 2.7 LCD drive control circuit ................................................................................................. 2-164 2.7.1 Explanation of operations ............................................................................................ 2-164 2.7.2 Pins .............................................................................................................................. 2-165 2.7.3 Related registers ......................................................................................................... 2-168 2.7.4 Register setting example ............................................................................................. 2-174 2.7.5 Application examples................................................................................................... 2-176 2.7.6 Notes on use ............................................................................................................... 2-180 2.8 Standby function ............................................................................................................... 2-181 2.8.1 Stop mode ................................................................................................................... 2-181 2.8.2 Wait mode ................................................................................................................... 2-186 2.8.3 State transitions of internal clock φ ...................................................................................... 2-189 2.9 Reset ....................................................................................................................................2-190 2.9.1 Explanation of operations ............................................................................................ 2-190 2.9.2 Internal state of the microcomputer immediately after reset release ........................... 2-192 2.9.3 Reset circuit .................................................................................................................2-193 2.9.4 Notes on the RESET pin ............................................................................................. 2-194 2.10 Oscillation circuit ............................................................................................................. 2-195 2.10.1 Oscillation circuit ........................................................................................................ 2-195 2.10.2 Internal clock φ ..........................................................................................................2-197 2.10.3 Oscillating operation .................................................................................................. 2-199 2.10.4 Oscillation stabilizing time ......................................................................................... 2-202 iii 3825 GROUP USER’S MANUAL T able of contents CHAPTER 3. APPENDIX 3.1 Built-in PROM version .......................................................................................................... 3-2 3.1.1 Product expansion ........................................................................................................... 3-2 3.1.2 Performance overview ..................................................................................................... 3-3 3.1.3 Pin configuration .............................................................................................................. 3-4 3.1.4 Functional block diagram ................................................................................................ 3-7 3.1.5 Notes on use ................................................................................................................... 3-8 3.2 Countermeasures against noise ....................................................................................... 3-10 3.2.1 Shortest wiring length .................................................................................................... 3-10 3.2.2 Connection of a bypass capacitor across the VSS line and the VCC line ....................... 3-11 3.2.3 Wiring to analog input pins ............................................................................................ 3-12 3.2.4 Oscillator concerns ........................................................................................................ 3-12 3.2.5 Installing an oscillator away from signal lines where potential levels change frequently............................ 3-13 3.2.6 Oscillator protection using VSS pattern .......................................................................... 3-13 3.2.7 Set up for I/O ports ........................................................................................................ 3-13 3.2.8 Providing of watchdog timer function by software ......................................................... 3-14 3.3 Control registers .................................................................................................................. 3-15 3.4 List of instruction codes ................................................................................................... 3-29 3.5 Machine instructions ........................................................................................................... 3-30 3.6 Mask ROM ordering method ............................................................................................. 3-40 3.7 Mark specification form ..................................................................................................... 3-52 3.8 Package outlines ................................................................................................................. 3-53 3.9 SFR allocation ...................................................................................................................... 3-55 3.10 Pin configuration ............................................................................................................... 3-56 3825 GROUP USER’S MANUAL iv List of figures List of figures CHAPTER 1. HARDWARE Fig. 1 Pin configuration of M38254M6-XXXFP .................................................................................. 1-2 Fig. 2 Pin configuration of M38254M6-XXXGP ................................................................................. 1-3 Fig. 3 Function block diagram ........................................................................................................... 1-4 Fig. 4 Part numbering ........................................................................................................................ 1-7 Fig. 5 Memory expansion plan (1) ..................................................................................................... 1-8 Fig. 6 Memory expansion plan (2) ..................................................................................................... 1-9 Fig. 7 Structure of CPU mode register ............................................................................................ 1-10 Fig. 8 Memory map diagram ............................................................................................................1-11 Fig. 9 Memory map of special function register (SFR) .................................................................... 1-12 Fig. 10 Structure of PULL register A and PULL register B .............................................................. 1-13 Fig. 11 Port block diagram (1) ......................................................................................................... 1-15 Fig. 12 Port block diagram (2) ......................................................................................................... 1-16 Fig. 13 Interrupt control ...................................................................................................................1-18 Fig. 14 Structure of interrupt-related registers ................................................................................. 1-18 Fig. 15 Connection example when using key input interrupt and port P2 block diagram ................ 1-19 Fig. 16 Timer block diagram ............................................................................................................1-20 Fig. 17 Structure of timer X mode register ....................................................................................... 1-21 Fig. 18 Structure of timer Y mode register ....................................................................................... 1-22 Fig. 19 Structure of timer 123 mode register ................................................................................... 1-23 Fig. 20 Block diagram of clock synchronous serial I/O .................................................................... 1-24 Fig. 21 Operation of clock synchronous serial I/O function ............................................................. 1-24 Fig. 22 Block diagram of UART serial I/O ........................................................................................1-25 Fig. 23 Operation of UART serial I/O function ................................................................................. 1-25 Fig. 24 Structure of serial I/O control registers ................................................................................ 1-27 Fig. 25 Structure of A-D control register .......................................................................................... 1-28 Fig. 26 A-D converter block diagram ...............................................................................................1-28 Fig. 27 Structure of segment output enable register and LCD mode register ................................. 1-29 Fig. 28 Block diagram of LCD controller/driver ................................................................................ 1-30 Fig. 29 Example of circuit at each bias ............................................................................................ 1-31 Fig. 30 LCD display RAM map ........................................................................................................ 1-32 Fig. 31 LCD drive waveform (1/2 bias) ............................................................................................ 1-33 Fig. 32 LCD drive waveform (1/3 bias) ............................................................................................ 1-34 Fig. 33 Structure of clock output control register ............................................................................. 1-35 Fig. 34 Clock output function block diagram .................................................................................... 1-35 Fig. 35 Example of reset circuit ....................................................................................................... 1-36 Fig. 36 Internal state of microcomputer immediately after reset ...................................................... 1-36 Fig. 37 Reset sequence ...................................................................................................................1-37 Fig. 38 Ceramic resonator circuit ..................................................................................................... 1-38 Fig. 39 External clock input circuit ................................................................................................... 1-38 Fig. 40 Clock generating circuit block diagram ................................................................................ 1-39 Fig. 41 State transitions of internal clock φ ............................................................................................... 1-40 Fig. 42 Programming and testing of One Time PROM version ....................................................... 1-42 Fig. 43 Circuit for measuring output switching characteristics ........................................................ 1-54 Fig. 44 Timing diagram .................................................................................................................... 1-55 i 3 825 GROUP USER’S MANUAL List of figures CHAPTER 2. APPLICATION Fig. 2.1.1 I/O port write and read ....................................................................................................... 2-2 Fig. 2.1.2 Structure of port Pi (i = 2, 4 to 8) direction register ............................................................ 2-3 Fig. 2.1.3 Structure of port P1 output control register ........................................................................ 2-4 Fig. 2.1.4 Port direction register setting example .............................................................................. 2-5 Fig. 2.1.5 Structure of port P1 output control register ........................................................................ 2-5 Fig. 2.1.6 Structure of PULL register A .............................................................................................. 2-6 Fig. 2.1.7 Structure of PULL register B .............................................................................................. 2-6 Fig. 2.1.8 Connection example 1 for key input .................................................................................. 2-8 Fig. 2.1.9 Key input control procedure 1 ............................................................................................ 2-8 Fig. 2.1.10 Timing diagram 1 where switch A is pressed .................................................................. 2-9 Fig. 2.1.11 Connection example 2 for key input .............................................................................. 2-10 Fig. 2.1.12 Key input control procedure 2 ........................................................................................ 2-10 Fig. 2.1.13 Timing diagram 2 where switch A is pressed ................................................................ 2-11 Fig. 2.2.1 Interrupt operation diagram ............................................................................................. 2-15 Fig. 2.2.2 Changes of stack pointer and program counter upon acceptance of interrupt request ... 2-17 Fig. 2.2.3 Processing time up to execution of interrupt processing routine ..................................... 2-18 Fig. 2.2.4 Timing after acceptance of interrupt request ................................................................... 2-18 Fig. 2.2.5 Interrupt control diagram ................................................................................................. 2-19 Fig. 2.2.6 Example of multiple interrupts ......................................................................................... 2-21 Fig. 2.2.7 Memory allocation of interrupt-related registers .............................................................. 2-22 Fig. 2.2.8 Structure of interrupt edge selection register ................................................................... 2-22 Fig. 2.2.9 Structure of interrupt request register 1 ........................................................................... 2-23 Fig. 2.2.10 Structure of interrupt request register 2 ......................................................................... 2-24 Fig. 2.2.11 Structure of interrupt control register 1 .......................................................................... 2-25 Fig. 2.2.12 Structure of interrupt control register 2 .......................................................................... 2-26 Fig. 2.2.13 Structure of processor status register ............................................................................ 2-27 Fig. 2.2.14 Structure of interrupt edge selection register ................................................................. 2-28 Fig. 2.2.15 Connection example when key input interrupt is used, and port P2 block diagram ....................................... 2-29 Fig. 2.2.16 Setting values (corresponding to Figure 2.2.15) of key input interrupt-related registers ................................ 2-30 Fig. 2.2.17 Register setting example ............................................................................................... 2-31 Fig. 2.3.1 Timer mode operation example ....................................................................................... 2-33 Fig. 2.3.2 Pulse output mode operation example ............................................................................ 2-35 Fig. 2.3.3 Event counter mode operation example .......................................................................... 2-37 Fig. 2.3.4 Pulse width measurement mode operation example ....................................................... 2-39 Fig. 2.3.5 Timer mode operation example with real time port function ............................................ 2-41 Fig. 2.3.6 Timer mode operation example ....................................................................................... 2-43 Fig. 2.3.7 Period measurement mode operation example ............................................................... 2-45 Fig. 2.3.8 Event counter mode operation example .......................................................................... 2-47 Fig. 2.3.9 Pulse width HL continuously measurement mode operation example ............................ 2-49 Fig. 2.3.10 Memory allocation of timer X- and the timer Y-related registers ................................... 2-50 Fig. 2.3.11 Structure of port P5 direction register ............................................................................ 2-51 Fig. 2.3.12 Structure of timer X latch ............................................................................................... 2-52 Fig. 2.3.13 Structure of timer X counter ........................................................................................... 2-53 Fig. 2.3.14 Structure of timer Y latch ............................................................................................... 2-54 Fig. 2.3.15 Structure of timer Y counter ........................................................................................... 2-55 Fig. 2.3.16 Structure of timer X mode register ................................................................................. 2-56 Fig. 2.3.17 Structure of timer Y mode register ................................................................................. 2-59 Fig. 2.3.18 Structure of interrupt request register 1 ......................................................................... 2-61 Fig. 2.3.19 Structure of interrupt request register 2 ......................................................................... 2-62 Fig. 2.3.20 Structure of interrupt control register 1 .......................................................................... 2-63 Fig. 2.3.21 Structure of interrupt control register 2 .......................................................................... 2-64 Fig. 2.3.22 Example of setting registers for using timer mode ........................................................ 2-65 Fig. 2.3.23 Example of setting registers for using pulse output mode ............................................. 2-66 Fig. 2.3.24 Example of setting registers for using event counter mode ........................................... 2-67 Fig. 2.3.25 Example of setting registers for using pulse width measurement mode ....................... 2-68 Fig. 2.3.26 Example of setting registers for using RTP ................................................................... 2-69 3 825 GROUP USER’S MANUAL ii List of figures Fig. 2.3.27 Example of setting registers for using timer mode ........................................................ 2-70 Fig. 2.3.28 Example of setting registers for using period measurement mode ............................... 2-71 Fig. 2.3.29 Example of setting registers for using event counter mode ........................................... 2-72 Fig. 2.3.30 Example of setting registers for using pulse width HL continuously measurement mode .......................... 2-73 Fig. 2.3.31 Example of peripheral circuit ......................................................................................... 2-74 Fig. 2.3.32 Connection of timer and setting of division ratio ............................................................ 2-74 Fig. 2.3.33 Setting of related registers ............................................................................................. 2-75 Fig. 2.3.34 Control procedure ..........................................................................................................2-75 Fig. 2.3.35 Example of peripheral circuit ......................................................................................... 2-76 Fig. 2.3.36 Setting of related registers ............................................................................................. 2-76 Fig. 2.3.37 Ringer signal waveform ................................................................................................. 2-77 Fig. 2.3.38 Operation timing when ringing pulse is input ................................................................. 2-77 Fig. 2.3.39 Control procedure ..........................................................................................................2-78 Fig. 2.3.40 Application connection example when RTP is used ...................................................... 2-79 Fig. 2.3.41 RTP output example ...................................................................................................... 2-80 Fig. 2.3.42 Timer X interrupt processing procedure example when RTP is used ........................... 2-80 Fig. 2.4.1 Timer mode operation example ....................................................................................... 2-85 Fig. 2.4.2 Rewriting example of counter and latch corresponding to timers 1 or 3 .......................... 2-86 Fig. 2.4.3 Rewriting example of timer 2 counter and timer 2 latch (Writing in timer 2 latch only) .... 2-87 Fig. 2.4.4 Pulse output example ...................................................................................................... 2-88 Fig. 2.4.5 Memory allocation of timer-related registers ................................................................... 2-89 Fig. 2.4.6 Structure of latches ..........................................................................................................2-90 Fig. 2.4.7 Structure of timer counters .............................................................................................. 2-91 Fig. 2.4.8 Structure of timer 123 mode register ............................................................................... 2-92 Fig. 2.4.9 Structure of interrupt request register 1 ........................................................................... 2-94 Fig. 2.4.10 Structure of interrupt request register 2 ......................................................................... 2-95 Fig. 2.4.11 Structure of interrupt control register 1 .......................................................................... 2-96 Fig. 2.4.12 Structure of interrupt control register 2 .......................................................................... 2-97 Fig. 2.4.13 Example of setting registers for timers 1, 2, and 3 ........................................................ 2-98 Fig. 2.4.14 Setting of related registers ............................................................................................. 2-99 Fig. 2.4.15 Control procedure ........................................................................................................ 2-100 Fig. 2.5.1 External connection example in clock synchronous mode ............................................ 2-102 Fig. 2.5.2 Shift clock ......................................................................................................................2-103 Fig. 2.5.3 Transmit operation in clock synchronous mode ............................................................ 2-106 Fig. 2.5.4 Transmit timing example in clock synchronous mode ................................................... 2-107 Fig. 2.5.5 Receive operation in clock synchronous mode ............................................................. 2-109 Fig. 2.5.6 Receive timing example in clock synchronous mode .................................................... 2-109 Fig. 2.5.7 Transmit/receive timing example in clock synchronous mode ...................................... 2-110 Fig. 2.5.8 External connection example in UART mode ................................................................ 2-111 Fig. 2.5.9 Transfer data format in UART mode ............................................................................. 2-113 Fig. 2.5.10 All transfer data formats in UART mode ...................................................................... 2-114 Fig. 2.5.11 Transmit timing example in UART mode ..................................................................... 2-116 Fig. 2.5.12 Receive timing example in UART mode ...................................................................... 2-118 Fig. 2.5.13 Memory allocation of serial I/O-related registers ......................................................... 2-120 Fig. 2.5.14 Structure of transmit/receive buffer register ................................................................ 2-120 Fig. 2.5.15 Structure of serial I/O status register ........................................................................... 2-121 Fig. 2.5.16 Structure of serial I/O control register .......................................................................... 2-123 Fig. 2.5.17 Structure of UART control register .............................................................................. 2-126 Fig. 2.5.18 Transmitting method in clock synchronous mode (1) .................................................. 2-128 Fig. 2.5.19 Transmitting method in clock synchronous mode (2) .................................................. 2-129 Fig. 2.5.20 Receiving method in clock synchronous mode (1) ...................................................... 2-130 Fig. 2.5.21 Receiving method in clock synchronous mode (2) ...................................................... 2-131 Fig. 2.5.22 Transmitting method in UART mode (1) ...................................................................... 2-132 Fig. 2.5.23 Transmitting method in UART mode (2) ...................................................................... 2-133 Fig. 2.5.24 Receiving method in UART mode (1) .......................................................................... 2-134 Fig. 2.5.25 Receiving method in UART mode (2) .......................................................................... 2-135 iii 3 825 GROUP USER’S MANUAL List of figures Fig. 2.6.1 Changes in A-D conversion register and comparison voltage during A-D conversion .. 2-143 Fig. 2.6.2 A-D converter equivalent connection diagram ............................................................... 2-144 Fig. 2.6.3 Memory allocation of A-D converter-related registers ................................................... 2-146 Fig. 2.6.4 Structure of A-D control register .................................................................................... 2-147 Fig. 2.6.5 Structure of A-D conversion register ............................................................................. 2-148 Fig. 2.6.6 Structure of CPU mode register .................................................................................... 2-149 Fig. 2.6.7 Structure of port P5 direction register ............................................................................2-150 Fig. 2.6.8 Structure of port P6 direction register ............................................................................2-151 Fig. 2.6.9 Structure of interrupt request register 2 ......................................................................... 2-152 Fig. 2.6.10 Structure of interrupt control register 2 ........................................................................ 2-153 Fig. 2.6.11 Absolute accuracy of A-D converter ............................................................................2-154 Fig. 2.6.12 Differential non-linearity error of A-D converter ........................................................... 2-155 Fig. 2.6.13 Operating conditions for using A-D converter .............................................................. 2-156 Fig. 2.6.14 Register initialization example when internal trigger is selected (1) ............................ 2-157 Fig. 2.6.15 Register initialization example when internal trigger is selected (2) ............................ 2-158 Fig. 2.6.16 Register initialization example when external trigger is selected (1) ........................... 2-159 Fig. 2.6.17 Register initialization example when external trigger is selected (2) ........................... 2-160 Fig. 2.6.18 Example of peripheral circuit ....................................................................................... 2-161 Fig. 2.6.19 Setting of related registers ........................................................................................... 2-161 Fig. 2.6.20 Control procedure ........................................................................................................ 2-162 Fig. 2.7.1 Memory allocation of LCD display-related registers ...................................................... 2-168 Fig. 2.7.2 Structure of segment output enable register ................................................................. 2-169 Fig. 2.7.3 Structure of LCD mode register ..................................................................................... 2-171 Fig. 2.7.4 Structure of port P0 direction register ............................................................................2-172 Fig. 2.7.5 Structure of PULL register A .......................................................................................... 2-173 Fig. 2.7.6 Example of setting registers for LCD display (1) ........................................................... 2-174 Fig. 2.7.7 Example of setting registers for LCD display (2) ........................................................... 2-175 Fig. 2.7.8 8-segment LCD panel display pattern example when the duty ratio number is 4 ......... 2-176 Fig. 2.7.9 LCD panel example ....................................................................................................... 2-177 Fig. 2.7.10 Segment allocation example ....................................................................................... 2-177 Fig. 2.7.11 LCD display RAM setting example .............................................................................. 2-177 Fig. 2.7.12 Setting of related registers ........................................................................................... 2-178 Fig. 2.7.13 Control procedure ........................................................................................................ 2-179 Fig. 2.8.1 Oscillation stabilizing time at restoration by reset input ................................................. 2-182 Fig. 2.8.2 Execution sequence example at restoration by occurrence of INT0 interrupt request .. 2-184 Fig. 2.8.3 Reset input time ............................................................................................................. 2-187 Fig. 2.8.4 State transitions of internal clock φ ......................................................................................... 2-189 Fig. 2.9.1 Internal reset state hold/release timing .......................................................................... 2-190 Fig. 2.9.2 Internal processing sequence immediately after reset release ..................................... 2-191 Fig. 2.9.3 Internal state of microcomputer immediately after reset release ................................... 2-192 Fig. 2.9.4 Poweron reset conditions .............................................................................................. 2-193 Fig. 2.9.5 Poweron reset circuit examples ..................................................................................... 2-193 Fig. 2.10.1 Oscillation circuit example using ceramic resonators .................................................. 2-195 Fig. 2.10.2 External clock input circuit example ............................................................................2-196 Fig. 2.10.3 Clock generating circuit block diagram ........................................................................ 2-197 Fig. 2.10.4 Structure of clock output control register ..................................................................... 2-198 Fig. 2.10.5 State transitions of internal clock φ ...................................................................................... 2-201 Fig. 2.10.6 Oscillation stabilizing time at poweron ......................................................................... 2-202 Fig. 2.10.7 Oscillation stabilizing time at reoscillation of XIN ....................................................................... 2-203 3 825 GROUP USER’S MANUAL iv List of figures CHAPTER 3. APPENDIX Fig. 3.1.1 Pin configuration of EPROM version (top view) ................................................................ 3-4 Fig. 3.1.2 Pin configuration of One Time PROM version (top view) (1) ............................................. 3-5 Fig. 3.1.3 Pin configuration of One Time PROM version (top view) (2) ............................................. 3-6 Fig. 3.1.4 Functional block diagram of built-in PROM version ........................................................... 3-7 Fig. 3.1.5 Programming and testing of One Time PROM version (shipped in blank) ........................ 3-9 Fig. 3.2.1 Wiring for the RESET input pin ........................................................................................3-10 Fig. 3.2.2 Wiring for clock I/O pins ................................................................................................... 3-10 Fig. 3.2.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ........................ 3-11 Fig. 3.2.4 Bypass capacitor across the VSS line and the VCC line ................................................... 3-11 Fig. 3.2.5 Analog signal line and a resistor and a capacitor ............................................................ 3-12 Fig. 3.2.6 Wiring for a large current signal line ................................................................................ 3-12 Fig. 3.2.7 Wiring to a signal line where potential levels change frequently ..................................... 3-13 Fig. 3.2.8 VSS pattern on the underside of an oscillator .................................................................. 3-13 Fig. 3.2.9 Setup for I/O ports ...........................................................................................................3-13 Fig. 3.2.10 Watchdog timer by software .......................................................................................... 3-14 Fig. 3.3.1 Structure of port P1 output control register ...................................................................... 3-15 Fig. 3.3.2 Structure of port Pi (i = 2, 4 to 8) direction registers ........................................................ 3-15 Fig. 3.3.3 Structure of PULL register A ............................................................................................ 3-16 Fig. 3.3.4 Structure of PULL register B ............................................................................................ 3-16 Fig. 3.3.5 Structure of serial I/O status register ............................................................................... 3-17 Fig. 3.3.6 Structure of serial I/O control register .............................................................................. 3-18 Fig. 3.3.7 Structure of UART control register .................................................................................. 3-19 Fig. 3.3.8 Structure of timer X mode register ................................................................................... 3-20 Fig. 3.3.9 Structure of timer Y mode register ................................................................................... 3-21 Fig. 3.3.10 Structure of timer 123 mode register ............................................................................. 3-22 Fig. 3.3.11 Structure of clock output control register ....................................................................... 3-22 Fig. 3.3.12 Structure of A-D control register .................................................................................... 3-23 Fig. 3.3.13 Structure of segment output register ............................................................................. 3-24 Fig. 3.3.14 Structure of LCD mode register ..................................................................................... 3-25 Fig. 3.3.15 Structure of interrupt edge selection register ................................................................. 3-26 Fig. 3.3.16 Structure of CPU mode register .................................................................................... 3-26 Fig. 3.3.17 Structure of interrupt request register 1 ......................................................................... 3-27 Fig. 3.3.18 Structure of interrupt request register 2 ......................................................................... 3-27 Fig. 3.3.19 Structure of interrupt control register 1 .......................................................................... 3-28 Fig. 3.3.20 Structure of interrupt control register 2 .......................................................................... 3-28 v 3 825 GROUP USER’S MANUAL List of tables List of tables CHAPTER 1. HARDWARE Table 1 Pin description (1) ................................................................................................................. 1-5 Table 2 Pin description (2) ................................................................................................................. 1-6 Table 3 List of supported products (1) ............................................................................................... 1-8 Table 4 List of supported products (2) ............................................................................................... 1-9 Table 5 I/O ports functions .............................................................................................................. 1-14 Table 6 Interrupt vector addresses and priority ............................................................................... 1-17 Table 7 Maximum number of display pixels at each duty ratio ........................................................ 1-29 Table 8 Bias control and applied voltage to VL1–VL3 ........................................................................................ 1-31 Table 9 Duty ratio control and common pins used .......................................................................... 1-31 Table 10 Programming adapter ....................................................................................................... 1-42 Table 11 Absolute maximum ratings ...............................................................................................1-43 Table 12 Recommended operating conditions (1) ........................................................................... 1-43 Table 13 Recommended operating conditions (2) ........................................................................... 1-44 Table 14 Electrical characteristics (1) .............................................................................................. 1-45 Table 15 Electrical characteristics (2) .............................................................................................. 1-46 Table 16 A-D converter characteristics ........................................................................................... 1-46 Table 17 Timing requirements 1 ...................................................................................................... 1-47 Table 18 Timing requirements 2 ...................................................................................................... 1-47 Table 19 Switching characteristics 1 ...............................................................................................1-48 Table 20 Switching characteristics 2 ...............................................................................................1-48 Table 21 Absolute maximum ratings (Extended operating temperature version) ............................ 1-49 Table 22 Recommended operating conditions (Extended operating temperature version) (1) ....... 1-49 Table 23 Recommended operating conditions (Extended operating temperature version) (2) ....... 1-50 Table 24 Electrical characteristics (Extended operating temperature version) (1) .......................... 1-51 Table 25 Electrical characteristics (Extended operating temperature version) (2) .......................... 1-52 Table 26 A-D converter characteristics (Extended operating temperature version) ........................ 1-52 Table 27 Timing requirements 1 (Extended operating temperature version) .................................. 1-53 Table 28 Timing requirements 2 (Extended operating temperature version) .................................. 1-53 Table 29 Switching characteristics 1 (Extended operating temperature version) ............................ 1-54 Table 30 Switching characteristics 2 (Extended operating temperature version) ............................ 1-54 CHAPTER 2. APPLICATION Table 2.1.1 Memory allocation of port registers ................................................................................ 2-3 Table 2.1.2 Memory allocation of port direction registers .................................................................. 2-4 Table 2.1.3 I/O ports which either pull-up or pull-down is controlled by software .............................. 2-5 Table 2.1.4 Termination of unused pins .......................................................................................... 2-14 Table 2.2.1 Interrupt sources and interrupt request generating conditions ..................................... 2-16 Table 2.2.2 List of interrupt bits for individual interrupt sources ...................................................... 2-20 Table 2.3.1 Real time ports and bits for storing data ....................................................................... 2-40 Table 2.3.2 Relation between timer X operating mode bits and operating modes .......................... 2-57 Table 2.3.3 Relation between timer Y operating mode bits and operating modes .......................... 2-60 Table 2.3.4 Table example for timer X setting value ....................................................................... 2-80 Table 2.3.5 Table example for RTP setting value ........................................................................... 2-80 Table 2.4.1 Relation between timer 2 count source selection bit and count sources ...................... 2-93 Table 2.4.2 Relation between timer 3 count source selection bit and count sources ...................... 2-93 Table 2.4.3 Relation between timer 1 count source selection bit and count sources ...................... 2-93 Table 2.5.1 Baud rate selection table (reference values) .............................................................. 2-112 Table 2.5.2 Each bit function of UART transmit data .................................................................... 2-113 Table 2.5.3 Control contents of transmit enable bit ....................................................................... 2-124 Table 2.5.4 Control contents of receive enable bit ........................................................................ 2-125 3 825 GROUP USER’S MANUAL i List of tables Table 2.5.5 Relation between UART control register and transfer data formats ........................... 2-127 Table 2.6.1 Expression for comparison voltage “Vref” ................................................................... 2-141 Table 2.6.2 List of pin functions used in A-D converter ................................................................. 2-145 Table 2.7.1 Pin functions by setting segment output enable register ............................................ 2-165 Table 2.7.2 Pin functions by setting the corresponding registers when they are not used as segment output pins .. 2-166 Table 2.7.3 Setting of segment output pins for LCD display ......................................................... 2-166 Table 2.7.4 Setting of output ports P3, P10–P15 and P0 ............................................................... 2-167 Table 2.7.5 Setting of pull-down pins ............................................................................................ 2-167 Table 2.8.1 State in the stop mode ................................................................................................ 2-181 Table 2.8.2 State in wait mode ...................................................................................................... 2-186 Table 2.9.1 Timers 1 and 2 at reset ...............................................................................................2-191 CHAPTER 3. APPENDIX Table 3.1.1 Product expansion of built-in PROM version .................................................................. 3-2 Table 3.1.2 Performance overview of built-in PROM version ............................................................ 3-3 ii 3 825 GROUP USER’S MANUAL CHAPTER 1 HARDWARE MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3825 group is the 8-bit microcomputer based on the 740 family core technology. The 3825 group has the LCD drive control circuit an 8-channel AD converter, and a Serial I/O as additional functions. The various microcomputers in the 3825 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. • • FEATURES • Basic machine-language instructions ....................................... 71 • The minimum instruction execution time ............................ 0.5 µs (at 8MHz oscillation frequency) • Memory size • • • • • • • ROM .................................................................. 4 K to 32 K bytes RAM ................................................................. 192 to 1024 bytes Programmable input/output ports ............................................. 43 Software pull-up/pull-down resistors (Ports P0–P8) Interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) Timers ........................................................... 8-bit ! 3, 16-bit ! 2 Serial I/O ...................... 8-bit ! 1 (UART or Clock-synchronized) A-D converter .................................................. 8-bit ! 8 channels LCD drive control circuit Bias ................................................................................... 1/2, 1/3 • • Duty ............................................................................ 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ......................................................................... 40 2 Clock generating circuit Clock (XIN-XOUT) .................................. Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode .................................................... 4.0 to 5.5 V (at 8MHz oscillation frequency and high-speed selected) In middle-speed mode ................................................ 2.5 to 5.5 V (at 8MHz oscillation frequency and middle-speed selected) In low-speed mode ...................................................... 2.5 to 5.5 V (Extended operating temperature version: 3.0 V to 5.5 V) Power dissipation In high-speed mode ........................................................... 32 mW (at 8 MHz oscillation frequency) In low-speed mode .............................................................. 45 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... – 20 to 85°C (Extended operating temperature version: –40 to 85°C) APPLICATIONS Camera, household appliances, consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30 /SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35 /SEG23 P36/SEG24 P37/SEG25 P00 /SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05 /SEG31 P06/SEG32 P07/SEG33 P10 /SEG34 P11/SEG35 P12/SEG36 P13 /SEG37 P14/SEG38 P15/SEG39 80 79 77 74 71 68 65 62 59 56 78 75 72 69 66 63 60 57 54 53 76 73 70 67 64 61 58 55 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 21 25 26 23 24 17 10 13 20 16 18 12 11 14 15 19 22 27 28 29 30 3 6 2 5 1 4 7 8 9 50 49 48 47 46 45 44 43 42 M38254M6-XXXFP 41 40 39 38 37 36 35 34 33 32 31 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/XCOUT P81/XCIN RESET P70 P71 P72 P73 Fig. 1 Pin configuration of M38254M6-XXXFP 1-2 C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3 P62/AN2 P61/AN1 P60 /AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45 / TXD P44/RXD P43 /INT1 P42/INT0 P41 / f(XIN)/5 / f(XIN )/10 P40 / f(XIN ) / f(XIN )/2 P77 P76 P75 P74 Package type : 100P6S-A 100-pin plastic-molded QFP SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 98 99 97 96 94 95 93 91 92 90 89 87 88 85 86 84 83 82 81 79 80 78 77 76 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 40 42 43 44 46 45 47 48 49 27 26 28 30 29 32 31 33 35 34 37 36 38 39 41 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Fig. 2 Pin configuration of M38254M6-XXXGP PIN CONFIGURATION (TOP VIEW) M38254M6-XXXGP Package type : 100P6D-A 100-pin plastic-molded LQFP P67/AN7 P66/AN6 P65 /AN5 P64/AN4 P63/AN3 P62 /AN2 P61/AN1 P60/AN0 P57/ADT P56/ TOUT P55 /CNTR1 P54/CNTR0 P53/RTP1 P52 /RTP0 P51/INT3 P50 /INT2 P47 /SRDY P46 /SCLK P45/ TXD P44/R XD P43/INT1 P42/INT 0 P41 / f(XIN)/5 / f(X IN )/10 P40 / f(XIN) / f(XIN )/2 P77 SEG13 SEG14 SEG15 SEG16 SEG17 P30 /SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35 /SEG23 P36/SEG24 P37/SEG25 P00 /SEG26 P01/SEG27 P02/SEG28 P03 /SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10 /SEG34 P11/SEG35 P12/SEG36 P13 /SEG37 P14 /SEG38 P15 /SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80 /XCOUT P81 /XCIN RESET P70 P71 P72 P73 P74 P75 P76 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1-3 XCOUT XCIN ADT INT2 , INT3 INT0, INT1 36 37 92 93 27 28 29 30 31 32 33 34 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 65 66 67 68 69 70 71 72 41 42 43 44 45 46 47 48 Key-on wake up P8 (2) P5 (8) P4 (8) Real time port function Fig. 3 Functional block diagram. 1-4 Reset input RESET (5 V) VCC (0 V) VSS 40 91 35 FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A) Clock input XIN Clock output XOUT 38 39 Data bus Clock generating circuit CPU A ROM LCD display RAM (20 bytes) 2 1 RAM 100 X Y S PCH PS Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) PCL 99 98 97 96 VL1 C1 C2 VL2 VL3 φ XCIN Subclock input XCOUT Subclock output LCD drive control circuit 95 94 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 COM0 COM1 COM2 COM3 A-D converter (8) SI/O (8) TOUT CNTR0, CNTR1 RTP0, RTP1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P7 (8) P6 (8) P3 (8) P2 (8) P1 (8) P0 (8) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O port P8 I/O port P7 I/O port P6 VREF AVSS (0 V) I/O port P5 I/O port P4 Output port P3 I/O port P2 Output port P1 Output port P0 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1. Pin description (1) Pin VCC, VSS Name Power source Function • Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 3.0 V to 5.5 V) • Reference voltage input pin for A-D converter. Function except a port function VREF Analog reference voltage Analog power source Reset input Clock input AVSS • GND input pin for A-D converter. • Connect to VSS. • Reset input pin for active “L” • Input and output pins for the main clock generating circuit. • Feedback resistor is built in between XIN pin and XOUT pin. • Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency. • If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. • This clock is used as the oscillating source of system clock. • Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage • Input 0 – VL3 voltage to LCD • External capacitor pins for a voltage multiplier (3 times) of LCD contorl. • LCD common output pins • COM2 and COM3 are not used at 1/2 duty ratio. • COM3 is not used at 1/3 duty ratio. • LCD segment output pins • • • • • • • • • • • • • • • • • 8-bit output port CMOS 3-state output structure Pull-down control is enabled. Port output control is enabled. 6-bit output port CMOS 3-state output structure Pull-down control is enabled. Port output control is enabled. 2-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. Pull-up control is enabled. • Key input (key-on wake up) interrupt input pins • LCD segment pins RESET XIN XOUT Clock output VL1 – VL3 C 1 , C2 LCD power source Charge-pump capacitor pin Common output COM0 – COM3 SEG0 – SEG17 P00/SEG26 – P07/SEG33 Segment output Output port P0 P10/SEG34 – P15/SEG39 Output port P1 P16, P17 I/O port P1 P20 – P27 I/O port P2 8-bit Input port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. • Pull-up control is enabled. • 8-bit output port • CMOS 3-state output structure • I/O direction register allows each pin to be individually programmed as either input or output. • Pull-up control is enabled. P30/SEG15 – P37/SEG25 Output port P3 • LCD segment pins 1-5 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 2. Pin description (2) Pin P40/f(XIN)/ f(XIN)/2, P41/f(XIN)/5/ f(XIN)/10 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/TOUT P57/ADT P60/AN0– P67/AN7 I/O port P6 • • • • 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. I/O port P5 • • • • 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. Name I/O port P4 • • • • Function Function except a port function 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. • Clock output pins • Interrupt input pins • Serial I/O function pins • Interrupt input pins • Real time port function pins • Timer function pins • Timer output pin • A-D trigger input pin • A-D conversion input pins P70 P71–P77 Input port P7 I/O port P7 • 1-bit input port • CMOS compatible input level • • • • • • • • • 7-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. 2-bit I/O port CMOS compatible input level CMOS 3-state output structure Pull-up control is enabled. I/O direction register allows each pin to be individually programmed as either input or output. • Sub-clock generating circuit I/O pins (Connect a resonator. External clock cannot be used.) P80/XCOUT P81/XCIN I/O port P8 1-6 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3825 4 M 6 - XXX FP Package type FP : 100P6S-A package GP : 100P6D-A package FS : 100D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character – : Standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes Fig. 4 Part Numbering 1-7 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3825 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM size ................................................... 16 K to 32 K bytes PROM size ................................................. 24 K to 32 K bytes RAM size ..................................................... 640 to 1024 bytes (2) Packages 100P6S-A ......................... 0.65 mm-pitch plastic molded QFP 100P6D-A ......................... 0.5 mm-pitch plastic molded LQFP 100D0 .............. Window type ceramic LCC (EPROM version) Memory Expansion Plan ROM size (bytes) 32K Mass product M38257M8/E8 28K Mass product 24K M38254M6 20K Mass product 16K M38254M4 12K 8K 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Fig. 5 Memory expansion Plan (1) Currently supported products are listed below. Table 3. List of supported products (1) Product M38254M4-XXXFP M38254M4-XXXGP M38254M6-XXXFP M38254M6-XXXGP M38257M8-XXXFP M38257E8-XXXFP M38257E8FP M38257M8-XXXGP M38257E8-XXXGP M38257E8GP M38257E8FS (P) ROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) RAM size (bytes) 640 640 Package 100P6S-A 100P6D-A 100P6S-A 100P6D-A 100P6S-A 32768 (32638) 1024 100P6D-A 100D0 Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Remarks As of May 1996 1-8 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) Mitsubishi plans to expand the 3825 group (extended operating temperature version) as follows: (1) Support for mask ROM versions ROM size ................................................... 16 K to 32 K bytes RAM size ..................................................... 640 to 1024 bytes (2) Packages 100P6S-A ......................... 0.65 mm-pitch plastic molded QFP Memory Expansion Plan ROM size (bytes) 32K Mass product M38257M8D 28K Mass product 24K M38254M6D 20K Mass product 16K M38254M4D 12K 8K 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Fig. 6 Memory expansion Plan (2) Currently supported products are listed below. Table 4. List of supported products (2) Product M38254M4DXXXFP M38254M6DXXXFP M38257M8DXXXFP (P) ROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) 32768 (32638) RAM size (bytes) 640 640 1024 100P6S-A Package Mask ROM version Mask ROM version Mask ROM version Remarks As of May 1996 1-9 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3825 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. CPU Mode Register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. b7 b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns “1” when read) (Do not write “0” to this bit) Port XC switch bit 0 : I/O port 1 : XCIN , XCOUT Main clock ( X IN -XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN )/2 (high-speed mode) 1 : f(XIN )/8 (middle-speed mode) Internal system clock selection bit 0 : XIN -XOUT selected (middle-/high-speed mode) 1 : XCIN -XCOUT selected (low-speed mode) Fig. 7 Structure of CPU mode register 1-10 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page The 256 bytes from addresses 000016 t o 00FF 16 a re called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 Address XXXX16 00FF 16 013F 16 01BF16 023F 16 02BF16 033F 16 03BF16 043F 16 XXXX16 Reserved area 044016 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 Address YYYY16 F000 16 E00016 D00016 C00016 B00016 A00016 900016 800016 Address ZZZZ 16 F080 16 E080 16 D08016 C08016 B080 16 A080 16 908016 808016 ROM FF0016 FFDC16 Interrupt vector area FFFE16 Reserved ROM area FFFF 16 Special page ZZZZ 16 YYYY16 Reserved ROM area (128 bytes) Not used RAM 000016 SFR area 004016 005416 010016 LCD display RAM area Zero page Fig. 8 Memory map diagram 1-11 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 000116 000216 Port P1 (P1) 000316 Port P1 output control register (P1C) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 Port P8 (P8) 001116 Port P8 direction register (P8D) 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16 002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 Clock output control register (TCON) 002B16 002C16 002D16 002E16 002F 16 003016 003116 003216 003316 003416 A-D control register (ADCON) 003516 A-D conversion register (AD) 003616 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F 16 Interrupt control register 2(ICON2) Fig. 9 Memory map of special function register (SFR) 1-12 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers The 3825 group has 43 programmable I/O pins arranged in seven I/O ports (ports P1 6, P1 7 P2, P4–P6, P71 –P77 and P8). The I/O ports have direction registers which determine the input/output direction of each individual pin. (Ports P16 and P17 are shared with bits 6 and 7 of the port P1 output control register). Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. b7 b0 PULL register A (PULLA : address 0016 16) P0, P10–P15 , P3 pull-down (shared with P0 and P3 output control : refer to the text) P16 –P17 pull-up P20 –P27 pull-up P80 , P81 pull-up P40 –P43 pull-up P44 –P47 pull-up Not used (return “0” when read) b7 b0 PULL register B (PULLB : address 0017 16) P50 –P53 pull-up P54 –P57 pull-up P60 –P63 pull-up P64 –P67 pull-up P71 –P73 pull-up P74 –P77 pull-up Not used (return “0” when read) 0 : Disable 1 : Enable Port P1 Output Control Register Bit 0 of the port P1 output control register (address 000316) enables control of the output of ports P10 to P15. When the bit is set to “1”, the port output function is valid. In this case, setting of the PULL register A to ports P1 0 to P15 is invalid. When resetting, bit 0 of the port P1 output control register is set to “0” (the port output function is invalid.) Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output port. Fig. 10 Structure of PULL register A and PULL register B Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL register B (address 0017 16), ports P0 to P8 can control either pulldown or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. (except for ports P0 and P3). Ports P0 and P3 share the port output control function with bit 0 of the PULL register A. When set to “1”, the port output function is invalid (Pull-down is valid). When set to “0”, the port output function is valid (Pull-down is invalid). The PULL register A setting is invalid for pins set to segment output on the segment output enable register. 1-13 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 5. I/O ports functions Pin P00/SEG26– P07/SEG33 Name Port P0 Input/Output Output I/O Format CMOS 3-state output Non-Port Function LCD segment output Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register Port P1 output control register PULL register A Key-on wake up interrupt input PULL register A Interrupt control register PULL register A Segment output enable register Clock output control register PULL register A PULL register A Interrupt edge selection register PULL register A Serial I/O control register Serial I/O status register UART control register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register PULL register B A-D control register (3) (4) (5) (6) (2) (7) (8) (9) (8) (9) (10) Diagram No. (1) P10/SEG34– P15/SEG39 Port P1 P16 , P17 Output CMOS 3-state output LCD segment output (1) Input/output, individual bits Port P2 Input/output, individual bits P20–P27 CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output (2) (2) P30/SEG18– P37/SEG25 P40/f(XIN)/ f(XIN)/2, P41/f(XIN)/5/ f(XIN)/10 P42/INT0, P43/INT1 P44/RXD P54/TXD P46/SCLK P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/TOUT P57/ADT P60/AN0– P67/AN7 P70 Port P3 Output LCD segment output (1) Clock output (2) Port P4 Input/output, individual bits CMOS compatible input level CMOS 3-state output External interrupt input Serial I/O function I/O External interrupt input Real time port function output Port P5 Input/output, individual bits CMOS compatible input level CMOS 3-state output Timer X function I/O Timer Y function input Timer 2 output A-D trigger input Port P6 Input/output, individual bits Input Port P7 Input/output, individual bits Input/output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output A-D conversion input (11) PULL register B Sub-clock generating circuit (12) (13) (14) (15) (16) P71–P77 P80/XCOUT Port P8 P81/XCIN COM0–COM3 SEG0–SEG17 Common Segment PULL register A CPU mode register LCD mode register Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 1-14 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0, P1 0–P15 , P3 LCD drive timing Segment data Data bus Port latch Interface logic level shift circuit VL2/VL3/VCC Segment/Port Segment VL1/VSS Port Port/Segment Port ON/OFF Pull-down (2) Ports P1 6, P17 , P2, P40 –P43 , P50 , P51 Pull-up control (3) Port P44 Pull-up control Serial I/O enable bit Reception enable bit Direction register Data bus Direction register Data bus Port latch Port latch Key-on wake up interrupt input INT0 –INT3 interrupt input Except P16 , P17 , P40 , P41 Serial I/O input (4) Port P45 Pull-up control P45 /TXD P-channel output disable bit Serial I/O enable bit Transmission enable bit Direction register Data bus Port latch (5) Port P46 Serial I/O clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Pull-up control Serial I/O output Serial I/O clock output Serial I/O clock input (6) Port P47 Pull-up control (7) Ports P52 , P53 Pull-up control Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch Direction register Data bus Port latch Serial I/O ready output Real time control bit Real time port data Fig. 11 Port block diagram (1) 1-15 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (8) Ports P54 , P56 Pull-up control (9) Ports P55 , P57 Pull-up control Direction register Direction register Data bus Port latch Data bus Pulse output mode Timer output CNTR0 interrupt input P54 only (10) Port P6 Pull-up control (11) Port P70 Direction register Direction register Data bus Port latch Data bus Port latch CNTR1 interrupt input A-D trigger interrupt input Port latch A-D conversion input Analog input pin selection bit (12) Ports P71 –P77 Port selection/Pull-up control (13) Port P80 Direction register Data bus Port latch Port selection/Pull-up control Port XC switch bit Direction register Data bus (14) Port P81 Port selection/Pull-up control Port XC switch bit Direction register Data bus Port latch Oscillation circuit Port P81 Port XC switch bit Port latch (15) COM0–COM3 VL3 Sub-clock generating circuit input (16) SEG0 –SEG17 VL2/VL3 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. VL2 VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS VL1/VSS Fig. 12 Port block diagram (2) 1-16 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts occur by seventeen sources: eight external, eight internal, and one software. Interrupt Operation When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. Notes on Use When the active edge of an external interrupt (INT0–INT3, CNTR0, or CNTR 1 ) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. Table 6. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 INT3 Key input (Key-on wake up) ADT 16 A-D conversion BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16 At completion of A-D conversion At BRK instruction execution Priority 1 2 3 4 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected 5 6 7 8 9 10 11 12 13 14 15 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an “L” level is applied) Valid when ADT interrupt is selected External interrupt (Valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. 1-17 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A 16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (return “0” when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C 16 ) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D 16 ) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F 16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers 1-18 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-on Wake Up) A Key-on wake up interrupt request is generated by applying “L” level to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 9, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXx "L" level output PULL register A Bit 2 = "1" Port P2 7 direction register = "1" VV Key input interrupt request V Port P27 latch P27 output V Port P26 direction register = "1" VV Port P26 latch P26 output V Port P25 direction register = "1" VV Port P25 latch P25 output V Port P24 direction register = "1" VV Port P24 latch P24 output V Port P23 direction register = "0" VV P23 input Port P23 latch Port P2 Input reading circuit V Port P22 direction register = "0" VV P22 input Port P22 latch V Port P21 direction register = "0" VV P21 input Port P21 latch V Port P20 direction register = "0" VV P20 input Port P20 latch V P-channel transistor for pull-up V V CMOS output buffer Fig. 15 Connection example when using key input interrupt and port P2 block diagram 1-19 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 3825 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Real time port control bit “1” P52 QD P52 data for real time port Latch P52 direction register “0” P52 latch Real time port control bit “1” QD P53 P53 direction register “0” P53 latch Latch Data bus P53 data for real time port Real time port control bit “0” “1” Timer X mode register write signal Timer X write control bit Timer X (high) latch (8) Timer X (high) (8) f(XIN )/16 (f(XIN )/16 in low-speed mode V) CNTR0 active edge switch bit “0” Timer X operating mode bit “00”,“01”,“11” Timer X stop control bit Timer X (low) latch (8) Timer X (low) (8) P54 /CNTR0 “10” “1” Pulse width measurement mode CNTR0 active edge switch bit “0” “1” P54 direction register P54 latch Pulse output mode Timer X interrupt request CNTR0 interrupt request Pulse output mode QS T Q Rising edge detection Falling edge detection Period measurement mode Timer Y operating mode bit “00”,“01”,“10” Pulse width HL continuously measurement mode CNTR1 interrupt request “11” P55 /CNTR1 CNTR1 active edge switch bit “0” “1” f(XIN )/16 (f(XCIN )! 16 in low-speed mode V) Timer Y stop control bit “00”,“01”,“11” Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (high) latch (8) Timer Y (high) (8) “10” Timer Y operating mode bit Timer Y interrupt request f(X IN )/16 (f(XCIN )!16 in low-speed mode V) Timer 1 count source selection bit “0” Timer 1 latch (8) XCIN Timer 1 (8) “1” Timer 2 count source selection bit Timer 2 latch (8) “0” Timer 2 (8) “1” f(XIN)/16 (f(XCIN )!16 in low-speed modeV) Timer 2 write control bit Timer 1 interrupt request Timer 2 interrupt request TOUT output active edge switch bit “0” P56/TOUT TOUT output control bit QS Timer 3 latch (8) Timer 3 (8) “1” Timer 3 count source selection bit T “1” Q P56 latch P56 direction register TOUT output control bit f(XIN )/16(f(XCIN )/16 in low-speed mode V) “0” Timer 3 interrupt request VInternal clock φ = XCIN /2. Fig. 16 Timer block diagram 1-20 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Pulse output mode Each time the timer underflows, a signal output from the CNTR 0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode. Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode. If CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P5 4 direction register to input mode. Note on CNTR0 Interrupt Active Edge Selection CNTR0 interrupt active edge depends on the CNTR 0 active edge switch bit. Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 a nd P5 3 e ach time the timer X underflows. While the real time port function is valid. (However, if the real time port control bit is changed from “0” to “1”, data are output without the timer X.) If the data for the real time port is changed, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. b7 b0 Timer X mode register (TXM : address 0027 16) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Fig. 17 Structure of timer X mode register 1-21 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Period measurement mode CNTR 1 i nterrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down/Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 p in input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Pulse width HL continuously measurement mode CNTR 1 i nterrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. b7 b0 Timer Y mode register (TYM : address 0028 16) Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Fig. 18 Structure of timer Y mode register Note on CNTR1 Interrupt Active Edge Selection CNTR1 interrupt active edge depends on the CNTR 1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 i nterrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 1-22 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. b7 b0 Timer 123 mode register (T123M :address 0029 16) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT output control bit 0 : T OUT output disabled 1 : T OUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) 1 : f(XCIN ) Not used (return “0” when read) Note : Internal clock φ is f(XCIN)/2 in the low-speed mode. Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Timer 2 Output Control When the timer 2 (T OUT) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the output mode. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 19 Structure of timer 123 mode register 1-23 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816). Data bus Address 0018 16 Receive buffer Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD Receive shift register Shift clock P46/SCLK f(XIN ) BRG count source selection bit 1/4 Serial I/O synchronization clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C 16 Falling-edge detector Clock control circuit P47 /SRDY F/F Shift clock P45 /TXD Transmit shift register Transmit buffer register (TB) Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 0019 16 Serial I/O status register Address 0018 16 Data bus Fig. 20 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output T XD Serial input R XD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal S RDY Write signal to receive/transmit buffer register (address 0018 16) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the T XD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 21 Operation of clock synchronous serial I/O function 1-24 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 0018 16 Receive buffer OE Character length selection bit 7 bits STdetector Receive shift register 8 bits Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P44 /RXD PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O synchronization clock selection bit P46/SCLK BRG count source selection bit 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 ST/SP/PA generator f(XIN ) 1/16 P45 /TXD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 0019 16 Transmit shift register Address 0018 16 Data bus Fig. 22 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output T XD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 VGenerated TSC=1V SP at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=1 Serial input R XD ST D0 D1 SP ST D0 RBF=0 RBF=1 D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 23 Operation of UART serial I/O function 1-25 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O Control Register (SIOCON) 001A16 The serial I/O control register contains eight control bits for the serial I/O function. UART Control Register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin. Serial I/O Status Register (SIOSTS) 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer/Receive Buffer Register (TB/ RB) 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. Baud Rate Generator (BRG) 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 1-26 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O status register (SIOSTS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns “1” when read) b7 b0 Serial I/O control register (SIOCON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN ) 1: f(XIN )/4 Serial I/O synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44 –P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44 –P47 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45 /TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) Fig. 24 Structure of serial I/O control registers 1-27 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The functional blocks of the A-D converter are described below. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500kHz during A-D conversion. Use a clock divided the main clock XIN as the internal clock φ. A-D Conversion Register (AD) 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. A-D Control Register (ADCON) 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the AD conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. b7 b0 A-D control register (ADCON : address 0034 16) Analog input pin selection bits 0 0 0 : P60 /AN0 0 0 1 : P61 /AN1 0 1 0 : P62 /AN2 0 1 1 : P63 /AN3 1 0 0 : P64 /AN4 1 0 1 : P65 /AN5 1 1 0 : P66 /AN6 1 1 1 : P67 /AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : OFF 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input falling Not used (returns “0” when read) Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages. Channel Selector The channel selector selects one of the input ports P6 7/AN7–P60/ AN0. Fig. 25 Structure of A-D control register Data bus b7 A-D control register P57/ADT 3 b0 A-D control circuit P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVSS VREF ADT/A-D interrupt request Channel selector Comparator A-D conversion register 8 Resistor ladder Fig. 26 A-D converter block diagram 1-28 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD DRIVE CONTROL CIRCUIT The 3825 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. LCD display RAM Segment output enable register LCD mode register Selector Timing controller Common driver Segment driver Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, • • • • • • • • the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 7. Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits b7 b0 Segment output enable register (SEG : address 0038 16) Segment output enable bit 0 0 : Output ports P3 0 –P35 1 : Segment output SEG 18–SEG23 Segment output enable bit 1 0 : Output ports P3 6 , P37 1 : Segment output SEG 24,SEG25 Segment output enable bit 2 0 : Output ports P0 0 –P05 1 : Segment output SEG 26–SEG31 Segment output enable bit 3 0 : Output ports P0 6 ,P07 1 : Segment output SEG 32,SEG33 Segment output enable bit 4 0 : Output port P1 0 1 : Segment output SEG 34 Segment output enable bit 5 0 : Output ports P1 1 –P15 1 : Segment output SEG 35–SEG39 Not used (return “0” when read) (Do not write “1” to this bit) b7 b0 LCD mode register (LM : address 0039 16) Duty ratio selection bits 0 0 : Not used 0 1 : 2 duty (use COM 0 , COM1 ) 1 0 : 3 duty (use COM 0 –COM2 ) 1 1 : 4 duty (use COM 0 –COM3 ) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disable 1 : Voltage multiplier enable LCD circuit divider division ratio selection bits 0 0 : Clock input 0 1 : 2 division of Clock input 1 0 : 4 division of Clock input 1 1 : 8 division of Clock input LCDCK count source selection bit (Note) 0 : f(XCIN )/32 1 : f(XIN )/8192 Note : LCDCK is a clock for a LCD timing controller. Fig. 27 Structure of segment output enable register and LCD mode register 1-29 Fig. 28 Block diagram of LCD controller/driver 1-30 LCD enable bit Address 0053 16 LCD display RAM LCD circuit divider division ratio selection bits 2 Voltage multiplier control bit Bias control bit LCD divider 2 Duty ratio selection bits LCDCK count source selection bit “1” f(XIN )/ 256 f(X CIN ) “0” Selector Selector Timing controller LCDCK Level shift Level shift Bias control Level Shift Level Shift Level Shift Level Shift Segment Segment driver driver Common driver Common driver Common driver Common driver Data bus Address 0040 16 Address 0041 16 Selector Selector Selector Selector Level shift Level shift Level shift Level shift Segment Segment Segment Segment driver driver driver driver MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SEG0 SEG1 SEG2 SEG3 P30/SEG18 P14/SEG38 P15/SEG39 VSS VL1 VL2 VL3 C1 C2 COM0 COM1 COM2 COM3 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE MULTIPLIER (3 TIMES) The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin V L1. (However, when using a 1/2 bias, connect VL1 and VL2 and apply voltage by external resistor division.) When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.3 V to the VL1 pin. When not using the voltage multiplier, apply proper voltage to the LCD power input pins (VL1–VL3). The voltage multiplier control bit (bit 4 of the LCD mode register) controls the voltage multiplier. Table 8. Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD 1/2 bias Note 1 : VLCD i s the maximum value of supplied voltage for the LCD panel. Table 9. Duty ratio control and common pins used Duty ratio 2 Duty ratio selection bit Bit 1 0 1 1 Bit 0 1 0 1 Common pins used COM0, COM1 (Note 1) COM0–COM2 (Note 2) COM0–COM3 Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–VL3), apply the voltage shown in Table 3 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). 3 4 Notes 1 : COM2 and COM3 are open 2 : COM3 is open Common Pin and Duty Ratio Control The common pins (COM0–COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). Contrast control Contrast control VL3 VL2 C2 C1 VL1 VL3 R1 VL2 C2 C1 VL1 R3 Open R2 Open VL3 R4 VL2 C2 C1 VL1 R5 Open Open R1=R2=R3 1/3 bias when using the voltage multiplier 1/3 bias when not using the voltage multiplier 1/2 bias R4=R5 Fig. 29 Example of circuit at each bias 1-31 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK)= (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) duty ratio Frame frequency= Bit 7 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG1 SEG0 SEG3 SEG2 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG39 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38 6 5 4 3 2 1 0 Fig. 30 LCD display RAM map 1-32 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2=VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 31 LCD drive waveform (1/2 bias) 1-33 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2 VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 32 LCD drive waveform (1/3 bias) 1-34 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK OUTPUT FUNCTION Input/output ports P40 and P41 can output clock. The input/output ports and clock output function are put under double function controlled by the clock output control register (address 002A16). Selection of Output Clock Frequency Bit 2 (output clock frequency selection bit) of the clock output control register selects an output clock frequency. When setting the output clock frequency selection bit to “0”, port P40 becomes the frequency of f(XIN ) and port P41 becomes the frequency of f(XIN)/5. At this time, the output pulse of port P40 depends on the XIN input pulse, while the output pulse of port P4 1 has duty ratio of about 40%. When setting the output clock frequency selection bit to “1”, port P40 becomes the frequency of f(XIN)/2 and port P41 becomes the frequency of f(XIN)/10. At this time, the output pulses of both ports P40 and P41 have duty ratio of 50%. Selection of Input/Output Ports and Clock Output Function Bits 0 and 1 of the clock output control register can select between the input/output ports and the clock output function. When selecting the clock output function, clock are output while the direction register of ports P40 and P41 are set to output. At the next cycle of rewriting the clock output control bit, P40 i s switched between the port output and the clock output. In synchronization with the fall of the clock (resulting from dividing XIN by 5) on rewriting the clock output control bit, P41 is switched between the port output and the clock output. b7 b0 Clock output control register (TCON : address 002A 16) P40 clock output control bit 0 : I/O port 1 : Clock output P41 clock output control bit 0 : I/O port 1 : Clock output Output clock frequency selection bit 0 : P4 0←f(XIN ), P41←f(XIN )/5 1 : P4 0←f(XIN )/2, P41 ←f(X IN )/10 Not used (return “0” when read) Fig. 33 Structure of clock output control register P40 port latch “0” XIN “0” “1” Output clock frequency selection bit “1” P40 direction register P40 clock output control bit P40 1/2 P41 port latch “0” 1/5 “0” “1” Output clock frequency selection bit “1” P41 direction register P41 clock output control bit P41 1/2 Fig. 34 Clock output function block diagram 1-35 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.5 V and 5.5 V, and the oscillation should be stable), reset is released. In order to give the XIN clock time to stabilize, internal operation does not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(XIN)/16) are complete. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for VCC of 2.5 V (Extended operating temperature version: the reset input voltage is less than 0.6V for VCC of 3.0V). Address ( 1 ) Port P0 ( 2 ) Port P1 0 0 0 0 16 0 0 0 2 16 Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 ( 3 ) Port P1 output control register 0 0 0 3 16 ( 4 ) Port P2 ( 5 ) Port P2 direction register ( 6 ) Port P3 ( 7 ) Port P4 ( 8 ) Port P4 direction register ( 9 ) Port P5 (10) Port P5 direction register (11) Port P6 (12) Port P6 direction register (13) Port P7 (14) Port P7 direction register (15) Port P8 (16) Port P8 direction register 0 0 0 4 16 0 0 0 5 16 0 0 0 6 16 0 0 0 8 16 0 0 0 9 16 0 0 0 A 16 0 0 0 B 16 0 0 0 C 16 0 0 0 D 16 0 0 0 E 16 000F 16 0 0 1 0 16 0 0 1 1 16 0 0 1 6 16 0 0 1 7 16 Power on Power source voltage 0V Reset input voltage 0V (Note) (17) PULL register A (18) PULL register B (19) Serial I/O status register (20) Serial I/O control register RESET VCC 0 0 1 9 16 1 0 0 0 0 0 0 0 0 0 1 A 16 0016 0.2VCC (21) UART control register (22) Timer X (low) (23) Timer X (high) (24) Timer Y (low) 0 0 1 B 16 1 1 1 0 0 0 0 0 0 0 2 0 16 0 0 2 1 16 0 0 2 2 16 0 0 2 3 16 0 0 2 4 16 0 0 2 5 16 0 0 2 6 16 0 0 2 7 16 0 0 2 8 16 0 0 2 9 16 0 0 2 A 16 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0016 Note. Reset release voltage : VCC = 2.5V (Extended operating temperature version : 3.0V) RESET VCC Power source voltage detection circuit (25) Timer Y (high) (26) Timer 1 (27) Timer 2 (28) Timer 3 (29) Timer X mode register (30) Timer Y mode register (31) Timer 123 mode register (32) Clock output control register (33) A-D control register 0 0 3 4 16 0 0 0 0 1 0 0 0 0 0 3 8 16 0 0 3 9 16 0 0 3 A 16 0016 0016 0016 Fig. 35 Example of reset circuit (34) Segment output enable register (35) LCD mode register (36) Interrupt edge selection register (37) CPU mode register (38) Interrupt request register 1 (39) Interrupt request register 2 (40) Interrupt control register 1 (41) Interrupt control register 2 (42) Processor status register (43) Program counter 0 0 3 B 16 0 1 0 0 1 0 0 0 0 0 3 C 16 0 0 3 D 16 0 0 3 E 16 003F 16 0016 0016 0016 0016 (PS) ! ! ! ! ! 1 ! ! (PCH) (PCL) Contents of address FFFD Contents of address FFFC 16 16 Note : The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ! : Undefined Fig. 36 Internal state of microcomputer immediately after reset 1-36 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN φ RESET Internal reset Reset address from vector table Address Data ? ? ? ? FFFC ADL FFFD ADH, ADL ADH SYNC Notes 1 : XIN and φ are in the relationship : f(XIN ) = 8 • f(φ) Notes 2 : A question mark (?) indicates an undefined status that depens on the previous status. XIN : about 8200 clock cycles Fig. 37 Reset sequence 1-37 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 3825 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the X OUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and X CIN a nd X COUT p ins function as I/O ports. The pull-up resistor of XCIN and X COUT pins must be made invalid to use the sub-clock. Oscillation Control Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either X IN o r X CIN d ivided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ i s not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Frequency Control Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of XIN. Low-speed mode The internal clock φ is half the frequency of XCIN. A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN a nd X CIN o scillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN)>3f(XCIN). • • XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT CIN COUT Fig. 38 Ceramic resonator circuit XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT Open External oscillation circuit VCC VSS Fig. 39 External clock input circuit 1-38 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT “1” “0” Port XC switch bit XIN XOUT Internal system clock selection bit (Note) Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” Timer 2 “1” Low-speed mode “1” 1/2 “0” Middle-/High-speed mode 1/4 1/2 Main clock division ratio selection bit Middle-speed mode Timing φ (Internal clock) High-speed mode or Low-speed mode Main clock stop bit Q S R WIT instruction S R Q Q S STP instruction STP instruction R Reset Interrupt disable flag I Interrupt request Note : When using the low-speed mode, set the port X C switch bit to “1” . Fig. 40 Clock generating circuit block diagram 1-39 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Middle-speed mode (f(φ) =1 MHz) CM7=0(8 MHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM6 “1” High-speed mode (f(φ) =4 MHz) “0” CM7 =0(8 MHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =0(32 kHz stopped) CM ” “1 M6 C ” “1 4 “0 ” “0 ” CM4 “1” “0 ” Middle-speed mode (f(φ) =1 MHz) CM7=0(8 MHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM6 “1” High-speed mode (f(φ) =4 MHz) “0” CM7 =0(8 MHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating) “0” Low-speed mode (f(φ) =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM7 “1” CM6 “1” Low-speed mode (f(φ) =16 kHz) “0” CM7 =1(32 kHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating) CM 7 “1” “0” CM 4 “1” C “0 M4 ” CM “1 ”6 “1 ” “0” “0” b7 b4 CPU mode register (CPUM : address 003B 16) CM ” “1 M6 C ” “1 5 “0 ” “ 0” “1 ” C “0 M5 ” CM 6 “0” “0” CM5 “1” ” “0 ” Low-speed mode (f(φ) =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) CM6 “1” Low-speed mode (f(φ) =16 kHz) “0” CM7=1(32 kHz selected) CM6=0(High-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle-/highspeed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock. Fig. 41 State transitions of internal clock φ 1-40 CM 5 “1” “1 CM4 : Port Xc switch bit 0: I/O port 1: XCIN , XCOUT CM5 : Main clock (XIN –XOUT ) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN )/2 (high-speed mode) 1: f(XIN )/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN –XOUT selected (middle-/high-speed mode) 1: XCIN –XCOUT selected (low-speed mode) MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the T XD pin after transmission is completed. Interrupt The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 1-41 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 10. Programming adapter Package 100P6S-A 100P6D-A 100D0 Name of Programming Adapter PCA4738F-100A PCA4738G-100 PCA4738L-100A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 36 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 42 Programming and testing of One Time PROM version 1-42 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Table 11. Absolute maximum ratings Symbol VCC VI VI VI VI VI VI VI VO VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P80, P81 Input voltage P70–P77 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 Output voltage P00–P07, P10–P15, P30–P37 Output voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 Output voltage VL3 Output voltage VL2, SEG0–SEG17 Output voltage XOUT Power dissipation Operating temperature Storage temperature At output port At segment output Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 7.0 –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V V V V V V V V V mW °C °C All voltages are based on VSS. Output transistors are cut off. Ta = 25°C RECOMMENDED OPERATING CONDITIONS Table 12. Recommended operating conditions (1) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.) Symbol Parameter High-speed mode f(XIN) = 8 MHz Middle-speed mode f(XIN) = 8 MHz Low-speed mode Min. 4.0 2.5 2.5 2.0 0 AVSS 0.7 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0 0 0 0 VCC VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC Limits Typ. 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 VCC Unit VCC VSS VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL Power source voltage V V V V V V V V V V V V V Power source voltage A-D conversion reference voltage Analog power source voltage Analog input voltage AN0–AN7 “H” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56, P60–P67, P70–P77, P80, P81 (CM4=0) “H” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57, “H” input voltage RESET “H” input voltage XIN “L” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56, P60–P67, P70–P77, P80, P81 (CM4=0) “L” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57 “L” input voltage RESET “L” input voltage XIN 1-43 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13. Recommended operating conditions (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) f(XIN) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current Parameter P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P40–P47,P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P40–P47,P50–P57, P60–P67, P80, P81 (Note 1) P71–P77 (Note 1) P00–P07,P10–P17, P20–P27, P30–P37 (Note 1) P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) Limits Min. Typ. Max. –20 –20 20 20 40 –10 –10 10 10 20 –0.5 –5.0 5.0 10 –0.1 –2.5 2.5 5.0 4.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz “L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1) “L” total average output current P71–P77 (Note 1) “H” peak output current “H” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P70–P77, P80, P81 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 3) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 3) (4.0 V ≤ VCC ≤ 5.5 V) (VCC ≤ 4.0 V) High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode Input frequency for timers X and Y (duty cycle 50%) Main clock input oscillation frequency (Note 4) (2!VCC) MHz –4 8.0 (4!VCC) –8 8.0 32.768 50 MHz MHz MHz kHz f(XCIN) Sub-clock input oscillation frequency (Note 4, 5) Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50%. 5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 1-44 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 14. Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter Test conditions IOH = –0.1 mA IOH = –25 µA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH “H” input current “H” input current Hysteresis Hysteresis Hysteresis “H” input current INT0–INT3, ADT, CNTR0, CNTR1, P20–P27 SCLK, RXD RESET P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P70–P77, P80, P81 RESET XIN 0.5 0.5 0.5 5.0 5.0 4.0 –5.0 –30 –6 –70 –25 –140 –45 –5.0 VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pull-downs “on” Output transistors “off” VCC = 3.0 V, VO = VCC, Pull-downs “on” Output transistors “off” VO = VCC, Pull-downs “off” Output transistors “off” VO = VSS, Pull-downs “off” Output transistors “off” –5.0 –4.0 30 6.0 70 25 140 45 5.0 –5.0 Min. VCC–2.0 VCC–1.0 VCC–2.0 VCC–0.5 VCC–1.0 2.0 0.5 1.0 2.0 0.5 1.0 Limits Typ. Max. Unit V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA µA VOH “H” output voltage P00–P07, P10–P15, P30–P37 VOH “H” output voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) VOL “L” output voltage P00–P07, P10–P15, P30–P37 VOL “L” output voltage P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) RESET: VCC=2.5 V to 5.5 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 3 V, VI = VSS Pull-ups “on” “L” input current IIL P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 IIL IIL IIL ILOAD “L” input current “L” input current “L” input current P70 RESET XIN Output load current P00–P07, P10–P15, P30–P37 ILEAK Output leak current P00–P07, P10–P15, P30–P37 Note 1: When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P8 0 is different from the value above mentioned. 1-45 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 15. Electrical characteristics (2) (VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” VL1 IL1 Power source voltage Power source current (VL1) (Note) Ta = 25 °C Ta = 85 °C 1.3 1.8 3.0 10 Min. 2.0 Limits Typ. Max. 5.5 Unit V 6.4 13 mA 1.6 3.2 mA 25 36 µA ICC Power source current 7.0 14.0 µA 15 22 µA 4.5 9.0 µA 0.1 1.0 10 2.3 6.0 50 µA V µA When using voltage multiplier VL1 = 1.8 V VL1 < 1.3 V Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. 1-46 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS Table 16. A-D converter characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.) Symbol – – tCONV RLADDER IVREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference input current Analog port input current Test conditions Min. Limits Typ. Max. 8 ±2 12.5 (Note) 12 VREF = 5 V 50 35 150 100 200 5.0 Unit Bits LSB µs kΩ µA µA VCC = VREF = 5 V f(XIN) = 8 MHz Note : When an internal trigger is used in middle-speed mode, it is 14 µs. 1-47 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 Table 17. Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. TIMING REQUIREMENTS 2 Table 18. Timing requirements 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 45 40 500/ (VCC–2) 250/ (VCC–2)–20 250/ (VCC–2)–20 230 230 2000 950 950 400 200 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. 1-48 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS 1 Table 19. Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.) Symbol twH(SCLK) twL(SCLK) td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. tc(SCLK)/2–30 tc(SCLK)/2–30 140 –30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns 10 10 Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 2 Table 20. Switching characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.) Symbol twH(SCLK) twL(SCLK) td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Min. tc(SCLK)/2–50 tc(SCLK)/2–50 –30 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns 350 20 20 Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. 1-49 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS (Extended Operating Temperature Version) Table 21. Absolute maximum ratings (Extended operating temperature version) Symbol VCC VI VI VI VI VI VI VI VO VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P80, P81 Input voltage P70–P77 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 Output voltage P00–P07, P10–P15, P30–P37 Output voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77 P80, P81 Output voltage VL3 Output voltage VL2, SEG0–SEG17 Output voltage XOUT Power dissipation Operating temperature Storage temperature At output port At segment output Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 7.0 –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VL3 Ta = 25°C –0.3 to VCC +0.3 300 –40 to 85 –65 to 150 Unit V V V V V V V V V V V V V V V mW °C °C All voltages are based on VSS. Output transistors are cut off. RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version) Table 22. Recommended operating conditions (Extended operating temperature version) (1) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.) Symbol Parameter High-speed mode f(XIN)=8 MHz Middle-speed mode Ta = –20 to 85°C f(XIN) = 8 MHz Ta = –40 to –20°C Low-speed mode VSS VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL Power source voltage A-D conversion reference voltage Analog power source voltage Analog input voltage AN0–AN7 “H” input voltage “H” input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage “L” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56, P60–P67, P70–P77, P80, P81 (CM4=0) P20–P27, P42–P44, P46, P50, P51, P54, P55, P57 RESET XIN P16, P17, P40, P41, P45, P47, P52, P53, P56, P60–P67, P70–P77, P80, P81 (CM4=0) P20–P27, P42–P44, P46, P50, P51, P54, P55, P57 RESET XIN Ta = –20 to 85°C Ta = –40 to –20°C Min. 4.0 2.5 3.0 2.5 3.0 2.0 0 AVSS 0.7 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0 0 0 0 VCC VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC Limits Typ. 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 VCC V V V V V V V V V V V V Unit VCC Power source voltage 1-50 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 23. Recommended operating conditions (Extended operating temperature version) (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current Parameter P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P40–P47,P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) Limits Min. Typ. Max. –20 –20 20 20 40 –10 –10 10 10 20 –0.5 –5.0 5.0 10 –0.1 –2.5 2.5 5.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA P40–P47,P50–P57, P60–P67, P80, P81 (Note 1) P71–P77 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P40–P47, P50–P57, P60–P67, P70–P71, P80, P81 (Note 1) “L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1) “L” total average output current P71–P77 (Note 1) “H” peak output current P00–P07, P10–P15, P30–P37 (Note 2) “H” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current “H” average output current “H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 2) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 3) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 3) (4.0 V ≤ VCC ≤ 5.5 V) Input frequency for timers X and Y (duty cycle 50%) (VCC ≤ 4.0 V) High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) MHz 4.0 (2!VCC)–4 MHz 8.0 MHz f(XIN) Main clock input oscillation frequency (Note 4) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 32.768 (4!VCC)–8 MHz 8.0 50 MHz kHz f(XCIN) Sub-clock input oscillation frequency (Note 4, 5) Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current is an average value measured over 100 ms. 4 : When the oscillation frequency has a duty cycle of 50%. 5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 1-51 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version) Table 24. Electrical characteristics (Extended operating temperature version) (1) (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5V, Ta = –40 to –20°C, unless otherwise noted) Symbol Parameter Test conditions IOH = –2.5 mA IOH = –0.6 mA VCC = 3.0 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 3.0 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 3.0 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 3.0 V Min. VCC–2.0 VCC–0.9 VCC–2.0 VCC–0.5 VCC–0.9 2.0 0.5 1.1 2.0 0.5 1.1 0.5 0.5 0.5 5.0 5.0 –5.0 Limits Typ. Max. Unit V V V V V V V V V V V V V V µA µA µA µA –30 –6 –70 –25 –140 –45 –5.0 VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pull-downs “on” Output transistors “off” VCC = 3.0 V, VO = VCC, Pull-downs “on” Output transistors “off” VO = VCC, Pull-downs “off” Output transistors “off” VO = VSS, Pull-downs “off” Output transistors “off” –4.0 30 6.0 70 25 170 55 5.0 –5.0 –5.0 µA µA µA µA µA µA µA µA µA VOH “H” output voltage P00–P07, P10–P15, P30–P37 VOH “H” output voltage P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) VOL “L” output voltage P00–P07, P10–P15, P30–P37 VOL “L” output voltage P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P71–P77, P80, P81 (Note 1) Hysteresis Hysteresis Hysteresis “H” input current INT0–INT3, ADT, CNTR0, CNTR1, P20–P27 SCLK, RXD RESET P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P70–P77, P80, P81 RESET XIN VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH RESET: VCC=2.5 V to 5.5 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 3 V, VI = VSS Pull-ups “on” “H” input current “H” input current 4.0 “L” input current IIL P16, P17, P20–P27,P40–P47, P50–P57, P60–P67, P70–P77, P80, P81 IIL IIL IIL ILOAD “L” input current “L” input current “L” input current P70 RESET XIN Output load current P00–P07, P10–P15, P30–P37 ILEAK Output leak current P00–P07, P10–P15, P30–P37 Note 1: When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P8 0 is different from the value above mentioned. 1-52 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 25. Electrical characteristics (Extended operating temperature version) (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” VL1 IL1 Power source voltage Power source current (VL1) (Note) Ta = 25°C Ta = 85°C 1.3 1.8 3.0 10 Min. 2.0 Limits Typ. Max. 5.5 Unit V 6.4 13 mA 1.6 3.2 mA 25 36 µA ICC Power source current 7.0 14 µA 15 22 µA 4.5 9.0 µA 0.1 1.0 10 2.3 6.0 50 µA V µA When using voltage multiplier VL1 = 1.8 V VL1 < 1.3 V Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. A-D CONVERTER CHARACTERISTICS Table 26. A-D converter characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.) Symbol – – tCONV RLADDER IVREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference input current Analog iinput current Test conditions Min. Limits Typ. Max. 8 VCC = VREF = 5 V f(XIN) = 8 MHz 12 VREF = 5 V 50 12.5 (Note) 35 150 100 200 5.0 ±2 Unit Bits LSB µs kΩ µA µA Note : When an internal trigger is used in middle-speed mode, it is 14 µs. 1-53 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 (Extended Operating Temperature Version) Table 27. Timing reguirements 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. TIMING REQUIREMENTS 2 (Extended Operating Temperature Version) Table 28. Timing reguirements 2 (Extended operating temperature version) (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Limits Typ. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 2 125 45 40 500/ (VCC–2) 250/ (VCC–2)–20 250/ (VCC–2)–20 230 230 2000 950 950 400 200 Max. Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. 1-54 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version) Table 29. Switching characteristics 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.) Symbol twH(SCLK) twL(SCLK) td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. tc(SCLK)/2–30 tc(SCLK)/2–30 140 –30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns 10 10 Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version) Table 30. Switching characteristics 2 (Extended operating temperature version) (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.) Symbol twH(SCLK) twL(SCLK) td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Min. tc(SCLK)/2–50 tc(SCLK)/2–50 –30 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns 350 20 20 Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. Measurement output pin 100 pF Measurement output pin 100 pF 1 kΩ CMOS output N-channel open-drain output (Note) Note : When bit 4 of the UART control register (address 001B 16) is “1”. (N-channel open-drain output mode) Fig. 43 Circuit for measuring output switching characteristics 1-55 MITSUBISHI MICROCOMPUTERS 3825 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAM tC(CNTR) tWH(CNTR) CNTR 0, CNTR 1 0.8VCC 0.2VCC tWL(CNTR) tWH(INT) INT0–INT3 0.8VCC 0.2VCC tWL(INT) tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN ) tWH(XIN) XIN 0.8VCC 0.2VCC tWL(XIN) tC(SCLK) tf SCLK 0.2VCC tWL(SCLK) tr 0.8VCC tWH(SCLK) tsu(RXD-SCLK ) RX D td(SCLK -TXD) TXD 0.8VCC 0.2VCC th(SCLK -RXD) tv(SCLK-TXD) Fig. 44 Timing diagram 1-56 CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 I/O pins Interrupts Timer X and timer Y Timer 1, timer 2, and timer 3 2.5 Serial I/O 2.6 A-D converter 2.7 LCD drive control circuit 2.8 Standby function 2.9 Reset 2.10 Oscillation circuit APPLICATION 2.1 I/O pins 2.1 I/O pins 2.1.1 I/O ports (1) I/O port write and read s The input-only ports and programmable I/O ports set for the input mode The input-only ports and the programmable I/O ports set for the input mode are floating. The value (pin state) input to the port is read by reading the port register corresponding to each port. In writing data into the port register corresponding to each port, the data is only written to the port register but the pin remains in the floating state. s Output-only ports and programmable I/O ports set for the output mode The value written to the port register corresponding to an output port or a programmable I/O port set for the output mode is output externally through a transistor. In reading the data of the port transistor corresponding to each port, the pin state is not read but the value written to the port register is read. Accordingly, even if the output “H” voltage is reduced or the output “L” voltage is increased by external load, the previous output value is correctly read. At output : •An output value is set by writing to the port register. •Reading a port register is possible. At input : •Writing to a port register is possible. •A pin state is read by reading the port register. “H” level output Port direction register (“1”) Port direction register V (“0”) Port register Port register (at writing) “L” level output Port register (at reading) Read the pin state V : The P- and N-channel transistors are cut off. Fig. 2.1.1 I/O port write and read 2–2 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins Table 2.1.1 shows the memory allocation of the port registers corresponding to each port. Table 2.1.1 Memory allocation of port registers Port P0 P1 P2 P3 P4 P5 P6 P7 P8 Port register address 0000 16 0002 16 0004 16 0006 16 0008 16 000A16 000C 16 000E16 0010 16 (2) Input/output switching of programmable I/O ports Input/output switching of the programmable I/O ports is performed by the port direction register corresponding to each port (Note). Figure 2.1.2 shows the structure of the port Pi (i = 2, 4 to 8) direction register, and Table 2.1.2 shows the memory allocation of the port direction registers corresponding to each port. Figure 2.1.4 shows a port direction register setting example. Note: F or ports P1 6 a nd P1 7 , input/output switching is performed by the port P1 output control register. Figure 2.1.3 shows the structure of the P1 output control register. Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 2, 4 to 8) [Address 05 16, 0916, 0B 16, 0D 16, 0F 16, 11 16] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi 0 input mode 1 : Port Pi 0 output mode 0 : Port Pi 1 input mode 1 : Port Pi 1 output mode 0 : Port Pi 2 input mode 1 : Port Pi 2 output mode 0 : Port Pi 3 input mode 1 : Port Pi 3 output mode 0 : Port Pi 4 input mode 1 : Port Pi 4 output mode 0 : Port Pi 5 input mode 1 : Port Pi 5 output mode 0 : Port Pi 6 input mode 1 : Port Pi 6 output mode 0 : Port Pi 7 input mode 1 : Port Pi 7 output mode At reset 0 RW × × × × × × × × 0 0 0 0 0 0 0 Notes 1: Nothing is allocated bit 0 of port P7 direction register and bit 2 to bit 7 of port P8 direction register. 2: The contents of the port Pi direction register cannot be read out (refer to “2.1.4 Notes on use” ). Fig. 2.1.2 Structure of port Pi (i = 2, 4 to 8) direction register 3825 GROUP USER’S MANUAL 2–3 APPLICATION 2.1 I/O pins Port P1 output control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 output control register (P1C) [Address 0316] B Name 0 Ports P10–P15 output control bit Functions 0 : Output function is invalid 1 : Output function is valid At reset R W 0 × 1 Nothing is allocated. These bits cannot be written to to and be read out. 5 6 7 Port P1 6 direction register Port P1 7 direction register 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 ×× 0 0 × × Fig. 2.1.3 Structure of port P1 output control register Table 2.1.2 Memory allocation of port direction registers Port Port direction register address 000316 ( Note) P16, P1 7 0005 16 P2 0009 16 P4 000B16 P5 000D 16 P6 000F16 P7 001116 P8 Note: At address 0003 16, the port P1 output control register is allocated. b7 Example : When setting “6B 16” 0 1 1 0 10 1 b0 1 to the port P2 direction register Input/output direction of port P2 P27 P26 P25 P24 P23 P22 P21 P20 Input Output Output Input Output Input Output Output Fig. 2.1.4 Port direction register setting example 2–4 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins (3) Output port control, pull-up control and pull-down control The port output function of ports P0, P1 0–P1 5, and P3 can be invalidated by software. The output function of ports P0 and P3 is invalidated by setting bit 0 of the PULL register A (address 001616 ) to “1.” At this time, ports P0 and P3 are pulled down internally, so that their pin level becomes “L.” The output function of ports P1 0 –P1 5 i s invalidated by setting bit 0 of the port P1 output control register (address 0003 16), so that their pin state is put into floating state. At this time, setting of the PULL register A becomes valid. The ports shown in Table 2.1.3 are controlled for pull-up and pull-down by software. Either pull-up or pull-down is controlled by the PULL register A (address 0016 16 ) and the PULL register B (address 001716). Figure 2.1.5 shows the structure of the PULL register A and Figure 2.1.6 shows the structure of the PULL register B. Table 2.1.3 I/O ports which either pull-up or pulldown is controlled by software Control Pull-down Pull-up Ports P0, P1 0–P1 5, P3 P1 6 , P17 , P2, P4–P6, P7 1–P7 7, P8 Port P1 output control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 output control register (P1C) [Address 0316] B Name 0 Ports P1 0–P15 output control bit Functions 0 : Output function is invalid 1 : Output function is valid At reset R W 0 × 1 Nothing is allocated. These bits cannot be written to to and be read out. 5 6 7 Port P1 6 direction register Port P1 7 direction register 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 ×× 0 0 × × Fig. 2.1.5 Structure of port P1 output control register 3825 GROUP USER’S MANUAL 2–5 APPLICATION 2.1 I/O pins PULL register A b7 b6 b5 b4 b3 b2 b1 b0 PULL register A (PULLA) [Address 1616] B Functions Name 0 P0, P1 0–P15, P3 pull-down 0 : No pull-down (P0, P3 output function is valid) 1 : Pull-down (P0, P3 output function is invalid) 1 P16, P1 7 pull-up 2 3 4 5 6, 7 0 : No pull-up 1 : Pull-up 0 : No pull-up P20–P2 7 pull-up 1 : Pull-up 0 : No pull-up P80, P8 1 pull-up 1 : Pull-up 0 : No pull-up P40–P4 3 pull-up 1 : Pull-up 0 : No pull-up P44–P4 7 pull-up 1 : Pull-up Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. At reset R W 1 0 0 0 0 0 0 0× Note: For ports set for the output mode, pull-up or pull-down is impossible (except ports P0 and P3). Fig. 2.1.6 Structure of PULL register A PULL register B b7 b6 b5 b4 b3 b2 b1 b0 PULL register B (PULLB) [Address 1716] B Name 0 P50–P5 3 pull-up 1 2 3 4 5 P54–P5 7 pull-up P60–P6 3 pull-up P64–P6 7 pull-up P71–P7 3 pull-up P74–P7 7 pull-up Functions 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up At reset R W 0 0 0 0 0 0 0 0× 6, Nothing is allocated. These bits cannot be written 7 to and are fixed to “0” at reading. Note: For ports set for the output mode, pull-up is impossible. Fig. 2.1.7 Structure of PULL register B 2–6 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins 2.1.2 Function pins Each function pin except I/O ports is described below. (1) Pins VCC a nd VSS f(X IN) MHz Power source input pins. In the high-speed mode, apply ( + 2) V–5.5 V to the V CC p in. 4 In the middle-speed mode or the low-speed mode, apply 2.5 V–5.5 V to the V CC p in. When Ta = –40 °C to –20 °C, use the extended operating temperature version, and apply 3.0 V–5.5 V to the V CC p in. In all modes, apply 0 V to the V SS p in. (2) VREF p in The reference voltage input pin for the A-D converter. Apply 2 V–VCC t o the V REF p in. (3) AVSS p in The GND input pin for the A-D converter. Apply the same voltage as that applied to the V SS p in to the AV SS p in. (4) Pins VL1 , V L2 a nd V L3 Power source input pins for LCD. Apply 0 ≤ VL1 ≤ VL2 ≤ V L3 ≤ V CC of voltage to these pins. And apply 0 V–VL 3 o f voltage to LCD. (5) Pins X IN a nd XOUT An input pin and an output pin for the main clock generating circuit. (6) RESET pin The 3825 group is reset internally by keeping the level of this pin at “L” for 2 µs or more. Reset state is released by returning the level of this pin to “H”. (7) Pins C 1 a nd C 2 External capacitor pins for a built-in voltage multiplier (3 times) of LCD. (8) Pins SEG0 t o SEG 17 Segment signal output pins for LCD. (9) Pins COM 0 t o COM 3 Common signal output pins for LCD. 3825 GROUP USER’S MANUAL 2–7 APPLICATION 2.1 I/O pins 2.1.3 Application examples The basic structure for key input without a pull-up resistor and an application examples of it are described below. In contrast to a method which uses a pull-up resistor, dissipating current incessantly, this method requires only a charging current for a very small capacitance, so it is especially suitable for a battery-driven unit. In the following description, ports A, B, C and D are only tentative names and differ from the real port names. (1) Basic structure for key input Figure 2.1.8 shows a connection example 1 for key input without a pull-up resistor and Figure 2.1.9 shows the key input control procedure 1. Figure 2.1.10 shows a timing diagram 1 where switch A is pressed. CMOS I/O port A CMOS I/O port B CMOS I/O port C Virtual capacitor (C) SW A SW B SW C r = 10 kΩ Fig. 2.1.8 Connection example 1 for key input V1 Key input V1 In the case of no key input, output “L” (Noise countermeasure). V2 Output “H” for charging to each port V2 A virtual capacitor (C) is charged by outputting “H.” (For capacitance, refer to the next page.) V3 Set the port direction register for input mode with an instruction immediately after “H” is output. (For the limit timer for ON/OFF judgment and the discharging time at ON, refer to the next page.) V4 For double reading to ensure data, repeat V2 and V3. After inputting data into the port direction register, judge ON/OFF of key input. V3 V4 Fig. 2.1.9 Key input control procedure 1 2–8 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins Œ  Charge time Ž T t2   Charge time t2 “H” output ‘ ’ CMOS I/O port A “L” output “H” output Input Read port state Input Read port state CMOS I/O port B “L” output “H” output Input t1 “H” output Input CMOS I/O port C “L” output “H” output Input “H” output Input Fig. 2.1.10 Timing diagram 1 where switch A is pressed The discharging time ( Ž ,  ) after completion of charge in Figure 2.1.10 is shown with the following expression. The discharging time (T) is obtained with T = CR. qThe capacitance of the virtual capacitor (C) is: Capacitance of microcomputer output transistors and input transistors ... Approx. 10 pF Capacitance of package pin ............................................................................. Several pF + Capacitance of each key wiring ....................................................................... Several pF (minimum) Approx. 10 pF q In the leak current standard at 5 V, the maximum value is 5 µA and the standard value is 0.05 µA. Accordingly, the minimum resistance (R) is 1 M Ω a nd the standard resistance is 100 M Ω. In the above condition, the discharging time (T) is obtained as follows: T (minimum) = 10 pF ! 1 M Ω = 1 0 ! 1 0 -12 ! 1 ! 1 0 6 = 1 0 ! 1 0 -6 ( s) T (standard) = 10 pF ! 1 00 M Ω = 1 0 ! 1 0 -12 ! 1 00 ! 1 0 6 = 1 ! 1 0 -3 ( s) Accordingly, the discharging time (T) is 10 µ s (minimum) to 1 ms (standard). 3825 GROUP USER’S MANUAL 2–9 APPLICATION 2.1 I/O pins TThe discharging time (t 2) at ON is obtained with t = Cr in the same way as the previous page, with the result of t = 100 ns. TJudge ON/OFF of key input within the time (t 1) which is obtained as follows: After the completion of “H” output, V t1 = V O ! e–t1/T t 1 = – T ! 1 n Vt1 VO VO : “ H” output voltage Vt1 : I nput voltage after t 1(s) The standard time at V O = 5 .0 V, V t1 = 3 .5 V t 1 = – 1 ! 1 0 –3 ! 1 n 3.5 5.0 ≈ 3 57 µ s (2) Key input application example According to the key input without a pull-up resistor described in (1), an effective application example where there are enough ports is shown below. This method reduces both current dissipation and quantity of parts compared with the example shown in (1). Figure 2.1.11 shows a connection example 2 for key input using port D and Figure 2.1.12 shows the key input control procedure 2. Figure 2.1.13 shows a timing diagram 2 where switch A is pressed. CMOS I/O port A CMOS I/O port B CMOS I/O port C CMOS I/O port D SW A SW B SW C Virtual capacitor (C) Fig. 2.1.11 Connection example 2 for key input V1 Key input V1 In the case of no key input, output “L” (Noise countermeasure). V2 Output “H” for charging to each port V3 V2 A virtual capacitor (C) is charged by outputting “H.” (For capacitance, refer to the previous page.) V3 Set the port direction register for input mode with an instruction immediately after “H” is output. V4 Output “L” with the next instruction (refer to “Figure 2.1.13 (A)” ) V5 For double reading to ensure data, repeat V2, V3 and V4. Set the port direction register for the input mode V4 After inputting “L” from the port D, judge ON/OFF of key input. V5 Fig. 2.1.12 Key input control procedure 2 2–10 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins (A) (A) Œ  Charge time t2 Ž T   Charge time ‘ ’ t2 “H” output CMOS I/O port A “L” output “H” output Input Read port state “H” output t1 Input Read port state Input CMOS I/O port B “L” output “H” output Input CMOS I/O port C “L” output “H” output Input “H” output Input CMOS I/O port D “L” output “H” output “L” output “H” output “L” output Fig. 2.1.13 Timing diagram 2 where switch A is pressed With the exception that “L” is output using port D for key input (refer to “Figure 2.1.13 (A)”), the basic structure is the same as that shown in (1). The examples shown in (1) and (2) are already put into practical use. However, be sure to evaluate them on the user’s side. In this example, the ports are the same structure as the equivalent circuit which a pull-up resistor of about 1 k is connected. 3825 GROUP USER’S MANUAL 2–11 APPLICATION 2.1 I/O pins 2.1.4 Notes on use When using I/O ports, note the following. (1) Reading the port direction register The value of the port direction register is not readable. The following cannot be used: • the data transfer instruction (LDA , etc.) • the operation instruction when the index X mode flag (T) is “1” • the addressing mode which uses the value of a direction register as an index • the bit-test instruction (BBC o r B BS , etc.) to a direction register • the read-modify-write instruction (ROR , C LB , or S EB , etc.) to a direction register Use instructions such as L DM a nd S TA , etc., to set the port direction registers. (2) When the data register (port latch) of an I/O port is modified with the bit managing instruction When the data register (port latch) of an I/O port is modified with the bit managing instruction V1, the value of the unspecified bit may be changed. REASON The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the data register of an I/O port, the following is executed to all bits of the data register. q As for a bit which is set for an input port: The pin state is read in the CPU, and is written to this bit after bit managing. q As for a bit which is set for an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: qEven when a port which is set as an output port is changed for an input port, its data register holds the output data. qAs for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents V1 bit managing instructions : S EB a nd C LB i nstruction (3) Pull-up control and pull-down control To pull-up or pull-down ports by software, note the following. qWhen ports P0 and P3 are pulled-down, output function of ports P0 and P3 is invalid. qTo pull-down ports P10–P15, set bit 0 of the port P1 output control register to “0” for invalidating the output function. When the output function is valid, the setting of bit 0 of the PULL register A is invalid (pull-down is impossible). qWhen ports P0, P10–P1 5 and P3 are used as segment output pins for LCD, the settings of bit 0 of the PULL register A are invalid (pull-down is impossible). q When ports P1 6 , P1 7 , P2, P4–P6 and P8 are set for the output mode, the settings of the bits corresponding to these ports of the PULL register A and PULL register B are invalid (pull-up or pulldown are impossible). 2–12 3825 GROUP USER’S MANUAL APPLICATION 2.1 I/O pins (4) Notes in standby state In standby state V2 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”, especially for I/O ports of the P-channel and the N-channel open-drain. Pull-up (connect the port to V CC) or pull-down (connect the port to V SS) these ports through a resistor. When determining a resistance value, note the following points: q External circuit q Variation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor as an option, note on varied current values. q When setting as an input port : Fix its input level q When setting as an output port : Prevent current from flowing out to external REASON Even when setting as an output port with its direction register, in the following state: q P-channel......when the content of the data register (port latch) is “0” q N-channel......when the content of the data register (port latch) is “1” the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are “undefined”. This may cause power source current. V 2 standby state : the stop mode by executing the S TP i nstruction the wait mode by executing the WIT i nstruction 3825 GROUP USER’S MANUAL 2–13 APPLICATION 2.1 I/O pins (5) Termination of unused pins Table 2.1.4 shows termination of unused pins. Table 2.1.4 Termination of unused pins Pins P1 6, P1 7 P2 0–P27 P4 0 / f (X IN) / f(X IN )/2 P41 / f(XIN)/5 / f(XIN)/10 P4 4/RxD P4 5/TxD P4 6/S CLK P4 7/SRDY P5 2/RTP0 P5 3/RTP1 P5 4/CNTR 0 P5 5/CNTR 1 P5 6/T OUT P5 7/ADT P6 0/AN0–P67/AN7 P7 1–P77 P8 0/XCOUT P8 1/XCIN P7 0 P4 2/INT 0 P4 3/INT 1 P5 0/INT 2 P5 1/INT 3 VL1–VL3 COM0–COM3 SEG0–SEG17 P00/SEG26–P07/SEG33 P10/SEG35–P15/SEG39 P30/SEG18–P37/SEG25 C 1, C 2 Terminations ŒAfter set for the input mode and put the built-in pull-up resistor in the ON state, open. V1 Set for the output mode and open at “L” or “H.”V2 Connect each pin to V CC o r VSS t hrough each resistor of 1 k to 10 k . ŒAfter disabling INT interrupts, set for the input mode, and put the built-in pull-up resistor in the ON state, open. V1 Set for the output mode and open at “L” or “H.”V2 Connect to VSS l evel Open V1 After reset and before the built-in pull-up (pull-down) resistor is put in the ON state by software, the built-in pull-up (pull-down) resistor is in the OFF state. Because of this, the potential at these pins are “undefined” and the power source current may increase. Since the direction register setup may be changed for the output mode because of a program runaway or noise, set direction register for the input mode periodically. And make the length of wiring which is connected I/O ports within 2 cm. V2 After reset and before I/O ports are switched for the output mode by software, I/O ports are set for the input mode. Because of this, the potential at these pins are “undefined” and the power source current may increase in the input mode. Since the direction register setup may be changed for the input mode because of a program runaway or noise, set direction register for the output mode periodically. And make the length of wiring which is connected I/O ports within 2 cm. 2–14 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts 2.2 Interrupts 2.2.1 Explanation of operations When an interrupt request is accepted, the contents immediately before acceptance of the interrupt requests of the following registers is automatically pushed onto the stack area in the order of Œ,  a nd Ž. Œ High-order (PCH ) contents of program counter  Low-order (PCL) contents of program counter Ž Contents of processor status register (PS) After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. When the R TI i nstruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of Ž,  and Œ a nd the processing executed immediately before acceptance of the interrupts is continued. Figure 2.2.1 shows an interrupt operation diagram. Executing routine ······· Interrupt occurs (Accepting interrupt request) Suspended operation Contents of program counter (high-order) are pushed onto stack Contents of program counter (low-order) are pushed onto stack Contents of processor status register are pushed onto stack Interrupt processing routine RTI instruction Contents of processor status register are poped from stack Contents of program counter (low-order) are poped from stack Contents of program counter (high-order) are poped from stack Resume processing ······· : Operation commanded by software : Internal operation to be performed automatically Fig. 2.2.1 Interrupt operation diagram 3825 GROUP USER’S MANUAL 2–15 APPLICATION 2.2 Interrupts (1) Interrupt request generating conditions Table 2.2.1 shows interrupt sources and interrupt request generating conditions. The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1.” When the following conditions are satisfied in this state, the interrupt request is accepted. For details, refer to “ 2.2.2 Control ”. ŒInterrupt disable flag = “0” (interrupts enabled) Interrupt enable bit = “1” (interrupts enabled) Table 2.2.1 Interrupt sources and interrupt request generating conditions Interrupt sources Interrupt request generating conditions Reference At detection of either rising or falling edge of INT 0 input 2.2.4 INT interrupts INT0 (Active edge selectable) At detection of either rising or falling edge of INT 1 input INT1 (Active edge selectable) At completion of serial I/O data reception Serial I/O receive At completion of serial I/O transmit shift or when transmit 2.5 Serial I/O1 Serial I/O transmit buffer register is empty At timer X underflow Timer X 2.3 Timer X and timer Y At timer Y underflow Timer Y At timer 2 underflow Timer 2 2.4 Timer 1, timer 2, and timer 3 At timer 3 underflow Timer 3 At detection of either rising or falling edge of CNTR 0 CNTR0 input (Active edge selectable) 2.3 Timer X and timer Y At detection of either rising or falling edge of CNTR 1 CNTR1 input (Active edge selectable) Timer 1 At timer 1 underflow 2.4 Timer 1, timer 2, and timer 3 INT2 At detection of either rising or falling edge of INT 2 input (Active edge selectable) INT3 At detection of either rising or falling edge of INT 3 input 2.2.4 INT interrupts (Active edge selectable) At falling of conjunction of input level for port P2 (at Key input 2.2.5 Key input interrupt input mode) (Key-on wake up) At detection of falling edge of ADT input ADT 2.6 A-D converter A-D conversion At completion of A-D conversion BRK instruction At BRK instruction execution SERIES 740 USER’S MANUAL 2–16 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts (2) Processing upon acceptance of an interrupt request Upon acceptance of an interrupt request, the following operations are automatically performed. Œ The processing being executed is stopped.  The contents of the program counter and the processor status register are pushed onto the stack area. Figure 2.2.2 shows changes of the stack pointer and the program counter upon acceptance of an interrupt request. Ž Concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. After the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to “0.” The interrupt disable flag is set to “1” so that multiple interrupts are disabled. Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. Program counter PCL Program counter (high-order) PCH Program counter (low-order) Stack pointer S (S) Interrupt request is accepted Program counter PCL PCH Vector address (from Interrupt vector area) Stack pointer S (S) – 3 Interrupt disable flag = “1” (s) – 3 Interrupt disable flag = “0” (S) Stack area Stack area Processor status register Program counter (low-order) (S) Program counter (high-order) Fig. 2.2.2 Changes of stack pointer and program counter upon acceptance of interrupt request 3825 GROUP USER’S MANUAL 2–17 APPLICATION 2.2 Interrupts (3) Timing after acceptance of an interrupt request The interrupt processing routine is started at the timing of machine cycle after completion of the executing instruction. Figure 2.2.3 shows the processing time up to the execution of an interrupt processing routine and Figure 2.2.4 shows timing after the acceptance of an interrupt request. Interrupt request occurs Interrupt operation starts V V Main routine Waiting time for pipeline postprocessing Push onto stack Vector fetch Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (At internal system clock φ = 3.15 MHz, 2.2 µ s to 7.3 µ s) V : Refer to “Figure 2.2.4” Fig. 2.2.3 Processing time up to execution of interrupt processing routine Waiting time for pipeline postprocessing Push onto stack Vector fetch Interrupt operation starts φ SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH PCL PS SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt (Note) SPS : “0016” or “0116” Note: Refer to “Table 7 in CHAPTER 1 HARDWARE .” Fig. 2.2.4 Timing after acceptance of interrupt request 2–18 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts 2.2.2 Control For interrupts except the B RK i nstruction interrupt, the acceptance of interrupt can be controlled by an interrupt request bit, an interrupt enable bit, and an interrupt disable flag. In this section, control of interrupts except the BRK instruction interrupt is described and Figure 2.2.5 shows an interrupt control diagram. Interrupt request bit Interrupt enable bit Interrupt request Interrupt disable flag BRK instruction Reset Fig. 2.2.5 Interrupt control diagram An interrupt request bit, an interrupt enable bit and an interrupt disable flag function independently and do not affect each other. An interrupt is accepted when all the following conditions are satisfied. q Interrupt request bit — “1” q Interrupt enable bit — “1” q Interrupt disable flag — “0” Though the interrupt priority is determined by software, a variety of priority processing can be performed by software using the above bits and flag. Table 2.2.2 shows a list of interrupt bits for individual interrupt sources. (1) Interrupt request bits The interrupt request bits are allocated to the interrupt request register 1 (address 003C16 ) and interrupt request register 2 (address 003D 16). The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1.” The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt is accepted, this bit is automatically cleared to “0.” Each interrupt request bit can be set to “0” by software, but it cannot be set to “1” by software. 3825 GROUP USER’S MANUAL 2–19 APPLICATION 2.2 Interrupts (2) Interrupt enable bits The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F 16). The interrupt enable bits control the acceptance of the corresponding interrupt request. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1” and this interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the interrupt request bit remains in the “1” state. When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request occurs when this bit is “1,” this interrupt is accepted (at interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request. When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the C LI i nstruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,” so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the C LI instruction within the interrupt processing routine. Figure 2.2.6 shows an example of multiple interrupts. Table 2.2.2 List of interrupt bits for individual interrupt sources Interrupt request bit Interrupt sources Address Bit INT0 003C16 b0 003C16 INT1 b1 003C16 Serial I/O receive b2 003C16 Serial I/O transmit b3 003C16 Timer X b4 003C16 Timer Y b5 003C16 Timer 2 b6 003C16 Timer 3 b7 003D16 CNTR0 b0 003D16 CNTR1 b1 003D16 Timer 1 b2 003D16 b3 INT2 003D16 b4 INT3 Key input 003D16 b5 ADT/A-D conversion 003D16 b6 Interrupt enable bit Address 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 003F16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 2–20 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts Interrupt request Nesting Reset Time Main routine I=1 C1 = 0, C2 = 0 Interrupt request 1 C1 = 1 I=0 Interrupt 1 Interrupt request 2 I=1 C2 = 1 I=0 Interrupt 2 I=1 RTI I=0 Multipul interrupt RTI I=0 I : Interrupt disable flag C1 : Interrupt enable bit of interrupt 1 C2 : Interrupt enable bit of interrupt 2 : They are set automatically. : Set by software. Fig. 2.2.6 Example of multiple interrupts 3825 GROUP USER’S MANUAL 2–21 APPLICATION 2.2 Interrupts 2.2.3 Related registers Figure 2.2.7 shows memory allocation of interrupt-related registers. Each of these registers is described below. Address 003A 16 Interrupt edge selection register (INTEDGE) 003C 16 003D 16 003E 16 003F 16 Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.2.7 Memory allocation of interrupt-related registers (1) Interrupt edge selection register (INTEDGE) The interrupt edge selection register (address 003A16 ) selects an active edge of each INT interrupt. Bit 0 to bit 3 select active edges of INT 0 –INT 3 p ins inputs. In the “0” state, the falling edge ( ) o f the corresponding pin input is active. In the “1” state, the rising edge ( ) o f the corresponding pin input is active. Figure 2.2.8 shows the structure of the interrupt edge selection register. Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address 3A16] B 0 1 2 3 4 to 7 Functions 0 : Falling edge active INT 0 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT 1 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT 2 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT 3 interrupt edge 1 : Rising edge active selection bit Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. Name At reset R W 0 0 0 0 0 0× Fig. 2.2.8 Structure of interrupt edge selection register 2–22 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts (2) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16) indicate whether an interrupt request has occurred or not. Figure 2.2.9 shows the structure of the interrupt request register 1 and Figure 2.2.10 shows the structure of the interrupt request register 2. The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the interrupt enable bits (refer to the next item). Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 3C 16] B 0 1 2 3 4 5 6 7 Name INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 V V V V V V V V V : “0” can be set by software, but “1” cannot be set. Fig. 2.2.9 Structure of interrupt request register 1 3825 GROUP USER’S MANUAL 2–23 APPLICATION 2.2 Interrupts Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 3D 16] B 0 Name Functions At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 0× CNTR 0 interrupt request bit 1 CNTR 1 interrupt request bit 2 Timer 1 interrupt request bit 3 INT2 interrupt request bit 4 INT3 interrupt request bit 5 Key input interrupt request bit 6 ADT/A-D conversion interrupt request bit 7 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. V : “0” can be set by software, but “1” cannot be set. Fig. 2.2.10 Structure of interrupt request register 2 2–24 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts (3) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E 16) and the interrupt control register 2 (address 003F 16) control each interrupt request source. Figure 2.2.11 shows the structure of the interrupt control register 1 and Figure 2.2.12 shows the structure of the interrupt control register 2. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1,” and the interrupt request is not accepted. When an interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (at interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 3E16] B 0 1 2 Name INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 3 Serial I/O transmit interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit Timer 2 interrupt 6 enable bit 7 Timer 3 interrupt enable bit Fig. 2.2.11 Structure of interrupt control register 1 3825 GROUP USER’S MANUAL 2–25 APPLICATION 2.2 Interrupts Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 3F16 ] B 0 1 2 3 4 5 6 Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/A-D conversion interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 00 7 Fix this bit to “0.” Fig. 2.2.12 Structure of interrupt control register 2 2–26 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts (4) Processor status register The processor status register is an 8-bit register. Figure 2.2.13 shows the structure of the processor status register. Bit 2 related to an interrupt is described below. s Interrupt disable flag : bit 2 The interrupt disable flag controls the acceptance of interrupt requests except BRK instruction interrupt. When this flag is “1,” the acceptance of an interrupt request is disabled. When this flag is “0,” the acceptance of an interrupt request is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the C LI i nstruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,” so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the C LI instruction within the interrupt processing routine. Processor status register b7 b2 Undefined 1 b0 Undefined Processor status register (PS) B 0 1 2 3 4 5 6 7 Flag name C : Carry flag Z : Zero flag I : Interrupt disable flag D Decimal mode flag : B : Break flag T : Index X mode flag V : Overflow flag N : Negative flag b7 b0 indicates initial value immediately after reset Fig. 2.2.13 Structure of processor status register 3825 GROUP USER’S MANUAL 2–27 APPLICATION 2.2 Interrupts 2.2.4 INT interrupts The INT interrupt requests occur by detecting a level change of each INT pin (INT0 –INT 3). (1) Active edge selection As an active edge, falling edge ( ) d etection or rising edge ( ) detection can be selected by bits 0 to 3 of the interrupt edge selection register (address 003A 16 ). In the “0” state, the falling edge of the corresponding pin is detected. In the “1” state, the rising edge of the corresponding pin is detected. The pins INT 0 t o INT 3 a re also used as I/O ports P4 2 , P43, P5 0 , and P5 1, but no register to switch between INT pin and I/O port is available. When the port is an input port, the active edges of the port are always detected. Accordingly, when using ports P4 2 , P4 3, P5 0 a nd P5 1 a s input ports, put the corresponding INT interrupt into the disabled state. If this interrupt is not disabled, an INT interrupt is caused by pin level change, so that the program runs away. Figure 2.2.14 shows the structure of the interrupt edge selection register. Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address 3A16] B Name Functions 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset R W 0 0 0 0 0 0× 0 INT0 interrupt edge selection bit 1 INT1 interrupt edge selection bit 2 INT2 interrupt edge selection bit 3 INT3 interrupt edge selection bit 4 Nothing is allocated. These bits cannot be to written to and are fixed to “0” at reading. 7 Fig. 2.2.14 Structure of interrupt edge selection register 2–28 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts 2.2.5 Key input interrupt The Key input interrupt request occurs when an “L” level voltage is applied to the pin set for the input mode of the port P2. For interrupt sources except the INT interrupts and the Key input interrupt, refer to “ CHAPTER 1” . (1) Connection example when the Key input interrupt is used When using the Key input interrupt, after set ports P20 to P23 for the input mode, configure an “L” level valid key-matrix. Figure 2.2.15 shows a connection example when the key input interrupt is used, and a port P2 block diagram. In the connection example in Figure 2.2.15, an Key input interrupt request is caused by pressing the key corresponding to one of ports P20 t o P2 3. Port PXx “L” level output PULL register A, b2 = “1” V1 P27 output V1 P26 output V1 P25 output V1 P24 output V1 P23 input V1 P22 input V1 P21 input V1 P20 input V2 V2 V2 V2 V2 V2 V2 V2 Port P27 Port P2 direction register, b7 = “1” latch Port P26 Port P2 direction register, b6 = “1” latch Port P25 Port P2 direction register, b5 = “1” latch Port P24 Port P2 direction register, b4 = “1” latch Port P23 Port P2 direction register, b3 = “0” latch Port P2 input reading circuit Port P22 Port P2 direction register, b2 = “0” latch Port P21 Port P2 direction register, b1 = “0” latch Port P20 Port P2 direction register, b0 = “0” latch V1: P-channel transistor for pull-up V2: CMOS output buffer Key input interrupt request Fig. 2.2.15 Connection example when key input interrupt is used, and port P2 block diagram 3825 GROUP USER’S MANUAL 2–29 APPLICATION 2.2 Interrupts (2) Set values of Key input interrupt-related registers When using the Key input interrupt, set the following: q Port P2 direction register (address 0005 16) q Bit 2 of PULL register A (address 0016 16 ) q Bit 5 of interrupt request register 2 (address 003D 16 ) = “0” q Bit 5 of interrupt control register 2 (address 003F 16) (Note) = “1” Figure 2.2.16 shows the setting values (corresponding to Figure 2.2.15) of the Key input interruptrelated registers. Note: F ix bit 7 of the interrupt control register 2 (address 003F 16) to “0”. b7 b0 1 1 1 1 0 0 0 0 Port P2 direction register [Address 0516] Bits corresponding to P20–P27 0 : Input port 1 : Output port b7 1 b0 PULL register A [Address 1616] P20–P27 pull-up 0 : No pull-up 1 : Pull-up b7 0 b0 Interrupt request register 2 [Address 3D16] Key input interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 0 1 b0 Interrupt control register 2 [Address 3F16] Key input interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled : “0” or “1.” Fig. 2.2.16 Setting values (corresponding to Figure 2.2.15) of key input interrupt-related registers 2–30 3825 GROUP USER’S MANUAL APPLICATION 2.2 Interrupts 2.2.6 Notes on use When using interrupts, note the following. (1) Register setting s Fix bit 7 of the interrupt control register 2 (address 003F16) to “0.” Nothing is allocated for this bit, however, do not write “1” to it. sWhen using I/O ports P42, P43, P50 and P51 as input ports, put the INT interrupts corresponding to each port into the disabled state. s When the active edges of the following interrupts are switched, the corresponding interrupt request bit may be set to “1.” To avoid accepting an interrupt request, we recommend the register setting example shown in Figure 2.2.17. qINT 0 i nterrupt to INT 3 i nterrupt qCNTR 0 i nterrupt and CNTR 1 i nterrupt Œ Set the corresponding interrupt enable bit to “0”  Set the interrupt active edge Ž Set the corresponding interrupt request bit to “0”  Set the corresponding interrupt enable bit to “1” Fig. 2.2.17 Register setting example 3825 GROUP USER’S MANUAL 2–31 APPLICATION 2.3 Timer X and timer Y 2.3 Timer X and timer Y 2.3.1 Explanation of timer X operations Timer X has 4 modes of operation. Operation in each mode is described below. (1) Timer mode Operation in the timer mode is described below. ŒStart of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the timer X counter (referred as “the X counter”) is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “00 16.” At this time, the value of the timer X latch (referred as “the X latch”) is transferred (reloaded) to the X counter. ŽInterrupt operation An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the X counter initial value + 1” count of the rising edge of the count source. Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.1 shows a timer mode operation example. 2–32 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Count period Count period T(s) = 1 ÷ count source frequency ! (the X counter initial value + 1) Timer mode operation example •UF : Underflow •RL : Reload •n : The X counter initial value Timer X stop control bit Count source Writing “1” Writing “0” Value of timer X counter RL n16 UF RL RL RL Count stop Count restart UF UF UF 000016 T Time Timer X interrupt request bit 1 Timer X interrupt enable bit 1 : •Clearing by writing “0” to the timer X interrupt request bit. •Clearing by accepting the timer X interrupt request when the timer X interrupt enable bit is “1.” 1 1 1 Fig. 2.3.1 Timer mode operation example 3825 GROUP USER’S MANUAL 2–33 APPLICATION 2.3 Timer X and timer Y (2) Pulse output mode The operation in the pulse output mode is the same as that in the timer mode, besides, which is added a pulse output operation. In this mode, a pulse whose polarity is reversed at every the X counter underflow is output from the P54 /CNTR0 p in. Operation in the pulse output mode is described below. ŒStart of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the X counter is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “00 16.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ŽPulse output A pulse whose polarity is reversed every the X counter underflow is output from the P54/CNTR0 pin. As a level at a start of pulse output, a “H” or “L” is selected by the CNTR 0 a ctive edge switch bit. At the time when the pulse output mode is selected by the timer X operating mode bits, a pulse output is started. Interrupt operation s Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. s Edge of pulse output At the edge of the pulse output from the P5 4/CNTR0 p in, an interrupt request occurs. At the same time, the CNTR0 i nterrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR0 i nterrupt enable bit. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 0 a ctive edge switch bit. Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.2 shows a pulse output mode operation example. 2–34 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Count period Count period T(s) = 1 ÷ count source frequency ! (the X counter initial value + 1) Pulse output mode operation example •UF : Underflow •RL : Reload •n : The X counter initial value Timer X stop control bit Count source Value of timer X counter RL n16 UF RL RL RL Count stop Count restart UF UF UF Writing “1” Writing “0” 000016 Select pulse output mode P54/CNTR0 pin Programmable I/O port CNTR0 active edge switch bit CNTR0 interrupt request bit 1 CNTR0 interrupt enable bit Timer X interrupt request bit 1 Timer X interrupt enable bit T Time 1 1 1 1 1 : •Clearing by writing “0” to the timer X interrupt request bit or the CNTR 0 interrupt request bit. •Clearing by accepting the timer X interrupt request and the CNTR 0 interrupt request when the respective interrupt enable bits are “1.” V : When the CNTR 0 active edge switch bit is “1” ; •The reverse-polarity pulse of above pulse is output. •The CNTR 0 interrupt request occurs at the rising edge of the output pulse. Fig. 2.3.2 Pulse output mode operation example 3825 GROUP USER’S MANUAL 2–35 APPLICATION 2.3 Timer X and timer Y (3) Event counter mode The operation in the event counter mode is the same as that in the timer mode except that the input signal to the P5 4 /CNTR 0 p in is used as a count source. Operation in the event counter mode is described below. ŒStart of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the X counter is decremented by 1 each time a count source is input. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 0 a ctive edge switch bit. Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “00 16.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ŽInterrupt operation s Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. s Edge of count source At the edge of the count source input from the P54/CNTR0 p in, an interrupt request occurs. At the same time, the CNTR0 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 0 i nterrupt enable bit. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 0 a ctive edge switch bit. Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.3 shows an event counter mode operation example. 2–36 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Count period Count period T(s) = 1 ÷ count source frequency ! (the X counter initial value + 1) Event counter mode operation example •UF •RL •n : Underflow : Reload : The X counter initial value Writing “1” Writing “0” Timer X stop control bit Count source (P54/CNTR0 pin) Value of timer X counter RL n16 UF RL RL RL Count stop Count restart UF UF UF 000016 Time CNTR0 active edge switch bit CNTR0 interrupt request bit 1 CNTR0 interrupt enable bit Timer X interrupt request bit 1 Timer X interrupt enable bit 1 : •Clearing by writing “0” to the timer X interrupt request bit or the CNTR 0 interrupt request bit. •Clearing by accepting the timer X interrupt request and the CNTR 0 interrupt request when the respective interrupt enable bits are “1.” V : When the CNTR0 active edge switch bit is “1” ; •Falling edge of the count source is valid. •The CNTR 0 interrupt request occurs at the rising edge of the output pulse. 1 1 1 1 1 1 1 CNTR0 interrupt request occurs at falling edge of the count source Fig. 2.3.3 Event counter mode operation example 3825 GROUP USER’S MANUAL 2–37 APPLICATION 2.3 Timer X and timer Y (4) Pulse width measurement mode In the pulse width measurement mode, the width (“H” or “L” level) of a pulse input from the P5 4/CNTR0 pin is measured. Operation in the pulse width measurement mode is described below. ŒCount operation Immediately after reset, the timer X stop control bit is in the “0” state. In this state, a count operation is continued in the period in which the measurement level is input to the P5 4/CNTR 0 p in. The value of the X counter is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “00 16.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ŽPulse width measurement As a pulse measurement period, a “H” or “L” is selected by the CNTR 0 a ctive edge switch bit. The difference between the initial value of the X counter and the X counter value at counter stop is a measured pulse width. A reload operation by reading the count value is not performed automatically. Accordingly, to continue the measurement, set the initial value anew by software. When reading a value from the timer X, read both registers in order of the timer X (high–order) and the timer X (low–order). Interrupt operation s Edge of pulse measured At the edge of the pulse input from the P54/CNTR 0 p in, an interrupt request occurs. At the same time, the CNTR0 i nterrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR0 i nterrupt enable bit. The CNTR0 active edge switch bit specifies an active edge. When “H” level width is measured, the falling edge ( ) is active, when “L” level width is measured, the rising edge ( ) is active. s Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by using the timer X interrupt enable bit. Figure 2.3.4 shows a pulse width measurement mode operation example. 2–38 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Pulse width Pulse width H(s) = 1 ÷ count source frequency ! (the X counter initial value – the X counter value at count stop) Pulse width measurement mode operation example •n : The X counter initial value •m: The X counter value at count stop Timer X stop coutrol bit Count source P54/CNTR0 pin CNTR0 active edge switch bit Value of timer X counter Set initial value to counter 2 Count start Set initial value to counter 2 Count start n16 Count stop m16 000016 H CNTR0 interrupt request bit CNTR0 interrupt enable bit Timer X interrupt request bit Timer X interrupt enable bit 1 : •Clearing by writing “0” to the CNTR 0 interrupt request bit. •Clearing by accepting the CNTR 0 interrupt request when the CNTR 0 interrupt enable bit is “1.” 2 : Set initial value to the timer X when timer X write control bit is “0.” V : When the CNTR0 active edge switch bit is “1” ; •“L” level width of the input pulse is measured. •The CNTR0 interrupt request occurs at the rising edge of the input pulse. 1 H Time Fig. 2.3.4 Pulse width measurement mode operation example 3825 GROUP USER’S MANUAL 2–39 APPLICATION 2.3 Timer X and timer Y (5) Real time port control The real time port control is the function which outputs preset data from the real time ports in synchronization with an underflow of the X counter. Table 2.3.1 shows real time ports and bits for storing data. This real time port control function is available in every mode. A data output from the real time port is started at setting the real time port control bit to “1” (when setting “1” to the real time port control bit of the timer X mode register, use the S EB instruction). When the data for real time port is rewritten, the rewritten values are output at the first underflow of the X counter after rewritting. Figure 2.3.5 shows a timer mode operation example with the real time port function. The real time port is also used as port P52 and P5 3 . When using the real time port, set the corresponding bit of the port P5 direction register (address 000B16) to “1” for the output mode. Table 2.3.1 Real time ports and bits for storing data Real time port RTP0 ( P52) RTP1 ( P53) Bit for storing data Bit 2 of timer X mode register Bit 3 of timer X mode register 2–40 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Timer mode operation example with real time port function •UF : Underflow •RL : Reload •n : The X counter initial value Timer X stop control bit Count source Value of timer X counter RL n16 UF RL RL RL UF UF UF 000016 Time 1 Real time port control bit Bit 2 of timer X mode register P52/RTP0 pin Programmable I/O port Bit 3 of timer X mode register P53/RTP1 pin Programmable I/O port 1 : In the case that following are set immediately after reset release, “0” is output from pins P52/RTP0 and P53/RTP1. •Set ports P52 and P53 for the output mode. •Set the real time port control bit to “1.” Rewrite Rewrite Rewrite Rewrite Rewrite Fig. 2.3.5 Timer mode operation example with real time port function 3825 GROUP USER’S MANUAL 2–41 APPLICATION 2.3 Timer X and timer Y 2.3.2 Explanation of timer Y operations Timer Y has 4 modes of operation. Operation in each mode is described below. (1) Timer Mode Operation in the timer mode is described below. ŒStart of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the timer Y counter (referred as “the Y counter”) is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). Reload operation The Y counter underflows at the first count pulse after the value of the Y counter reaches “0016.” At this time, the value of the timer Y latch (referred as “the Y latch”) is transferred (reloaded) to the Y counter. ŽInterrupt operation An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the Y counter initial value + 1” count of the rising edge of the count source. Stop of count operation By writing “1” to the timer Y stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer Y stop control bit. Figure 2.3.6 shows a timer mode operation example. 2–42 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Count period Count period T(s) = 1 ÷ count source frequency ! (the Y counter initial value + 1) Timer mode operation example •UF : Underflow •RL : Reload •n : The Y counter initial value Timer Y stop control bit Count source Writing “1” Writing “0” Value of timer Y counter RL n16 UF RL RL RL Count stop Count restart UF UF UF 000016 T Timer Y interrupt request bit 1 Timer Y interrupt enable bit 1 : •Clearing by writing “0” to the timer Y interrupt request bit. •Clearing by accepting the timer Y interrupt request when the timer Y interrupt enable bit is “1.” 1 1 1 Time Fig. 2.3.6 Timer mode operation example 3825 GROUP USER’S MANUAL 2–43 APPLICATION 2.3 Timer X and timer Y (2) Period measurement mode In the period measurement mode, the period of a pulse input from the P5 5/CNTR 1 p in is measured. Operation in the period measurement mode is described below. ŒStart of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). Reload operation At the edge of the pulse input from the P5 5 /CNTR 1 p in, the value of the Y latch is transferred (reloaded) to the Y counter. The count value immediately before reload is held until it is read out once after reload. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR1 a ctive edge switch bit. The value of the Y latch is also reloaded at the Y counter underflow. ŽPeriod measurement As a period measurement duration, the following is selected by the CNTR1 a ctive edge switch bit (bit 6) : Duration from the falling edge to the falling edge (bit 6 = “0”) Duration from the rising edge to the rising edge (bit 6 = “1”) The difference between the count value at an active edge input and that immediately before reload is a measured period. Interrupt operation s Edge of input pulse At the edge of the pulse input from the P5 5/CNTR 1 p in, an interrupt request occurs. At the same time, the CNTR1 i nterrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR1 i nterrupt enable bit. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 1 a ctive edge switch bit. s Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. Figure 2.3.7 shows a period measurement mode operation example. 2–44 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Pulse period Pulse period T(s) = 1 ÷ count source frequency ! (the Y counter initial value – the Y counter value immediately before reload ) Period measurement mode operation example •RL : Reload •n : The Y counter initial value •m : The Y counter value immediately before reload Timer Y stop control bit Count source P55/CNTR1 pin CNTR1 active edge switch bit Value of timer Y counter RL n16 RL RL m16 000016 T T Time CNTR1 interrupt request bit 1 CNTR1 interrupt enable bit Timer Y interrupt request bit Timer Y interrupt enable bit 1 : •Clearing by writing “0” to the CNTR 1 interrupt request bit. •Clearing by accepting the CNTR 1 interrupt request when the CNTR 1 interrupt enable bit is “1.” V : When the CNTR1 active edge switch bit is “1” ; •From the rising edge to the rising edge of the input pulse is measured. •The CNTR1 interrupt request occurs at the rising edge of the input pulse. 1 1 Fig. 2.3.7 Period measurement mode operation example 3825 GROUP USER’S MANUAL 2–45 APPLICATION 2.3 Timer X and timer Y (3) Event counter mode The operation in the event counter mode is the same as that in the timer mode except that the input signal to the P5 5 /CNTR 1 p in is used as a count source. Operation in the event counter mode is described below. ŒStart of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 1 a ctive edge switch bit. Reload operation The Y counter underflows at the first count pulse after the value of the Y counter reaches “00 16.” At this time, the value of the Y latch is transferred (reloaded) to the Y counter. ŽInterrupt operation s Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. s Edge of count source At the edge of the count source input from the P55/CNTR1 p in, an interrupt request occurs. At the same time, the CNTR1 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 1 i nterrupt enable bit. As an active edge, the falling edge ( ) o r rising edge ( ) is specified by the CNTR 1 a ctive edge switch bit. Stop of count operation By writing “1” in the timer Y stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set in the timer Y stop control bit. Figure 2.3.8 shows an event counter mode operation example. 2–46 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Count period Count period T(s) = 1 ÷ count source frequency ! (the Y counter initial value + 1) Event counter mode operation example •UF •RL •n : Underflow : Reload : The Y counter initial value Writing “1” Writing “0” Timer Y stop control bit Count source (P55/CNTR1 pin) Value of timer Y counter RL n16 UF RL RL RL Count stop Count restart UF UF UF 000016 T CNTR1 active edge switch bit CNTR1 interrupt request bit 1 CNTR1 interrupt enable bit Timer Y interrupt request bit 1 Timer Y interrupt enable bit 1 : •Clearing by writing “0” to the timer Y interrupt request bit or the CNTR 1 interrupt request bit. •Clearing by accepting the timer Y interrupt request and the CNTR 1 interrupt request when the respective interrupt enable bits are “1.” V : When the CNTR1 active edge switch bit is “1” ; •Falling edge of the count source is valid. •The CNTR1 interrupt request occurs at the rising edge of the output pulse. 1 1 1 1 1 1 1 Time CNTR0 interrupt request occurs at falling edge of the count source Fig. 2.3.8 Event counter mode operation example 3825 GROUP USER’S MANUAL 2–47 APPLICATION 2.3 Timer X and timer Y (4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the width (“H” and “L” level) of pulses input from the P5 5/CNTR 1 p in are continuously measured. With the exception that reload and an interrupt request occur at both edges of pulses input from the P55/CNTR1 pin, the operation in the pulse width HL continuously measurement mode is the same as that in the period measurement mode. The pulse width HL continuously measurement mode of operation is described below. ŒStart of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. The count source is f(XIN)/16 (low-speed mode ; f(X CIN)/16). Reload operation At both edges of the pulse input from the P55 /CNTR 1 p in, the value of the timer Y is transferred (reloaded) to the Y counter. The count value immediately before reload is held until it is read out once after reload. The value of the Y latch is also reloaded at the Y counter underflow. ŽPulse width measurement The difference between the count value at an active edge input and that immediately before reload is a measured pulse width. When reading a value from the timer Y, read both registers in order of the timer Y (high–order) and the timer Y (low–order). Interrupt operation s Edge of input pulse At both edges of pulses input from the P5 5 /CNTR 1 p in, an interrupt request occurs. At the same time, the CNTR1 i nterrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR1 i nterrupt enable bit. s Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. Figure 2.3.9 shows a pulse width HL continuously measurement mode operation example. 2–48 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y Pulse width Pulse width H(s) = 1 ÷ count source frequency ! (the Y counter initial value – the Y counter value immediately before reload) Operation example in pulse width HL continuously measurement mode •RL : Reload •n : The Y counter initial value •m : The Y counter value immediately before reload Timer Y stop control bit Count source P55/CNTR1 pin CNTR1 active edge switch bit RL RL RL Value of timer Y counter n16 m16 000016 H H Time CNTR1 interrupt request bit 1 CNTR1 interrupt enable bit Timer Y interrupt request bit Timer Y interrupt enable bit 1 1 1 : •Clearing by writing “0” to the CNTR1 interrupt request bit. •Clearing by accepting the CNTR1 interrupt request when the CNTR1 interrupt enable bit is “1.” Fig. 2.3.9 Pulse width HL continuously measurement mode operation example 3825 GROUP USER’S MANUAL 2–49 APPLICATION 2.3 Timer X and timer Y 2.3.3 Related registers Figure 2.3.10 shows the memory allocation of the timer X- and timer Y-related registers. Each of these registers is described below. Address 000B16 Port P5 direction register (P5D) 002016 002116 002216 002316 Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) 002716 002816 Timer X mode register (TXM) Timer Y mode register(TYM) 003C16 003D16 003E16 003F16 Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.3.10 Memory allocation of timer X- and timer Y-related registers 2–50 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y (1) Port P5 direction register (P5D) The port P5 direction register (address 000B 16) selects the I/O direction of port P5. Figure 2.3.11 shows the structure of the port P5 direction register. The CNTR 0 p in is also used as P5 4 , while the CNTR 1 p in is also used as P5 5. s Timer X In the pulse output mode, set bit 4 to “1” for the output mode. In the event counter mode or the pulse width measurement mode, set bit 4 to “0” for the input mode. The real time port RTP 0 p in is also used as P52, while the RTP1 p in is also used as P53. To use as the RTP0 pin, set bit 2 to “1” for the output mode. To use as the RTP1 pin, set bit 3 to “1” for the output mode. s Timer Y In the period measurement mode or the event counter mode or the pulse width HL continuously measurement mode, set bit 5 to “0” to set it for the input mode. Port P5 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (P5D) [Address 0B16] B Name Functions 0 : Port P5 0 input mode 1 : Port P5 0 output mode 0 : Port P5 1 input mode 1 : Port P5 1 output mode 0 : Port P5 2 input mode 1 : Port P5 2 output mode 0 : Port P5 3 input mode 1 : Port P5 3 output mode 0 : Port P5 4 input mode 1 : Port P5 4 output mode 0 : Port P5 5 input mode 1 : Port P5 5 output mode 0 : Port P5 6 input mode 1 : Port P5 6 output mode 0 : Port P5 7 input mode 1 : Port P5 7 output mode At reset R W × 0 0 0 0 0 0 0 0 × × × × × × × 0 Port P5 direction register 1 2 3 4 5 6 7 Note : Port P5 direction register cannot be read out. P57 ADT P56 TOUT P55 P54 P53 CNTR 1 CNTR 0 RTP1 P52 RTP0 P51 INT 3 P50 INT2 Fig. 2.3.11 Structure of port P5 direction register 3825 GROUP USER’S MANUAL 2–51 APPLICATION 2.3 Timer X and timer Y (2) Timer X latch and timer X counter (TXL and TXH) The timer X latch (referred as “the X latch”) and the timer X counter (referred as “the X counter”) consist of 16 bits in a combination of high-order (address 002116 ) and low-order (address 002016). The X latch and the X counter are allocated at the same address. To access the X latch and the X counter, access both the timer X (low-order) and the timer X (high-order). s Read When the timer X (high-order) and the timer X (low-order) are read out, the value of the X counter (count value) are read out. Read both registers in the order of the timer X (high-order) and the timer X (low-order). Do not write any value to the timer X (high-order) and the timer X (low-order) before the timer X (loworder) has been read out. In this case, timer X will not operate normally. s Write When a value is written to the timer X (low-order) and the timer X (high-order), the value is set in the X latch and the X counter at the same time. Writing to the X latch only can be selected by the timer X write control bit (refer to “2.3.3 Related registers, (4) Timer X mode register”). Write the values to both registers in the order of the timer X (low-order) and the timer X (high-order). Do not read timer X (low-order) and the timer X (high-order) before the timer X (high-order) has been written. In this case, timer X will not operate normally. q Timer X latch The X latch is a register which holds the value to be transferred (reloaded) automatically to the X counter as the initial value of the X counter at the X counter underflow. Figure 2.3.12 shows the structure of the timer X latch. The contents of the X latch cannot be read out. qTimer X latch Timer X (high-order, low-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer X (high-order, low-order) (TXH, TXL) [Address 2116, 2016] At reset R W × 1 0 •Set “0000 16 to FFFF 16” as timer X count value. to •Write high-order byte of setting value to TXH, 7 and low-order byte to TXL, respectively. •The values of TXH and TXL are set to the respective X latches and transferred automatically to the respective X counters at the X counter underflow. B Functions Note : Write both registers in the order of TXL and TXH. Fig. 2.3.12 Structure of timer X latch 2–52 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y q Timer X counter The X counter counts the count source. Figure 2.3.13 shows the structure of the timer X counter. The contents of the X counter are decremented by 1 each time a count source is input. The division ratio of the counter is represented by the following expression. Division ratio of the X counter = 1 the X counter initial value + 1 qTimer X counter Timer X (high-order, low-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer X (high-order, low-order) (TXH, TXL) [Address 2116, 2016] B Functions At reset R W 1 0 •Set “0000 16 to FFFF 16” as timer X count value. to •The value of the X counter is decremented by 7 1 each time a count source is input. •When the timer X write control bit is “0,” the values of TXH and TXL are set to the respective X latches at the same time. •The values of each X counter are read out by reading the respective timer Xs. Notes 1 : Write both registers in the order of TXL and TXH. 2 : Read both registers in the order of TXH and TXL. Fig. 2.3.13 Structure of timer X counter 3825 GROUP USER’S MANUAL 2–53 APPLICATION 2.3 Timer X and timer Y (3) Timer Y latch and timer Y counter (TYL and TYH) The timer Y latch (referred as “the Y latch”) and the timer Y counter (referred as “the Y counter”) consist of 16 bits in a combination of high-order (address 002316) and low-order (address 002216). The Y latch and Y counter are allocated at the same address. To access the Y latch and the Y counter, access both the timer Y (low-order) and the timer Y (high-order). s Read When the timer Y (high-order and low-order) are read out, the value of the Y counter (count value) are read out. Read both registers in the order of the timer Y (high-order) and the timer Y (low-order). Do not write any value to the timer Y (high-order and low-order) before the timer Y (low-order) has been read out. In this case, timer Y will not operate normally. s Write When a value is written to the timer Y (low-order and high-order), the value is set in the Y latch and the Y counter at the same time. Write the values to both registers in the order of the timer Y (loworder) and the timer Y (high-order). Do not read the timer Y (low-order and high-order) before the timer Y (high-order) has been written. In this case, timer Y will not operate normally. qTimer Y latch The Y latch is a register which holds the value to be transferred (reloaded) automatically to the Y latch as the initial value of the Y counter at the Y counter underflow. Figure 2.3.14 shows the structure of the timer Y latch. Reload is performed at the following : •At the Y counter underflow •At the edge of the input pulse from the P5 5/CNTR 1 p in (period measurement mode/pulse width HL coutinuously measurement mode) The contents of the Y latch cannot be read out. qTimer Y latch Timer Y (high-order, low-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (high-order, low-order) (TYH, TYL) [Address 2316, 2216] At reset R W × 1 0 •Set “0000 16 to FFFF 16” as timer Y count value. to •Write high-order byte of setting value to TYH, 7 and low-order byte to TYL, respectively. •The values of TYH and TYL are set to the respective Y latches and transferred automatically to the respective Y counters at the Y counter underflow. Note : Write both registers in the order of TYL and TYH. B Functions Fig. 2.3.14 Structure of timer Y latch 2–54 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y q Timer Y counter The Y counter counts the count source. Figure 2.3.15 shows the structure of the timer Y counter. The contents of the Y counter are decremented by 1 each time a count source is input. The division ratio of the counter is represented by the following expression. Division ratio of the Y counter = 1 the Y counter initial value + 1 In the period measurement mode or the pulse width HL coutinuously measurement mode, the value immediately before reload is held until it is read out once after reload. The count operation is coutinued. qTimer Y counter Timer Y (high-order, low-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (high-order, low-order) (TYH, TYL) [Address 2316, 2216] B Functions At reset R W 1 0 •Set “0000 16 to FFFF 16” as timer Y count value. to •The value of the Y counter is decremented 7 by 1 each time a count source is input. •The values of each Y counter are read out by reading the respective timer Ys. •The Y counter value immediately before reload is held until it is read out once after reload. (period measurement mode/pulse width HL continuously measurement mode) Notes 1 : Write both registers in the order of TYL and TYH. 2 : Read both registers in the order of TYH and TYL. Fig. 2.3.15 Structure of timer Y counter 3825 GROUP USER’S MANUAL 2–55 APPLICATION 2.3 Timer X and timer Y (4) Timer X mode register (TXM) The timer X mode register (address 002716) consists of bits which select operation or control counting. Figure 2.3.16 shows a structure of the timer X mode register. Each bit is described below. Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address 2716] B 0 Name Timer X write control bit Real time port control bit Functions 0 : Write value in latch and counter 1 : Write value in latch only 0 : Real time port function invalid 1 : Real time port function valid 0: 1: 0: 1: b5b4 At reset R W 0 1 0 2 3 4 5 6 P52 data for real time port P53 data for real time port Timer X operating mode bits “L” level output “H” level output “L” level output “H” level output 0 0 0 0 0 CNTR 0 active edge switch bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode •CNTR 0 interrupt 0 : Falling edge active 1 : Rising edge active •Pulse output mode 0 : Start at initial level “H” output 1 : Start at initial level “L” output •Event counter mode 0 : Rising edge active 1 : Falling edge active •Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width 0 : Count start 1 : Count stop 7 Timer X stop control bit 0 Fig. 2.3.16 Structure of timer X mode register 2–56 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y s Timer X write control bit (bit 0) The timer X write control bit controls writing to the timer X (low-order and high-order). When bit 0 is “0,” the value written in the timer X (low-order and high-order) are set into both the X latch and the X counter at the same time. When bit 0 is “1,” the value written in the timer X (low-order and high-order) is set into the X latch only. When a value is written into the X latch only, this rewritten value is transferred to the X counter at the first X counter underflow after rewriting. s Real time port control bit (bit 1) The real time port control bit selects a function to output data from the real time port. When bit 1 is “0,” this function is invalid. When the bit is “1,” this function is valid. For an explanation of operations, refer to “ 2.3.1 Explanation of timer X operations, (5) Real time port control.” s Data for real time port (bit 2 and bit 3) The data for real time port is the data to be output from the real time port. s Timer X operating mode bits (bit 4 and bit 5) The timer X operating mode bits select a operating mode of the timer X. Table 2.3.2 shows the relation between the timer X operating mode bits and the operating modes. For an explanation of each mode operation, refer to the section pertaining to the explanation of each operation. Table 2.3.2 Relation between timer X operating mode bits and operating modes b5 0 0 1 1 b4 0 1 0 1 Operation mode Timer mode Pulse output mode Event counter mode Pulse width measurement mode 3825 GROUP USER’S MANUAL 2–57 APPLICATION 2.3 Timer X and timer Y s CNTR 0 a ctive edge switch bit (bit 6) The CNTR0 active edge switch bit has a function which selects an active edge of the CNTR 0 interrupt, and functions for each mode. qCNTR0 interrupt When bit 6 is “0,” the falling edge ( ) is active. When bit 6 is “1,” the rising edge ( ) is active. qPulse output mode In the pulse output mode, the initial level at the start of pulse output is selected. When bit 6 is “0,” the initial level is “H.” When bit 6 is “1,” the initial level is “L.” qEvent counter mode An active edge of the count source is selected. When bit 6 is “0,” the rising edge ( ) is active. When bit 6 is “1,” the falling edge ( ) is active. qPulse width measurement mode A duration of pulse width measured is selected. When bit 6 is “0,” the “H” level width is measured. When bit 6 is “1,” the “L” level width is measured. s Timer X stop control bit (bit 7) The timer X stop control bit controls the count operation of the timer X. By writing “0” to bit 7, a count source is input to the X counter, so that a count operation is started. As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started after reset release. By writing “1” to bit 7, the input of count source to the X counter is stopped, so that the count operation stops. In the pulse width measurement mode, however, a count operation is performed only in the period in which the measurement level is input to the P5 4 /CNTR 0 p in when bit 7 is in the “0” state. At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the X counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in the stop state. 2–58 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y (5) Timer Y mode register (TYM) The timer Y mode register (address 002816) consists of bits which select operation or control counting. Figure 2.3.17 shows a structure of the timer Y mode register. Each bit is described below. Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address 2816] B Name Functions At reset R W 0 0× 0 Nothing is allocated. These bits cannot be to written to and are fixed to “0” at reading. 3 4 Timer Y operating mode bits 5 6 CNTR 1 active edge switch bit b5b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode •CNTR 1 interrupt 0 : Falling edge active 1 : Rising edge active •Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge •Event counter mode 0 : Rising edge active 1 : Falling edge active 0 0 0 7 Timer Y stop control bit 0 : Count start 1 : Count stop 0 Fig. 2.3.17 Structure of timer Y mode register 3825 GROUP USER’S MANUAL 2–59 APPLICATION 2.3 Timer X and timer Y s Timer Y operating mode bits (bit 4 and bit 5) The timer Y operating mode bits select a operating mode of the timer Y. Table 2.3.3 shows the relation between the timer Y operating mode bits and the operating modes. For an explanation of each mode operation, refer to the section pertaining to the explanation of each operation. Table 2.3.3 Relation between timer Y operating mode bits and operating modes b5 0 0 1 1 b4 0 1 0 1 Operation mode Timer mode Period measurement mode Event counter mode Pulse width HL continuously measurement mode s CNTR 1 a ctive edge switch bit (bit 6) The CNTR1 active edge switch bit has a function which selects an active edge of the CNTR 1 interrupt and functions for each mode. In the pulse width HL continuously measurement mode, this bit is invalid. qCNTR1 interrupt When bit 6 is “0,” the falling edge ( ) is active. When bit 6 is “1,” the rising edge ( ) is active. In the pulse width HL continuously measurement mode, an interrupt request occurs at the both edges regardless of the value of this bit. qPeriod measurement mode This bit selects the duration which is measured. When bit 6 is “0,” the falling edge to the falling edge duration is measured. When bit 6 is “1,” the rising edge to the rising edge duration is measured. qEvent counter mode An active edge of the count source is selected. When bit 6 is “0,” the rising edge ( ) is active. When bit 6 is “1,” the falling edge ( ) is active. s Timer Y stop control bit (bit 7) The timer Y stop control bit controls the count operation of the timer Y. By writing “0” to bit 7, a count source is input to the Y counter, so that a count operation is started. As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started after reset release. By writing “1” to bit 7, the input of count source to the Y counter is stopped, so that the count operation stops. At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in the stop state. 2–60 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y (6) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D 16) indicate whether an interrupt request has occured or not. Figure 2.3.18 shows the structure of the interrupt request register 1 and Figure 2.3.19 shows the structure of the interrupt request register 2. The occurrence of an interrupt request (timer X, timer Y, CNTR 0 , and CNTR 1 i nterrupt requests) causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the corresponding interrupt enable bit (refer to the next item). For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 3C16] B 0 1 2 3 4 5 6 7 Name INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 V V V V V V V V V : “0” can be set by software, but “1” cannot be set. Fig. 2.3.18 Structure of interrupt request register 1 3825 GROUP USER’S MANUAL 2–61 APPLICATION 2.3 Timer X and timer Y Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 3D16] B 0 Name Functions At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 0× CNTR 0 interrupt request bit 1 CNTR 1 interrupt request bit 2 Timer 1 interrupt request bit 3 INT2 interrupt request bit 4 INT3 interrupt request bit 5 Key input interrupt request bit 6 ADT/A-D conversion interrupt request bit 7 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. V : “0” can be set by software, but “1” cannot be set. Fig. 2.3.19 Structure of interrupt request register 2 2–62 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y (7) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E 16) and the interrupt control register 2 (address 003F 16) control each interrupt request source. Figure 2.3.20 shows the structure of the interrupt control register 1 and Figure 2.3.21 shows the structure of the interrupt control register 2. When an interrupt enable bit (timer X, timer Y, CNTR 0 , and CNTR 1 i nterrupt enable bits) is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit only is set to “1,” and the interrupt request is not accepted. When the interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 3E16] B 0 1 2 3 4 5 6 7 Name INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 Fig. 2.3.20 Structure of interrupt control register 1 3825 GROUP USER’S MANUAL 2–63 APPLICATION 2.3 Timer X and timer Y Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] B 0 1 2 3 4 5 6 Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/A-D conversion interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 00 7 Fixed this bit to “0.” Fig. 2.3.21 Structure of interrupt control register 2 2–64 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y 2.3.4 Register setting example In the following, an example of setting registers for using each mode of the timer X and timer Y is described. (1) Timer X s Timer mode Figure 2.3.22 shows an example of setting registers for using the timer mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the timer X interrupt enable bit and the timer X interrupt request bit to “0.” •After setting  below, set the timer X interrupt enable bit to “1” (interrupts enabled) . 2: Write values in the order of the timer X (low-order) and the timer X (high-order). ŒSetting of timer X mode register Select timer mode or others b7 b0 1 00 TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P52 data for real time port b3 : P53 data for real time port b5, b4 : Timer X operating mode bits 0 0 : Timer mode b6 : CNTR0 active edge switch bit b7 : Timer X stop control bit 1 : Count stop Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ŽSet count value (high-order) to timer X (high-order) (TXH) [Address 2116] Set timer X stop control bit of timer X mode register to “0” to start counting Fig. 2.3.22 Example of setting registers for using timer mode 3825 GROUP USER’S MANUAL 2–65 APPLICATION 2.3 Timer X and timer Y sPulse output mode Figure 2.3.23 shows an example of setting registers for using the pulse output mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer X or CNTR0) and the interrupt request bits (timer X or CNTR0) to “0.” •After setting  below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled) . 2: Write values in the order of the timer X (low-order) and the timer X (high-order). ŒPort P5 direction register b7 b0 1 P5D : Port P5 direction register [Address 0B16] b4 : Bit corresponding to port P54 1 : Output mode Setting of timer X mode register Select pulse output mode or others b7 b0 1 01 TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P52 data for real time port b3 : P53 data for real time port b5, b4 : Timer X operating mode bits 0 1 : Pulse output mode b6 : CNTR0 active edge switch bit 0 : Start at initial level “H” level output 1 : Start at initial level “L” level output b7 : Timer X stop control bit 1 : Count stop ŽSet count value (low-order) to timer X (low-order) (TXL) [Address 2016] Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] Set timer X stop control bit of timer X mode register to “0” to start counting Fig. 2.3.23 Example of setting registers for using pulse output mode 2–66 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y s Event counter output mode Figure 2.3.24 shows an example of setting registers for using the event counter mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer X or CNTR0) and the interrupt request bits (timer X or CNTR0) to “0.” •After setting  below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled) . 2: Write values in the order of the timer X (low-order) and the timer X (high-order). ŒPort P5 direction register b7 b0 0 P5D : Port P5 direction register [Address 0B16] b4 : Bit corresponding to port P54 0 : Input mode Setting of timer X mode register Select event counter mode or others b7 b0 1 10 TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P52 data for real time port b3 : P53 data for real time port b5, b4 : Timer X operating mode bits 1 0 : Event counter mode b6 : CNTR0 active edge switch bit 0 : Rising edge active 1 : Falling edge active b7 : Timer X stop control bit 1 : Count stop ŽSet count value (low-order) to timer X (low-order) (TXL) [Address 2016] Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] Set timer X stop control bit of timer X mode register to “0” to start counting Fig. 2.3.24 Example of setting registers for using event counter mode 3825 GROUP USER’S MANUAL 2–67 APPLICATION 2.3 Timer X and timer Y s Pulse width measurement mode Figure 2.3.25 shows an example of setting registers for using the pulse width measurement mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer X or CNTR 0) and the interrupt request bits (timer X or CNTR 0) to “0.” •After setting  below, set the interrupt enable bits (timer X or CNTR 0) to “1” (interrupts enabled) . 2: Write values in the order of the timer X (low-order) and the timer X (high-order). ŒPort P5 direction register b7 b0 0 P5D : Port P5 direction register [Address 0B16] b4 : Bit corresponding to port P54 0 : Input mode Setting of timer X mode register Select pulse width measurement mode or others b7 b0 1 11 TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P52 data for real time port b3 : P53 data for real time port b5, b4 : Timer X operating mode bits 1 1 : Pulse width measurement mode b6 : CNTR0 active edge switch bit 0 : Measure “H” level width 1 : Measure “L” level width b7 : Timer X stop control bit 1 : Count stop ŽSet count value (low-order) to timer X (low-order) (TXL) [Address 2016] Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] Set timer X stop control bit of timer X mode register to “0” to start counting Fig. 2.3.25 Example of setting registers for using pulse width measurement mode 2–68 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y s Real time port function Figure 2.3.26 shows an example of setting registers for using the real time port (referred as RTP) function. [Notes on use] Notes 1: After reset release, port P5 direction register is set for the input mode, so pins P52/RTP0 and P53/RTP1 operate as ordinary input ports. For using as RTP, be sure to set the corresponding bits of the port P5 direction register for the output mode. 2: Change RTP output data as required, for example, by using an interrupt. 3: Do not change ports P52 and P53 selected as RTP into input pins during RTP operation. ŒPort P5 direction register b7 b0 P5D : Port P5 direction register [Address 0B16] b2, b3 : Bits corresponding to ports P52 (RTP0) and P53 (RTP1) 0 : Input mode 1 : Output mode Setting of timer X mode register Select RTP or others b7 b0 1 1 TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b1 : Real time port control bit 1 : Real time port function valid b2 : P52 data for real time port b3 : P53 data for real time port b5, b4 : Timer X operating mode bits 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode b6 : CNTR0 active edge switch bit •CNTR0 interrupt 0 : Falling edge active 1 : Rising edge active •Pulse output mode 0 : Start at initial level “H” output 0 : Start at initial level “L” output •Event counter mode 0 : Rising edge active 1 : Falling edge active •Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width b7 : Timer X stop control bit 1 : Count stop ŽSet count value (low-order) to timer X (low-order) (TXL) [Address 2016] Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] Set timer X stop control bit of timer X mode register to “0” to start counting Fig. 2.3.26 Example of setting registers for using RTP 3825 GROUP USER’S MANUAL 2–69 APPLICATION 2.3 Timer X and timer Y (2) Timer Y s Timer mode Figure 2.3.27 shows an example of setting registers for using the timer mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the timer Y interrupt enable bit and the timer Y interrupt request bit to “0.” •After setting  below, set the timer Y interrupt enable bit to “1” (interrupts enabled) . 2: Write values in the order of the timer Y (low-order) and the timer Y (high-order). ŒSetting of timer Y mode register Select timer mode or others b7 b0 1 00 TYM : Timer Y mode register [Address 2816] b5, b4 : Timer Y operating mode bits 0 0 : Timer mode b6 : CNTR1 active edge switch bit b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated Set count value (low-order) to timer Y (low-order) (TYL) [Address 2216] ŽSet count value (high-order) to timer Y (high-order) (TYH) [Address 2316] Set timer Y stop control bit of timer Y mode register to “0” to start counting Fig. 2.3.27 Example of setting registers for using timer mode 2–70 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y s Period measurement mode Figure 2.3.28 shows an example of setting registers for using the period measurement mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR 1) to “0.” •After setting  below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled) . 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order). ŒPort P5 direction register b7 b0 0 P5D : Port P5 direction register [Address 0B16] b5 : Bit corresponding to port P55 0 : Input mode Setting of timer Y mode register Select period measurement mode or others b7 b0 1 01 TYM : Timer Y mode register [Address 2816] b5, b4 : Timer Y operating mode bits 0 1 : Period measurement mode b6 : CNTR1 active edge switch bit 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated ŽSet count value (low-order) to timer Y (low-order) (TYL) [Address 2216] Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] Set timer Y stop control bit of timer Y mode register to “0” to start counting Fig. 2.3.28 Example of setting registers for using period measurement mode 3825 GROUP USER’S MANUAL 2–71 APPLICATION 2.3 Timer X and timer Y s Event counter mode Figure 2.3.29 shows an example of setting registers for using the event counter mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR 1) to “0.” •After setting  below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled) . 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order). ŒPort P5 direction register b7 b0 0 P5D : Port P5 direction register [Address 0B16] b5 : Bit corresponding to port P55 0 : Input mode Setting of timer Y mode register Select event counter mode or others b7 b0 1 10 TYM : Timer Y mode register [Address 2816] b5, b4 : Timer Y operating mode bits 1 0 : Event counter mode b6 : CNTR1 active edge switch bit 0 : Rising edge active 1 : Falling edge active b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated ŽSet count value (low-order) to timer Y (low-order) (TYL) [Address 2216] Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] Set timer Y stop control bit of timer Y mode register to “0” to start counting Fig. 2.3.29 Example of setting registers for using event counter mode 2–72 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y s Pulse width HL countinuously measurement mode Figure 2.3.30 shows an example of setting registers for using the pulse width HL countinuously measurement mode. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR 1) to “0.” •After setting  below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled) . 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order). ŒPort P5 direction register b7 b0 0 P5D : Port P5 direction register [Address 0B16] b5 : Bit corresponding to port P55 0 : Input mode Setting of timer Y mode register Select pulse width HL continuously measurement mode or others b7 b0 1 11 TYM : Timer Y mode register [Address 2816] b5, b4 : Timer Y operating mode bits 1 1 : Pulse width HL continuously measurement mode b6 : CNTR1 active edge switch bit Invalid in pulse width HL continuously measurement mode b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated ŽSet count value (low-order) to timer Y (low-order) (TYL) [Address 2216] Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] Set timer Y stop control bit of timer Y mode register to “0” to start counting Fig. 2.3.30 Example of setting registers for using pulse width HL continuously measurement mode 3825 GROUP USER’S MANUAL 2–73 APPLICATION 2.3 Timer X and timer Y 2.3.5 Application examples (1) Pulse output mode : Piezoelectric buzzer output Outline : T he rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : •The rectangular waveform which is divided clock f(XIN) = 8 MHz up to about 2 kHz is output from the P54/CNTR 0 p in. •The level of the P54 /CNTR0 p in fixes to “H” while a piezoelectric buzzer output is stopped. Figure 2.3.31 shows an example of a peripheral circuit, Figure 2.3.32, a connection of the timer and a setting of the division ratio, Figure 2.3.33, the setting of the related registers, and Figure 2.3.34, the control procedure. The “H” level is output while a piezoelectric buzzer output is stopped. 3825 group P54/CNTR 0 250 µs 250 µs PiPiPi.... Set a division ratio so that the underflow cycle of the timer X is this value. Fig. 2.3.31 Example of peripheral circuit Fix f(XIN) = 8 MHz 1/16 Timer X 1/125 CNTR 0 Fig. 2.3.32 Connection of timer and setting of division ratio 2–74 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y b7 b0 X X X 1 X X X X P5D : Port P5 direction register [Address 0B16] b4 : Bit corresponding to port P54 1 : Output mode b7 b0 1 X 0 1 X X X X TXM : Timer X mode register [Address 2716] b5, b4 : Timer X operating mode bits 0 1 : Pulse output mode b7 : Timer X stop control bit 1 : Count stop Note : Write values in the order of the low-order byte and the TXH : Timer X (high-order) [Address 2116] 0016 high-order byte. Set “division ratio – 1 (124 : 007C16)” in the timer X register b7 b0 X X X 1 X X X X ICON1 : Interrupt control register 1 [Address 3E16] b4 : Timer X interrupt enable bit 1 : Interrupt enabled 7C16 TXL : Timer X (low-order) [Address 2016] Fig. 2.3.33 Setting of related registers RESET Initialization CLT CLD SEI ICON1 (Address 3E 16) ← XXX0XXXX 2 ← 1X01XXXX 2 TXM (Address 27 16) P5D (Address 0B 16), bit 4 ← 1 P5 (Address 0A 16), bit 4 ← 1 ← 7C16 TXL (Address 20 16) ← 0016 (125 – 1) TXH (Address 21 16) ICON1 (Address 3E 16) CLI Main processing ← XXX1XXXX 2 All interrupts; Disabled Timer X interrupt; Disabled CNTR0 output stops at this point (A piezoelectric buzzer output stops) Set port conditions at stop of a piezoelectric buzzer output (“H” level output) Timer X interrupt; Enabled Interrupts; Enabled A piezoelectric buzzer request generated during the main processing is processed at the output unit Switch bit 7 of TXM Count (ON) ↔ Stop (OFF) N (= Request) Immediately after no request? ←1 ←1 Y (= No request) TXL (Address 20 16) TXH (Address 21 16) TXM (Address 27 16), bit 7 ← 7C16 ← 0016 (125 – 1) ←0 Output unit A piezoelectric buzzer request has occurred? N (= OFF) Y (= ON) TXM (Address 27 16), bit 7 P5 (Address 0A 16), bit 4 Fig.2.3.34 Control procedure 3825 GROUP USER’S MANUAL 2–75 APPLICATION 2.3 Timer X and timer Y (2) Pulse width measurement mode: Ringer signal detection Outline : A telephone ringing pulse V is detected by applying the timer X interrupt and the pulse width measurement mode. Specifications : •Whether a telephone call exists or not is judged by measuring a pulse width output from the “H” active ringing pulse detection circuit. •f(X IN ) = 8 MHz is used as the count source. •When the following condition is satisfied, it is regard as normal. 200 ms ≤ p ulse width of a ringing pulse < 1 .2 s Figure 2.3.35 shows an example of a peripheral circuit, Figure 2.3.36, the setting of the related registers, Figure 2.3.37, a ringing pulse waveform, Figure 2.3.38, an operation timing when a ringing pulse is input, and Figure 2.3.39, the control procedure. 3825 group CNTR0 Ringing pulse detection circuit Telephone circuit V Ringing pulse : Signal which is sent by turning on/off (make/break) the telephone line. Each country has a different standard. In this case, Japanese domestic standard is adopted as an example. Fig. 2.3.35 Example of peripheral circuit b7 b0 X X X 0 X X X X P5D : Port P5 direction register [Address 0B16] b4 : Bit corresponding to port P54 0 : Input mode b7 b0 1 0 1 1 X X X X TXM : Timer X mode register [Address 2716] b5, b4 : Timer X operating mode bits 1 1 : Pulse width measurement mode b6 : CNTR0 active edge switch bit 0 : •Pulse width measurement mode (Measure “H” level width) •CNTR0 interrupt (Falling edge active) b7 : Timer X stop control bit 1 : Count stop A716 6116 TXL : Timer X (low-order) [Address 2016] TXH : Timer X (high-order) [Address 2116] Note : Write values in the order of the low-order byte and the high-order byte. Set “division ratio – 1 (24999 : 61A716) ” in the timer X register b7 b0 X X X 1 X X X X ICON1 : Interrupt control register 1 [Address 3E16] b7 b0 0 X X X X X X 1 ICON2 : Interrupt control register 2 [Address 3F16] b0 : CNTR0 interrupt enable bit 1 : Interrupt enabled b4 : Timer X interrupt enable bit 1 : Interrupt enabled Fig. 2.3.36 Setting of related registers 2–76 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y 16 Hz Ringing pulse from telephone line OFF ON Approx. 1 second Ringing duration Waveform-shaped signal input to microcomputer Approx. 2 second No ringing duration Fig. 2.3.37 Ringer signal waveform Ringing duration Approx. 1 second Signal input to microcomputer No ringing duration Approx. 2 second Ringing duration Approx. 1.2 second or more No ringing duration Signal input to microcomputer Timer X value Reload Timer X value Reload Timer X interrupt 4 to 23 interrupts occur CNTR0 interrupt Timer X interrupt 24 or more interrupts occur CNTR0 interrupt Fig. 2.3.38 Operation timing when ringing pulse is input 3825 GROUP USER’S MANUAL 2–77 APPLICATION 2.3 Timer X and timer Y RESET Initialization CLT CLD SEI ICON1 (Address 3E16) ← XXX0XXXX2 ICON2 (Address 3F16) ← 0XXXXXX02 P5D (Address 0B16), bit 4 ← 0 ← 1011XXXX2 TXM (Address 2716) TXL (Address 2016) ← A716 TXH (Address 2116) ← 6116 (25000 – 1) TXM (Address 2716), bit 7 ← 0 ICON1 (Address 3E16) ICON2 (Address 3F16) CLI ← XXX1XXXX2 ← 0XXXXXX12 All interrupts; Disabled Timer X interrupt; Disabled CNTR0 interrupt; Disabled Set P54/CNTR0 pin for input mode Connect timer X Set “division ratio – 1” to timer X (low-order) and timer X (high-order) (Set values in the order of low-order byte and high-order byte) Timer count start Timer X interrupt; Enabled P54/CNTR0 interrupt; Enabled Interrupts; Enabled CNTR0 interrupt processing routine The number of underflows is within the range ? CNTR0 interrupt occurs at transition from “H” to “L” of waveform which is input to P54/CNTR0 pin Y Timer X value is within the range ? Y Judged as presence of ringing pulse (Set ringer flag) N Check the number of underflows counted by timer X interrupt → If the number is 4 or less and 24 or more, the pulse is abnormal Check pulse width → When pulse width is within range, the pulse is normal N Timer X interrupt occurs at timer X underflow (at every 50 ms) TXL (Address 2016) ← A716 TXH (Address 2116) ← 6116 (25000 – 1) Reload to timer X register RTI N A ringing pulse exists ? (Ringer flag = “H”) Y Processing when a ringing pulse exists Timer X interrupt processing routine Count the number of underflows If 24 underflows or more are counted, regard the ringing pulse as out of standard, and execute error processing RTI Fig. 2.3.39 Control procedure 2–78 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y (3) Real time port function : Stepping motor drive Outline : A stepping motor is driven by applying a timer X interrupt and the real time port (referred as “RTP”) function. Specifications : • T he RTP output time is controlled by changing a timer X setting value in a timer X interrupt processing. • The RTP output pattern to the motor driver by changing data for RTP. Figure 2.3.40 shows an application connection example when the RTP is used. Figure 2.3.41 shows an RTP output example. Table 2.3.4 and Table 2.3.5 show table examples for it. Figure 2.3.42 shows a timer X interrupt processing procedure example when the RTP is used. 3825 group RTP setting value table TXM Data for RTP RTP0 (P52) RTP1 (P53) Timer X setting value table Motor driver Stepping motor Timer X Fig. 2.3.40 Application connection example when RTP is used RTP output time Timer X setting value (T 1) Timer X setting value (T2) Timer X Timer X setting value setting value (T 3) (T4) (T 5) (T6) RTP0 output RTP1 output RTP output pattern Œ RTP output pattern  RTP output pattern Ž RTP output pattern  Œ Fig. 2.3.41 RTP output example 3825 GROUP USER’S MANUAL 2–79 APPLICATION 2.3 Timer X and timer Y Table 2.3.4 Table example for timer X setting value RTP output time T1 T2 T3 T4 T5 T6 T7 T8 Timer X setting value 2FD016 2B7116 208116 186916 13C916 13A916 122116 11C116 Table 2.3.5 Table example for RTP setting value RTP output pattern Œ  Ž  RTP setting values TXM, b2 TXM, b3 0 0 0 1 1 0 1 1 [Notes on use] Notes 1 : When there is no necessity for changing the timer X underflow time in , omit it. 2 : When writing to the latch only is selected as the timer X write control, the timer X value (TXL, TXH) is rewritten at the first underflow after . 3 : Execute another timer X interrupt processing in Œ to . Interrupt processing routine Œ Push to stack area  Transfer the next timer X underflow time from internal ROM table and store it in TXL (address 2016) and TXH (address 2116). Ž Transfer RTP output data at the next timer X underflow from internal ROM table and store it in bits 2 and 3 of TXM (address 2716) .  Pop from stack area RTI Fig. 2.3.42 Timer X interrupt processing procedure example when RTP is used 2–80 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y 2.3.6 Notes on use Notes on using each mode of the timer X and timer Y are described below. (1) Timer X s Common to all modes q When reading or writing for timer X, be sure to execute for both the timer X (high-order) and the timer X (low-order). When reading a value from the timer X, read it in the order of the timer X (highorder) and the timer X (low-order). When writing a value to the timer X, execute in the order of the timer X (low-order) and the timer X (high-order). If the following operations are performed for the timer X, abnormal operation will occur. •Write operation before execution of timer X (low-order) reading •Read operation before execution of timer X (high-order) writing •In writing for the latch only (timer X write control bit = “1”), if writing timing for the high-order latch is almost same as the underflow timing, a normal value may not be set in the high-order counter. s Pulse output mode q In the pulse output mode, set the bit 4 (corresponding to the P5 4/CNTR0) of the port P5 direction register (address 000B 16) to “1” (output mode). q When the bit 4 (corresponding to the P5 4/CNTR 0 ) of the port P5 register (address 000A 16) in the pulse output mode is read, the value of the port register are not read out but the output value of the pin is read out. sEvent counter mode qWhen using the event counter mode, set the bit 4 (corresponding to the P5 4/CNTR 0) of the port P5 direction register (address 000B 16) to “0” (input mode). q The maximum input frequency in the event counter mode is: 4 MHz (250 ns) .................................................. at V CC = 4 .0 V to 5.5 V 500 (2 ! V CC ) – 4 MHz ( ns) .......... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “H” pulse width is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “L” pulse is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 sPulse width measurement mode q In the pulse width measurement mode, set the bit 4 (corresponding to P54/CNTR0) of the port P5 direction register (address 000B 16) to “0” (input mode). q In reading the value of the P54/CNTR0 p in as an input pin, the value is “1” at “H” level input or “0” at “L” level input regardless of the value of the CNTR0 a ctive edge switch bit. q Setting the CNTR0 a ctive edge switch bit effects on the active edge of an interrupt. Consequently, a CNTR 0 i nterrupt request may be caused by setting the CNTR 0 a ctive edge switch bit. As a countermeasure against the above, switch the active edge after disabling the CNTR0 interrupt, then set the CNTR 0 i nterrupt request bit to “0.” q The minimum “H” pulse width in the pulse width measurement mode is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “L” pulse is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 3825 GROUP USER’S MANUAL 2–81 APPLICATION 2.3 Timer X and timer Y s Real time port function q After reset release, the port P5 direction register is set for the input mode, so the pins P50 –P5 7 function as ordinary I/O ports. For the pin to be used as RTP, be sure to set the corresponding bits of the port P5 direction register for the output mode. qFor a pin used as RTP, do not change this port for the input mode during real time port operation. qChange RTP output data as required, for example, by using a timer X interrupt. (2) Timer Y s Common to all modes qWhen reading or writing for timer Y, be sure to execute for both the timer Y (high-order) and the timer Y (low-order). When reading a value from the timer Y, read it in the order of the timer Y (highorder) and the timer Y (low-order). When writing a value to the timer Y, execute in the order of the timer Y (low-order) and the timer Y (high-order). If the following operations are performed for the timer Y, abnormal operation will occur. •Write operation before execution of timer Y (low-order) reading •Read operation before execution of timer Y (high-order) writing s Period measurement mode q In the period measurement mode, set the bit 5 (corresponding to the P55 /CNTR 1) of the port P5 direction register (address 000B16 ) to “0” (input mode). qSetting the CNTR1 a ctive edge switch bit effects on the active edge of an interrupt. Consequently, the CNTR1 i nterrupt request may be caused by setting the CNTR 1 a ctive edge switch bit. A s a countermeasure, switch the active edge after disabling the CNTR 1 i nterrupt, then set the CNTR1 i nterrupt request bit to “0.” qThe maximum input frequency in the period measurement mode is: 4 MHz (250 ns) .................................................. at V CC = 4 .0 V to 5.5 V 500 (2 ! V CC ) – 4 MHz ( ns) .......... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “H” pulse width is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “L” pulse is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 s Event counter mode qIn the event counter mode, set the bit 5 (corresponding to the P55/CNTR1) of the port P5 direction register (address 000B 16 ) to “0” (input mode). qSetting the CNTR 1 a ctive edge switch bit, the active edge of an interrupt is also affected. Consequently, a CNTR1 i nterrupt request may be caused by setting the CNTR1 a ctive edge switch bit. qThe maximum input frequency in the event counter mode is: 4 MHz (250 ns) .................................................. at V CC = 4 .0 V to 5.5 V ( 500 ns) .......... at V CC = 2 .5 V to 4.0 V (2 ! V CC ) – 4 MHz V CC – 2 The minimum “H” pulse width is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 2–82 3825 GROUP USER’S MANUAL APPLICATION 2.3 Timer X and timer Y The minimum “L” pulse is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 sPulse width HL continuously measurement mode qIn the pulse width HL continuously measurement mode, set the bit 5 (corresponding to P5 5/CNTR1) of the port P5 direction register (address 000B 16) to “0” (input mode). q The CNTR 1 i nterrupt request occurs at both edges of input pulses regardless of the value of the CNTR 1 a ctive edge switch bit. q The minimum “H” pulse width in the pulse width HL continuously measurement mode is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 The minimum “L” pulse is: 105 ns .................................................................. at V CC = 4 .0 V to 5.5 V 250 ( – 20 ns) ........................................... at V CC = 2 .5 V to 4.0 V V CC – 2 3825 GROUP USER’S MANUAL 2–83 APPLICATION 2.4 Timer 1, timer 2, and timer 3 2.4 Timer 1, timer 2, and timer 3 2.4.1 Explanation of operations Timer 1 to timer 3 are 8-bit timers that operate in the timer mode. The timer mode is a count-down system, so the value of the counter is decremented each time a count source is input. When the counter underflows, an interrupt request occurs. The timer 2 can also output a pulse whose polarity is reversed at each underflow. (1) Timer mode Operation of the timers 1 to 3 in the timer mode are described below. ŒStart of count operation A count operation is automatically started after reset release. The value of the counter is decremented by 1 each time a count source is input. Reload operation The counter underflows at the first count pulse after the value of the counter reaches “0016.” At this time, the value of the corresponding timer latch is transferred (reloaded) to the counter. ŽInterrupt operation An interrupt request occurs at the counter underflow. At the same time, the corresponding interrupt request bit is set to “1.” The occurrence of each interrupt is controlled by the interrupt enable bit. The acceptance of the interrupt request causes the interrupt request bit which has been set to “1” to be automatically cleared to “0.” It can also be cleared to “0” by software. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the counter initial value + 1” count of the rising edge of the count source. Figure 2.4.1 shows a timer mode operation example. 2–84 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 Count period Count period T (s) = 1 ÷ count source frequency ! (the counter initial value + 1) Operation example in timer mode •UF : Underflow •RL : Reload •n : The counter initial value Count source RL RL RL RL Value of counter n16 UF UF UF UF 0016 T Time Interrupt request bit Interrupt enable bit 1 1 1 1 1 : •Clearing by writing “0” to the corresponding interrupt request bit of the timers 1 to 3. •Clearing by accepting the corresponding interrupt request of the timers 1 to 3 when the corresponding interrupt enable bit is “1.” Fig. 2.4.1 Timer mode operation example 3825 GROUP USER’S MANUAL 2–85 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (2) Rewriting the value of the counter and the latch When data is written to the timer, the values of the counter and the latch are rewritten. For rewriting the values of the counters and the latches corresponding to each timer is described below. s Timer 1 and timer 3 By writing a value to the timer, the value is set simultaneously in both the counter and the latch. Accordingly, the counter period, when a value is written to the timer during counting, becomes inaccurate. Figure 2.4.2 shows an rewriting example of the counter and the latch corresponding to the timers 1 or 3. Rewriting example of counter •UF : Underflow •RL : Reload •n : The counter initial value before rewriting •m : The counter initial value after rewriting Write “m16” to timer m16 RL Value of counter RL n16 UF RL UF UF 0016 Inaccurate count period Interrupt request bit 1 Interrupt enable bit 1 : •Clearing by writing “0” to the interrupt request bit corresponding to the timers 1 or 3. •Clearing by accepting the interrupt request corresponding to the timers 1 or 3 when the corresponding interrupt enable bit is “1.” 1 1 Time Fig. 2.4.2 Rewriting example of counter and latch corresponding to timers 1 or 3 2–86 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 s Timer 2 The write operation to the timer 2 counter is controlled by the timer 2 write control bit (bit 2 at address 0029 16). (bit 2 = “0”) As the write operation is the same as that to the timer 1 and the timer 3, refer to the previous section, “s Timer 1 and timer 3.” (bit 2 = “1”) When a value is written to the timer 2, the value is set in the timer 2 latch only. The rewritten value is reloaded onto the timer 2 counter at the first underflow after rewriting. Figure 2.4.3 shows an rewriting example of the timer 2 counter and the timer 2 latch. Rewriting example of timer 2 counter •UF : Underflow •RL : Reload •n : The counter initial value before rewriting •m : The counter initial value after rewriting Write “m16” to timer RL m16 RL Value of counter RL n16 UF RL UF UF UF 0016 Time Timer 2 write control bit Interrupt request bit 1 Interrupt enable bit 1 : •Clearing by writing “0” to the timer 2 interrupt request bit. •Clearing by accepting the timer 2 interrupt request when the timer 2 interrupt request bit is “1.” 1 1 1 Fig. 2.4.3 Rewriting example of timer 2 counter and timer 2 latch (Writing in timer 2 latch only) 3825 GROUP USER’S MANUAL 2–87 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (3) Pulse output by timer 2 The timer 2 can output a pulse whose polarity is reversed at each the timer 2 counter underflow. Figure 2.4.4 shows a pulse output example. From the moment that the T OUT o utput control bit is set to “1,” pulses are output from the P5 6/TOUT output pin. The polarity is reversed every the timer 2 counter underflow. To output pulses, set bit 6 of the port P5 direction register for the output mode by setting it to “1.” Pulse output example by timer 2 •UF : Underflow •RL : Reload •n : The timer 2 counter initial value Value of timer 2 counter FF16 n16 0016 Timer 2 interrupt request bit Timer 2 interrupt enable bit TOUT output control bit TOUT output active edge switch bit P56/TOUT pin Programmable I/O port 1 : •Clearing by writing “0” to the timer 2 interrupt request bit. •Clearing by accepting the timer 2 interrupt request when the timer 2 interrupt enable bit is “1.” 1 1 1 1 1 1 1 1 1 1 RL UF Timer Write “1” Fig. 2.4.4 Pulse output example 2–88 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 2.4.2 Related registers Figure 2.4.5 shows memory allocation of timer-related registers. Each of these registers is described below. Address 002416 002516 002616 Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) 002916 Timer 123 mode register (T123M) 003C16 003D16 003E16 003F16 Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.4.5 Memory allocation of timer-related registers 3825 GROUP USER’S MANUAL 2–89 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (1) Timer latches and timer counters (corresponding to timers 1 to 3) The latches and the counters each consist of 8 bits and are allocated at the same address for each timer. To access a latch and a counter, access the corresponding timer. When the timer is read out, the value of the counter (count value) is read out. s Latch The latch is a register which holds the value to be transferred (reloaded) automatically to the counter as the initial value of the counter at the counter underflow. It is impossible to read out the value of the latch. Figure 2.4.6 the structure of the latches. For the rewrite operation of the value of the latch, refer to “ 2.4.1 Explanation of operations, (2) Rewriting the value of the counter and the latch.” qTimer 1 latch and timer 3 latch Timer 1 and timer 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 and timer 3 (T1,T3) [Address 2416, 26 16] B Functions At reset R W × 1 0 •Set “0016 to FF 16” as timers 1 or 3 count value . to •The values of each timer are set to the 7 respective latches and transferred automatically to the respective counters at the counter underflow. qTimer 2 latch Timer 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address 2516] B 0 1 to 7 Functions •Set “0016 to FF 16” as timer 2 count value . •The value of timer 2 is set to the timer 2 latch and transferred automatically to the timer 2 counter at the timer 2 counter underflow. At reset R W × 1 0 × Fig. 2.4.6 Structure of latches 2–90 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 sCounters The counters count the count source V1. Figure 2.4.7 shows the structure of the timer counters. The value of the counter is decremented by 1 each time a count source is input. The division ratio of the counters is represented by the following expression. Division ratio of the counter = 1 the counter initial value + 1 When the timer is read out, the value of the counter (count value) is read out. For the rewriting operation for the value of the counter, refer to “ 2.4.1 Explanation of operations, (2) Rewriting the value of the counter and the latch.” V 1: For count source selection, refer to “ 2.4.2 Related registers, (2) Timer 123 mode register.” qTimer 1 counter and timer 3 counter Timer 1 and timer 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 and timer 3 (T1, T3) [Address 2416, 2616] B Functions At reset R W 1 0 •Set “0016 to FF16” as timers 1 or 3 count value. to •The value of the counter is decremented by 7 1 each time a count source is input. •The values of each timer are set to the respective counters. •The respective count values are read out by reading each timer. qTimer 2 counter Timer 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address 2516] Functions At reset R W 1 0 •Set “0016 to FF16” as timer 2 count value. •The value of the counter is decremented by 1 each time a count source is input. •When timer 2 write control bit is “0,” the value 1 of the timer 2 is set to the timer 2 counter. 0 to •The timer 2 count value is read out by reading 7 the timer 2. B Fig. 2.4.7 Structure of timer counters 3825 GROUP USER’S MANUAL 2–91 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (2) Timer 123 mode register (T123M) The timer 123 mode register (address 002916 ) consists of T OUT o utput control bit, the count source selection bits, and others. Figure 2.4.8 shows the structure of the timer 123 mode register. Each bit is described below. Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address 29 16] B 0 Name TOUT output active edge switch bit TOUT output control bit Timer 2 write control bit Functions 0 : Start at “H” output 1 : Start at “L” output 0 : TOUT output disabled 1 : TOUT output enabled At reset R W 0 1 0 2 3 0 : Write value in latch and counter 1 : Write value in latch only Timer 2 count source 0 : Timer 1 underflow 1 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Timer 3 count source 0 : Timer 1 underflow 1 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 0 0 4 0 Timer 1 count source 0 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 1 : f(X CIN) 6, 7 Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. Note: Internal clock φ is f(X CIN)/2 in the low-speed mode. 5 0 0 0× Fig. 2.4.8 Structure of timer 123 mode register 2–92 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 s T OUT o utput active edge switch bit (bit 0) The T OUT o utput active edge switch bit selects an initial level of the T OUT o utput. When bit 0 is “0,” the output pulse from the P5 6 /T OUT p in is started at the “H” level. When bit 0 is “1,” the output pulse from the P5 6 /T OUT p in is started at the “L” level. s T OUT o utput control bit (bit 1) The T OUT o utput control bit controls the T OUT o utput. When bit 1 is “0,” the T OUT o utput is disabled. When bit 1 is “1,” the T OUT o utput is enabled. s Timer 2 write control bit (bit 2) The timer 2 write control bit controls writing to the timer 2. When bit 2 is “0,” a simultaneous write operation to both the timer 2 latch and the timer 2 counter is set. When a value is written to the timer 2, the value is set into both the timer 2 latch and the timer 2 counter at the same time. When bit 2 is “1,” a write operation to the latch only is set. When a value is written into the timer 2, the value is set into the timer 2 latch only. When a value is written into the timer 2 latch only, this rewritten value is transferred to the timer 2 counter at the first timer 2 counter underflow after rewriting. s Timer 2 count source selection bit (bit 3) The timer 2 count source selection bit selects a count source of the timer 2. Table 2.4.1 shows the relation between the timer 2 count source selection bit and count sources. Table 2.4.1 Relation between timer 2 count source selection bit and count sources bit 3 0 1 Timer 2 count source Timer 1 underflow f(XIN)/16 (In low speed mode; f(XCIN)/16) s Timer 3 count source selection bit (bit 4) The timer 3 count source selection bit selects a count source of the timer 3. Table 2.4.2 shows the relation between the timer 3 count source selection bit and count sources. Table 2.4.2 Relation between timer 3 count source selection bit and count sources bit 4 0 1 Timer 3 count source Timer 1 underflow f(XIN)/16 (In low speed mode; f(XCIN)/16) s Timer 1 count source selection bit (bit 5) The timer 1 count source selection bit selects a count source of the timer 1. Table 2.4.3 shows the relation between the timer 1 count source selection bit and count sources. Table 2.4.3 Relation between timer 1 count source selection bit and count sources Count source examples Timer 1 count source bit 5 f(XIN) = 8 MHz f(XCIN) = 32.768 kHz f(XIN)/16 (In low speed mode; f(XCIN)/16) 500 kHz 2.048 kHz 0 f(XCIN) — 32.768 kHz 1 3825 GROUP USER’S MANUAL 2–93 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (3) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16) indicate whether an interrupt request has occured or not. Figure 2.4.9 shows the structure of the interrupt request register 1 and Figure 2.4.10 shows the structure of the interrupt request register 2. The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bit can be cleared to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the interrupt enable bit (refer to the next item). For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 3C 16] B 0 1 2 3 4 5 6 7 Name INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 V V V V V V V V V : “0” can be set by software, but “1” cannot be set. Fig. 2.4.9 Structure of interrupt request register 1 2–94 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 3D16] B 0 Name Functions At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 0× CNTR 0 interrupt request bit 1 CNTR 1 interrupt request bit 2 Timer 1 interrupt request bit 3 INT2 interrupt request bit 4 INT3 interrupt request bit 5 Key input interrupt request bit 6 ADT/A-D conversion interrupt request bit 7 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. V : “0” can be set by software, but “1” cannot be set. Fig. 2.4.10 Structure of interrupt request register 2 3825 GROUP USER’S MANUAL 2–95 APPLICATION 2.4 Timer 1, timer 2, and timer 3 (4) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E 16) and the interruot contorol register 2 (address 003F 16) control each interrupt request source. Figure 2.4.11 shows the structure of the interrupt control register 1 and Figure 2.4.12 shows the structure of the interrupt control register 2. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit only is set to “1,” and the interrupt request is not accepted. When the interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 3E16] B 0 1 2 Name INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 3 Serial I/O transmit interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 2 interrupt enable bit 7 Timer 3 interrupt enable bit Fig. 2.4.11 Structure of interrupt control register 1 2–96 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 3F16 ] B 0 1 2 3 4 5 6 Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/A-D conversion interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 00 7 Fix this bit to “0.” Fig. 2.4.12 Structure of interrupt control register 2 3825 GROUP USER’S MANUAL 2–97 APPLICATION 2.4 Timer 1, timer 2, and timer 3 2.4.3 Register setting example Figure 2.4.13 shows an example of setting registers for timers 1, 2, and 3. [Notes on use] Notes 1: For using interrupt processing, set the following : •Before setting Œ below, clear the respective timer interrupt enable bits and the timer respective interrupt request bits to “0.” •After setting  below, set the respective timer interrupt enable bits to “1” (interrupts enabled). 2: The values written in the timers 1 and 3 are set into both the respective latches and the respective counters at the same time. 3: To enable the T OUT output when the timer 2 is used, set port P5 6 (this port is also used the T OUT pin) for the output mode. 4: Write values in the order of the timer 1, timer 2, and timer 3. ŒSetting of timer 123 mode register Select count source or others b7 b0 T123M : Timer 123 mode register [Address 29 16] b0 : TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output b1 : TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled b2 : Timer 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only b3 : Timer 2 count source selection bit 0 : Timer 1 underflow 1 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) b4 : Timer 3 count source selection bit 0 : Timer 1 underflow 1 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) b5 : Timer 1 count source selection bit 0 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) 1 : f(XCIN) Set count value to timer 1 (T1) [Address 24 16] ŽSet count value to timer 2 (T2) [Address 25 16] Set count value to timer 3 (T3) [Address 26 16] Fig. 2.4.13 Example of setting registers for timers 1, 2, and 3 2–98 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 2.4.4 Application example Timer mode: Clock function (measurement of one second) Outline: T he input clock is divided by timer, with a timer 1 interrupt caused every 0.4 ms, 1 second is counted. Thus, the clock is counted up every second. Specification: • Division of f(X CIN) = 32 kHz by timer 1 causes an interrupt. •The counter value counted by the timer 1 interrupt is checked in the main routine. If 1 second has elapsed, the clock counts up. Figure 2.4.14 shows the setting of the related registers and Figure 2.4.15 shows the control procedure. b7 b0 1 X X X X X T123M : Timer 123 mode register [Address 2916] b5 : Timer 1 count source selection bit 1 : f(XCIN) : Noting is allocated 7F16 T1 : Timer 1 [Address 2416] Set “division ratio – 1 (127 : 7F16) ” in the timer 1 Notes 1 : 1 second = 1/32 kHz ! (127 + 1) ! 250 Division ratio 2 : Write values in the order of the timer 1, timer 2, and timer 3. Counted in interrupt processing b7 b0 0 X X X X 1 X X ICON2 : Interrupt control register 2 [Address 3F16] b2 : Timer 1 interrupt enable bit 1 : Interrupt enabled Fig. 2.4.14 Setting of related registers 3825 GROUP USER’S MANUAL 2–99 APPLICATION 2.4 Timer 1, timer 2, and timer 3 RESET Initialization CLT CLD SEI ICON2 (Address 3F16) ← 0XXXX0XX2 T123M (Address 2916) ← XX1XXXXX2 T1 (Address 2416) ← 7F16 (128 – 1) All interrupts; Disabled Timer 1 interrupt; Disabled Connect timer 1 Set “division ratio – 1” to timer 1 (Set in the order of timer 1, timer 2, and timer 3) Timer count start Timer 1 interrupt; Enabled Interrupts; Enabled ICON2 (Address 3F16) ← 0XXXX1XX2 CLI Interrupts every 0.4 ms Timer 1 interrupt processing routine 1 second counter + 1 Clock stop ? Y Check if the clock has already been set N 1 second has elapsed ? (1 second counter = 250 ?) Y Clear 1 second counter V Count up clock (Second—Year) Clear the counter counted by interrupt processing N Check a lapse of 1 second RTI Main processing (Note) ← 7F16 T1 (Address 2416) IREQ2 (Address 3D16), bit 2 ← 0 1 second counter ←0 Note : This processing is performed only at completing to set the clock Specify so that all processing within the loop markedV is repeated in a cycle of 1 second or less When restarting the clock from zero second after completing to set the clock, set timers again. Fig. 2.4.15 Control procedure 2–100 3825 GROUP USER’S MANUAL APPLICATION 2.4 Timer 1, timer 2, and timer 3 2.4.5 Notes on use (1) Notes on using timer 1 to timer 3 sWhen the count sources of timers 1 to 3 are switched, a short pulse occurs in counted input signals, so the timer count value may change greatly. sWhen the timer 1 output is selected as a count source of timer 2 or timer 3, a short pulse occurs in the output signal at writing value into the timer 1, so the count value of the timer 2 or timer 3 may change greatly. sFor the above reasons, set values in the order of timer 1, timer 2, and timer 3 after setting their count sources. (2) Timer 2 write control When writing to the latch only is selected, the value written into the timer 2 (address 002516) is written only in the latch for reloading. This rewritten value is transferred to the timer 2 counter at the first underflow after rewriting. Usually, a value is written in both the latch and the counter at the same time. That is, when a value is written to timer, it is set in both the latch and the counter. (3) Timer 2 output control In the timer 2 (T OUT) output enable state, a signal whose polarity is reversed each time the timer 2 counter underflows is output from the TOUT pin. In this case, set the port P56 (this is used as the TOUT pin) for the output mode. 3825 GROUP USER’S MANUAL 2–101 APPLICATION 2.5 Serial I/O 2.5 Serial I/O 2.5.1 Explanation of operations As a serial I/O1, it is possible to select either the clock synchronous serial I/O mode or the clock asynchronous serial I/O (UART) mode. This section describes operations in both the clock synchronous mode and the clock asynchronous (UART) mode. When serial I/O is actually used, refer to “ 2.5.4 Register setting example.” (1) Clock synchronous serial I/O mode In the clock synchronous mode, 8 shift clocks generated in the clock control circuit are used as synchronizing clocks for transfer. In synchronization with these shift clocks, the transmit operation on the transmitter and the receive operation on the receiver are simultaneously executed. The transmitter transmits each 1-bit data from the P45/TxD pin in synchronization with t he falling of the shift clocks. The receiver receives each 1-bit data from the P44/RxD pin in synchronization with t he rising of the shift clocks. Figure 2.5.1 shows an external connection example in the clock synchronous mode. 3825 group Œ XIN 8 Receive buffer register Receive shift register 1/4 Clock control circuit BRG 1/(n+1) 1/4 Transmit shift register Transmit buffer register 8 3825 group  8 Transmit buffer register Transmit shift register Clock control circuit RxD TxD SCLK SCLK TxD RxD Receive shift register Receive buffer register 8 Internal clock is selected External clock is selected Fig. 2.5.1 External connection example in clock synchronous mode 2–102 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O sShift clock Ordinarily, when clock synchronous transfer is performed between microcomputers, an internal clock is selected for one of them, and it outputs 8 shift clocks generated by a start of transmit operation from the P46/SCLK pin. An external clock is selected for the other microcomputer, and it uses the clock input from the P4 6/S CLK p in as a shift clock. Figure 2.5.2 shows a shift clock. 3825 group Œ XIN 8 Receive buffer register Receive shift register 1/4 Clock control circuit BRG 1/(n+1) SCLK 1/4 TxD RxD 3825 group  8 Transmit buffer register Transmit shift register Clock control circuit RxD Shift clock TxD SCLK Transmit shift register Transmit buffer register 8 Receive shift register Receive buffer register 8 Internal clock is selected Fig. 2.5.2 Shift clock External clock is selected 3825 GROUP USER’S MANUAL 2–103 APPLICATION 2.5 Serial I/O s Data transfer rate (baud rate) When an internal clock is used, the data transfer rate (baud rate), which is a shift clock frequency in the clock synchronous mode, is determined by baud rate generator (BRG). When the BRG count source selection bit (bit 0) of the serial I/O control register (address 001A16) is “0,” XIN pin input clock is input to the BRG, when this bit is “1,” X IN p in input clock divided by 4 is input to the BRG. The expression for baud rate is shown below. qWhen selecting an internal clock (Using BRG) Baud rate = Division ratio [bps] XIN pin input V1 ! ( BRG setting value V2 + 1) ! 4 V 1 Division ratio; Select “1,” or “4” V 2 BRG setting value; 0 to 255 (00 16 t o FF 16) qWhen selecting an external clock Baud rate = Frequency of input clock to P4 6/S CLK p in [bps] 2–104 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O s Transmit operation in the clock synchronous mode Transmit operation in the clock synchronous mode is described below. q Start of transmit operation A transmit operation is started by writing transmit data into the transmit buffer register (address 0018 16 ) in the transmit enable state. V1 q Transmit operation ŒBy writing transmit data into the transmit buffer register, the transmit buffer empty flag (bit 0) of the serial I/O status register (address 0019 16 ) is cleared to “0.” Data bus [Address 1816] Write transmit data b0 1 0 Transmit buffer register Serial I/O status register [Address 1916] The transmit data written in the transmit buffer register is transferred to the transmit shift register.V2 ŽWhen a data transfer from the transmit buffer register to the transmit shift register is completed, the transmit buffer empty flag is set to “1.” V3 The transmit data transferred to the transmit shift register is output from the P4 5/TxD pin in synchronization with the falling of the shift clocks.  The data is output from the least significant bit of the transmit shift register. Each time 1bit data is output, the data of the transmit shift register is shifted by 1 bit toward the least significant bit. Transmit buffer register Transfer transmit data Transmit shift register Serial I/O status register [Address 1916] 0 1 b0 b0 D 7 D 6 D5 D 4 D 3 D2 D 1 Transmit shift register D0 P45/TxD b0 D 7 D6 D 5 D 4 D3 D 2 Transmit shift register D1 P45/TxD V1: Initialization of register or others for a transmit operation. Refer to “2.5.4 Register setting example.” V 2: When the transmit interrupt source selection bit (bit 3) of the serial I/O control register (address 001A16) is set to “0,” a serial I/O transmit interrupt request occurs immediately after transfer in  . When this bit is set to “1,” a transmit interrupt request occurs at the time of ’. V 3: While the transmit buffer empty flag is “1,” it is possible to write the next transmit data into the transmit/receive buffer register. 3825 GROUP USER’S MANUAL 2–105 APPLICATION 2.5 Serial I/O ‘At the time when a transmit shift operation starts, the transmit shift register shift completion flag (bit 2) of the serial I/O status register is cleared to “0.” V4 b0 D7 D6 D 5 D4 D3 D2 D1 Transmit shift register Serial I/O status register [Address 19 16] D0 P45/TxD 1 0 b2 ’At the time when the transmit shift operation completes, the transmit shift register shift completion flag is set to “1.” V 2 V4 b0 D7 Transmit shift register Serial I/O status register [Address 19 16] 0 1 b2 P45/TxD V4: When an internal clock is used as a synchronizing clock, supplying the shift clock to the transmit shift register stops automatically at the completion of 8-bit transmission. However, when the next transmit data is written to the transmit buffer register while the transmit shift register shift completion flag is “0,” supplying the shift clock is continued. Shift clock Transmit shift register b7 b0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D0 D1 D2 D7 Fig. 2.5.3 Transmit operation in clock synchronous mode 2–106 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Write “1” Transmit enable bit Write transmit data to transmit buffer register Write next transmit data Transmit buffer empty flag Transmit shift register shift completion flag Shift clock TxD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 Fig. 2.5.4 Transmit timing example in clock synchronous mode 3825 GROUP USER’S MANUAL 2–107 APPLICATION 2.5 Serial I/O s Receive operation in the clock synchronous mode Receive operation in the clock synchronous mode is described below. qStart of receive operation A receive operation is started by writing the following data into the receive buffer register (address 001816) in the receive enable state.V1 •Transmit data in the full duplex data transfer mode •Arbitrary dummy data in the half duplex data transfer mode qReceive operation ŒEach 1-bit data is read into the receive shift register from the P44/RxD pin in synchronization with the rising of the shift clocks. P44/RxD b0 D1 D0 Receive shift register The data enters first into the most significant bit of the receive shift register. Each time 1bit data is received, the data of the receive shift register is shifted by 1 bit toward the least significant bit. Ž When 1-byte data has been input into the receive shift register, the data of the receive shift register is transferred to the receive buffer register (address 001816). V2 b0 D4 P44/RxD D3 D2 D1 D0 Receive shift register Receive shift register D7 D6 D5 D4 D3 D2 D1 D 0 Transfer receive data [Address 18 16] Receive buffer register  When a data transfer to the receive buffer register is completed, the receive buffer full flag (bit 1) of the serial I/O status register (address 001916) is set to “1,” V3 a s erial I/O receive interrupt request occurs. Serial I/O status register [Address 19 16] 0 1 b1 V1: Initialization of register or others for a receive operation. Refer to “ 2.5.4 Register setting example.” V2: When data remains without reading out the data of the receive buffer register (the receive buffer full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun error flag of the serial I/O status register is set to “1.” At this time, the data of the receive shift register is not transferred to the receive buffer register, but the former data of the receive buffer register is held. V3: The receive buffer full flag is cleared to “0” by reading out the receive buffer register. 2–108 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Shift clock b7 Receive shift register b0 D0 D1 D 0 D2 D 1 D 0 D7 D6 D5 D4 D3 D2 D1 D0 Fig. 2.5.5 Receive operation in clock synchronous mode Write “1” Receive enable bit Read out receive buffer register Receive buffer full flag Write data to receive buffer register Shift clock RxD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 Fig. 2.5.6 Receive timing example in clock synchronous mode 3825 GROUP USER’S MANUAL 2–109 APPLICATION 2.5 Serial I/O s Transmit/receive timing example in the clock synchronous mode Figure 2.5.7 shows a data transmit/receive timing example in the clock synchronous mode. 3825 group Œ TXD RXD SCLK 3825 group  TXD RXD SCLK Write “1” Transmit enable bit Write transmit data to transmit buffer register Write next transmit data Transmit buffer empty flag Transmit shift register shift completion flag Shift clock TXD Write “1” Receive enable bit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 Read out receive buffer register Receive buffer full flag D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 RXD Fig. 2.5.7 Transmit/receive timing example in clock synchronous mode 2–110 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O (2) Clock asynchronous serial I/O (UART) mode As the clock asynchronous mode (UART mode), data is transmitted and received in asynchronous form unifying the data transfer rate and the transfer data format between the transmitter and the receiver. Figure 2.5.8 shows an external connection example in the UART mode. 3825 group Œ XIN 8 Receive buffer register Receive shift register 1/4 Clock control circuit BRG 1/(n+1) 1/16 TxD RxD 3825 group  8 Transmit buffer register Transmit shift register Clock control circuit BRG 1/16 1/(n+1) XIN RxD TxD 1/4 Transmit shift register Transmit buffer register 8 Receive shift register Receive buffer register 8 3825 group Ž 8 Transmit buffer register Transmit shift register Clock control circuit BRG 1/16 1/(n+1) RxD XIN TxD 1/4 Receive shift register Receive buffer register 8 Fig. 2.5.8 External connection example in UART mode 3825 GROUP USER’S MANUAL 2–111 APPLICATION 2.5 Serial I/O s Data transfer rate (baud rate) When an internal clock is used, the data transfer rate (baud rate), which is a shift clock frequency in the UART mode, is determined by baud rate generator (BRG). When the BRG count source selection bit (bit 0) of the serial I/O control register (address 001A16) is “0,” X IN p in input clock is input to the BRG, when this bit is “0,” XIN pin input clock divided by 4 is input to the BRG. The expression for baud rate is shown below. qWhen selecting an internal clock (Using BRG) Baud rate = Division ratio [bps] XIN pin input V1 ! ( BRG setting value V2 + 1) ! 16 V 1 Division ratio; Select “1,” or “4” V 2 BRG setting value; 0 to 255 (00 16 t o FF 16) qWhen selecting an external clock Frequency of input clock to P4 6/S CLK p in 16 Baud rate = [bps] Table 2.5.1 Baud rate selection table (reference values) Baud rates [bps] BRG count source At X IN i nput = 4.9152 MHz 300 600 1200 2400 4800 9600 19200 38400 76800 153600 307200 At X IN i nput = 8 MHz 488.28125 976.5625 1953.125 3906.25 7812.5 15625 31250 62500 125000 250000 500000 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 X IN i nput/4 XIN i nput XIN i nput 255 (FF 16) 127 (7F 16) 63 (3F 16) 31 (1F 16) 15 (0F 16) 7 (07 16 ) 3 (03 16 ) 1 (01 16 ) 0 (00 16 ) 1 (01 16 ) 0 (00 16 ) BRG setting value 2–112 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O sTransfer data format Data transfer format is set by the UART control register (address 001B16 ). Figure 2.5.9 shows a transfer data format in the UART mode, Table 2.5.2, the each bit function of UART transmit data, Figure 2.5.10, all transfer data formats in the UART mode. qFor 1ST–8DATA–1PA–2SP Transmit data Data bit (8 bits) Next transmit data (at continuous output) ST LSB D0 D1 D6 MSB D7 PA SP SP ST D0 D1 Fig. 2.5.9 Transfer data format in UART mode Table 2.5.2 Each bit function of UART transmit data Bit ST (Start bit) DATA (Data bit) PA (Parity bit) Functions Indicates a start of data transmission. A “L” signal for one bit is added just before transmit data. Indicates the transmit data written in the transmit buffer register, “0 2” data is a “L” signal and “1 2 ” data is a “H” signal. These bits are called as character bits. To improve the reliability of data, this bit is added just after the last data bit. The value of this bit changes in accordance with the value of the parity selection bit so that the number of “1” in the transmit/receive data (including the parity bit) can always be an even or an odd number. Indicates an completion of data transmission. This bit is added just after the last data bit (or just after a parity bit in the parity checking enabled). As a stop bit, a “H” signal for 1 bit or 2 bits is output. SP (Stop bit) 3825 GROUP USER’S MANUAL 2–113 APPLICATION 2.5 Serial I/O ST Di PA SP : Start bit : Data bit : Parity bit : Stop bit qFor 7-bit UART mode ST ST ST ST LSB D0 LSB D0 LSB D0 LSB D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D4 D4 D4 D4 D5 D5 D5 D5 MSB D6 MSB D6 MSB D6 MSB D6 SP SP PA PA SP SP SP SP qFor 8-bit UART mode ST ST ST ST LSB D0 LSB D0 LSB D0 LSB D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 MSB D7 MSB D7 MSB D7 MSB D7 SP SP PA PA SP SP SP SP Fig. 2.5.10 All transfer data formats in UART mode 2–114 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O s Transmit operation in the UART mode Transmit operation in the UART mode is described below. q Start of transmit operation A transmit operation is started by writing transmit data into the transmit buffer register (address 0018 16 ) in the transmit enable state. V1 q Transmit operation ŒBy writing transmit data into the transmit buffer register, the transmit buffer empty flag (bit 0) of the serial I/O status register (address 0019 16 ) is cleared to “0.” Data bus [Address 18 16] Write transmit data Transmit buffer register The transmit data written in the transmit buffer register is transferred to the transmit shift register.V2 Serial I/O status register [Address 19 16] b0 1 0 Transmit buffer register Transfer transmit data Transmit shift register ŽWhen a data transfer from the transmit buffer register to the transmit shift register is completed, the transmit buffer empty flag is set to “1.” V3 Serial I/O status register [Address 19 16] 0 1 b0 The transmit data transferred to the transmit shift register is output from the P4 5/TxD pin in synchronization with the falling of the shift clock, beginning with the start bit. A start bit, a parity bit and a stop bit are automatically generated and output in accordance with the contents set in the UART control register.  The data is output from the least significant bit of the transmit shift register. Each time 1bit data is output, the data of the transmit shift register is shifted by 1 bit toward the least significant bit. b0 D7 D 6 D5 D4 D3 D2 D1 D0 Transmit shift register ST P45/TxD b0 D7 D6 D5 D4 D3 D 2 D1 Transmit shift register D0 P45/TxD V1: Initialization of register or others for a transmit operation. Refer to “2.5.4 Register setting example.” V 2: When the transmit interrupt source selection bit (bit 3) of the serial I/O control register (address 001A16) is set to “0,” a serial I/O transmit interrupt request occurs immediately after transfer in . When this bit is set to “1,” a transmit interrupt request occurs at the time of ’. V 3: While the transmit buffer empty flag is “1,” it is possible to write the next transmit data into the transmit/receive buffer register. 3825 GROUP USER’S MANUAL 2–115 APPLICATION 2.5 Serial I/O ‘At the time when a transmit shift operation starts, the transmit shift register shift completion flag (bit 2) of the serial I/O status register is cleared to “0.” V4 b0 D7 D6 D5 D4 D3 D 2 D1 D0 Transmit shift register Serial I/O status register [Address 19 16] ST P45/TxD 1 0 b2 SP P45/TxD ’After the lapse of a 1/2 period V5 of the shift clock from a transmission start of stop bit, the transmit shift register shift completion flag is set to “1.” V2 V4 Serial I/O status register [Address 19 16] 0 1 b2 V4: When an internal clock is used as a synchronizing clock, supplying the shift clock to the transmit shift register stops automatically at the completion of 8-bit transmission. However, when the next transmit data is written to the transmit buffer register while the transmit shift register shift completion flag is “0,” supplying the shift clock is continued. V 5: In the case of 2 stop bits, after the lapse of a 1/2 period of the shift clock from a start of the second stop bit transmission. Shift clock Write transmit data to transmit buffer register Write next transmit data Transmit buffer empty flag Transmit shift register shift completion flag TXD ST D0 D1 D2 D6 PAR SP SP ST D0 Fig. 2.5.11 Transmit timing example in UART mode 2–116 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O s Receive operation in the UART mode Receive operation in the UART mode is described below. q Start of receive operation In the receive enable state, V 1 s et the receive enable bit (bit 5) of the serial I/O control register (address 001A 16 ) into the enabled state (“1”). With this operation, a start bit is detected and a receive operation of serial data is started. q Receive operation Œ With the lapse of a 1/2 period of the shift clock from detection of the falling of the P4 4/ RxD pin input, the P4 4 /RxD pin level is checked. When it is “L” level, the bit is judged as a start bit. When it is “H” level, the bit is judged as noise, so the receive operation is stopped, being put into wait status for a start bit again. Each 1-bit data is read into the receive shift register from the P44 /RxD pin in synchronization with the rising of the shift clocks. P44/RXD Shift clock R XD (Noise) R XD (ST) b0 D1 D0 Receive shift register Ž The data after the detection of the start bit enters first into the most significant bit of the receive shift register. Each time 1-bit data is received, the data of the receive shift register is shifted by 1 bit toward the least significant bit.  When a specified number of bits has been input into the receive shift register, the data of the receive shift register are transferred to the receive buffer register (address 0018 16). V2V3 b0 D4 P44/RXD D3 D2 D1 D0 Receive shift register Receive shift register D7 D6 D5 D4 D3 D2 D1 D0 Transfer receive data [Address 18 16] Receive buffer register V 1: Initialization of register or others for a receive operation. Refer to “2.5.4 Register setting example.” V 2: When the data bit length is 7 bits, bits 0 to 6 of the receive buffer register are receive data, and bit 7 (MSB) is cleared to “0.” V 3: When data remains without reading out the data of the receive buffer register (the receive buffer full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun error flag of the serial I/O status register is set to “1.” At this time, the data of the receive shift register is not transferred to the receive buffer register, but the former data of the receive buffer register is held. 3825 GROUP USER’S MANUAL 2–117 APPLICATION 2.5 Serial I/O  After the lapse of a 1/2 period of the shift clock from a reception start of stop bit, the receive buffer full flag (bit 1) of the serial I/O status register is set to “1.” And a serial I/O receive interrupt request occurs. ‘Error flag detection is performed concurrently with the occurrence of a serial I/O receive interrupt request. V4: The receive buffer full flag is cleared to “0” by reading out the receive buffer register. Shift clock RXD (SP) Serial I/O status register [Address 1916] 0 1 b1 Write “1” Receive enable bit Start receiving at falling of ST Check that ST is “L” level RXD ST D0 D1 D2 D6 PAR SP SP ST D0 Shift clock Fig. 2.5.12 Receive timing example in UART mode (3) Processing upon occurrence of errors s Parity error, framing error, or summing error When a parity error, a framing error, or a summing error occurs, the flag corresponding to each error in the serial I/O status register is set to “1.” These flags are not cleared to “0” automatically, so set them to “0” by software. These flags are set to “0” by one of the following operations. •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register s Overrun error An overrun error occurs when data is already input in the receive buffer register and yet all data is input in the receive shift register. If an overrun error occurs, the data of the receive shift register is not transferred and the data of the receive buffer register is held. At this time, even if the data of the receive buffer register is read out, the data of the receive shift register is not transferred. Consequently, the data of the receive shift register becomes unreadable, so that the receive data becomes invalid. If an overrun error occurs, after set the overrun error flag of the serial I/O status register to “0,” perform a receive operation again. The overrun error flag is set to “0” by one of the following operations. •Set the serial I/O enable bit to “0” •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register 2–118 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O 2.5.2 Pins The serial I/O uses 4 pins, namely, pins for data transmit, data receive, shift clock transmit/receive, and receive enable signal output. All these pins are also used as port P4 and switched their functions by the serial I/O enable bit (bit 7) and S RDY o utput enable bit (bit 2) of the serial I/O control register (address 001A16). The function of each pin is described below. (1) Data transmit pin [TxD] This pin outputs each bit of transmit data and is used as port P45. When the serial I/O enable bit of the serial I/O control register is set to “1,” this pin functions as a serial I/O data output pin. (2) Data receive pin [RxD] This pin inputs each bit of receive data and is used as port P4 4. When the serial I/O enable bit of the serial I/O control register is set to “1,” this pin functions as a serial I/O data input pin. (3) Shift clock transmit/receive pin [SCLK] sClock synchronous mode This pin inputs (receives from the outside) or outputs (supplies to the outside) a shift clock used for transmission and reception. When the serial I/O synchronization clock selection bit (bit 1) of the serial I/O control register is set to “0” (use of internal clock), a shift clock is output to the outside. When this bit is set to “1” (use of external clock), a shift clock is input from the outside. sUART mode When the serial I/O synchronization clock selection bit (bit 1) of the serial I/O control register is set to “1” (use of external clock), a shift clock is supplied from the outside. When this bit is set to “0” (use of internal clock), this pin does not function. (4) Receive enable signal output pin [S RDY] This pin notifies the outside of the receive enable state in the clock synchronous mode. This pin does not function in the UART mode. •The S RDY o utput enable bit (bit 2) of the serial I/O control register is set to “1.” •The transmit enable bit (bit 4) of the serial I/O control register is set to “1.” When the above two conditions are satisfied, the pin level changes from “H” to “L” at the timing which data is written into the receive buffer register, notifying the outside of the receive enable state. 3825 GROUP USER’S MANUAL 2–119 APPLICATION 2.5 Serial I/O 2.5.3 Related registers Figure 2.5.13 shows the memory allocation of serial I/O-related registers. They are the transmit/receive buffer register, serial I/O status register, serial I/O control register, and UART control register. (1) Transmit/receive buffer register (TB/RB) This register (adress 0018 16) is used to write serial I/O transmit data or to read receive data (used for both the clock synchronous mode and the UART mode). For data transmission, transmit data is written into this register. Received data is obtained by reading out this register. Address 001816 001916 001A16 001B16 Transmit/receive buffer register (TB/RB) Serial I/O status register s (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Fig. 2.5.13 Memory allocation of serial I/O-related registers Transmit/receive buffer register b7b6b5b4b3b2b1b0 Transmit/receive buffer register(TB/RB) [ Address 18 16] Functions At reset R W B 0 At transmit ? to • Set “ 00 16 to FF16” as transmit data. 7 • The transmit data is transferred automatically to transmit shift register by writing transmit data. At receive • When all receive data has been input into the receive shift register, the receive data is automatically transferred to this register. Fig. 2.5.14 Structure of transmit/receive buffer register 2–120 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O (2) Serial I/O status register (SIOSTS) This register (address 0019 16 ) consists of the following flags: •flags representing the states of the registers used for transmission/reception •error flags. This is a read-only register. Bit 7 is unused and set to “1” at reading. Serial I/O status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status register (SIOSTS) [Address 19 16] B 0 1 2 3 4 5 6 7 Name Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Transmit shift register shift completion flag (TSC) Overrun error flag (OE) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) Functions 0: Buffer full 1: Buffer empty 0: Buffer empty 1: Buffer full 0: Transmit shift in progress 1: Transmit shift completed 0: No error 1: Overrun error 0: No error 1: Parity error 0: No error 1: Framing error 0: (OE) U (PE) U (FE) = 0 1: (OE) U (PE) U (FE) = 1 At reset R W × 0 0 0 0 0 0 0 1 × × × × × × 1× Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading. Fig. 2.5.15 Structure of serial I/O status register s Transmit buffer empty flag (bit 0) This flag is automatically cleared to “0” by writing transmit data into the transmit buffer register. After the transmit data is written in the transmit buffer register, it is transferred to the transmit shift register. When this transfer is completed and the transmit buffer register becomes empty, this flag is automatically is set to “1.” It is possible to write transmit data into the transmit buffer register only while the transmit buffer empty flag is “1.” This flag is valid in both the clock synchronous mode and the UART mode. s Receive buffer full flag (bit 1) When all receive data has been input to the receive shift register and then this receive data is transferred to the receive buffer register, this flag is automatically is set to “1.” When the transferred receive data is read out from the receive buffer register, the flag is automatically is cleared to “0.” If all the next receive data is input to the receive shift register when the receive buffer flag is “1” (the receive buffer register is not yet read out), the overrun error flag is set to “1.” This flag is valid in both the clock synchronous mode and the UART mode. 3825 GROUP USER’S MANUAL 2–121 APPLICATION 2.5 Serial I/O s Transmit shift register shift completion flag (bit 2) When a shift operation (transmission of the first data bit) is started by shift clock after transmit data is transferred to the transmit shift register, this flag is cleared to “0.” When the shift operation is completed (completion of transmission of the last data bit), the flag is set to “1.” This flag is valid in both the clock synchronous mode and the UART mode. s Overrun error flag (bit 3) If all the next receive data is input to the receive shift register when data has been input (not read out) in the receive buffer register, this flag is set to “1” (occurrence of an overrun error). This flag is set to “0” by one of the following operations. •Set the serial I/O enable bit to “0” •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register This flag is valid in both the synchronous mode and the UART mode. s Parity error flag (bit 4) In the UART mode, this flag checks an even parity or odd parity by hardware. When the parity of received data is different from the set parity, this flag is set to “1.” This flag is set to “0” by one of the following operations. •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register This flag is valid only in the parity enable state in the UART mode. s Framing error flag (bit 5) In the UART mode, this flag judges whether frame synchronization is abnormal. When the stop bit of receive data cannot be received at the set timing, this flag is set to “1.” This flag is set to “0” by one of the following operations. •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register This flag is valid only in the UART mode. s Summing error flag (bit 6) This flag is set to “1” when an overrun error, parity error, or framing error occurs. This flag is set to “0” by one of the following operations. •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register This flag is valid in both the clock synchronous mode and the UART mode. 2–122 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O (3) Serial I/O control register (SIOCON) This register (address 001A16) controls various functions related to the serial I/O, such as transmit/ receive modes, clocks, and pin functions. All the bits of this register are read and written by software. Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address 1A 16] B 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Functions 0: f(XIN) 1: f(XIN)/4 •In clock synchronous mode 0: BRG output/4 1: External clock input •In UART mode 0: BRG output/16 1: External clock input/16 2 SRDY output enable bit (SRDY) 0: P47/SRDY pin operates as I/O port P4 7 1: P47/SRDY pin operates as signal output pin SRDY (SRDY signal indicates receive enable state) 0: When transmit buffer has emptied 1: When transmit shift operation is completed 0: Transmit disabled 1: Transmit enabled 0: Receive disabled 1: Receive enabled 0: Clock asynchronous serial I/O (UART) mode 1: Clock synchronous serial I/O mode 0: Serial I/O disabled (pins P4 4–P47 operate as I/O pins) 1: Serial I/O enabled (pins P4 4–P47 operate as serial I/O pins) 0 At reset R W 0 0 3 Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O mode selection bit (SIOM) Serial I/O enable bit (SIOE) 0 4 5 6 0 0 0 7 0 Fig. 2.5.16 Structure of serial I/O control register 3825 GROUP USER’S MANUAL 2–123 APPLICATION 2.5 Serial I/O s BRG count source selection bit (bit 0) This bit selects a count source to be input to the BRG. In the “0” state, an undivided XIN input signal is input to the BRG. In the “1” state, an XIN i nput signal divided by 4 is input to the BRG. s Serial I/O synchronous clock selection bit (bit 1) This bit selects a synchronizing clock to be used in the serial I/O1. qClock synchronous mode When this bit is set to “0,” a BRG output divided by 4 becomes a shift clock. In the “1” state, an external clock (P4 6/SCLK p in input) becomes a shift clock as it is. qUART mode In the “0” state, a BRG output divided by 16 becomes a shift clock. In the “1” state, an external clock (P4 6/SCLK p in input) divided by 16 becomes a shift clock. s SRDY o utput enable bit (bit 2) When the S RDY f unction is used in the clock synchronous mode, set this bit to “1.” In the “0” state, the P47 /S RDY p in functions as an I/O port P47. In the UART mode, the value of this bit is invalid, so that the P4 7/S RDY p in functions as an I/O port P47. s Transmit interrupt source selection bit (bit 3) This bit determines a source which generates a serial I/O transmit interrupt request. In the “0” state, a serial I/O transmit interrupt request occurs at the time when the values of the transmit buffer register are transferred to the transmit shift register. In the “1” state, a serial I/O transmit interrupt request occurs at the time when the shift operation of the transmit shift register is completed. s Transmit enable bit (bit 4) This bit controls a transmit operation. This bit controls as shown in Table 2.5.3 only when the serial I/O enable bit is “1” (serial I/O enabled). When the serial I/O enable bit is “0” (serial I/O disabled), this bit is invalid. Table 2.5.3 Control contents of transmit enable bit Transmit enable bit 0 1 P4 5/TXD pin function Port P4 5 Data transmit pin T X D Transmit buffer empty flag Set to “0” Flag function is valid V1 Transmit shift register shift completion flag V2 V 1: Bit 0 of serial I/O status register V 2: Bit 2 of serial I/O status register 2–124 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O s Receive enable bit (bit 5) This bit controls receive operation. This bit controls as shown in Table 2.5.4 only when the serial I/O enable bit (bit 7) is “1” (serial I/O enabled). When the serial I/O enable bit is “0” (serial I/O disabled), this bit is invalid. Table 2.5.4 Control contents of receive enable bit Receive enable bit 0 1 P44 /RX D pin function Port P44 Data receive pin RX D Receive buffer full flag Set to “0” Flag function is valid V1 Each error flag V2 V 1: Bit 1 of serial I/O status register V 2: Bits 3, 4, 5, and 6 of serial I/O status register s Serial I/O mode selection bit (bit 6) This bit selects a transmit/receive mode of the serial I/O. In the UART mode, set this bit to “0.” In the clock synchronous mode, set it to “1.” s Serial I/O enable bit (bit 7) When the serial I/O function is used, set this bit to “1.” When the bit is set to “1,” the pins P4 4/RxD, P4 5/TxD, and P4 6/SCLK function as RxD, TxD, and S CLK respectively (Furthermore, when the SRDY o utput enable bit is set to “1,” the P47/S RDY p in functions as an S RDY p in). In the “0” state, they function as ports P4 4–P4 7 r espectively. 3825 GROUP USER’S MANUAL 2–125 APPLICATION 2.5 Serial I/O (4) UART control register (UARTCON) This register (address 001B 16) controls the transfer data format in the UART mode and the output format of the P45 /TxD pin. UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address 1B 16] B Name Functions 0: 8 bits 0 Character length selection bit (CHAS) 1: 7 bits 0: Parity checking disabled 1 Parity enable bit 1: Parity checking enabled (PARE) 0: Even parity 2 Parity selection bit 1: Odd parity (PARS) 0: 1 stop bit 3 Stop bit length selection bit (STPS) 1: 2 stop bits 4 P45/TxD P-channel 0: CMOS output (in output mode) output disable bit 1: N-channel open-drain output (POFF) (in output mode) 5 Nothing is allocated. These bits cannot be written to to and are fixed to “1” at reading. 7 At reset R W 0 0 0 0 0 1 1× Fig. 2.5.17 Structure of UART control register s Character length selection bit (bit 0) This bit selects data bit length of the UART transfer data format. In the “0” state, the data bit length is 8 bits. In the “1” state, the data bit length is 7 bits. s Parity enable bit (bit 1) This bit is set to “1” to make a parity check and to “0” to make no parity check. In the “1” state, the parity error flag becomes valid. s Parity selection bit (bit 2) This bit selects a parity type of the UART transfer data format. In the “0” state, the parity type is an even parity. In the “1” state, it is an odd parity. s Stop bit length selection bit (bit 3) This bit selects a stop bit length of the UART transfer data format. In the “0” state, the stop bit length is 1 stop bit. In the “1” state, the stop bit length is 2 stop bits. s P45/TxD P-channel output disable bit (bit 4) This bit controls the output type of the P4 5 /TxD pin. In the “0” state, the output type is CMOS output in the output mode. In the “1” state, the output type is N-channel open-drain output in the output mode. The 5 low-order bits of the UART control register can be read and written. The 3 high-order bits are unused and read-only bits. At reading, all the bits are set to “1.” 2–126 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Table 2.5.5 Relation between UART control register and transfer data formats UART control register Transfer data format b3 b2 b1 b0 0 0 0 0 1 1 1 1 X X X X X X X X 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 ST–8 ST–7 ST–8 ST–7 ST–8 ST–7 ST–8 ST–7 DATA–1 DATA–1 DATA–1 DATA–1 DATA–2 DATA–2 DATA–1 DATA–1 SP SP PA–1 PA–1 SP SP PA–2 PA–2 SP SP SP SP X: “0” or “1” ST: Start bit DATA: Data bit PA: Parity bit SP: Stop bit 3825 GROUP USER’S MANUAL 2–127 APPLICATION 2.5 Serial I/O 2.5.4 Register setting example (1) Clock synchronous serial I/O mode Figure 2.5.18 and Figure 2.5.19 show a transmitting method in the clock synchronous mode. Figure 2.5.20 and Figure 2.5.21 show a receiving method in the clock synchronous mode. [Notes on use] Notes 1: To use an INT pin or input port for watching S RDY, set as required. 2: When an external clock is selected in setting Ž below, BRG setting is not required in setting  below. 3: In the full duplex data transfer mode, set the receive enable bit (bit 5) to “1” (receive enabled) in setting Ž below. 4: To use a serial I/O transmit interrupt, set in the following sequence. 5: When no serial I/O transmit interrupt is used, omit settings Œ, , , ‘ and “ below. ŒDisable Serial I/O transmit interrupt b7 0 b0 ICON1: Interrupt control register 1 [Address 3E16] b3: Serial I/O transmit interrupt enable bit 0: Interrupts disabled Set the value to baud rate generator (BRG) [Address 1C 16] ŽSetting of serial I/O control register Selection of clock synchronous, transmit, or others b7 11 b0 1 SIOCON: Serial I/O control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b1: Serial I/O synchronous clock selection bit (In clock synchronous mode) 0: BRG output/4 1: External clock input b2: SRDY output enable bit 0: P47/SRDY pin operates as I/O port P47 1: P47/SRDY pin operates as signal output pin SRDY (SRDY signal indicates receive enable state) b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b4: Transmit enable bit 1: Transmit enabled b5: Receive enable bit 0: Receive disabled 1: Receive enabled b6: Serial I/O mode selection bit 1: Clock synchronous serial I/O mode b7: Serial I/O enable bit 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) Continued to Figure 2.5.19 Fig. 2.5.18 Transmitting method in clock synchronous mode (1) 2–128 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Continued from Figure 2.5.18 One or more instructions (e.g., NOP) after Ž Set the serial I/O transmit interrupt request to “0” b7 0 b0 IREQ1: Interrupt request register 1 [Address 3C16] b3: Serial I/O transmit interrupt request bit 0: No interrupts request issued ‘Enable serial I/O transmit interrupt b7 1 b0 ICON: Interrupt control register 1 [Address 3E16] b3: Serial I/O transmit interrupt enable bit 1: Interrupts enabled ’Set transmit data to transmit buffer register (TB) [Address 1816] “Processing of serial I/O transmit interrupt Fig. 2.5.19 Transmitting method in clock synchronous mode (2) 3825 GROUP USER’S MANUAL 2–129 APPLICATION 2.5 Serial I/O [Notes on use] Notes 1: To use an INT pin or input port for watching S RDY, set as required. 2: When an external clock is selected in setting Ž below, BRG setting is not required in setting  below. 3: In the full duplex data transfer mode, set the receive enable bit (bit 4) to “1” (receive enabled) in setting Ž below. 4: To use a serial I/O receive interrupt, set in the following sequence. 5: When no serial I/O receive interrupt is used, omit setting Œ, , , ‘ and “ below. ŒDisable Serial I/O receive interrupt b7 0 b0 ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O receive interrupt enable bit 0: Interrupts disabled Set the value to baud rate generator (BRG) [Address 1C 16] ŽSetting of serial I/O control register Selection of clock synchronous, receive, or others b7 111 b0 SIOCON: Serial I/O control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b1: Serial I/O synchronous clock selection bit (In clock synchronous mode) 0: BRG output/4 1: External clock input b2: SRDY output enable bit 0: P47/SRDY pin operates as I/O port P47 1: P47/SRDY pin operates as signal output pin SRDY (SRDY signal indicates receive enable state) b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b4: Transmit enable bit 0: Transmit disabled 1: Transmit enabled b5: Receive enable bit 1: Receive enabled b6: Serial I/O mode selection bit 1: Clock synchronous serial I/O mode b7: Serial I/O enable bit 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) Continued to Figure 2.5.21 Fig. 2.5.20 Receiving method in clock synchronous mode (1) 2–130 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Continued from Figure 2.5.20 One or more instructions (e.g., NOP) after Ž Set the serial I/O receive interrupt request to “0” b7 0 b0 IREQ1: Interrupt request register 1 [Address 3C16] b2: Serial I/O receive interrupt request bit 0: No interrupt request issued ‘Enable serial I/O receive interrupt b7 1 b0 ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O receive interrupt enable bit 1: Interrupts enabled ’Set transmit data to receive buffer register (RB) [Address 1816] In full duplex data transfer mode, set transmit data. In half duplex data transfer mode, set arbitrary dummy data. “Processing of serial I/O receive interrupt Fig. 2.5.21 Receiving method in clock synchronous mode (2) 3825 GROUP USER’S MANUAL 2–131 APPLICATION 2.5 Serial I/O (2) Clock asynchronous serial I/O (UART) mode Figure 2.5.22 and Figure 2.5.23 show a transmitting method in the UART mode. Figure 2.5.24 and Figure 2.5.25 show a receiving method in the UART mode. [Notes on use] Notes 1: When an external clock is selected in setting Ž below, BRG setting is not required in setting  below. 2: In the full duplex data transfer mode, set the receive enable bit (bit 5) to “1” (receive enabled) in setting Ž below. 3: To use a serial I/O transmit interrupt, set in the following sequence. 4: When no serial I/O transmit interrupt is used, omit setting Œ, , ‘ and “ below. ŒDisable Serial I/O transmit interrupt b7 0 b0 ICON1: Interrupt control register 1 [Address 3E16] b3: Serial I/O transmit interrupt enable bit 0: Interrupts disabled Set the value to baud rate generator (BRG) [Address 1C16] ŽSetting of serial I/O control register Selection of clock asynchronous mode, transmit, or others b7 10 b0 1 SIOCON: Serial I/O control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b1: Serial I/O synchronous clock selection bit (In UART mode) 0: BRG output/16 1: External clock input/16 b2: SRDY output enable bit Invalied in UART mode b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b4: Transmit enable bit 1: Transmit enabled b5: Receive enable bit 0: Receive disabled 1: Receive enabled b6: Serial I/O mode selection bit 0: Clock asynchronous serial I/O (UART) mode b7: Serial I/O enable bit 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) Continued to Figure 2.5.23 Fig. 2.5.22 Transmitting method in UART mode (1) 2–132 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Continued from Figure 2.5.22 Setting of UART control register b7 b0 UARTCON: UART control register [Address 1B16] b0: Character length selection bit 0: 8 bits 1: 7 bits b1: Parity enable bit 0: Parity checking disabled 1: Parity checking enabled b2: Parity selection bit 0: Even parity 1: Odd parity b3: Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits b4: P45/TxD P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) : Nothing is allocated Set the serial I/O transmit interrupt request to “0” b7 (Allow an interval of one or more instructions after Ž) b0 IREQ1: Interrupt request register 1 [Address 3C16] 0 b3: Serial I/O transmit interrupt request bit 0: No interrupt request issued ‘Enable serial I/O transmit interrupt b7 1 b0 ICON1: Interrupt control register 1 [Address 3E16] b3: Serial I/O transmit interrupt enable bit 1: Interrupts enabled ’Set transmit data to transmit buffer register (TB) [Address 1816] “Processing of serial I/O transmit interrupt Fig. 2.5.23 Transmitting method in UART mode (2) 3825 GROUP USER’S MANUAL 2–133 APPLICATION 2.5 Serial I/O [Notes on use] Notes 1: When an external clock is selected in setting Ž below, BRG setting is not required in setting  below. 2: In the full duplex data transfer mode, set the receive enable bit (bit 4) to “1” (receive enabled) in setting Ž below. 3: To use a serial I/O receive interrupt, set in the following sequence. 4: When no serial I/O receive interrupt is used, omit setting Œ, , ‘ and ’ below. ŒDisable Serial I/O receive interrupt b7 0 b0 ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O receive interrupt enable bit 0: Interrupts disabled Set the value to baud rate generator (BRG) [Address 1C16] ŽSetting of serial I/O1 control register Selection of clock asynchronous, receive, or others b7 101 b0 SIOCON: Serial I/O control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b1: Serial I/O synchronous clock selection bit (In UART mode) 0: BRG output/16 1: External clock input/16 b2: SRDY output enable bit Invalied in UART mode b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b4: Transmit enable bit 0: Transmit disabled 1: Transmit enabled b5: Receive enable bit 1: Receive enabled b6: Serial I/O mode selection bit 0: Clock asynchronous serial I/O (UART) mode b7: Serial I/O enable bit 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) Continued to Figure 2.5.25 Fig. 2.5.24 Receiving method in UART mode (1) 2–134 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O Continued from Figure 2.5.24 Setting of UART control register b7 b0 UARTCON: UART control register [Address 1B16] b0: Character length selection bit 0: 8 bits 1: 7 bits b1: Parity enable bit 0: Parity checking disabled 1: Parity checking enabled b2: Parity selection bit 0: Even parity 1: Odd parity b3: Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits b4: P45/TxD P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) : Nothing is allocated Clear the serial I/O receive interrupt request (Allow an interval of one or more instruction after Ž) b0 b7 IREQ1: Interrupt request register 1 [Address 3C16] 0 b2: Serial I/O receive interrupt request bit 0: No interrupt issued ‘Enable serial I/O receive interrupt b7 1 b0 ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O receive interrupt enable bit 1: Interrupts enabled ’Processing of serial I/O receive interrupt Fig. 2.5.25 Receiving method in UART mode (2) 3825 GROUP USER’S MANUAL 2–135 APPLICATION 2.5 Serial I/O (3) Initialization of serial I/O operation The operating procedure of the serial I/O control register for initialization of the serial I/O operation is described below. s Initialization of receive operation By setting the receive enable bit (bit 5 of SIOCON) to “0” or setting the serial I/O enable bit (bit 7 of SIOCON) to “0,” the receive operation is stopped and initialized as shown below. The initialization items of receive operation are as follows. •Stopping and initializing the shift clock to the receive shift register. •Setting the receive shift register to “0.” •Setting each error flag (overrun error flag, parity error flag, framing error flag, summing error flag) to “0.” •Setting the receive buffer full flag (RBF) to “0.” s Initialization of transmit operation Basically, the transmit operation is stopped and initialized by setting the transmit enable bit (bit 4 of SIOCON) to “0.” The initialization items of transmit operation are as follows. •Stopping and initializing the shift clock to the transmit shift register •Setting the receive shift register to “0” (However, when an external clock is used in the clock synchronous mode, the receive shift register is not set to “0” unless the input clock of the S CLK p in is “H”). •Setting the transmit buffer empty flag (bit 0 of SIOSTS) and the transmit shift register shift completion flag (bit 2 of SIOSTS) to “0.” (When bit 4 is set to “0,” bits 0 and 2 are cleared to “0” forcibly. After that, when bit 4 is set to “1,” bits 0 and 2 are set to “1.”) When all conditions below are satisfied, initialization is not performed only by setting bit 4 of SIOCON to “0.” It is also necessary to set bit 5 of SIOCON to “0.” •In the full duplex data transfer •In the clock synchronous mode •When an internal clock is used •When bit 5 of SIOCON is “1” (receive enabled) In the clock synchronous mode of the full duplex data transfer, the same clock is used for transmission and reception. When an internal clock is used, the shift clock is started by writing data into the transmit buffer at both transmission and reception, so both transmit and receive operations use a clock generating circuit of the transmitter. Because of this, the serial I/O is designed so that even if only a receive operation is performed, the transmit circuit may be operated internally to generate a shift clock when an internal clock is used in the clock synchronous mode. Accordingly, note that the transmitter may operate even when bit 4 of SIOCON is “0.” The transmit operation cannot be initialized only by setting the serial I/O enable bit (bit 7 of SIOCON) to “0.” 2–136 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O (4) Processing upon occurrence of an errors s Parity error, framing error, or summing error If a parity error, a framing error, or a summing error occurs, the flag corresponding to each error in the serial I/O status register is set to “1.” These flags cannot be cleared to “0” automatically, so set them to “0” by software. The parity error flag, framing error flag, and summing error flag is set to “0” by setting the receive enable bit to “0” or writing dummy data into the serial I/O status register. sOverrun error An overrun error occurs when data is already input in the receive buffer register and yet all data is input in the receive shift register. If an overrun error occurs, the data of the receive shift register is not transferred and the data of the receive buffer register is held. At this time, even if the data of the receive buffer register is read out, the data of the receive shift register is not transferred. Consequently, the data of the receive shift register becomes unreadable, so that the receive data becomes invalid. If an overrun error occurs, after set the overrun error flag of the serial I/O status register to “0,” perform a receive operation again. The overrun error flag is set to “0” by one of the following operations. •Set the serial I/O enable bit to “0” •Set the receive enable bit to “0” •Write data (arbitrary) into the serial I/O status register 3825 GROUP USER’S MANUAL 2–137 APPLICATION 2.5 Serial I/O 2.5.5 Notes on use (1) Notes on clock selection The 3825 group can select either internal clock or external clock as a synchronizing clock. When an external clock is selected as an synchronizing clock in the clock synchronous mode, note the following. s In the clock synchronous mode ŒFor an external clock source, when the duty cycle is 50%, use the following clock. 1.25 MHz or less....... at V CC = 4 .0 V to 5.5 V 500 kHz or less.........at V CC = 2 .5 V to 4.0 V To change the duty cycle, set the both “H” and “L” widths as follows. 370 ns min. ............. at V CC = 4 .0 V to 5.5 V 950 ns min. ............. at V CC = 2 .5 V to 4.0 V  The shift operation of the transmit shift register or the receive shift register is continued while synchronizing clocks are input to the serial I/O circuit. Accordingly, stop a synchronizing clock input after 8 clocks are input. When the internal clock is selected, the synchronizing clock input is automatically stopped. ŽTo select an external clock as a synchronizing clock at data transmission, set the transmit enable bit to “1” and write data into the transmit buffer register while the SCLK s ignal is “H.” When an external clock is selected as a synchronizing clock in the UART mode, note the following. s In the UART mode For an external clock source, when the duty ratio is 50%, use the following clock. 5 MHz or less..... at V CC = 4 .0 V to 5.5 V 2 MHz or less..... at V CC = 2 .5 V to 4.0 V To change the duty cycle, set the “H” and “L” widths as follows. 93 ns min. ........at V CC = 4 .0 V to 5.5 V 238 ns min. ........at VCC = 2 .5 V to 4.0 V (2) For serial I/O transmit or receive interrupts ŒFor a serial I/O transmit interrupt, set a value in the serial I/O control register, then set the serial I/O transmit interrupt request bit (bit 3 at address 003C16) to “0” with the C LB i nstruction. After setting Œ , set the serial I/O transmit enable bit (bit 3 at address 003E16 ) to “1.” ŽFor a serial I/O receive interrupt, set a value in the serial I/O control register, then set the serial I/O receive interrupt request bit (bit 2 at address 003C 16) to “0” with the C LB i nstruction. After setting Ž, set the serial I/O receive interrupt enable bit (bit 2 at address 003E 16 ) to “1.” (3) Transmit interrupt request when the transmit enable bit is “1” When the transmit enable bit is set to “1,” the transmit buffer empty flag and the transmit shift register shift completion flag are set to “1.” Accordingly, even if either timing is selected as transmit interrupt generating timing, an serial I/O transmit interrupt request occurs and the serial I/O transmit interrupt request bit is set to “1.” To use a serial I/O transmit interrupt, set the transmit enable bit to “1,” then set the serial I/O transmit interrupt request bit to “0” once. After that, set the serial I/O transmit interrupt enable bit to “1” (interrupts enabled). 2–138 3825 GROUP USER’S MANUAL APPLICATION 2.5 Serial I/O (4) For disabling transmission after completion of 1-byte data transmission As a means to know the completion of data transmission, a reference to the transmit shift register shift completion flag (TSC flag) is available in the 3825 group. The TSC flag is cleared to “0” during data transmission. Upon the completion of data transmission, this flag is set to “1.” Accordingly, after confirming that the TSC flag is set to “1,” disable transmission. The transmission can thus be terminated after 1-byte transmission. However, the TSC flag is set to “1” even when the serial I/O enable bit is set to “1” (serial I/O enabled). After that, it is not cleared to “0” until transmission is started by generating a shift clock. For this reason, if transmission is disabled by referring to the TSC flag at this time, data is not transmitted. After the transmission is started, refer to the TSC flag. (5) When the P4 5/TxD pin is used as an N-channel open-drain output Bit 4 of the UART control register (address 001B16) is the P45/TxD P-channel output disable bit. The bit 4 is valid in an ordinary port, in the clock synchronous mode, or in the UART mode. When this bit is “0,” the ordinary CMOS output is selected. When the bit is “1,” the N-channel opendrain output is selected. However, do not apply to the P4 5/T X D a voltage of VCC + 0 .3 V or more even when it is used as a serial I/O function pin of the N-channel open-drain output. 3825 GROUP USER’S MANUAL 2–139 APPLICATION 2.6 A-D converter 2.6 A-D converter 2.6.1 Explanation of operations The operations of the A-D converter are described below. (1) When an internal trigger is selected (To cause an ADT/A-D conversion interrupt request upon completion of A-D conversion) s By setting bit 3 of the A-D control register (address 003416 ) to “0,” A-D conversion is started. sUpon the completion of A-D conversion, bit 3 of the A-D control register is set to “1.” At the same time, an ADT/A-D conversion interrupt request occurs. (2) When an external trigger is selected (To cause an ADT/A-D conversion interrupt request upon completion of A-D conversion) s By setting bit 3 of A-D control register to “0” and then inputting a falling signal to the ADT pin, A-D conversion is started. sUpon the completion of A-D conversion, bit 3 of the A-D control register is set to “1.” At the same time, an ADT/A-D conversion interrupt request occurs. (3) When an external trigger is selected (To cause an ADT/A-D conversion interrupt request upon inputting a falling signal to the ADT pin) s By setting bit 3 of A-D control register to “0” and then inputting a falling signal to the ADT pin, A-D conversion is started. At the same time, an ADT/A-D conversion interrupt request occurs. s Upon the completion of A-D conversion, bit 3 of the A-D control register is set to “1.” 2–140 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter 2.6.2 Conversion method As an A-D conversion method, successive comparison approximation is adopted. The comparison voltage “V ref” internally generated is compared with the analog input voltage “VIN” which is input from an analog input pin (AN 0 –AN 7 ) and the result is input successively to each bit of the A-D conversion register (address 0035 16) to obtain a digital value. (1) Function of each block The function of each block in the A-D converter is shown below. sComparison voltage generator (resistor ladder) Divides the voltage between the AV SS p in and the VREF p in by 256 and output a divided voltage to the comparator as comparison voltage “V ref.” sChannel selector Connects an analog input pin selected by bits 2 to 0 of the A-D control register (address 0034 16) to the comparator. sComparator Compares the analog input voltage “V IN” with the comparison voltage “Vref” and input the result to the A-D conversion register. (2) Internal Operation At the time when the A-D conversion is started, the following operations are automatically performed. sThe A-D conversion register becomes “00 16.” s The most significant bit of the A-D conversion register is set to “1.” sThe comparison voltage “V ref” is input to the comparator. The comparison voltage “V ref” is specified by the A-D conversion register contents “n” and the reference voltage “V REF” which is input from the V REF p in. Table 2.6.1 shows an expression for the comparison voltage “Vref.” Table 2.6.1 Expression for comparison voltage “Vref ” A-D conversion register contents “n” (decimal notation) 0 1 to 255 Vref ( V) 0 VREF 256 ! ( n – 0.5) 3825 GROUP USER’S MANUAL 2–141 APPLICATION 2.6 A-D converter s The comparison voltage “Vref” is compared 8 times with the analog input voltage “V IN.” Each time a comparison ends, the result is input to the A-D conversion register. With a change of the A-D conversion register, the comparison voltage “Vref” changes, too. Figure 2.6.1 shows changes in the A-D conversion register and comparison voltage during A-D conversion. ŒDetermination of the most significant bit (bit 7) of the A-D conversion register Bit 7 is determined by the first comparison result. The comparison voltage “Vref” is compared with the analog input voltage “VIN” and the result determines bit 7 as follows. When V ref < V IN : bit 7 holds “1” When V ref > V IN : bit 7 becomes “0” Determination of bits 6 to 0 of the A-D conversion register Bit 6 is determined by the second comparison result. First, bit 6 of the A-D conversion register is set to “1.” Next, the comparison voltage “Vref ” is compared with the analog input voltage “VIN ” and the result determines bit 6 as follows. When V ref < V IN : bit 6 holds “1” When V ref > V IN: bit 6 becomes “0” Likewise, bits 5 to 0 are determined by the third to eighth comparison results. With the above operations, the digital value (contents of the A-D conversion register) corresponding to the analog input voltage “V IN ” is determined by one bit at a time. s Upon the completion of A-D conversion, bit 3 of the A-D control register is set to “1.” An A-D conversion result can be obtained by reading out the A-D conversion register after bit 3 of the A-D control register is set to “1.” The A-D conversion result is held in the A-D conversion register until bit 3 of the A-D control register is set to “1” again after the completion of the next A-D conversion. 2–142 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter Contents of A-D conversion register A-D conversion start Reference voltage [V] 00000000 10000000 11000000 12100000 12345671 0 VREF VREF – 2 512 VREF ± VREF – VREF 2 4 512 VREF ± VREF ± VREF VREF – 2 8 4 512 VREF ± VREF ± VREF ± ..... 2 4 8 ....... ± VREF – VREF 512 256 1st comparison start 2nd comparison start 3rd comparison start 8th comparison start A-D conversion completion (8th comparison completion) 12345678 Disital value corresponding to analog input voltage m m : Value determined by m th (m = 1 to 8) result Fig. 2.6.1 Changes in A-D conversion register and comparison voltage during A-D conversion (3) Conversion time In the high-speed operation mode, A-D conversion terminates in a maximum 50 cycles (12.5 µs at f(X IN) = 8 MHz) after a start of A-D conversion. In the middle-speed operation mode, A-D conversion terminates in a maximum 56 cycles (14 µ s at f(X IN) = 8 MHz) after a start of A-D conversion. For the A-D converter, the main clock input oscillation frequency f(XIN) divided by 2 is used (Note 1), so A-D conversion time is obtained basically by the following expression. Conversion clock period = 2 f(XIN) A-D conversion time = Conversion clock period ! C onversion cycle However, the number of conversion cycles varies depending on internal clock φ a nd trigger. Notes 1: U se the A-D converter in the state where bits 5 and 7 of the CPU mode register (address 003B 16) are “0” (high-speed mode or middle-speed mode). As the comparator is composed of a capacitance coupling, use the A-D converter in a state of f(X IN) ≥ 500 kHz. 2: W hen an external trigger is selected, the A-D conversion being executed is stopped by inputting a falling signal to the ADT pin during A-D conversion, and A-D conversion is resumed. The A-D conversion register holds the previous conversion result until A-D conversion is completed. 3: When an external trigger is selected, an ADT/A-D conversion interrupt may occur by switching the interrupt source selection bit from “1” to “0” or “0” to “1.” 3825 GROUP USER’S MANUAL 2–143 APPLICATION 2.6 A-D converter (4) Equivalent connection diagram Figure 2.6.2 shows an A-D converter equivalent connection diagram. VCC VSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 b2 b1 b0 Analog input voltage VIN Sample clock VCC AVSS Chopper amplifier A-D conversion register ADT/A-D conversion interrupt request Reference voltage Vref A-D control register VREF Reference clock AVSS Built-in D-A converter Fig. 2.6.2 A-D converter equivalent connection diagram 2–144 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter 2.6.3 Pins Table 2.6.2 shows a list of pin functions used in the A-D converter. Table 2.6.2 List of pin functions used in A-D converter Functions Pins Name •Analog input voltage input pins. •Apply a voltage of AV SS–V CC. Analog input AN 0–AN7 •These pins are also used as P6 0–P6 7. •External trigger input pin. External trigger input ADT •This pin is also used as P5 7. VREF AVSS Reference voltage input Analog power source voltage input •Reference voltage input pin. •Apply a voltage of 2 V–V CC. •GND input pin. •Apply the same voltage as the VSS p in. (1) Pin-related setting sAnalog input pins (AN 0–AN 7) When using the A-D converter, select a pin to be used as an analog input pin by bits 2 to 0 of the A-D control register (address 0034 16 ). Use the A-D converter in the state where the bit of the port P6 direction register (address 000D16 ) corresponding to the pin used as an analog input pin is “0.” s External trigger input pin (ADT) When using the external trigger, set bit 5 of the A-D control register to “1.” Use the A-D converter in the state where bit 7 of the port P5 direction register (address 000B 16) is “0.” Note: The ports P5 and P6 direction registers are not readable. To set these registers, use the STA instruction, L DM i nstruction, or other instructions. 3825 GROUP USER’S MANUAL 2–145 APPLICATION 2.6 A-D converter 2.6.4 Related registers Figure 2.6.3 shows a memory allocation of the A-D converter-related registers. Each register is described below. Address 000B16 000D16 003416 003516 003B16 003D16 003F16 Port P5 direction register (P5D) Port P6 direction register(P6D) A-D control register (ADCON) A-D conversion register (AD) CPU mode register (CPUM) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) Fig. 2.6.3 Memory allocation of A-D converter-related registers 2–146 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (1) A-D control register (ADCON) The A-D control register (address 0034 16) consists of bits which controls for the A-D converter. Figure 2.6.4 shows the structure of the A-D control register. Each bit is described below. A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address 3416] B 0 1 2 Name Analog input pin selection bits Functions b2 b1 b0 At reset R W 0 0 0 0 0 0: AN 0 0 0 1: AN 1 0 1 0: AN 2 0 1 1: AN 3 1 0 0: AN 4 1 0 1: AN 5 1 1 0: AN 6 1 1 1: AN 7 3 4 A-D conversion completion bit VREF input switch bit 0: Conversion in progress 1: Conversion completed 0: OFF 1: ON 0: A-D external trigger invalid (internal trigger selected) 1: A-D external trigger valid (external trigger selected) 0: At A-D conversion completed 1: At falling of ADT pin input 1 0 5 A-D external trigger valid bit 0 6 Interrupt source selection bit 0 0× 7 Nothing is allocated. This bit cannot be written to and is fixed “0” at reading. 0 Note: When an internal trigger is selected, A-D conversion is started by setting bit 3 to “0.” Writing only “0” to bit 3 is valid. Even if “1” is written to bit 3, it is not set to “0.” Accordingly, to write values to the ADCON without affecting bit 3, set bit 3 to “1.” Fig. 2.6.4 Structure of A-D control register 3825 GROUP USER’S MANUAL 2–147 APPLICATION 2.6 A-D converter s Analog input pin selection bits: bits 2 to 0 Select an analog input pin. The pins which are not used as analog input pins of port P6 function as programmable I/O ports. s A-D conversion completion bit: bit 3 Indicates the operating state of the A-D converter. During A-D conversion, this bit is set to “1” after completion of A-D conversion. When an internal trigger is selected, A-D conversion is started by setting this bit to “0.” (Note) s V REF i nput switch bit: bit 4 Connects the VREF pin to the comparison voltage generator. When the A-D converter is used, be sure to set this bit to “1.” When the A-D converter is not used, the power dissipation is reduced by setting this bit to “0.” s A-D external trigger valid bit: bit 5 Determines whether A-D conversion is started by an external trigger or internal trigger. s Interrupt source selection bit: bit 6 Selects ADT/A-D conversion interrupt request generating timing. Notes 1: When an internal trigger is selected, set the A-D conversion completion bit after setting bits 2 to 0 and bits 6 to 4 of the A-D control register. 2: W hen an external trigger is selected, an ADT/A-D conversion interrupt may occur by switching the interrupt source selection bit from “1” to “0” or “0” to “1.” Before accepting an interrupt, set the interrupt request bit to “0” after disabling interrupts and setting the interrupt source selection bit. (2) A-D conversion register (AD) The A-D conversion register (address 0035 16 ) stores A-D conversion results. This is a read-only register. Figure 2.6.5 shows the structure of the A-D conversion register. A-D conversion register b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address 3516] Functions 0 Read-only register which stores A-D to conversion results. 7 B At reset R W 0 × Fig. 2.6.5 Structure of A-D conversion register 2–148 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (3) CPU mode register (CPUM) The CPU mode register (address 003B 16) consists of the stack page selection bit and control bits for the internal system clock φ . Use the A-D converter in the state where bits 5 and 7 of this register are “0” (high-speed mode or middle-speed mode). Figure 2.6.6 shows the structure of the CPU mode register. The operating clock of the A-D converter is the main clock input frequency f(XIN )/2. Use the A-D converter in the state of f(X IN) ≥ 500 kHz. CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register (CPUM) [Address 3B16] B 0 1 Name Processor mode bits Functions b1b0 At reset R W 0 0 00: Single-chip mode 01: 10: Not available 11: Stack page selection bit Fix this bit to “1.” Port X C switch bit 0: I/O port 1: X CIN, XCOUT 0: 0 page 1: 1 page 2 3 4 0 1 0 0 1 11 5 Main clock (X IN–XOUT) 0: Oscillating stop bit 1: Stopped 6 Main clock division ratio selection bit 0: f(X IN)/2 (high-speed mode) 1: f(X IN)/8 (middle-speed mode) 0: X IN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) 7 Internal system clock selection bit 0 Fig. 2.6.6 Structure of CPU mode register 3825 GROUP USER’S MANUAL 2–149 APPLICATION 2.6 A-D converter (4) Port P5 direction register (P5D) The port P5 direction register (address 000B16) switches the I/O direction of port P5. When an external trigger is selected, hold bit 7 of this register at “0.” Figure 2.6.7 shows the structure of the port P5 direction register. Port P5 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (P5D) [Address B 16] B Name Functions 0 : Port P5 0 input mode 1 : Port P5 0 output mode 0 : Port P5 1 input mode 1 : Port P5 1 output mode 0 : Port P5 2 input mode 1 : Port P5 2 output mode 0 : Port P5 3 input mode 1 : Port P5 3 output mode 0 : Port P5 4 input mode 1 : Port P5 4 output mode 0 : Port P5 5 input mode 1 : Port P5 5 output mode 0 : Port P5 6 input mode 1 : Port P5 6 output mode 0 : Port P5 7 input mode 1 : Port P5 7 output mode At reset R W × 0 0 0 0 0 0 0 0 × × × × × × × 0 Port P5 direction register 1 2 3 4 5 6 7 Note : Port P5 direction register cannot be read out (refer to “2.1 I/O pins” ). Fig. 2.6.7 Structure of port P5 direction register 2–150 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (5) Port P6 direction register (P6D) The port P6 direction register (address 000D 16) switches the I/O direction of port P6. Hold the bit of this register which corresponds to the port used as an analog input pin at “0.” Figure 2.6.8 shows the structure of the port P6 direction register. Port P6 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (P6D) [Address 0D 16] B Name Functions 0: Port P6 0 input mode 1: Port P6 0 output mode 0: Port P6 1 input mode 1: Port P6 1 output mode 0: Port P6 2 input mode 1: Port P6 2 output mode 0: Port P6 3 input mode 1: Port P6 3 output mode 0: Port P6 4 input mode 1: Port P6 4 output mode 0: Port P6 5 input mode 1: Port P6 5 output mode 0: Port P6 6 input mode 1: Port P6 6 output mode 0: Port P6 7 input mode 1: Port P6 7 output mode At reset R W 0 0 0 0 0 0 0 0 × × × × × × × × 0 Port P6 direction register 1 2 3 4 5 6 7 Note: Port P6 direction register cannot be read out (refer to “2.1 I/O pins” ). Fig. 2.6.8 Structure of port P6 direction register 3825 GROUP USER’S MANUAL 2–151 APPLICATION 2.6 A-D converter (6) Interrupt request register 2 (IREQ2) The interrupt request register 2 (address 003D 16) indicates whether an interrupt request has occurred or not. Figure 2.6.9 shows the structure of the interrupt request register 2. The occurrence of an ADT/A-D conversion interrupt request causes bit 6 to be set to “1.” The bit 6 is automatically cleared to “0” by the acceptance of the ADT/A-D conversion interrupt request. The interrupt request bit can be cleared to “0” by software, but it cannot be set to “1” by software. The occurrence of the ADT/A-D conversion interrupt is controlled by the ADT/A-D conversion interrupt enable bit (refer to the next item). For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 3D16] B 0 Name Functions At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 0× CNTR 0 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued 0 : No interrupt request issued 1 CNTR 1 interrupt 1 : Interrupt request issued request bit 0 : No interrupt request issued 2 Timer 1 interrupt 1 : Interrupt request issued request bit INT2 interrupt 0 : No interrupt request issued 3 request bit 1 : Interrupt request issued 0 : No interrupt request issued 4 INT3 interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 5 Key input interrupt request bit 1 : Interrupt request issued ADT/A-D conversion 0 : No interrupt request issued 6 interrupt request bit 1 : Interrupt request issued 7 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. V : “0” can be set by software, but “1” cannot be set. Fig. 2.6.9 Structure of interrupt request register 2 2–152 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (7) Interrupt control register 2 (ICON2) The interrupt contorol register 2 (address 003F 16) controls each interrupt request source. Figure 2.6.10 shows the structure of the interrupt control register 2. When bit 6 is “0,” the ADT/A-D interrupt request is disabled. When bit 6 is “1,” the ADT/A-D interrupt request is enabled. The bit 6 can be set to “0” or “1” by software. For details of interrupts, refer to “ 2.2 Interrupts.” Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] B 0 1 2 3 4 5 6 7 Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/A-D conversion interrupt enable bit Fix this bit to “0.” Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 00 Fig. 2.6.10 Structure of interrupt control register 2 3825 GROUP USER’S MANUAL 2–153 APPLICATION 2.6 A-D converter 2.6.5 Measuring various A-D converter standard characteristics The measuring various A-D converter standard characteristics is described below. (1) Absolute accuracy The absolute accuracy is the difference expressed in LSB between an output code obtained by actual measurement and an expected output code of the A-D converter with ideal characteristics. The analog input voltage at absolute accuracy measurement is assumed to be a mid-point of the input voltage width (= 1 LSB) which outputs the same code from the A-D converter with ideal characteristics. For example, when V REF = 5 .12 V, the width of 1 LSB is 20 mV. So 0 mV, 20 mV, 40 mV, 60 mV ......or 5120 mV is selected as an analog input voltage. When the A-D converter is actually used, the analog input voltage range is AV SS t o V REF. But if the VREF value is lowered, the accuracy degrades. Every output code for voltage of V REF–V CC is “FF16.” Figure 2.6.11 shows the absolute accuracy of the A-D converter. Absolute accuracy = ±2 LSB indicates that when the analog input voltage is 100 mV, the output code expected from the ideal A-D converter is “05 16 ” but the actual A-D conversion result is in the range of “03 16 ” to “07 16 .” The absolute accuracy includes a zero error and a full-scale error but not a quantization error. Output code 0916 0816 Absolute accuracy 0716 0616 0516 0416 0316 – 2LSB 0216 0116 0016 0 20 40 60 80 100 120 140 160 180 200 220 Analog input voltage (mV) + 2LSB Ideal A-D conversion characteristics Limitless resolution A-D conversion characteristics Fig. 2.6.11 Absolute accuracy of A-D converter 2–154 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (2) Differential non-linearity error The differential non-linearity error indicates the difference between the analog input voltage width in which the same code is output at actual measurement and the input voltage width (= 1 LSB) which outputs the same output code from the A-D converter with ideal characteristics. For example, when VREF = 5.12 V, the width of 1 LSB is 20 mV. However, when differential non-linearity error = ±1 LSB, the analog input voltage width which outputs the same code is 0 mV to 40 mV. Figure 2.6.12 shows the differential non-linearity error of the A-D converter. Output code 0916 0816 0716 0616 0516 0416 0316 0216 0116 0016 0 20 40 60 80 100 120 140 160 180 Differential non-linearity error 1LSB width A-D conversion characteristics at actual measurement 1LSB width Analog input voltage (mV) Fig. 2.6.12 Differential non-linearity error of A-D converter 3825 GROUP USER’S MANUAL 2–155 APPLICATION 2.6 A-D converter 2.6.6 Register setting example A register setting example when the A-D converter is used is described below. (1) Operating conditions To use the A-D converter, first set as shown in Figure 2.6.13. ŒSet the main clock oscillation frequency f(XIN) ≥ 500 kHz Apply a voltage of 2 V–VCC to reference voltage input pin VREF ŽApply same voltage as VSS pin to analog power source voltage input pin AVSS Select high-speed mode or middle-speed mode b7 00 1 b0 0 0 CPUM: CPU mode register [Address 3B16] b0, b1: Processor mode bits b1b0 00: Shingle-chip mode b2: Stack page selection bit b3: Fix this bit to “1” b4: Port XC switch bit b5: Main clock (XIN–XOUT) stop bit 0: Oscillating b6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) b7: Internal system clock selection bit 0: XIN–XOUT selected When external trigger is used Setting of port P5 direction register (Note) Set A-D trigger input pin b7 b0 0 P5D: Port P5 direction register [Address 0B16] b7: Bit corresponding to port P57 0: Input mode When internal trigger is used ‘Setting of port P6 direction register (Note) Set ports used as analog input pins to input mode b7 b0 P6D: Port P6 direction register [Address 0D16] b7: Bit corresponding to port P60 –P67 0: Input mode 1: Output mode Note: The ports P5 and P6 direction registers cannot read out. Use the STA instruction, the LDM instruction, or others for setting these registers. Fig. 2.6.13 Operating conditions for using A-D converter 2–156 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter (2) Register initialization example Figure 2.6.14 and Figure 2.6.15 show a register initialization example when an internal trigger is selected. Figure 2.6.16 and Figure 2.6.17 show a register initialization example when an external trigger is selected. ŒInitialization of A-D converter (Select analog input pin, trigger, interrupt generating timing, or others) b7 b0 011 ADCON: A-D control register [Address 3416] b2 to b0: Analog input pin selection bits b2b1b0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 b3 : A-D conversion completion bit 1: Conversion completed b4 : VREF input switch bit 1: ON b5 : A-D external trigger valid bit 0: A-D external trigger invalid (internal trigger selected) b6 : Interrupt sources selection bit 0: At A-D conversion completed 1: At falling of ADT pin input : Nothing is allocated Setting for interrupts (This is not necessary when ADT/A-D conversion interrupt is not used) b7 b0 0 PS: Processor status register b2: Interrupt disable flag 0: Interrupts enabled b7 0 b0 IREQ2: Interrupt request register 2 [Address 3D16] b6: ADT/A-D conversion interrupt request bit 0: Interrupts enabled ICON2: Interrupt control register 2 [Address 3F16] b6: ADT/A-D conversion interrupt enable bit 0: Interrupts enabled b7: Fix this bit to “0” : Nothing is allocated b7 01 b0 Continued to Figure 2.6.15 Fig. 2.6.14 Register initialization example when internal trigger is selected (1) 3825 GROUP USER’S MANUAL 2–157 APPLICATION 2.6 A-D converter Continued from Figure 2.6.14 ŽSet A-D conversion completion bit to “0,” and start A-D conversion b7 0 b0 ADCON: A-D control register [Address 3416] b3 : A-D conversion completion bit 0: Conversion in progress : Nothing is allocated A-D conversion start When no interrupt is used Confirm that A-D conversion is completed (bit 3 = “1”) b7 b0 ADCON: A-D control register [Address 3416] b3 : A-D conversion completion bit 0: Conversion in progress 1: Conversion completed : Nothing is allocated When an interrupt is used Read the A-D conversion result within ADT/ A-D conversion interrupt processing b7 b0 AD: A-D conversion register [Address 3516] A-D conversion result (Note) Note: In reading during A-D conversion (bit 3 of A-D control register = “0”), the previous A-D conversion result is read out. Read A-D conversion result b7 b0 AD: A-D conversion register [Address 3516] A-D conversion result (Note) Note: In reading during A-D conversion (bit 3 of A-D control register = “0”), the previous A-D conversion result is read out. Fig. 2.6.15 Register initialization example when internal trigger is selected (2) 2–158 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter ŒInitialization of A-D converter (Select analog input pin, trigger, interrupt generating timing, or others) b7 b0 1 11 1 ADCON: A-D control register [Address 3416] b2 to b0: Analog input pin selection bits b2b1b0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 b3 : A-D conversion completion bit 1: Conversion completed b4 : VREF input switch bit 1: ON b5 : A-D external trigger valid bit 1: A-D external trigger valid (external trigger selected) b6 : Interrupt sources selection bit 1: At falling of ADT pin input : Nothing is allocated Setting for interrupts (This is not necessary when ADT/A-D conversion interrupt is not used) b7 b0 0 PS: Processor status register b2: Interrupt disable flag 0: Interrupts enabled b7 0 b0 IREQ2: Interrupt request register 2 [Address 3D16] b6: ADT/A-D conversion interrupt request bit 0: No interrupt request issued ICON2: Interrupt control register 2 [Address 3F16] b6: ADT/A-D conversion interrupt enable bit 0: Interrupts enabled b7: Fix this bit to “0” : Nothing is allocated b7 01 b0 Continued to Figure 2.6.17 Fig. 2.6.16 Register initialization example when external trigger is selected (1) 3825 GROUP USER’S MANUAL 2–159 APPLICATION 2.6 A-D converter Continued from Figure 2.6.16 ŽInput a falling signal to ADT pin Note: If a falling signal is input to ADT pin during A-D conversion (bit 3 of A-D control register = “0”), the A-D conversion being executed is stopped. So initialize A-D conversion register again to resume the conversion. A-D conversion start When no interrupt is used Confirm that A-D conversion is completed (bit 3 = “1”) b7 b0 ADCON: A-D control register [Address 3416] b3 : A-D conversion completion bit 0: Conversion in progress 1: Conversion completed : Nothing is allocated When an interrupt is used Read the A-D conversion result within ADT/ A-D conversion interrupt processing b7 b0 AD: A-D conversion register [Address 3516] A-D conversion result (Note) Note: In reading during A-D conversion (bit 3 of A-D control register = “0”), the previous A-D conversion result is read out. Read A-D conversion result b7 b0 AD: A-D conversion register [Address 3516] A-D conversion result (Note) Note: In reading during A-D conversion (bit 3 of A-D control register = “0”), the previous A-D conversion result is read out. Fig. 2.6.17 Register initialization example when external trigger is selected (2) 2–160 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter 2.6.7 Application example: Detection of battery voltage and battery temperature Outline: T he battery voltage and its temperature are detected by using the A-D converter. Specification: • A-D conversion is performed every second and the data on battery voltage and battery temperature are input. •With an ADT/A-D conversion interrupt that occurs upon completion of A-D conversion, voltage data or temperature data is input. An analog input pin is also selected. Figure 2.6.18 shows an example of a peripheral circuit, Figure 2.6.19, setting of related registers, Figure 2.6.20, the control procedure. 3825 I/O ports + Charging circuit – AN0 AN1 Thermistor Battery pack Fig. 2.6.18 Example of peripheral circuit b7 b0 X X X XX X 0 0 P6D: Port P6 direction register [Address 0D16] b1, b0 : Bits corresponding to ports P60, P61 0: Input mode b7 b0 0 0 1 1 0 0 0 ADCON: A-D control register [Address 3416] b2, b1, b0: Analog input pin selection bits 000: AN0 V To select AN1, set “001.” b3: A-D conversion completion bit 1: Conversion completed b4: VREF input switch bit 1: ON b5: A-D external trigger valid bit 0: A-D external trigger invalid b6: Interrupt sources selection bit 0: At falling of ADT pin input b7 b0 0 1 XXX XX X ICON2: Interrupt control register 2 [Address 3F16] b6: ADT/A-D conversion interrupt enable bit 1: Interrupts enabled : Nothing is allocated Fig. 2.6.19 Setting of related registers 3825 GROUP USER’S MANUAL 2–161 APPLICATION 2.6 A-D converter RESET Initialization CLT CLD SEI P6D [Address 0D16], bits 1, 0 ←002 ICON2 [Address 3F16] ←00XXXXXX2 ADCON [Address 3416] ←X00110002 ICON2 [Address 3F16] CLI ←01XXXXX12 All interrupts; Disabled Set ports P60,P61 pin for input mode ADT/A-D conversion interrupt; Disabled Connect AN0 pin, set A-D control register Enable ADT/A-D conversion interrupt Interrupts; Enabled 1 second has elapsed? ADCON [Address 3416], b3←0 Start A-D conversion ADT/A-D conversion start Read A-D conversion register Read A-D conversion result ADT/A-D conversion interrupt occurs at completion of A-D conversion Current valid analog input pin? AN0 Voltage data processing Process input digital data AN1 Temperature data processing ADCON [Address 3416], b2, b1, b0←0012 ADCON [Address 3416], b2, b1, b0←0002 Change analog input pin (AN1↔AN0) RTI Fig. 2.6.20 Control procedure 2–162 3825 GROUP USER’S MANUAL APPLICATION 2.6 A-D converter 2.6.8 Notes on use When using the A-D converter, notes the following. (1) Operating conditions for using A-D converter Operate the A-D converter in the following conditions. sThe comparator is composed of a capacitance coupling. If the oscillation frequency is low, the charge will be lost. Accordingly, make sure that f(XIN) at least 500 kHz during A-D conversion. Do not execute the S TP i nstruction or W IT i nstruction during A-D conversion. s When an external trigger is selected, the A-D conversion being executed is stopped by inputting a falling signal to the ADT pin during A-D conversion, and A-D conversion is resumed. s Apply a voltage of 2 V–V CC t o the reference voltage input pin VREF . Note that if the VREF v alue is lowered, the accuracy degrades. s Apply the same voltage as the VSS p in to the analog power source voltage input pin AVSS. s Set the port used as an analog input pin for the input mode. (Corresponding bit of port P6 direction register (address 000D16) = “0”) (Note) Note: T he port P6 direction register cannot read out. Use the S TA i nstruction or L DM i nstruction to set the port P6 direction register. s When not using the A-D converter, connect the A-D converter power source pin AVSS t o V SS l ine which is the analog system. (2) Other notes Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µ F to 1 µ F. Further, be sure to verify the operation of application products on the user side. An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A-D comparison precision to be worse. 3825 GROUP USER’S MANUAL 2–163 APPLICATION 2.7 LCD drive control circuit 2.7 LCD drive control circuit The 3825 group includes the controller/drivers of Liquid Crystal Display (LCD). This section describes an explanation of LCD control circuit operations, pins, related registers, usage and application examples. 2.7.1 Explanation of operations (1) LCD drive waveform example Refer to “ CHAPTER 1 Hardware, LCD drive control circuit.” (2) LCD drive timing The frequency of the internal signal LCDCK and the frame frequency to generate LCD drive timing are as follows. f (LCDCK) = Count source frequency for LCDCK Division ratio of LCD circuit divider Frame frequency = f ( LCDCK) Duty ratio number 2–164 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit 2.7.2 Pins SEG 0 –SEG 17 a re used as pins for LCD display. The pins P3 0 /SEG18–P3 7/SEG 25 a nd P00 /SEG 26–P0 7/ SEG33 and P10/SEG34–P15/SEG39 are available as segment output pins (SEG18–SEG39). By switching the corresponding registers, the segment output pin or output pin is selected. Table 2.7.1 shows the pin function by setting segment output enable register and Table 2.7.2 shows the pin functions by setting the corresponding registers when they are not used as segment output pins. Table 2.7.1 Pin functions by setting segment output enable register Setting Pins Register SEG (Address 003816 ) b0 (Bit 0 of segment output enable register) Value 1 0 1 0 1 0 1 0 1 0 1 0 Pin function Segment output Output port Segment output Output port Segment output Output port Segment output Output port Segment output Output port Segment output Output port P3 0/SEG18 –P3 5/SEG 23 P3 6/SEG24, P3 7/SEG25 SEG (Address 003816 ) b1 (Bit 1 of segment output enable register) P0 0/SEG26– P0 5/SEG31 SEG (Address 003816 ) b2 (Bit 2 of segment output enable register) P0 6/SEG32, P0 7/SEG33 SEG (Address 003816 ) b3 (Bit 3 of segment output enable register) P1 0/SEG34 SEG (Address 0038 16) b4 (Bit 4 of segment output enable register) P1 1/SEG35– P1 5/SEG39 SEG (Address 0038 16) b5 (Bit 5 of segment output enable register) Note: When the microcomputer is in the reset state, the output or segment output pins are pulled-down, so that a “L” level is output from segment-only pins. 3825 GROUP USER’S MANUAL 2–165 APPLICATION 2.7 LCD drive control circuit Table 2.7.2 Pin functions by setting the corresponding registers when they are not used as segment output pins Setting Ports Register PULLA (Address 0016 16) b0 (Bit 0 of PULL register A) Value 1 0 1 0 1 0 Pin function Pull-down pin Output function is invalid No pull-down (When being set for output mode) Pull-down pin Output function is invalid No pull-down (When being set for output mode) Output port Output port function is invalid Pull-down pin (When bit 0 of P1C is “0”) No pull-down P3 0–P3 7 P00–P07 PULLA (Address 001616 ) b0 (Bit 0 of PULL register A) P1C (Address 000316 ) b0 (Bit 0 of port P1 output control register) P10–P15 PULLA (Address 0016 16 ) b0 (Bit 0 of PULL register A) 1 0 (1) Segment output pins (SEG 0–SEG 39) Up to 40 segment outputs can be selected. Table 2.7.3 shows setting of segment output pins for LCD display. Table 2.7.3 Setting of segment output pins for LCD display Pins SEG0–SEG 17 P3 0/SEG 18– P3 5/SEG 23 P3 6/SEG24, P3 7/SEG25 P0 0/SEG26– P0 5/SEG31 P0 6/SEG32, P0 7/SEG33 P10/SEG 34 P1 1/SEG35– P1 5/SEG39 Segment output-only pin Ports P3 0 –P3 5 a re used as segment signal output pins (SEG 18–SEG 23) by setting bit 0 of the segment output enable register (address 0038 16) to “1.” Ports P36 and P37 are used as segment signal output pins (SEG24, SEG25) by setting bit 1 of the segment output enable register (address 003816) to “1.” Ports P0 2– P0 5 a re used as segment signal output pins (SEG 26 –SEG 31 ) by setting bit 2 of the segment output enable register (address 0038 16) to “1.” Ports P0 6 a nd 0 7 a re used as segment signal output pins (SEG 32, SEG33 ) by setting bit 3 of the segment output enable register (address 0038 16) to “1.” Port P10 is used as segment signal output pins (SEG34) by setting bit 4 of the segment output enable register (address 0038 16) to “1.” Ports P1 1– P1 5 a re used as segment signal output pins (SEG 35 –SEG 39 ) by setting bit 5 of the segment output enable register (address 003816 ) to “1.” Setting 2–166 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit (2) Ports P0, P1 0 –P1 5 a nd P3 When pins P3 0 /SEG 18–P3 7/SEG 25, P0 0/SEG 26–P0 7/SEG 33, P1 0/SEG 34–P1 5/SEG 39 a re not used as segment outputs, they can be used as output ports P3 and P0. Table 2.7.4 shows the setting of output ports P3, P1 0–P1 5 a nd P0. Table 2.7.4 Setting of output ports P3, P1 0–P15 a nd P0 Ports P30–P3 5 P36, P3 7 P0 0–P05 P06 , P0 7 P10 P11–P1 5 Setting By setting bit 0 of segment output enable register (address 003816) to “0,” then setting bit 0 of PULL register A (address 001616 ) to “0.” By setting bit 1 of segment output enable register (address 003816) to “0,” then setting bit 0 of PULL register A (address 001616 ) to “0.” By setting bit 2 of segment output enable register (address 003816) to “0,” then setting bit 0 of PULL register A (address 001616 ) to “0.” By setting bit 3 of segment output enable register (address 003816 ) to “0,” then setting bit 0 of PULL register A (address 0016 16) to “0.” By setting bit 4 of segment output enable register (address 003816) to “0,” then setting bit 0 of port P1 output control register (address 0038 16) to “1.” By setting bit 5 of segment output enable register (address 003816) to “0,” then setting bit 0 of port P1 output control register (address 0038 16) to “1.” (3) P3, P10 –P15 a nd P0 pull-down pins When pins P30 /SEG18–P3 7/SEG 25, P0 0/SEG 26–P07 /SEG33, P1 0/SEG34 –P15/SEG 39 are not used as ports, it is possible to exert pull-down control. Table 2.7.5 shows the setting of pull-down pins. Table 2.7.5 Setting of pull-down pins Pins P30/SEG 18– P37/SEG 25 P00/SEG 26– P07/SEG 33 P1 0/SEG34– P1 5/SEG39 Setting By setting bits 0 and 1 of the segment output enable register (address 003816) to “0,” then setting bit 0 of PULL register A (address 001616 ) to “1.” By setting bits 2 and 3 of the segment output enable register (address 0038 16) to “0,” then setting bit 0 of PULL register A (address 0016 16 ) to “1.” By setting bits 4 and 5 of the segment output enable register (address 003816) to “0,” next setting bit 0 of the port P1 output control register (address 000316) to “0,” then setting bit 1 of PULL register A (address 0016 16) to “1.” 3825 GROUP USER’S MANUAL 2–167 APPLICATION 2.7 LCD drive control circuit 2.7.3 Related registers Figure 2.7.1 shows the memory allocation of LCD display-related registers. Address 0003 16 Port P1 output control register (P1C) 001616 PULL register A (PULLA) 0038 16 0039 16 Segment output enable register (SEG) LCD mode register (LM) Fig. 2.7.1 Memory allocation of LCD display-related registers 2–168 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit (1) Segment output enable register (SEG) The pins P30/SEG18–P37/SEG25, P00/SEG26–P07/SEG33, P10/SEG34–P15/SEG39 can be used as segment output pins by setting bits 0 to 5 of the segment output enable register (address 0038 16 ). The pins corresponding to the bits which are set to “1” among bits 0 to 5 of the segment output enable register (address 0038 16) are used as segment output pins. The pins corresponding to the bits which are set to “0” are used as output ports. Figure 2.7.2 shows the structure of the segment output enable register. Segment output enable register b7 b6 b5 b4 b3 b2 b1 b0 00 Segment output enable register (SEG) [Address 3816] B Name 0 Segment output enable bit 0 1 Segment output enable bit 1 2 Segment output enable bit 2 3 Segment output enable bit 3 4 Segment output enable bit 4 5 Segment output enable bit 5 Functions At reset R W 0: Output ports P30–P35 0 1: Segment output SEG18–SEG23 0: Output ports P36, P37 0 1: Segment output SEG24, SEG25 0: Output ports P00–P05 0 1: Segment output SEG26–SEG31 0: Output ports P06, P07 1: Segment output SEG32, SEG33 0: Output port P10 1: Segment output SEG34 0: Output ports P11–P15 1: Segment output SEG35–SEG39 0 0 0 0 00 6,7 Fix these bits to “0.” Fig. 2.7.2 Structure of segment output enable register 3825 GROUP USER’S MANUAL 2–169 APPLICATION 2.7 LCD drive control circuit (2) LCD mode register (LM) The LCD mode register (address 0039 16 ) controls various functions of the LCD controller/driver. Figure 2.7.3 shows the structure of the LCD mode register. q Bits 0, 1 : Duty ratio selection bits Select a duty ratio number fit for the LCD panel used. qBit 2 : Bias control bit Select a bias value fit for the LCD panel used. qBit 3 : LCD enable bit This bit turns on and off the LCD. When this bit is set to “1,” the bits which are set to “1” in the LCD display RAM are displayed on the LCD. When this bit is set to “0,” the whole LCD display is turned off. qBit 4 : Voltage multiplier control bit This bit enables or disables the voltage multiplier. When this bit is set to “1,” the multiplier is used. When this bit is set to “0,” the multiplier is not used. When 1/2 bias is selected, set this bit to “0.” q Bits 5, 6 : LCD circuit divider division ratio selection bits These bits are used to select a division ratio for generating the frequency of the LCDCK, which is the clock for the LCD timing controller. Select a division ratio so as to generate LCDCK fit for the LCD panel used. qBit 7 : LCDCK count source selection bit This bit is used to select a count source of the above LCDCK. At transition from the high-speed, middle-speed or low-speed mode to the low-power operation, or others, change the count source as required. 2–170 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit LCD mode register b7 b6 b5 b4 b3 b2 b1 b0 0 LCD mode register (LM) [Address 3916] B Name b1b0 Functions 00: Not available 01: 2 (use COM0, COM1) 10: 3 (use COM0–COM2) 11: 4 (use COM0–COM3) 0: 1/3 bias 1: 1/2 bias 0: LCD OFF 1: LCD ON 0: Voltage multiplier disable 1: Voltage multiplier enable b6b5 At reset R W 0 0 0 Duty ratio selection bits 1 2 Bias control bit 3 LCD enable bit 4 Voltage multiplier control bit 0 0 0 0 5 LCD circuit divider division ratio selection bits (Note 1) 6 7 LCDCK count source selection bit (Note 2) 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source 0: f(XCIN)/32 1: f(XIN)/8192 0 Notes 1: Reference values at f(XIN) = 8 MHz 00: 977 Hz 01: 488 Hz 10: 244 Hz 11: 122 Hz 2: LCDCK is a clock for a LCD timing controller. Fig. 2.7.3 Structure of LCD mode register 3825 GROUP USER’S MANUAL 2–171 APPLICATION 2.7 LCD drive control circuit (3) Port P1 output control register (P1C) When it is specified that pins P10 /SEG34–P1 5/SEG 39 are used as output ports by bits 4 and 5 of the segment output enable register (address 0038 16), the setting of the port P1 output control register (address 000316) is valid. When bit 0 of the port P1 output control register is set to “1,” port ports P10 –P1 5 a re output ports. When this bit is set to “0,” the output function is invalid, so that the setting of bit 0 of the PULL register A (address 0016 16) becomes valid. At reset, bit 0 of the port P1 output control register is set to “0.” Figure 2.7.4 shows the structure of the port P1 output control register. Port P1 output control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 output control register (P1C) [Address 03 16] B 0 Name Ports P1 0–P1 5 output control bit Functions 0 : Output function is invalid 1 : Output function is valid At reset R W 0 × 1 Nothing is allocated. These bits cannot be written to to and be read out. 5 6 7 Port P1 6 direction register Port P1 7 direction register 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 ×× 0 0 × × Fig. 2.7.4 Structure of port P0 direction register 2–172 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit (4) PULL register A (PULLA) When ports P3, P1 0–P15, and P0 are set for the output mode, the setting of bit 0 of the PULL register A (address 0016 16) is valid. The pull-down function of ports P3, P1 0–P1 5, and P0 is made effective by setting bit 0 of the PULL register A to “1.” When ports P1 0 –P15 a re set for output mode by bit 0 of the port P1 output control register, the setting of the PULL register A is invalid. Figure 2.7.5 shows the structure of the PULL register A. PULL register A b7 b6 b5 b4 b3 b2 b1 b0 PULL register A (PULLA) [Address 1616] B Name 0 Ports P0 0–P0 7, P10–P1 5, P30–P3 7 pull-down bit Functions 0 : No pull-down (P0, P3 output function is valid) 1 : Pull-down (P0, P3 output function is invalid) At reset R W 1 1 Ports P1 6, P1 7 pull-up bit 2 3 4 5 6, 7 0 : No pull-up 1 : Pull-up 0 : No pull-up Ports P2 0–P2 7 pull-up bit 1 : Pull-up 0 : No pull-up Ports P8 0–P8 7 pull-up bit 1 : Pull-up 0 : No pull-up Ports P4 0–P4 3 pull-up bit 1 : Pull-up 0 : No pull-up Ports P4 4–P4 7 pull-up bit 1 : Pull-up Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. 1 0 1 0 0 0 0× Note: For ports set for the output mode, pull-up or pull-down is impossible (except ports P0 and P3). Fig. 2.7.5 Structure of PULL register A 3825 GROUP USER’S MANUAL 2–173 APPLICATION 2.7 LCD drive control circuit 2.7.4 Register setting example Figure 2.7.6 and Figure 2.7.7 show an example of setting registers for LCD display. [Note on use] Note : For pulling down ports P0, P1 and P3, refer to “2.7.2 Pins, (3) Ports P3, P1 0–P15 and P0 pull–down pins” ŒSetting of segment output enable register Select segment pins or others b7 00 b0 SEG: Segment output enable register [Address 38 16] b0: Segment output enable bit 0 0: Output ports P3 0–P35 1: Segment output SEG 18–SEG23 b1: Segment output enable bit 1 0: Output ports P3 6, P37 1: Segment output SEG 24, SEG25 b2: Segment output enable bit 2 0: Output ports P0 0–P05 1: Segment output SEG 26–SEG31 b3: Segment output enable bit 3 0: Output ports P0 6, P07 1: Segment output SEG 32, SEG33 b4: Segment output enable bit 4 0: Output ports P1 0 1: Segment output SEG 34 b5: Segment output enable bit 5 0: Output ports P1 1–P15 1: Segment output SEG 35–SEG39 b7, b6: Fix these bits to “0” Continued to Figure 2.7.7 Fig. 2.7.6 Example of setting registers for LCD display (1) 2–174 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit Continued from Figure 2.7.6 Setting of LCD mode register Select count source, bias, or others b7 0 b0 LM: LCD mode register [Address 39 16] b1, b0: Duty ratio selection bits b1b0 00: Not used 01: 2 (use COM 0, COM1) 10: 3 (use COM 0–COM2) 11: 4 (use COM 0–COM3) b2: Bias control bit 0: 1/3 bias 1: 1/2 bias b3: LCD enable bit 0: LCD OFF 1: LCD ON b4: Voltage multiplier control bit 0: Voltage multiplier disable b6, b5: LCD circuit divider division ratio selection bits b6b5 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source b7: LCDCK count source selection bit 0: f(XCIN)/32 1: f(XIN)/8192 ŽSetting display data into the RAM (Address 40 16 to 5316) for LCD display By writing “1” to bits in the RAM for LCD display, the corresponding segments of the LCD panel becomes ready for lighting Fig. 2.7.7 Example of setting registers for LCD display (2) 3825 GROUP USER’S MANUAL 2–175 APPLICATION 2.7 LCD drive control circuit 2.7.5 Application examples (1) LCD panel display pattern example Figure 2.7.8 shows an 8-segment LCD panel display pattern example when the duty ratio number is 4. LCD display RAM 5316 5216 5116 5016 4F16 4E16 4D16 4C16 4B16 4A16 4916 4816 4716 4616 4516 4416 4316 4216 4116 4016 (Address) 1 1 1 0 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 0 COM3 COM2 COM1 COM0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 SEG0 SEG1 Display RAM map high-order SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 Display RAM map low-order b0 b7 B C H SEGa SEGb D H C D COM2 G A COM3 COM1 Fig. 2.7.8 8-segment LCD panel display pattern example when duty ratio number is 4 COM0 F E E G F B A 2–176 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit (2) LCD panel example Figure 2.7.9 to Figure 2.7.11 show an LCD panel example and a segment allocation example for it, and an LCD display RAM setting example. ’ AUTO SLOW PRINT Fig. 2.7.9 LCD panel example 1 2 3 4 5 6 ’ AUTO SLOW PRINT 7 Fig. 2.7.10 Segment allocation example a Bit Address 004016 004116 004216 004316 004416 004516 004616 7 6 g g g g g g SLOW AUTO 5 f f f f f f 4 e e e e e e 3 d d d d d d 2 c c c c c c 1 b b b b b b PRINT 0 a a a a a a 1 2 3 4 5 6 7 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 f e d g b c ’ Fig. 2.7.11 LCD display RAM setting example 3825 GROUP USER’S MANUAL 2–177 APPLICATION 2.7 LCD drive control circuit (3) Control procedure Figure 2.7.12 shows the setting of related registers to turn on all the LCD display in Figure 2.7.9, and Figure 2.7.13 shows the control procedure. Specifications: •Voltage multiplier is used. •Frame frequency = 122 Hz •Duty ratio number = 4, Bias value = 1/3 •Segment output; SEG 0 t o SEG13 a re used. •Ports P3, P0 and P1 0–P1 5 a re set as output ports. b7 b0 0 0 0 0 0 0 0 0 SEG: Segment output enable register [Address 3816] b0: Segment output enable bit 0 0: Output ports P30–P35 b1: Segment output enable bit 1 0: Output ports P36, P37 b2: Segment output enable bit 2 0: Output ports P00–P05 b3: Segment output enable bit 3 0: Output ports P06, P07 b4: Segment output enable bit 4 0: Output port P10 b5: Segment output enable bit 5 0: Output ports P11–P15 b7, b6: Fix these bits to “0” b7 b0 1 0 1 1 0 0 1 1 LM: LCD mode register [Address 3916] b1, b0: Duty ratio selection bits b1b0 11: 4 (use COM0–COM3) b2: Bias control bit 0: 1/3 bias b3: LCD enable bit 0: LCD OFF (after setting data into the RAM for LCD display, turn on) b4: Voltage multiplier control bit 1: Voltage multiplier enable b6, b5: LCD circuit divider division ratio selection bits b6b5 01: 2 division of LCDCK count source V b7: LCDCK count source selection bit 1: f(XIN)/8192 V V: •f(LCDCK) = Count source frequency for LCDCK/LCD circuit division ratio •Frame frequency = f(LCDCK)/duty ratio number From the above, the frame frequency at f(XIN) = 8 MHz is as follows: Frame frequency f = 8 ! 10 8192 6 1 !2 1 ! 4 ≈ 122.070 Hz Fig. 2.7.12 Setting of related registers 2–178 3825 GROUP USER’S MANUAL APPLICATION 2.7 LCD drive control circuit RESET Initialization CLT CLD SEI SEG (Address 38 16) LM (Address 39 16) P1C (Address 03 16) PULLA (Address 16 16) ←00000001 2 ←10100011 2 ←XXXXXXX1 2 ←XXXXXXXX 2 All interrupts; Disabled Set ports/segments Set LCD mode register Set port P1 for output mode Set pull-up, pull-down VSet in the order of port P1 output control register and PULL register A Set values in LCDRAMX (Set it to “1” to turn on or to “0” to turn it off) LCDRAM0 (Address 40 16)←11111111 2 LCDRAM1 (Address 41 16)←11111111 2 LCDRAM2 (Address 42 16)←11111111 2 LCDRAM3 (Address 43 16)←11111111 2 LCDRAM4 (Address 44 16)←01111111 2 LCDRAM5 (Address 45 16)←01111111 2 LCDRAM6 (Address 46 16)←11111111 2 LM (Address 39 16), bit 3 ←1 CLI Turn on LCD Interrupts; Enabled When switching LCD ON (OFF) segments LCDRAMX (Address XX 16) ←XXXXXXXX 2 Rewrite bits corresponding to LCD ON (OFF) segments Fig. 2.7.13 Control procedure 3825 GROUP USER’S MANUAL 2–179 APPLICATION 2.7 LCD drive control circuit 2.7.6 Notes on use (1) For transition from the high-speed or the middle-speed mode to the low-power operation of the lowspeed mode: Œ S elect oscillation at 32 kHz (CM 4 = 1 )  C ount source for LCDCK; select f(X CIN )/32 (LM7 = 0 ) Ž I nternal system clock; select X CIN–X COUT ( CM7 = 1 )  S top main clock X IN–X OUT ( CM 5 = 1 ) In the above order, execute transition. Execute the setting  a fter the oscillation at 32 kHz (setting Œ) becomes completely stable. (2) If the STP instruction is executed while the LCD is turned on by setting bit 3 of the LCD mode register to “1,” a DC voltage is applied to the LCD. For this reason, do not execute the STP instruction while the LCD is lighting. (3) When the LCD is not used, open the segment and the common pins. Connect VL1 t o VL3 –VSS. (4) When using the voltage multiplier, with applying 1.3 V or more to the V L1 pin, set the bit 4 of the LCD mode register to “1.” If setting the bit to “1” with applying 1.3 V or less to the V L1 p in, a current of maximum 50 µ A may occur at the time that the voltage multiplier starts operating. 2–180 3825 GROUP USER’S MANUAL APPLICATION 2.8 Standby function 2.8 Standby function The 3825 group is provided with a standby function to stop the CPU by software and put the CPU into the low-power operation. The following two types of standby function are available. •Stop mode by the S TP i nstruction •Wait mode by the W IT i nstruction 2.8.1 Stop mode The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both XIN and XCIN stops and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating. As a result, power dissipation is reduced. (1) State in the stop mode The stop mode is set by executing the S TP instruction.V1 In the stop mode, the oscillation of both X IN and X CIN stops, so that all the functions stop, providing a low-power operation. Table 2.8.1 shows the state in the stop mode. V 1: After setting the LCD enable bit (bit 3) of the LCD mode register to “0,” execute the STP instruction. Table 2.8.1 State in the stop mode Item Oscillation CPU Internal clock φ I/O ports P0–P7 State in stop mode Stop Stop Stop at “H” level The state where S TP i nstruction is executed is held Timer, serial I/O, Stop LCD display functions 3825 GROUP USER’S MANUAL 2–181 APPLICATION 2.8 Standby function (2) Release of stop mode The stop mode is released by reset input or by the occurrence of an interrupt request. There is a difference in restore processing from the stop mode by reset input and by an interrupt request. s Restoration by reset input By holding the “L” input level of the RESET pin in the stop mode for 2 µ s or more, the reset state is set, so that the stop mode is released. At the time when the stop mode is released, oscillation is started. At this time, the inside of the microcomputer is in the reset state. After the input level of the RESET pin is returned to the “H,” the reset state is released in approximately 8,000 cycles of the X IN i nput. The oscillation is unstable at start of oscillation. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. The time to hold the internal reset state is reserved as the oscillation stabilizing time. Figure 2.8.1 shows the oscillation stabilizing time at restoration by reset input. At release of the stop mode, the contents of the internal RAM previous to the reset are held. However, the contents of the CPU register and SFR are not held. For resetting, refer to “ 2.9 Reset.” Time to hold internal reset state = approximately 8000 cycles of XIN input Stop mode VCC RESET XIN (Note) Execute STP instruction Restored by reset input Note: No waveform may be input to XIN (in low-speed mode) Oscillation stabilizing time 2 µ s or more Fig. 2.8.1 Oscillation stabilizing time at restoration by reset input 2–182 3825 GROUP USER’S MANUAL APPLICATION 2.8 Standby function sRestoration by an interrupt request The occurrence of an interrupt request in the stop mode releases the stop mode. As a result, oscillation is resumed. The interrupt requests available for restoration are: • INT 0–INT 3 • Serial I/O transmit/receive using an external clock • Timer X/Y using an external clock • Key input (key-on wake up) However, to use the above interrupt requests for restoration from the stop mode, a fter setting the following, execute the S TP i nstruction in order to enable the interrupt request to be used. [Necessary register setting] Œ I nterrupt disable flag I = “0” (interrupts enabled)  B oth timers 1 and 2 interrupt enable bits = “0” (interrupts disabled) Ž I nterrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request issued)  I nterrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) For interrupts, refer to “ 2.2 Interrupts.” The oscillation is unstable at start of oscillation. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. At restoration by an interrupt request, the time to wait for supplying the internal clock φ to the CPU is automatically generated V1 by timers 1V2 and 2.V2 This wait time is reserved as the oscillation stabilizing time on the system clock side. Figure 2.8.2 shows an execution sequence example at restoration by the occurrence of an INT 0 interrupt request. V 1: At restoration from the stop mode, all bits except bit 4 of the timer 123 mode register (address 0029 16 ) are set to “0.” As a count source of the timer 1, an f(XIN)/16 or f(X CIN)/16 clock is selected. As a count source of the timer 2, the timer 1 underflow is selected. Immediately after the oscillation is started, the count source is supplied to the timer 1 counter, so that a count operation is started. The supplying the internal clock φ to the CPU is started at the timer 2 underflow. V 2: When the S TP i nstruction is executed, “FF 16 ” and “01 16 ” are automatically set in the timer 1 counter/latch and timer 2 counter/latch respectively. 3825 GROUP USER’S MANUAL 2–183 APPLICATION 2.8 Standby function qWhen restoring from stop mode by using INT0 interrupt (rising edge selected) Stop mode Oscillation stabilizing time (approximately 8000 cycles) XIN or XCIN (System clock) INT0 pin “FF16” XIN; “H” XCIN; in high-impedance state 512 counts Timer 1 counter Timer 2 counter INT0 interrupt request bit Peripheral device CPU Operating Operating “0116” Stopping Stopping Operating Operating •Execute STP instruction •512 counts down by timer 1 •INT0 interrupt •Start supplying internal clock φ signal input (INT0 interrupt to CPU request occurs) •Accept INT0 interrupt request •Oscillation start •Timer 1 count start Note: As a count source, f(XIN)/16 or f(XCIN)/16 is input. Either f(XIN)/16 or f(XCIN)/16 is selected by bit 7 of CPU mode register. Fig. 2.8.2 Execution sequence example at restoration by occurrence of INT 0 i nterrupt request 2–184 3825 GROUP USER’S MANUAL APPLICATION 2.8 Standby function (3) Notes on using the stop mode sRelease sources The release sources of the stop mode are shown below. •Reset input •INT0 –INT 3 interrupts •Serial I/O transmit/receive interrupts using an external clock •Timers X/Y interrupts using an external clock •Key input interrupt (key-on wake up) Each INT pin (INT0, INT1, INT 2, INT3) is also used as ports P42, P43, P50 or P51 and each key input pin is also used as port P2. To use INT 0 to INT3 interrupts, after setting the corresponding bits of the following direction registers to “0” t o set them for the input mode, execute the S TP i nstruction. •Port P4 direction register (address 0009 16) •Port P5 direction register (address 000B16 ) sRegister setting To use the above interrupt requests for restoration from the stop mode, a fter setting the following, execute the S TP i nstruction in order to enable the interrupt request to be used. [Necessary register setting] Œ I nterrupt disable flag I = “0” (interrupts enabled)  B oth timers 1 and 2 interrupt enable bits = “0” (interrupts disabled) Ž I nterrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request issued)  I nterrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) •At restoration from the stop mode, the values of the timers 1, 2 and 123 mode registers are automatically rewritten. Accordingly, set each of them again. •To prevent a DC voltage from being applied to the LCD, after setting the LCD enable bit (bit 3) of the LCD mode register to “0,” execute the S TP i nstruction. sClock after restoration After restoration from the stop mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are held. Accordingly, when both X IN and XCIN were oscillating before execution of the S TP i nstruction, the oscillation of both X IN a nd X CIN i s resumed at restoration from the stop mode by an interrupt request. In the above case, when the X IN s ide is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the X IN i nput is reserved at restoration from the stop mode. At this time, note that the oscillation on the X CIN s ide may not be stabilized even after the lapse of the oscillation stabilizing time (of the X IN s ide). 3825 GROUP USER’S MANUAL 2–185 APPLICATION 2.8 Standby function 2.8.2 Wait mode The wait mode is set by execution of the W IT i nstruction. In the wait mode, the oscillation is continued, but the internal clock φ s tops at the “H” level. Since the oscillation is continued regardless of the CPU stop, the peripheral units operate. (1) States in the wait mode By executing the WIT instruction, the wait mode is set. In the wait mode, the internal clock φ which is supplied to the CPU stops at the “H” level. The continuation of oscillation permits clock supply to the peripheral units. Table 2.8.2 shows the state in the wait mode. Table 2.8.2 State in wait mode Item Oscillation CPU Internal clock φ I/O ports P0–P7 State in wait mode Operating Stop Stop at “H” level The state where W IT i nstruction is executed is held. Operating Timer, serial I/O, LCD display functions 2–186 3825 GROUP USER’S MANUAL APPLICATION 2.8 Standby function (2) Release of wait mode The wait mode is released by reset input or by the occurrence of an interrupt request. There is a difference in restore processing from the wait mode by use of reset input and by use of an interrupt request. In the wait mode, oscillation is continued, so an instruction can be executed immediately after the wait mode is released. sRestoration by reset input The reset state is provided by holding the input level of the RESET pin at “L” for 2 µs or more in the wait mode. As a result, the wait mode is released. At the time when the wait mode is released, the supplying the internal clock φ to the CPU is started. The reset state is released in approximately 8,000 cycles of the X IN input after the input of the RESET pin is returned to the “H” level. At release of the wait mode, the contents of the internal RAM previous to the reset are held. However, the contents of the CPU mode register and SFR are not held. Figure 2.8.3 shows the reset input time. For reset, refer to “ 2.9 Reset.” Time to hole internal reset state = approximately 8000 cycles of XIN input Wait mode VCC RESET XIN (Note) Execute WIT instruction Restored by reset input Oscillation stabilizing time 2 µs or more Note: No waveform may be input to XIN (in low-speed mode) Fig. 2.8.3 Reset input time 3825 GROUP USER’S MANUAL 2–187 APPLICATION 2.8 Standby function s Restoration by an interrupt request In the wait mode, the occurrence of an interrupt request releases the wait mode and the supplying the internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration is accepted, so the interrupt processing routine is executed. However, to use an interrupt for restoration from the wait mode, a fter setting the following, execute the W IT i nstruction in order to enable the interrupt to be used. [Necessary Œ I nterrupt  I nterrupt issued) Ž I nterrupt register setting] disable flag I = “0” (interrupts enabled) request bit of the interrupt source to be used for restoration = “0” (no interrupt request enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) For interrupts, refer to “ 2.2 Interrupts.” (3) Notes on the wait mode s Restoration by INT 0 t o INT3 i nterrupt requests Each INT pin (INT0, INT1, INT2, INT3) is also used as ports P42, P43, P50 or P51 and each key input pin is also used as port P2. To use INT 0 to INT3 interrupts, set the corresponding bits of the following direction registers to “0” f or setting the input mode. And then, execute the W IT i nstruction. •Port P4 direction register (address 0009 16) •Port P5 direction register (address 000B16 ) s Restoration by key input interrupt request The pins for a key input interrupt is also used as port P2. To use a key input interrupt, set the corresponding bits of the port P2 direction register (address 000516) to “0” for setting the input mode. And then, execute the W IT i nstruction. s Register setting To use the above interrupt requests for restoration from the stop mode, a fter setting the following, execute the W IT i nstruction in order to enable the interrupt request to be used. [Necessary Œ I nterrupt  I nterrupt issued) Ž I nterrupt register setting] disable flag I = “0” (interrupts enabled) request bit of the interrupt source to be used for restoration = “0” (no interrupts request enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) 2–188 3825 GROUP USER’S MANUAL APPLICATION 2.8 Standby function 2.8.3 State transitions of internal clock φ Figure 2.8.4 shows the state transitions of the internal clock φ w hen the standby function is used. RESET Middle-speed mode (f (φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1”↔“0” High-speed mode (f (φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM4 “1”↔“0” “1 CM ” C ↔“0 4 “1 M ”↔ 6 ” “0 ” Middle-speed mode (f (φ ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” High-speed mode (f (φ ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1”↔“0” CM7 “1”↔“0” CM 4 “1”↔“0” 4 M” C “1 ”↔ 6 ” “0 CM “0 ”↔ “1 b7 b4 CPU mode register (CPUM) [Address 3B16] CM4: Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM5: Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “1 CM ”↔ 5 “1 CM “0 ”↔ 6 ” “0 ” 5 M” C “1 ”↔ 6 ” “0 CM “0 ”↔ “1 CM5 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) Notes 1: Switch the mode by the allows shown between the mode blocks.( Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is released. 3: Timer and LCD operate in the wait mode. 4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2. 6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to the middle-/high-speed mode. 7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 2.8.4 State transitions of internal clock φ 3825 GROUP USER’S MANUAL CM5 “1”↔“0” 2–189 APPLICATION 2.9 Reset 2.9 Reset The internal reset state is provided by applying a “L” level to the RESET pin. After that, the reset state is released by applying a “H” level to the RESET pin, so that the program is executed in the middle-speed mode starting from the contents at the reset vector address. 2.9.1 Explanation of operations Figure 2.9.1 shows the internal reset state hold/release timing. Internal processing sequence Internal clock φ 2 µs or more RESET Middle-speed = approximately 8000 cycles of X IN input Hold reset state Fig. 2.9.1 Internal reset state hold/release timing 2–190 3825 GROUP USER’S MANUAL APPLICATION 2.9 Reset The reset state is provided by applying a “L” level to the RESET pin at power source voltage of 2.5 V to 5.5 V. Allow 2 µs or more as “L” level applying time. By applying a “H” level to the RESET pin in the internal reset state, the timers and their count source shown in Table 2.9.1 is automatically set. After that, the internal reset state is released by the timer 2 underflow. After applying “H” level, only the main clock oscillates in the middle-speed mode regardless of the oscillation state previous to internal resetting. The X CIN p in on the sub-clock side becomes the input port. After the internal reset state is released, the program is run from the address determined with the contents (high-order address) at address FFFD 16 a nd the contents (low-order address) at address FFFC 16. Figure 2.9.2 shows the internal processing sequence immediately after reset release. Table 2.9.1 Timers 1 and 2 at reset Item Timer 1 Timer 2 FF16 Value 01 16 Count source f (XIN)/16 Timer 1 underflow VCC f(XIN) 1 µs at f(X IN) = 8 MHz Internal clock φ 2 µs or more RESET Approximately 8000 cycles of X IN input Internal reset Address bus Data bus SYNC Internal clock φ : CPU reference clock frequency = f(X IN)/8 (middle-speed mode immediately after reset) AH, AL : Interrupt jump destination addresses SYNC : CPU operation code fetch cycle (This is a internal signal, so that it cannot be observed from the external unit) : Undefined FFFC16 FFFD16 AL,AH AL AH Fig. 2.9.2 Internal processing sequence immediately after reset release 3825 GROUP USER’S MANUAL 2–191 APPLICATION 2.9 Reset 2.9.2 Internal state of the microcomputer immediately after reset release Figure 2.9.3 shows the internal state of the microcomputer immediately after reset release. The contents of all other registers except registers in Figure 2.9.3 and internal RAM are undefined at poweron reset. Port P1 output control register Port P2 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register PULL register A PULL register B Serial I/O status register Serial I/O control register UART control register Timer X (low-order) Timer X (high-order) Timer Y (low-order) Timer Y (high-order) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register Clock output control register A-D control register Segment output enable register LCD mode register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Address b7 Contents of register b1 0016 000316 0016 000516 0016 000916 0016 000B16 000D16 0016 000F16 0016 001116 0016 001616 0116 001716 0016 001916 1 00 0 000 0 001A16 0016 001B16 1 11 0 000 0 002016 FF16 002116 FF16 002216 FF16 002316 FF16 002416 FF16 002516 0116 002616 0016 002716 0016 002816 0016 002916 0016 002A16 0016 003416 0 00 0 100 0 003816 0016 003916 0016 003A16 0016 10 0 100 0 003B16 0 003C16 0016 003D16 0016 003E16 0016 003F16 0016 (PS) X X X X X 1 X X (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Notes X : Undefined The contents of all other registers and internal RAM are undefined at poweron reset, so they must be initialized by software. Fig. 2.9.3 Internal state of microcomputer immediately after reset release 2–192 3825 GROUP USER’S MANUAL APPLICATION 2.9 Reset 2.9.3 Reset circuit Design a configuration of the reset circuit so that the reset input voltage may be 0.5 V or less at the time when the power source voltage passes 2.5 V (for the extended operating temperature version, 0.6 V or less at the time when the power source voltage passes 3.0 V). Figure 2.9.4 shows the poweron reset conditions and Figure 2.9.5 shows poweron reset circuit examples. Power on VCC 2.5 V 0V RESET 0V 0.5 V V For extended operating temperature version, 0.6 V or less at the time when power source voltage passes 3.0 V. Fig. 2.9.4 Poweron reset conditions 3825 group RESET 35 VCC 91 3825 group RESET 35 VCC 91 Power source voltage detection circuit Fig. 2.9.5 Poweron reset circuit examples 3825 GROUP USER’S MANUAL 2–193 APPLICATION 2.9 Reset 2.9.4 Notes on the RESET pin In case where the reset signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS p in. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following: qMake the length of the wiring which is connected to a capacitor as short as possible. qBe sure to check the operation of application products on the user side. REASON If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 2–194 3825 GROUP USER’S MANUAL APPLICATION 2.10 Oscillation circuit 2.10 Oscillation circuit 2.10.1 Oscillation circuit Two oscillation circuits are included to obtain clocks required for operations. • XIN–XOUT o scillation circuit............Main clock (XIN i nput) oscillation circuit • XCIN–X COUT o scillation circuit........Sub-clock (X CIN input) oscillation circuit A clock V1 obtained by dividing the frequency input to the clock input pins XIN o r X CIN is an internal clock φ . The internal clock φ i s used as a standard for operations. V 1: The internal clock φ v aries with modes. •High-speed mode ........Frequency input to the X IN p in/2 •Middle-speed mode .....Frequency input to the X IN p in/8 •Low-speed mode .........Frequency input to the XCIN p in/2 (1) Oscillation circuit using ceramic resonators Figure 2.10.1 shows an oscillation circuit example using ceramic resonators. As shown in the figure, an oscillation circuit can be formed by connecting a ceramic resonator or a quartz-crystal oscillator between the pins X IN a nd the X OUT a nd between the pins XCIN a nd X COUT. As the XIN–X OUT o scillation circuit includes a feedback resistor, an external resistor is omissible. As the X CIN –X COUT o scillation circuit does not include any feedback resistor, connect a feedback resistor externally. Regarding circuit constants for R f, R d, CIN, C OUT, CCIN a nd C COUT, ask the resonator manufacturer for information, and set the values recommended by the resonator manufacturer. 3825 group XCIN 36 Rf XCOUT 37 Rd XIN 38 XOUT 39 CCIN CCOUT CIN COUT Fig. 2.10.1 Oscillation circuit example using ceramic resonators 3825 GROUP USER’S MANUAL 2–195 APPLICATION 2.10 Oscillation circuit (2) External clock input circuit An external clock can also be supplied to the main clock oscillation circuit. Figure 2.10.2 shows an external clock input circuit example. As an external clock to be input to the XIN p in, use a pulse signal with a duty ratio of 50%. At this time, open the X OUT p in. Any clock externally generated cannot be input to the X CIN p in directly. C ause oscillation with an external ceramic resonator. 3825 group XCIN 36 Rf XCOUT 37 XIN 38 XOUT 39 Open External oscillation circuit CCIN CCOUT VCC VSS Rd Fig. 2.10.2 External clock input circuit example 2–196 3825 GROUP USER’S MANUAL APPLICATION 2.10 Oscillation circuit 2.10.2 Internal clock φ The internal clock φ i s the standard for operations. (1) Clock generating circuit The clock generating circuit controls the oscillation of the oscillation circuit. The generated clock (internal clock φ) is supplied to the CPU and peripheral units. Figure 2.10.3 shows the clock generating circuit block diagram. Oscillation can be stopped and resumed by the clock generating circuit. XCIN XCOUT “1” “0” Port Xc switch bit XIN XOUT Internal system clock selection bit (Note) “1” Low-speed mode 1/2 “0” Middle-/high-speed mode 1/4 1/2 Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” “1” Timer 2 Main clock division ratio selection bit “1” Middle-speed mode “0” High-/low-speed mode Timing φ (Internal clock) Main clock stop bit QS R STP instruction WIT instruction SQ R QS R STP instruction Reset Interrupt disable flag (I) Interrupt request Note: When using the low-speed mode, set the port Xc switch bit to “1.” Fig. 2.10.3 Clock generating circuit block diagram 3825 GROUP USER’S MANUAL 2–197 APPLICATION 2.10 Oscillation circuit (2) Clock output function s Switching between I/O port function and clock output function The internal clock φ i s output from the pins P40 / f (XIN ) / f(XIN)/2 and P4 1 / f (XIN)/5 / f(X IN)/10 by setting P40/P41 clock output control bits (bits 0 and 1) of the clock output control register (address 002A16 ) to “1.” To output clock, set bits 0 and 1 of port P4 direction register to “1” (output mode). The pin P40 / f(XIN) / f(X IN)/2 functions as the clock output pin at φ cycle immediately after the P4 0 clock output control bit is set to “1.” The pin P41 / f (X IN)/5 / f(X IN)/10 functions as the clock output pin in synchronization with a rising edge of clock (XIN /5) immediately after the P41 c lock output control bit is set to “1.” s Selection of output clock frequency The output clock frequency is selected by setting the output clock frequency selection bit (bit 2) of the clock output control register. When the clock output frequency selection bit is “0,” f(X IN) clock is output from the P4 0 / f (X IN ) / f(XIN)/2 pin, f(X IN)/5 clock is output from the P4 1 / f(X IN)/5 / f(X IN)/10 pin. At this time, a duty ratio of output waveform from the P40 / f(X IN) / f(X IN)/2 pin depends on X IN input waveform. A duty ratio of output waveform from the P41 / f (X IN)/5 / f(X IN)/10 is approximately 40%. When the clock output frequency selection bit is “1,” f(X IN )/2 clock is output from the P4 0 / f(XIN) / f(XIN)/2 pin, f(XIN)/10 clock is output from the P41 / f(X IN)/5 / f(XIN)/10 pin. At this time, both duty ratio of output waveform from the pins P40 / f (X IN) / f(X IN )/2 and P4 1 / f (X IN)/5 / f(X IN)/10 is approximately 50%. Figure 2.10.4 shows the structure of the clock output control register. Clock output control register b7 b6 b5 b4 b3 b2 b1 b0 Clock output control register (TCON) [Address 2A 16] Name 0 P40 clock output control bit B Functions 0: Port function 1: Clock output (Port direction register = “1”) 0: Port function 1: Clock output (Port direction register = “1”) 0: P4 0←f(XIN), P4 1←f(XIN)/5 1: P4 0←f(XIN)/2, P4 1←f(XIN)/10 At reset R W 0 1 P41 clock output control bit 0 2 Output clock frequency selection bit 0 3 Nothing is allocated. These bits cannot be to written to and are fixed to “0” at reading. 7 0 0× Fig. 2.10.4 Structure of clock output control register 2–198 3825 GROUP USER’S MANUAL APPLICATION 2.10 Oscillation circuit 2.10.3 Oscillating operation The start and stop sources for oscillating operation are described below. (1) Oscillating operation At reset release, the middle-speed mode is provided. At this time, only the main clock oscillates and the X CIN a nd X COUT p ins function as I/O ports. To use the sub-clock, set the P8 0, P81 pull-up (bit 3) of the PULL register A (address 0016 16) to “0” and disconnect each pull-up resistor of the XCIN a nd X COUT p ins. sMiddle-speed mode The internal clock φ after reset release is obtained by dividing f(X IN) by 8 (the f(XIN) is the frequency which is input to the X IN p in). When changing to the high-speed mode: Set the main clock division ratio selection bit (bit 6) of the CPU mode register (address 003B 16) to “0.” When changing to the low-speed mode: Change the mode according to the following procedure. Œ S et the port Xc switch bit (bit 4) of the CPU mode register to “1.”  G enerate the oscillation stabilizing time of X CIN i nput by software. Ž S et the internal system clock selection bit (bit 7) of the CPU mode register to “1.” sHigh-speed mode The clock obtained by dividing f(X IN ) by 2 is an internal clock φ. When changing to the middle-speed mode: Set the main clock division ratio selection bit (bit 6) of the CPU mode register to “1.” When changing to the low-speed mode: Change the mode according to the following procedure. Œ S et the port Xc switch bit (bit 4) of the CPU mode register to “1.”  G enerate the oscillation stabilizing time of XCIN i nput by software. Ž S et the internal system clock selection bit (bit 7) of the CPU mode register to “1.” 3825 GROUP USER’S MANUAL 2–199 APPLICATION 2.10 Oscillation circuit s Low-speed mode The clock obtained by dividing the frequency f(XCIN) input to the XCIN pin by 2 is an internal clock φ . In the low-speed mode, the oscillation of the main clock is stopped by setting the main clock (XIN – XOUT ) stop bit to “1,” so that the low-power operation can be attained. When changing to the middle- or high-speed modes: Change the mode according to the following procedure. Œ S et the main clock (X IN–X OUT) stop bit (bit 5) of the CPU mode register to “0.”  G enerate the oscillation stabilizing time of X IN i nput by software. Ž S et the internal system clock selection bit (bit 7) of the CPU mode register to “0.”  S pecify the main clock division ratio selection bit (bit 6) of the CPU mode register. Notes1: Make a mode change from the middle- or high-speed modes to the low-speed mode after the oscillation of both the main clock and the sub-clock is stabilized (for oscillation stabilizing time, ask the resonator manufacturer for information). 2: F or the sub-clock, the stabilizing of oscillation requires much time. When making a change from the middle-speed or high-speed modes to the stop mode and then making a return from the stop mode while the sub-clock oscillates, the oscillation of the sub-clock is not yet stabilized even when the main clock has become stable and the CPU has been restored. 3: F or a mode change, set to f(X IN) > f(X CIN ) ! 3 . (2) Oscillating operation in the stop mode After the stop mode is provided by executing the S TP i nstruction, every oscillation stops and the internal clock φ s tops at the “H” level. At the time when restoration is made from the stop mode by rest input or by the occurrence of an interrupt request for restoration, oscillation starts. For the details of the stop mode, refer to “ 2.8.1 Stop mode.” (3) Oscillating operation in the wait mode After the wait mode is provided by executing the WIT instruction, the internal clock φ supplied to the CPU stops at the “H” level. As oscillation is continued, the supply of internal clock φ to the peripheral units is continued. At the time when restoration is made from the wait mode by reset input or by the occurrence of an interrupt request for restoration, the supply of internal clock φ to the CPU starts. For the details of the wait mode, refer to “ 2.8.2 Wait mode.” 2–200 3825 GROUP USER’S MANUAL APPLICATION 2.10 Oscillation circuit (4) State transitions of internal clock φ Figure 2.10.5 shows the state transitions of the internal clock φ . RESET Middle-speed mode (f (φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1”↔“0” High-speed mode (f (φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM4 “1”↔“0” “1 CM ”↔ 4 “1 CM “0 ”↔ 6 ” “0 ” Middle-speed mode (f (φ ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” High-speed mode (f (φ ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1”↔“0” CM7 “1”↔“0” CM 4 “1”↔“0” 4 M” C “1 ”↔ 6 ” “0 CM “0 ”↔ “1 b7 b4 CPU mode register (CPUM) [Address 3B16] CM4: Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM5: Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “1 CM ”↔ 5 “1 CM “0 ”↔ 6 ” “0 ” 5 M” C “1 ”↔ 6 ” “0 M 0 C ↔“ ” “1 CM5 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) CM6 “1”↔“0” Low-speed mode (f (φ ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) Notes 1: Switch the mode by the allows shown between the mode blocks.( Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is released. 3: Timer and LCD operate in the wait mode. 4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2. 6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to the middle-/high-speed mode. 7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 2.10.5 State transitions of internal clock φ 3825 GROUP USER’S MANUAL CM5 “1”↔“0” 2–201 APPLICATION 2.10 Oscillation circuit 2.10.4 Oscillation stabilizing time In the oscillating circuit using ceramic resonators, the oscillation is unstable for a certain time when the oscillation of the resonators starts. The time required for stabilizing of oscillation is called oscillation stabilizing time. An appropriate oscillation stabilizing time is required in accordance with the conditions of the oscillation circuit in use. F or oscillation stabilizing time, ask the resonator manufacturer for information. (1) Oscillation stabilizing time at poweron In the oscillating circuit using ceramic resonators, oscillation is unstable for a certain time immediately after poweron. At reset release, the oscillation stabilizing time for approximately 8,000 cycles of XIN input is automatically generated. Figure 2.10.6 shows the oscillation stabilizing time at poweron. qMiddle-/high-speed mode VCC RESET XIN Oscillation stabilizing time Internal reset 2.5 V 2 µs or more Release internal reset state Fig. 2.10.6 Oscillation stabilizing time at poweron 2–202 3825 GROUP USER’S MANUAL APPLICATION 2.10 Oscillation circuit (2) Oscillation stabilizing time at restoration from the stop mode In the stop mode, oscillation stops. When restoration is made from the stop mode by reset input or an interrupt request, the oscillation stabilizing time for approximately 8,000 cycles of X IN input or XCIN input is automatically generated as at poweron. At restoration made by reset, XIN i nput is a clock source of oscillation stabilizing time. At restoration made by an interrupt request, either XIN input or XCIN input set as a system clock immediately before execution of the S TP i nstruction becomes a count source of oscillation stabilizing time. When XIN input is a system clock, the oscillation stabilizing time at restoration becomes approximately 8,000 cycles of XIN input. However, note that the oscillation on the XCIN side may not be stable even after the lapse of this oscillation stabilizing time. For the details of the stop mode, refer to “ 2.8.1 Stop mode.” (3) Oscillation stabilizing time at reoscillation of XIN When starting the oscillation of XIN which was stopped by setting the main clock (XIN–X OUT) stop bit of the CPU mode register to “1,” set this bit to “0.” At this time, generate oscillation stabilizing time by software. Figure 2.10.7 shows the oscillation stabilizing time at reoscillation of X IN. VCC Main clock (XIN–XOUT) stop bit XIN Note: For oscillation stabilizing time, ask the resonator manufacturer for information. Oscillation stabilizing time (Note) Fig. 2.10.7 Oscillation stabilizing time at reoscillation of XIN 3825 GROUP USER’S MANUAL 2–203 CHAPTER 3 APPENDIX 3.1 Built-in PROM version 3.2 Countermeasures against noise 3.3 Control registers 3.4 List of instruction codes 3.5 Machine instructions 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outlines 3.9 SFR allocation 3.10 Pin configuration APPENDIX 3.1 Built-in PROM version 3.1 Built-in PROM version In contrast with the mask ROM version, the microcomputer with a built-in programmable ROM is called the built-in programmable ROM version (referred as “the built-in PROM version”). The following two types of built-in PROM version are available. •EPROM version ........................The contents of the built-in EPROM version can be written, deleted and rewritten. •One Time PROM version.......The contents of the built-in PROM can be written only once and cannot be deleted and rewritten. The EPROM version has the function of the One Time PROM version and also permits deleting and rewriting the contents of the PROM. 3.1.1 Product expansion Table 3.1.1 shows the product expansion of the built-in PROM version. Table 3.1.1 Product expansion of built-in PROM version Product M38257E8-XXXFP One Time M38257E8FP PROM 24576 bytes M38257E8-XXXGP (24446 bytes) M38257E8GP EPROM 24576 bytes (24446 bytes) 100P6S-A V1 PCA4738F-100A PROM RAM Package Programming adapter Remarks Shipped after programming and inspection at plant Shipped in blank V4 Shipped after programming PCA4738G-100 and inspection at plant Shipped in blank V4 640 bytes 100P6D-A V2 M38257E8FS 100D0 V3 PCA4738L-100A EPROM version V1 V2 V3 V4 100P6S-A : 100P6D-A : 100D0 : Shipped in blank : 0.65 mm-pitch plastic molded QFP 0.5 mm-pitch plastic molded QFP 0.65 mm-pitch ceramic LCC The product is shipped without writing any data in the built-in PROM Note: T he number in parentheses denotes a user ROM capacity. 3–2 3825 GROUP USER’S MANUAL APPENDIX 3.1 Built-in PROM version 3.1.2 Performance overview Table 3.1.2 shows a performance overview of the built-in PROM version. The performance of the built-in PROM version is the same as that of the mask ROM version with the exception that the PROM is built in. Table 3.1.2 Performance overview of built-in PROM version Parameter Basic instructions Instruction execution time Memory sizes PROM RAM Programmable I/O ports Oscillation frequency Main clock f(XIN) Sub-clock f(XCIN) Interrupts Timers Serial I/O A-D converter LCD (Liquid Crystal Display) drive control functions Clock output function Clock generating circuit Power source voltage Performance 71 0.5 µs (minimum instructions at 8MHz oscillation frequency) 24576 bytes (user ROM capacity: 24446 bytes) 640 bytes 43 8 MHz (maximum) 32 kHz (standard) to 50 kHz (maximum) 17 sources, 16 vectors (includes key input interrupt) 8-bit ! 3 16-bit ! 2 8-bit ! 1 (operable in clock synchronous mode and UART mode) 8-bit ! 8 c hannels Select 1/2 or 1/3 Select duty ratio value of 2, 3, or 4 40 (maximum) 4 (maximum) 2-bit output 2 built-in circuits (connect an external ceramic resonator or an external quartz-crystal oscillator) 2.5 V (minimum) to 5.0 V (standard) to 5.5 V (maximum) For extended operating temperature version (Ta = –40 °C to –20 °C): 3.0 V (minimum) to 5.0 V (standard) to 5.5 V (maximum) V4.0 V (minimum) in high-speed mode. However, at f(X IN) = (4 ! V CC – 8 ) MHz, 2.5 V to 4.0 V is possible. 32 mW (at 8 MHz oscillation frequency, V CC = 5 V ) 0.045 mW (at 32 kHz oscillation frequency, V CC = 3 V ) –20 °C to 85 °C (for extended operating temperature version: –40 °C to 85 °C) CMOS silicon gate 100D0 (0.65 mm-pitch ceramic LCC) 100P6S-A (0.65 mm-pitch plastic mold QFP) 100P6D-A (0.5 mm-pitch plastic mold QFP) Bias Duty ratio Segment output Common output Power dissipation High-speed mode Low-speed mode Operating temperature range Device structure Packages EPROM version One Time PROM version Note: T he parts enclosed by thick line denotes performance peculiar to the PROM version. 3825 GROUP USER’S MANUAL 3–3 APPENDIX 3.1 Built-in PROM version 3.1.3 Pin configuration The pin configuration of the built-in PROM version is the same as that of the mask ROM version. Figure 3.1.1 shows the pin configuration of the EPROM version. SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 P30/SEG 18 P31/SEG 19 P32/SEG 20 P33/SEG 21 P34/SEG 22 P35/SEG 23 P36/SEG 24 P37/SEG 25 P00/SEG 26 P01/SEG 27 P02/SEG 28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 VCC VREF AV SS COM 3 COM 2 COM 1 COM 0 VL3 VL2 C2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/X COUT P81/X CIN RESET P70 P71 P72 P73 M38257E8FS P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG 37 P14/SEG 38 P15/SEG 39 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 C1 VL1 P67/AN 7 P66/AN 6 P65/AN5 P64/AN4 P63/AN 3 P62/AN2 P61/AN1 P60/AN 0 P57/ADT P56/TOUT P55/CNTR 1 P54/CNTR 0 P53/RTP 1 P52/RTP 0 P51/INT3 P50/INT 2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT 0 P41 / f(X IN)/5 / f(X IN)/10 JAPAN Package Type : 100D0 Fig. 3.1.1 Pin configuration of EPROM version (top view) 3–4 3825 GROUP USER’S MANUAL P40 / f(XIN) / f(X IN)/2 P77 P76 P75 P74 APPENDIX 3.1 Built-in PROM version Figure 3.1.2 and Figure 3.1.3 show the pin configurations of the One Time PROM version. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 VCC VREF AV SS COM 3 COM 2 COM 1 COM 0 VL3 VL2 C2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/X COUT P81/X CIN RESET P70 P71 P72 P73 M38257E8-XXXFP M38257E8FP C1 VL1 P67/AN 7 P66/AN 6 P65/AN5 P64/AN4 P63/AN 3 P62/AN 2 P61/AN1 P60/AN0 P57/ADT P56/TOUT P55/CNTR 1 P54/CNTR 0 P53/RTP 1 P52/RTP 0 P51/INT 3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT 1 P42/INT0 Package type : 100P6S-A Fig. 3.1.2 Pin configuration of One Time PROM version (top view) (1) 3825 GROUP USER’S MANUAL P41 / f(XIN)/5 / f(X IN)/10 P40 / f(XIN) / f(X IN)/2 P77 P76 P75 P74 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG 38 P15/SEG 39 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 P30/SEG18 P31/SEG19 P32/SEG 20 P33/SEG 21 P34/SEG 22 P35/SEG 23 P36/SEG 24 P37/SEG 25 P00/SEG 26 P01/SEG 27 P02/SEG 28 P03/SEG 29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 3–5 APPENDIX 3.1 Built-in PROM version 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 VCC VREF AV SS COM 3 COM 2 COM 1 COM 0 VL3 VL2 C2 C1 VL1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/XCOUT P81/XCIN RESET P70 P71 P72 P73 P74 P75 P76 P67/AN7 P66/AN6 P65/AN 5 P64/AN4 P63/AN3 P62/AN 2 P61/AN 1 P60/AN0 P57/ADT P56/TOUT P55/CNTR 1 P54/CNTR 0 P53/RTP1 P52/RTP 0 P51/INT 3 P50/INT 2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT 1 P42/INT0 P41 / f(X IN)/5 / f(X IN)/10 Package type : 100P6D Fig. 3.1.3 Pin configuration of One Time PROM version (top view) (2) 3–6 3825 GROUP USER’S MANUAL P40 / f(X IN) / f(X IN)/2 P77 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 P30/SEG 18 P31/SEG 19 P32/SEG 20 P33/SEG 21 P34/SEG 22 P35/SEG 23 P36/SEG 24 P37/SEG 25 P00/SEG 26 P01/SEG 27 P02/SEG 28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG 34 P11/SEG 35 P12/SEG36 P13/SEG37 M38257E8-XXXGP M38257E8GP Main clock input XIN Reset input RESET 35 91 40 Main clock output XOUT Data bus 2 VL1 1 C1 100 (5V) VCC (0V) VSS 38 39 Clock generating circuit CPU PROM RAM C2 99 VL2 98 VL3 XCIN Sub-clock input XCOUT Sub-clock output φ Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) PCH A X Y S PCL PS LCD display RAM (20 bytes) LCD drive control circuit 97 96 95 94 COM0 COM1 COM2 COM3 Address bus 90 89 88 87 86 85 84 83 Converter (8) Tout CNTR0,CNTR1 RTP0,RTP1 ADT 3.1.4 Functional block diagram Figure 3.1.4 shows the functional block diagram of the built-in PROM version. 36 37 27 28 29 30 31 32 33 34 92 93 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 INT2,INT3 INT0,INT1 Fig. 3.1.4 Functional block diagram of built-in PROM version Serial I/O (8) 3825 GROUP USER’S MANUAL Key-on wake up XCOUT P5(8) P4(8) P3(8) 82 81 80 79 78 77 76 75 74 73 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 XCIN P8(2) P7(8) P6(8) P2(8) P1(8) P0(8) 3 4 5 6 7 8 9 10 65 66 67 68 69 70 71 72 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O port P8 I/O port P5 I/O port P4 VREF I/O port P7 I/O port P6 AVSS (0V) Output port P3 I/O port P2 Output port P1 Output port P0 3.1 Built-in PROM version Note : Pin numbers are for package type 100P6S-A. APPENDIX 3–7 APPENDIX 3.1 Built-in PROM version 3.1.5 Notes on use Notes on using the built-in PROM version are described below. (1) All products of built-in PROM version s Notes on programming qWhen programming the contents of the PROM, use the dedicated programming adapter. This permits programming with a general-purpose PROM programmer. At that time, set all of SW1, SW2 and SW3 in the above programming adapter to “OFF.” qAs a high voltage is used for programming, be careful not to apply overvoltage to pins. Special care must be exercised at poweron. s Notes on reading When reading out the contents of the PROM, use the dedicated programming adapter as in programming. This permits reading out with a general-purpose PROM programmer. At that time, set all of SW1, SW2 and SW3 in the programmer to “OFF.” s Notes on using port P7 0 When using port P7 0 a s an input port in the One Time PROM/EPROM version, connect a resistors of several k externally to port P70 in series. If this pin is not used, connect a resistor of several k externally to VSS i n series (for improvement of the value withstand noise operation failure). For details, refer to “3.2 Countermeasures against noise, 3.2.1 Shortest wiring length, (3) Wiring to the V PP p in of the One Time PROM version and the EPROM version.” (2) EPROM Version s Notes on deleting qSunlight and fluorescent lamps include light which may delete programmed information. For use in the read mode, cover the transparent glass part of the delete window with a seal or others. qThe seal to cover the transparent glass part is prepared by us. This seal is metallic (aluminium) for reasons of prevention of information-deleting light and toughness. Be careful not to bring this seal into contact with lead pins of the microcomputer. qBefore deleting information, clean the transparent glass. Finger marks and seal paste may block ultraviolet rays and effect delete characteristics. s Notes on mounting qTo mount the EPROM version for a purpose other than evaluation, use a suitable mounting socket. When mounting a ceramic package on the socket, fix it securely with silicone resin. 3–8 3825 GROUP USER’S MANUAL APPENDIX 3.1 Built-in PROM version (3) One Time PROM version s Notes on setting the PROM programmer area q For products shipped in blank, access to the first 128 bytes and addresses FFFE16 and FFFF16 in the built-in PROM user area is inhibited. Note the above point when setting the PROM programmer area. s Notes before actual use The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not performed in the assembly process and the following processes. To ensure reliability after programming, performing programming and test according to the Figure 3.1.5 before actual use are recommended. Programming with PROM programmer Screening (Caution) (Leave at 150 °C for 40 hours) Verification with PROM programmer Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Functional check in target device Fig. 3.1.5 Programming and testing of One Time PROM version (shipped in blank) 3825 GROUP USER’S MANUAL 3–9 APPENDIX 3.2 Countermeasures against noise 3.2 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.2.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the reset input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the V SS p in with the shortest possible wiring (within 20 mm). Reason The reset works to initialize the internal state of a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS RESET VSS Reset circuit VSS RESET VSS Fig. 3.2.1 Wiring for the RESET input pin (2) Wiring for clock input/output pins qMake the length of wiring which is connected to clock I/O pins as short as possible. qMake the length of wiring (within 20 mm) across the grouding lead of a capacitor which is connected to an oscillator and the V SS p in of a microcomputer as short as possible. q Separate the V SS p attern only for oscillation from other V SS p atterns. Noise XIN XOUT VSS XIN XOUT VSS Fig. 3.2.2 Wiring for clock I/O pins 3–10 3825 GROUP USER’S MANUAL APPENDIX 3.2 Countermeasures against noise Reason A microcomputer’s operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS l evel of a microcomputer and the V SS l evel of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring to the VPP pin of the One Time PROM version and the EPROM version qMake the length of wiring which is connected to the V PP p in as short as possible. qConnect an approximately 5 kΩ resistor to the V PP p in in serial (refer to F igure 3.2.3 ). V 1 When a microcomputer does not have the CNVSS pin, the V PP pin is also as the input pin adjacent to the RESET input pin. Reason The V PP p in of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the V PP p in, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. 3.2.2 Connection of a bypass capacitor across the V SS l ine and the V CC l ine Connect an approximately 0.1 µF bypass capacitor across the V SS l ine and the V CC l ine as follows: q Connect a bypass capacitor across the V SS p in and the V CC p in at equal length. q Connect a bypass capacitor across the V SS p in and the VCC pin with the shortest possible wiring. qUse lines with a larger diameter than other signal lines for V SS l ine and V CC l ine. 3825 Approximately 5 kΩ V V For M38257E8; Approximately 10 k Ω P70/VPP RESET When the microcomputer does not have the CNV SS pin, the V PP pin is also used as the input pin adjacent to the RESET pin. Fig. 3.2.3 Wiring for the V PP pin of the One Time PROM and the EPROM version Chip VCC VSS Fig. 3.2.4 Bypass capacitor across the V SS l ine and the VCC l ine 3825 GROUP USER’S MANUAL 3–11 APPENDIX 3.2 Countermeasures against noise 3.2.3 Wiring to analog input pins qConnect an approximately 100 Ω to 1 k Ω resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. qConnect an approximately 1000 pF capacitor across the V SS p in and the analog input pin. Besides, connect the capacitor to the VSS p in as close as possible. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the V SS p in is grounded at a position far away from the V SS p in, noise on the GND line may enter a microcomputer through the capacitor. 3.2.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Installing an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Noise Sensor Microcomputer Analog input pin VSS Fig. 3.2.5 Analog signal line and a resistor and a capacitor Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.2.6 Wiring for a large current signal line 3–12 3825 GROUP USER’S MANUAL APPENDIX 3.2 Countermeasures against noise 3.2.5 Installing an oscillator away from signal lines where potential levels change frequently Install an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3.2.6 Oscillator protection using V SS p attern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the V SS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS p attern from other V SS p atterns. Do not cross CNTR XIN XOUT VSS Fig. 3.2.7 Wiring to a signal line where potential levels change frequently An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines 3.2.7 Setup for I/O ports Setup I/O ports using hardware and software as follows: q Connect a resistor of 100 Ω o r more to an I/O port in series. q As for an input port, read data several times by a program for checking whether input levels are equal or not. qAs for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. qRewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. Fig. 3.2.8 V SS p attern on the underside of an oscillator Noise Data bus Direction register Data register I/O port pins Noise Fig. 3.2.9 Setup for I/O ports 3825 GROUP USER’S MANUAL 3–13 APPENDIX 3.2 Countermeasures against noise 3.2.8 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. qAssigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. q Decrements the SWDT contents by 1 at each interrupt processing. qDetermins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). q Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: Œ If the SWDT contents are not initialized to the initial value N but continued to decrement and if they exceed the limit (and reach 0 or less) Main routine (SWDT) ← N CLI Main processing ≠N (SWDT) = N? =N Interrupt processing routine (SWDT) ← (SWDT) – 1 Interrupt processing >0 RTI Return Main routine errors (SWDT) ≤ 0? ≤0 q Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. q Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: xIf the SWDT contents do not change after interrupt processing If the changed SWDT contents are abnormal (In Figure 3.2.10, the main routine determines that the interrupt processing routine has failed only if the SWDT contents do not change). Interrupt processing routine errors Fig. 3.2.10 Watchdog timer by software 3–14 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers 3.3 Control registers Port P1 output control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 output control register (P1C) [Address 03 16] Name B 0 Ports P1 0–P1 5 output control bit Functions 0 : Output function is invalid 1 : Output function is valid At reset R W × 0 1 Nothing is allocated. These bits cannot be written to to and be read out. 5 6 7 Port P1 6 direction register Port P1 7 direction register 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 ×× 0 0 × × Fig. 3.3.1 Structure of port P1 output control register Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 2, 4 to 8) [Address 05 16, 0916, 0B 16, 0D 16, 0F 16, 11 16] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi 0 input mode 1 : Port Pi 0 output mode 0 : Port Pi 1 input mode 1 : Port Pi 1 output mode 0 : Port Pi 2 input mode 1 : Port Pi 2 output mode 0 : Port Pi 3 input mode 1 : Port Pi 3 output mode 0 : Port Pi 4 input mode 1 : Port Pi 4 output mode 0 : Port Pi 5 input mode 1 : Port Pi 5 output mode 0 : Port Pi 6 input mode 1 : Port Pi 6 output mode 0 : Port Pi 7 input mode 1 : Port Pi 7 output mode At reset 0 RW × × × × × × × × 0 0 0 0 0 0 0 Notes 1: Nothing is allocated bit 0 of port P7 direction register and bit 2 to bit 7 of port P8 direction register. 2: The contents of the port Pi direction register cannot be read out (refer to “2.1.4 Notes on use” ). Fig. 3.3.2 Structure of port Pi (i = 2, 4 to 8) direction registers 3825 GROUP USER’S MANUAL 3–15 APPENDIX 3.3 Control registers PULL register A b7 b6 b5 b4 b3 b2 b1 b0 PULL register A (PULLA) [Address 1616] B Functions Name P0, P1 0–P15, P3 pull-down 0 : No pull-down 0 (P0, P3 output function is valid) 1 : Pull-down (P0, P3 output function is invalid) 1 P16, P1 7 pull-up 2 3 4 5 6, 7 0 : No pull-up 1 : Pull-up 0 : No pull-up P20–P2 7 pull-up 1 : Pull-up 0 : No pull-up P80, P8 1 pull-up 1 : Pull-up 0 : No pull-up P40–P4 3 pull-up 1 : Pull-up 0 : No pull-up P44–P4 7 pull-up 1 : Pull-up Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. At reset R W 1 0 0 0 0 0 0 0× Note: For ports set for the output mode, pull-up or pull-down is impossible (except ports P0 and P3). Fig. 3.3.3 Structure of PULL register A PULL register B b7 b6 b5 b4 b3 b2 b1 b0 PULL register B (PULLB) [Address 1716] B Name 0 P50–P5 3 pull-up 1 2 3 4 5 P54–P5 7 pull-up P60–P6 3 pull-up P64–P6 7 pull-up P71–P7 3 pull-up P74–P7 7 pull-up Functions 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up At reset R W 0 0 0 0 0 0 0 0× 6, Nothing is allocated. These bits cannot be written 7 to and are fixed to “0” at reading. Note: For ports set for the output mode, pull-up is impossible. Fig. 3.3.4 Structure of PULL register B 3–16 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers Serial I/O status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status register (SIOSTS) [Address 19 16] B 0 1 2 3 4 5 6 7 Name Functions At reset R W × 0 0 0 0 0 0 0 1 × × × × × × 1× 0: Buffer full Transmit buffer 1: Buffer empty empty flag (TBE) Receive buffer full flag 0: Buffer empty (RBF) 1: Buffer full Transmit shift register shift 0: Transmit shift in progress completion flag (TSC) 1: Transmit shift completed Overrun error flag 0: No error (OE) 1: Overrun error Parity error flag 0: No error (PE) 1: Parity error Framing error flag 0: No error (FE) 1: Framing error Summing error flag 0: (OE) U (PE) U (FE) = 0 (SE) 1: (OE) U (PE) U (FE) = 1 Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading. Fig. 3.3.5 Structure of serial I/O status register 3825 GROUP USER’S MANUAL 3–17 APPENDIX 3.3 Control registers Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address 1A16] B 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Functions 0: f(X IN) 1: f(X IN)/4 •In clock synchronous mode 0: BRG output/4 1: External clock input •In UART mode 0: BRG output/16 1: External clock input/16 0: P47/SRDY pin operates as I/O port P4 7 1: P47/SRDY pin operates as signal output pin S RDY (SRDY signal indicates receive enable state) 0: When transmit buffer has emptied 1: When transmit shift operation is completed 0: Transmit disabled 1: Transmit enabled 0: Receive disabled 1: Receive enabled 0: Clock asynchronous serial I/O (UART) mode 1: Clock synchronous serial I/O mode 0: Serial I/O disabled (pins P4 4–P47 operate as I/O pins) 1: Serial I/O enabled (pins P4 4–P47 operate as serial I/O pins) 0 At reset R W 0 0 2 SRDY output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O mode selection bit (SIOM) Serial I/O enable bit (SIOE) 0 4 5 6 0 0 0 7 0 Fig. 3.3.6 Structure of serial I/O control register 3–18 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address 1B 16] B Name Functions 0: 8 bits 0 Character length selection bit (CHAS) 1: 7 bits 0: Parity checking disabled 1 Parity enable bit 1: Parity checking enabled (PARE) 0: Even parity Parity selection bit 2 1: Odd parity (PARS) 0: 1 stop bit 3 Stop bit length selection bit (STPS) 1: 2 stop bits 0: CMOS output (in output mode) 4 P45/TxD P-channel 1: N-channel open-drain output output disable bit (in output mode) (POFF) 5 Nothing is allocated. These bits cannot be written to to and are fixed to “1” at reading. 7 At reset R W 0 0 0 0 0 1 1× Fig. 3.3.7 Structure of UART control register 3825 GROUP USER’S MANUAL 3–19 APPENDIX 3.3 Control registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address 2716] B 0 Name Timer X write control bit Real time port control bit Functions 0 : Write value in latch and counter 1 : Write value in latch only 0 : Real time port function invalid 1 : Real time port function valid 0: 1: 0: 1: b5b4 At reset R W 0 1 0 2 3 4 5 6 P52 data for real time port P53 data for real time port Timer X operating mode bits “L” level output “H” level output “L” level output “H” level output 0 0 0 0 0 CNTR 0 active edge switch bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode •CNTR 0 interrupt 0 : Falling edge active 1 : Rising edge active •Pulse output mode 0 : Start at initial level “H” output 1 : Start at initial level “L” output •Event counter mode 0 : Rising edge active 1 : Falling edge active •Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width 0 : Count start 1 : Count stop 7 Timer X stop control bit 0 Fig. 3.3.8 Structure of timer X mode register 3–20 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address 2816 ] Name Functions 0 Nothing is allocated. These bits cannot be to written and are fixed to “0” at reading. 3 4 Timer Y operating mode bits 5 6 CNTR 1 active edge switch bit b5b4 B At reset R W 0 0× 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode •CNTR 1 interrupt 0 : Falling edge active 1 : Rising edge active •Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge •Event counter mode 0 : Rising edge active 1 : Falling edge active 0 0 0 7 Timer Y stop control bit 0 : Count start 1 : Count stop 0 Fig. 3.3.9 Structure of timer Y mode register 3825 GROUP USER’S MANUAL 3–21 APPENDIX 3.3 Control registers Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M) [Address 2916] B 0 Name TOUT output active edge switch bit TOUT output control bit Timer 2 write control bit Functions 0 : Start at “H” output 1 : Start at “L” output 0 : T OUT output disabled 1 : T OUT output enabled At reset R W 0 1 0 2 3 0 : Write value in latch and counter 1 : Write value in latch only Timer 2 count source 0 : Timer 1 underflow 1 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Timer 3 count source 0 : Timer 1 underflow 1 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 0 0 4 0 Timer 1 count source 0 : f(X IN)/16 selection bit (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 1 : f(X CIN) 6, 7 Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. Note: Internal clock φ is f(X CIN)/2 in the low-speed mode. 5 0 0 0× Fig. 3.3.10 Structure of timer 123 mode register Clock output control register b7 b6 b5 b4 b3 b2 b1 b0 Clock output control register (TCON) [Address 2A16] B Name 0 P40 clock output control bit Functions 0: Port function 1: Clock output (Port direction register = “1”) 0: Port function 1: Clock output (Port direction register = “1”) 0: P4 0←f(XIN), P41←f(XIN)/5 1: P4 0←f(XIN)/2, P41←f(XIN)/10 At reset R W 0 1 P41 clock output control bit 0 2 Output clock frequency selection bit 0 3 Nothing is allocated. These bits cannot be to written to and are fixed to “0” at reading. 7 0 0× Fig. 3.3.11 Structure of clock output control register 3–22 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address 3416] B 0 1 2 Name Analog input pin selection bits Functions b2 b1 b0 At reset R W 0 0 0 0 0 0: AN 0 0 0 1: AN 1 0 1 0: AN 2 0 1 1: AN 3 1 0 0: AN 4 1 0 1: AN 5 1 1 0: AN 6 1 1 1: AN 7 3 4 A-D conversion completion bit VREF input switch bit 0: Conversion in progress 1: Conversion completed 0: OFF 1: ON 0: A-D external trigger invalid (internal trigger selected) 1: A-D external trigger valid (external trigger selected) 0: At A-D conversion completed 1: At falling of ADT pin input 1 0 5 A-D external trigger valid bit 0 6 Interrupt source selection bit 0 0× 7 Nothing is allocated. This bit cannot be written to and is fixed “0” at reading. 0 Note: When an internal trigger is selected, A-D conversion is started by setting bit 3 to “0.” Writing only “0” to bit 3 is valid. Even if “1” is written to bit 3, it is not set to “0.” Accordingly, to write values to the ADCON without affecting bit 3, set bit 3 to “1.” Fig. 3.3.12 Structure of A-D control register 3825 GROUP USER’S MANUAL 3–23 APPENDIX 3.3 Control registers Segment output enable register b7 b6 b5 b4 b3 b2 b1 b0 00 Segment output enable register (SEG) [Address 3816] B Name Functions At reset R W 0: Output ports P30–P35 0 1: Segment output SEG18–SEG23 0: Output ports P36, P37 0 1: Segment output SEG24, SEG25 0: Output ports P00–P05 0 1: Segment output SEG26–SEG31 0: Output ports P06, P07 0 1: Segment output SEG32, SEG33 0: Output port P10 0 1: Segment output SEG34 0: Output ports P11–P15 0 1: Segment output SEG35–SEG39 0 00 0 Segment output enable bit 0 1 Segment output enable bit 1 2 Segment output enable bit 2 3 Segment output enable bit 3 4 Segment output enable bit 4 5 Segment output enable bit 5 6,7 Fix these bits to “0.” Fig. 3.3.13 Structure of segment output register 3–24 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers LCD mode register b7 b6 b5 b4 b3 b2 b1 b0 0 LCD mode register (LM) [Address 3916] B 0 1 Name Duty ratio selection bits b1b0 Functions 00: Not available 01: 2 (use COM0, COM1) 10: 3 (use COM0–COM2) 11: 4 (use COM0–COM3) 0: 1/3 bias 1: 1/2 bias 0: LCD OFF 1: LCD ON 0: Voltage multiplier disable 1: Voltage multiplier enable b6b5 At reset R W 0 0 2 Bias control bit 3 LCD enable bit 4 Voltage multiplier control bit 0 0 0 0 5 LCD circuit divider division ratio selection bits (Note 1) 6 7 LCDCK count source selection bit (Note 2) 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source 0: f(XCIN)/32 1: f(XIN)/8192 0 Notes 1: Reference values at f(XIN) = 8 MHz 00: 977 Hz 01: 488 Hz 10: 244 Hz 11: 122 Hz 2: LCDCK is a clock for a LCD timing controller. Fig. 3.3.14 Structure of LCD mode register 3825 GROUP USER’S MANUAL 3–25 APPENDIX 3.3 Control registers Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address 3A16 ] B 0 1 2 3 4 to 7 Functions 0 : Falling edge active INT0 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT1 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT2 interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT3 interrupt edge 1 : Rising edge active selection bit Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. Name At reset R W 0 0 0 0 0 0× Fig. 3.3.15 Structure of interrupt edge selection register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register (CPUM) [Address 3B 16] B 0 1 Name Processor mode bits Functions b1b0 At reset R W 0 0 00: Single-chip mode 01: 10: Not available 11: Stack page selection bit Fix this bit to “1.” Port X C switch bit 0: I/O port 1: XCIN, XCOUT 0: 0 page 1: 1 page 2 3 4 0 1 0 0 1 11 5 Main clock (X IN–XOUT) 0: Oscillating stop bit 1: Stopped 6 Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) 7 Internal system clock selection bit 0 Fig. 3.3.16 Structure of CPU mode register 3–26 3825 GROUP USER’S MANUAL APPENDIX 3.3 Control registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 3C 16] B 0 1 2 3 4 5 6 7 Name INT 0 interrupt request bit INT 1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 V V V V V V V V V : “0” can be set by software, but “1” cannot be set. Fig. 3.3.17 Structure of interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 3D 16] B 0 1 2 3 4 5 6 7 Name CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT 2 interrupt request bit INT 3 interrupt request bit Key input interrupt request bit ADT/A-D conversion interrupt request bit Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 V V V V V V V 0× 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. V : “0” can be set by software, but “1” cannot be set. Fig. 3.3.18 Structure of interrupt request register 2 3825 GROUP USER’S MANUAL 3–27 APPENDIX 3.3 Control registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 3E 16] B 0 1 2 3 4 5 6 7 Name INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 Fig. 3.3.19 Structure of interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] B 0 1 2 3 4 5 6 7 Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/A-D conversion interrupt enable bit Fix this bit to “0.” Functions 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled At reset R W 0 0 0 0 0 0 0 0 00 Fig. 3.3.20 Structure of interrupt control register 2 3–28 3825 GROUP USER’S MANUAL APPENDIX 3.4 List of instruction codes 3.4 List of instruction codes D3 – D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 – D4 0 1 2 3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y — STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A — ROR A — B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK ORA JSR IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y CLT JSR SP SET — PHP — 0001 1 BPL JSR ABS BMI — BIT ZP — COM ZP — TST ZP — STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP — CPX ZP — CLC — BIT ABS LDM ZP JMP ABS — JMP IND — STY ABS — LDY ABS ORA CLB ASL ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC AND CLB ROL ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI EOR STP IND, X (Note) EOR IND, Y — PHA 0101 5 BVC CLI EOR CLB LSR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS ADC MUL IND, X (Note) ADC IND, Y STA IND, X STA IND, Y LDA IND, X — RRF ZP — LDX IMM PLA 0111 7 BVS SEI ADC CLB ROR ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS — LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B LDA JMP IND, Y ZP, IND SLW CMP (Note) IND, X WIT CMP IND, Y — CLV TSX LDX LDA LDY CLB ABS, X ABS, X ABS, Y 5, ZP CPY ABS — CPX ABS — CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D CLD — DEC CMP CLB ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E FST SBC (Note) IND, X DIV SBC IND, Y — INX NOP 1111 F SED — INC SBC CLB ABS, X ABS, X 7, ZP 3-byte instruction 2-byte instruction 1-byte instruction 3825 GROUP USER’S MANUAL 3-29 APPENDIX 3.5 Machine instructions 3.5 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 A←A+M+C When T = 1 M(X) ← M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. “AND’s” the accumulator and memory contents. The results are entered into the accumulator. “AND’s” the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is “0”. Branches when the contents of the bit specified in the accumulator or memory is “1”. Branches when the contents of carry flag is “0”. Branches when the contents of carry flag is “1”. Branches when the contents of zero flag is “1”. 24 3 IMM # OP n 69 2 A # OP n 2 BIT, A # OP n ZP # OP n 65 3 BIT, ZP # OP n 2 # ASL C← 7 0 ←0 BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT Ab o r M b = 0 ? Ab o r M b = 1 ? C = 0? C = 1? Z = 1? V A M BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA N = 1? Z = 0? N = 0? PC ← PC ± offset B←1 M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 M(S) ← PS S←S–1 PCL ← ADL PCH ← ADH BRK 3-30 V When T = 1 M(X) ← M(X) V AND (Note 1) When T = 0 A←A M 29 2 2 25 3 2 M 0A 2 1 06 5 2 13 4 + 2i 03 4 + 2i 2 17 5 + 2i 07 5 + 2i 3 2 3 “AND’s” the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is “1”. Branches when the contents of zero flag is “0”. 2 Branches when the contents of negative flag is “0”. Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1 3825 GROUP USER’S MANUAL APPENDIX 3.5 Machine instructions Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 N N 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N • • • • • Z • 16 6 2 0E 6 3 1E 7 3 N • • • • • Z C • • • • • • • • • 90 2 • • • • • • • 2 • • • • • • • • B0 2 2 • • • • • • • • F0 2 2 • • • • • • • • 2C 4 3 M7 M6 • • • • Z • 30 2 2 • • • • • • • • D0 2 2 • • • • • • • • 10 2 2 • • • • • • • • 80 4 2 • • • • • • • • • • • 1 • 1 • • 3825 GROUP USER’S MANUAL 3-31 APPENDIX 3.5 Machine instructions Addressing mode Symbol Function Details IMP OP n BVC (Note 4) BVS (Note 4) CLB V = 0? Branches when the contents of overflow flag is “0”. Branches when the contents of overflow flag is “1”. Clears the contents of the bit specified in the accumulator or memory to “0.” Clears the contents of the carry flag to “0”. 18 2 1 1B 2 + 2i 1 1F 5 + 2i 2 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # V = 1? Ab o r M b ← 0 C←0 D←0 I←0 T←0 V←0 When T = 0 A–M When T = 1 M(X) – M M←M X–M CLC CLD Clears the contents of decimal mode flag to “0.” Clears the contents of interrupt disable flag to “0.” Clears the contents of index X mode flag to “0.” Clears the contents of overflow flag to “0.” D8 2 1 CLI 58 2 1 CLT 12 2 1 CLV B8 2 1 CMP (Note 3) Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one’s complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 2 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1’s complement of the remainder on the stack. “Exclusive-ORs” the contents of accumulator and memory. The results are stored in the accumulator. “Exclusive-ORs” the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Connects oscillator output to the XOUT pin. E2 2 1 88 2 1 C9 2 2 C5 3 2 COM 44 5 2 CPX E0 2 2 E4 3 2 CPY Y–M A ← A – 1 or M←M–1 X←X–1 Y←Y–1 A ← (M(zz + X + 1), M(zz + X)) / A M(S) ← 1’s complememt of Remainder S←S–1 When T = 0 – A← AVM When T = 1 – M(X) ← M(X) V M C0 2 2 C4 3 2 DEC 1A 2 1 C6 5 2 DEX DEY 1 DIV EOR (Note 1) 49 2 2 45 3 2 FST A ← A + 1 or M←M+1 X←X+1 Y←Y+1 INC Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 2 1 3A 2 1 E6 5 2 INX INY C8 2 1 3-32 3825 GROUP USER’S MANUAL APPENDIX 3.5 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n 50 2 N • 70 2 2 • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • 0 • • • • • • • • 0 • • • • 0 • • • • • • D5 4 CD 4 0 • • • • • • 2 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 N • • • • • Z C N EC 4 • • • • • Z • 3 N • • • • • Z C CC 4 3 N • • • • • Z C D6 6 2 CE 6 3 DE 7 3 N • • • • • Z • N • • • • • Z • N E2 16 2 • • • • • Z • • • • • • • • • 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N • • • • • Z • • F6 6 EE 6 • • • • • • • 2 3 FE 7 3 N • • • • • Z • N • • • • • Z • N • • • • • Z • 3825 GROUP USER’S MANUAL 3-33 APPENDIX 3.5 Machine instructions Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL ← ADL PCH ← ADH If addressing mode is IND PCL ← M (ADH, ADL) PCH ← M (ADH, ADL + 1) If addressing mode is ZP, IND PCL ← M(00, ADL) PCH ← M(00, ADL + 1) M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 After executing the above, if addressing mode is ABS, PCL ← ADL PCH ← ADH If addressing mode is SP, PCL ← ADL PCH ← FF If addressing mode is ZP, IND, PCL ← M(00, ADL) PCH ← M(00, ADL + 1) When T = 0 A←M When T = 1 M(X) ← M M ← nn X←M Y←M Jumps to the specified address. IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # JSR After storing contents of program counter in stack, and jumps to the specified address. LDA (Note 2) Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value. A9 2 2 A5 3 2 LDM 3C 4 3 LDX Load index register X with contents of memory. Load index register Y with contents of memory. 0 →C Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 2 1 A2 2 2 A6 3 2 LDY A0 2 2 A4 3 2 LSR 7 0→ 4A 2 1 46 5 2 MUL (Note 5) M(S) · A ← A ! M(zz + X) S←S–1 NOP PC ← PC + 1 When T = 0 A←AVM When T = 1 M(X) ← M(X) V M ORA (Note 1) “Logical OR’s” the contents of memory and accumulator. The result is stored in the accumulator. “Logical OR’s” the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X. 09 2 2 05 3 2 3-34 3825 GROUP USER’S MANUAL APPENDIX 3.5 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n 6C 5 # OP n 2 # OP n # OP n N • 20 6 3 02 7 2 22 5 2 • • • • • • • • B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N • • • • • Z • • • • • • • • • B6 4 B4 4 56 6 2 AE 4 AC 4 4E 6 3 BE 5 3 N • • • • • Z • 2 3 BC 5 3 N • • • • • Z • 2 3 5E 7 3 0 • • • • • Z C 62 15 2 • • • • • • • • • • • • • • • • 15 4 2 0D 4 3 1D 5 3 19 5 3 01 6 2 11 6 2 N • • • • • Z • 3825 GROUP USER’S MANUAL 3-35 APPENDIX 3.5 Machine instructions Addressing mode Symbol Function Details IMP OP n PHA M(S) ← A S←S–1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 48 3 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # PHP M(S) ← PS S←S–1 08 3 1 PLA S←S+1 A ← M(S) 68 4 1 PLP S←S+1 PS ← M(S) 28 4 1 ROL 7 ← 0 ←C ← 2A 2 1 26 5 2 ROR 7 C→ 0 → 6A 2 1 66 5 2 RRF 7 → S←S+1 PS ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) 0 → 82 8 2 RTI Returns from an interrupt routine to the main routine. 40 6 1 RTS Returns from a subroutine to the main routine. 60 6 1 SBC (Note 1) (Note 5) When T = 0 A←A–M–C When T = 1 M(X) ← M(X) – M – C Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to “1.” Sets the contents of the carry flag to “1.” 38 2 1 E9 2 2 E5 3 2 SEB Ab o r M b ← 1 C←1 D←1 I←1 T←1 0B 2 + 2i 1 0F 5 + 2i 2 SEC SED Sets the contents of the decimal mode flag to “1.” Sets the contents of the interrupt disable flag to “1.” Sets the contents of the index X mode flag to “1.” Disconnects the oscillator output from the XOUT pin. F8 2 1 SEI 78 2 1 SET 32 2 1 SLW C2 2 1 3-36 3825 GROUP USER’S MANUAL APPENDIX 3.5 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n N • • • • • • • • • N • • • • • Z • (Value saved in stack) 36 6 2 2E 6 3 3E 7 3 N • • • • • Z C 76 6 2 6E 6 3 7E 7 3 N • • • • • Z C • • • • • • • • (Value saved in stack) • • • • • • • • F5 4 2 ED 4 3 FD 5 3 F9 5 3 E1 6 2 F1 6 2 N V • • • • Z C • • • • • • • • • • • • • • • 1 • • • • 1 • • • • • • • • 1 • • • • 1 • • • • • • • • • • • • • 3825 GROUP USER’S MANUAL 3-37 APPENDIX 3.5 Machine instructions Addressing mode Symbol Function Details IMP OP n STA M←A Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A # OP n ZP # OP n 85 4 42 2 BIT, ZP # OP n 2 # STP (Note 5) STX M←X M←Y X←A Y←A M = 0? X←S A←X S←X A←Y Stops the oscillator. 1 Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to AA 2 index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are “0” or not. Transfers the contents of the stack pointer to BA 2 index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 8A 2 1 A8 2 1 86 4 84 4 2 STY 2 TAX TAY 1 TST 64 3 2 TSX TXA 1 TXS 9A 2 1 TYA 98 2 1 WIT (Note 5) Notes 1 2 3 4 5 C2 2 1 : The number of cycles “n” is increased by 3 when T is 1. : The number of cycles “n” is increased by 2 when T is 1. : The number of cycles “n” is increased by 1 when T is 1. : The number of cycles “n” is increased by 2 when branching has occurred. : N, V, and Z flags are invalid in decimal operation mode. 3-38 3825 GROUP USER’S MANUAL APPENDIX 3.5 Machine instructions Addressing mode ZP, X OP n 95 5 ZP, Y # OP n 2 ABS # OP n 8D 5 ABS, X # OP n 3 9D 6 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n 3 99 6 # OP n 3 # OP n 81 7 # OP n 2 91 7 # OP n 2 N • • • • • • • • • 96 5 2 8E 5 3 • • • • • • • • 94 5 2 8C 5 3 • • • • • • • • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • • • • • • • • • N • • • • • Z • • • • • • • • • Symbol IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + – V – V – ← X Y S PC PS PCH PCL ADH ADL FF nn M V Symbol Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes M(X) M(S) M(ADH, ADL) M(00, ADL) Ab Mb OP n # 3825 GROUP USER’S MANUAL 3-39 APPENDIX 3.6 Mask ROM ordering method 3.6 Mask ROM ordering method 3–40 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–41 APPENDIX 3.6 Mask ROM ordering method 3–42 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–43 APPENDIX 3.6 Mask ROM ordering method 3–44 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–45 APPENDIX 3.6 Mask ROM ordering method 3–46 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–47 APPENDIX 3.6 Mask ROM ordering method 3–48 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–49 APPENDIX 3.6 Mask ROM ordering method 3–50 3825 GROUP USER’S MANUAL APPENDIX 3.6 Mask ROM ordering method 3825 GROUP USER’S MANUAL 3–51 APPENDIX 3.7 Mark specification form 3.7 Mark specification form 3–52 3825 GROUP USER’S MANUAL APPENDIX 3.8 Package outlines 3.8 Package outlines 3825 GROUP USER’S MANUAL 3–53 APPENDIX 3.8 Package outlines 3–54 3825 GROUP USER’S MANUAL APPENDIX 3.9 SFR allocation 3.9 SFR allocation 000016 Port P0 (P0) 000116 000216 Port P1 (P1) 000316 Port P1 output control register (P1C) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 Port P8 (P8) 001116 Port P8 direction register (P8D) 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIOCON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16 002016 Timer X (low-order) (TXL) 002116 Timer X (high-order) (TXH) 002216 Timer Y (low-order) (TYL) 002316 Timer Y (high-order) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 Clock output control register (TCON) 002B16 002C16 002D16 002E16 002F 16 003016 003116 003216 003316 003416 A-D control register (ADCON) 003516 A-D conversion register (AD) 003616 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F 16 Interrupt control register 2(ICON2) Memory map of special function register (SFR) 3825 GROUP USER’S MANUAL 3–55 3–56 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 APPENDIX 3.10 Pin configuration 96 97 95 93 94 92 90 91 89 88 87 86 84 85 83 82 81 3.10 Pin configuration 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN CONFIGURATION (TOP VIEW) Pin configuration of M38254M6-XXXFP M38254M6-XXXFP 3825 GROUP USER’S MANUAL Package type : 100P6S-A 100-pin plastic-molded QFP 42 43 44 45 46 47 48 49 41 40 31 33 32 34 35 36 39 38 37 50 C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3 P62/AN2 P61/AN1 P60 /AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45 / TXD P44/RXD P43 /INT1 P42/INT0 P41 / f(XIN)/5 / f(XIN )/10 P40 / f(XIN ) / f(XIN )/2 P77 P76 P75 P74 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30 /SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35 /SEG23 P36/SEG24 P37/SEG25 P00 /SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05 /SEG31 P06/SEG32 P07/SEG33 P10 /SEG34 P11/SEG35 P12/SEG36 P13 /SEG37 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/XCOUT P81/XCIN RESET P70 P71 P72 P73 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 98 99 97 96 94 95 93 91 92 90 89 87 88 85 86 84 83 82 81 79 80 78 77 76 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 40 42 43 44 46 45 47 49 48 27 26 28 30 29 32 31 33 35 34 37 36 38 39 41 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PIN CONFIGURATION (TOP VIEW) Pin configuration of M38254M6-XXXGP M38254M6-XXXGP 3825 GROUP USER’S MANUAL Package type : 100P6D-A 100-pin plastic-molded QFP P67/AN7 P66/AN6 P65 /AN5 P64/AN4 P63/AN3 P62 /AN2 P61/AN1 P60/AN0 P57/ADT P56/ TOUT P55 /CNTR1 P54/CNTR0 P53/RTP1 P52 /RTP0 P51/INT3 P50 /INT2 P47 /SRDY P46 /SCLK P45/ TXD P44/R XD P43/INT1 P42/INT 0 P41 / f(XIN)/5 / f(X IN )/10 P40 / f(XIN) / f(XIN )/2 P77 SEG13 SEG14 SEG15 SEG16 SEG17 P30 /SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35 /SEG23 P36/SEG24 P37/SEG25 P00 /SEG26 P01/SEG27 P02/SEG28 P03 /SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10 /SEG34 P11/SEG35 P12/SEG36 P13 /SEG37 P14 /SEG38 P15 /SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80 /XCOUT P81 /XCIN RESET P70 P71 P72 P73 P74 P75 P76 3.10 Pin configuration APPENDIX 3–57 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 3825 Group Jul. First Edition 1995 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1995 MITSUBISHI ELECTRIC CORPORATION User’s Manual 3825 Group H-EE379-A KI-9507 Printed in JAPAN (ROD) © 1995 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Jul. 1995. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition Revision Description 3825 Group User’s Manual Rev. date 980220 (1/1) GRADE A MESC TECHNICAL NEWS No. M380-14-9907 Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” This news includes a few corrections and supplementary explanation for the following documents. Please refer to the corrected information as shown below. q U ser’s Manual attaching this news • 3820 Group (Printed & PDF documents, 1995.7 issued, document number: H-EE367-A) • 3822 Group (Printed & PDF documents, 1995.3 issued, document number: H-ED347-A) • 3825 Group (Printed & PDF documents, 1995.7 issued, document number: H-EE379-A) (1/ 4) M380-14-9907 Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.1 Page 3820 Group 3822 Group 3825 Group (1) Timer X s T imer Previous change User’s Manual P2-66 [Notes on use] User’s Manual P2-65 Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the timer X interrupt enable bit and User’s Manual P2-65 the timer X interrupt request bit to “0”. •After setting  below, set the timer X interrupt enable bit to “1” mode (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer X stops counting (before setting Œ below), clear the timer X interrupt enable bit to “0”. •After setting Ž below, clear the timer X interrupt request bit to “0” and next set the timer X interrupt enable bit to “1” (interrupt enabled). •Set  last. 3820 Group 3822 Group 3825 Group (1) Timer X s P ulse User’s Manual P2-67 Previous change User’s Manual P2-66 User’s Manual P2-66 [Notes on use] Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer X or output mode CNTR0) and the interrupt request bits (timer X or CNTR0) to “0”. •After setting  below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer X stops counting (before setting  below), clear the interrupt enable bit (timer X or CNTR0) to “0”. •After setting  below, clear the interrupt request bit (timer X or CNTR0) to “0” and next set the interrupt enable bit (timer X or CNTR0) to “1” (interrupt enabled). •Set  last. 3820 Group 3822 Group 3825 Group (1) Timer X s E vent User’s Manual P2-68 Previous change User’s Manual P2-67 User’s Manual P2-67 [Notes on use] Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer X or counter mode CNTR0) and the interrupt request bits (timer X or CNTR0) to “0”. •After setting  below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer X stops counting (before setting  below), clear the interrupt enable bit (timer X or CNTR0) to “0”. •After setting  below, clear the interrupt request bit (timer X or CNTR0) to “0” and next set the interrupt enable bit (timer X or CNTR0) to “1” (interrupt enabled). •Set  last. (2 / 4) M380-14-9907 Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.2 Page 3820 Group 3822 Group 3825 Group (1) Timer X s P ulse mode Previous change User’s Manual P2-69 [Notes on use] User’s Manual P2-68 Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer X or User’s Manual P2-68 CNTR0) and the interrupt request bits (timer X or CNTR0) to “0”. •After setting  below, set the interrupt enable bits (timer X or width measurement CNTR0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer X stops counting (before setting  below), clear the interrupt enable bit (timer X or CNTR0) to “0”. •After setting  below, clear the interrupt request bit (timer X or CNTR0) to “0” and next set the interrupt enable bit (timer X or CNTR0) to “1” (interrupt enabled). •Set  last. 3820 Group 3822 Group 3825 Group (2) Timer Y s T imer User’s Manual P2-71 [Notes on use] User’s Manual P2-70 Notes 1: For using interrupt processing, set the following: User’s Manual P2-70 •Before setting Œ below, clear the timer Y interrupt enable bit and the timer Y interrupt request bit to “0”. mode •After setting  below, set the timer Y interrupt enable bit to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer Y stops counting (before setting Œ below), clear the timer Y interrupt enable bit to “0”. •After setting Ž below, clear the timer Y interrupt request bit to “0” and next set the timer Y interrupt enable bit to “1” (interrupt enabled). •Set  last. 3820 Group User’s Manual 3822 Group User’s Manual 3825 Group User’s Manual (2) Timer Y s P eriod measurement P2-72 Previous change P2-71 [Notes on use] P2-71 Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer Y or mode CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0”. •After setting  below, set the interrupt enable bits (timer Y or CNTR1) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer Y stops counting (before setting  below), clear the interrupt enable bit (timer Y or CNTR1) to “0”. •After setting  below, clear the interrupt request bit (timer Y or CNTR1) to “0” and next set the interrupt enable bit (timer Y or CNTR1) to “1” (interrupt enabled). •Set  last. 3820 Group 3822 Group 3825 Group (2) Timer Y s E vent User’s Manual P2-73 Previous change User’s Manual P2-72 [Notes on use] User’s Manual P2-72 Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer Y or counter mode CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0”. •After setting  below, set the interrupt enable bits (timer Y or CNTR1) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer Y stops counting (before setting  below), clear the interrupt enable bit (timer Y or CNTR1) to “0”. •After setting  below, clear the interrupt request bit (timer Y or CNTR1) to “0” and next set the interrupt enable bit (timer Y or CNTR1) to “1” (interrupt enabled). •Set  last. (3 /4) M380-14-9907 Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.3 Page Previous change 3820 Group User’s Manual P2-74 [Notes on use] 3822 Group User’s Manual P2-73 Notes 1: For using interrupt processing, set the following: •Before setting Œ below, clear the interrupt enable bits (timer Y or 3825 Group User’s Manual P2-73 CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0”. (2) Timer Y •After setting  below, set the interrupt enable bits (timer Y or s P ulse width HL continuCNTR1) to “1” (interrupts enabled). ously measurement mode After change [Notes on use] Notes 1: For using interrupt processing, set the following: •Before timer Y stops counting (before setting  below), clear the interrupt enable bit (timer Y or CNTR1) to “0”. •After setting  below, clear the interrupt request bit (timer Y or CNTR1) to “0” and next set the interrupt enable bit (timer Y or CNTR1) to “1” (interrupt enabled). •Set  last. (4 /4)