3851

3851 Group (Built-in 24 KB or more ROM) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0066-0101Z Rev.1.01 Oct 15, 2003 DESCRIPTION The 3851 group (built-in 24 KB or more ROM) is the 8-bit microcomputer based on the 740 family core technology. The 3851 group (built-in 24 KB or more ROM) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, I2C-BUS interface, and A-D converter. FEATURES Basic machine-language instructions ..................................... 71 Minimum instruction execution time ................................. 0.5 µs (at 8 MHz oscillation frequency) Memory size ROM ................................................................ 24K to 32K bytes RAM .................................................................... 640 to 1K bytes Programmable input/output ports ........................................... 34 Interrupts ................................................ 17 sources, 16 vectors Timers ............................................................................ 8-bit X 4 Serial I/O1 .................... 8-bit X 1(UART or Clock-synchronized) Serial I/O2 ................................... 8-bit X 1(Clock-synchronized) Multi-master I2C-BUS interface .................................. 1 channel PWM .............................................................................. 8-bit X 1 A-D converter ............................................... 10-bit X 5 channels Watchdog timer ........................................................... 16-bit X 1 Clock generating circuit ................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................. 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode ................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) Power dissipation In high-speed mode ......................................................... 34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode Except M38517F8FP/SP ................................................. 60 µW M38517F8FP/SP ............................................................ 450 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range .................................. –20 to 85°C APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/SCL2/TxD P24/SDA2/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP) Fig. 1 M38517M8-XXXFP/SP pin configuration M38517M8-XXXFP/SP Rev.1.01 Oct 15, 2003 page 1 of 89 FUNCTIONAL BLOCK Rev.1.01 Reset input VSS VCC 1 15 18 21 FUNCTIONAL BLOCK DIAGRAM Main-clock input XIN RESET CNVSS Main-clock output XOUT Fig.2 Functional block diagram 3851 Group (Built-in 24 KB or more ROM) Oct 15, 2003 CPU 19 20 Sub-clock Sub-clock input output XCIN XCOUT Clock generating circuit page 2 of 89 ROM X Prescaler 12(8) RAM Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 ) Y Prescaler X(8) A Timer 1( 8 ) S PC H PS CNTR1 PC L Prescaler Y(8) CNTR0 Watchdog timer Reset A-D converter (10) PWM (8) SI/O1(8) I2C SI/O2(8) XCOUT INT0– INT3 XCIN P4(5) P3(5) P2(8) P1(8) P0(8) 23 38 39 40 41 42 45 678 9 10 11 12 13 1416 17 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 VREF AVSS 3851 Group (Built-in 24 KB or more ROM) Table 1 Pin description Pin VCC, VSS CNVSS VREF AVSS RESET XIN XOUT Name Power source CNVSS input Reference voltage input Analog power source input Reset input Clock input Clock output Functions •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reference voltage input pin for A-D converter. •Analog power source input pin for A-D converter. •Connect to Vss. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •P10 to P17 (8 bits) are enabled to output large current for LED drive. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •P22 to P25 can be switched between CMOS compatible input level or SMBUS input level in the I2C-BUS interface function. •P20, P21, P24 to P27: CMOS3-state output structure. •P2 4, P25 : N-channel open-drain structure in the I2CBUS interface function. •P22, P23: N-channel open-drain structure. P30/AN0– P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM I/O port P3 •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. I/O port P4 •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. • Interrupt input pin • SCMP2 output pin • Interrupt input pin • PWM output pin • Timer Y function pin • Interrupt input pins • A-D converter input pin • I2C-BUS interface function pin/ Serial I/O1 function pins • Serial I/O1 function pin • Serial I/O1 function pin/Timer X function pin • Sub-clock generating circuit I/O pins (connect a resonator) • I2C-BUS interface function pins • Serial I/O2 function pin Function except a port function P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10–P17 P20/XCOUT P21/XCIN P22/SDA1 P23/SCL1 P24/SDA2/RxD P25/SCL2/TxD P26/SCLK1 P27/CNTR0/ SRDY1 I/O port P0 I/O port P1 I/O port P2 Rev.1.01 Oct 15, 2003 page 3 of 89 3851 Group (Built-in 24 KB or more ROM) PART NUMBERING Product name M3851 4 M 6 – XXX SP Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. – : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. ROM/PROM/Flash memory size 9 : 36864 bytes 1 : 4096 bytes A : 40960 bytes 2 : 8192 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 3 Part numbering Rev.1.01 Oct 15, 2003 page 4 of 89 3851 Group (Built-in 24 KB or more ROM) GROUP EXPANSION Renesas plans to expand the 3851 group (built-in 24 KB or more ROM) as follows. Packages 42P4B ......................................... 42-pin shrink plastic-molded DIP 42P2R-A/E ......................................... 42-pin plastic-molded SSOP 42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version) Memory Type Support for mask ROM, One Time PROM, and flash memory versions. Memory Size Flash memory size ......................................................... 32 K bytes Mask ROM size ................................................. 24 K to 32 K bytes One Time PROM size ..................................................... 24 K bytes RAM size ............................................................... 640 to 1 K bytes Memory Expansion Plan ROM size (bytes) ROM exteranal 32K 28K Mass production Mass production M38517M8/F8 24K 20K 16K 12K 8K M38514M6/E6 384 512 640 768 896 1024 1152 RAM size (bytes) 1280 1408 1536 2048 Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig. 4 Memory expansion plan Rev.1.01 Oct 15, 2003 page 5 of 89 3851 Group (Built-in 24 KB or more ROM) Currently planning products are listed below. Table 2 Support products Product name M38514M6-XXXSP M38514E6-XXXSP M38514E6SP M38514E6SS M38514M6-XXXFP M38514E6-XXXFP M38514E6FP ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package Remarks Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) 42P4B 24576 (24446) 640 42S1B-A 42P2R-A/E Table 3 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM) corresponding products 3851 group (built-in 16 KB ROM) 3851 group (built-in 24 KB or more ROM) M38513M4-XXXFP/SP M38514M6-XXXFP/SP M38513E4-XXXFP/SP M38514E6-XXXFP/SP M38513E4FP/SP M38514E6FP/SP M38513E4SS M38514E6SS M38517M8-XXXFP/SP M38517F8FP/SP Table 4 Differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM) 3851 group (built-in 16 KB ROM) 3851 group (built-in 24 KB or more ROM) Serial I/O 1: Serial I/O 2: Serial I/O1 (UART or Clock-synchronized) (UART or Clock-synchronized) Serial I/O2 (Clock-synchronized) A-D converter Unserviceable in low-speed mode Serviceable in low-speed mode Large current port 5: P13–P17 8: P10–P17 Notes on differences between 3851 group (built-in 16 KB ROM), 3851 group (built-in 24 KB or more ROM) (1) The absolute maximum ratings of 3851 group (built-in 24 KB or more ROM) is smaller than that of 3851 group (built-in 16 KB ROM). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8) VI = –0.3 to 6.5 V (M38517F8) (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after reset.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. Rev.1.01 Oct 15, 2003 page 6 of 89 3851 Group (Built-in 24 KB or more ROM) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3851 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 5 740 Family CPU register structure Rev.1.01 Oct 15, 2003 page 7 of 89 3851 Group (Built-in 24 KB or more ROM) On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 6 Register push and pop at interrupt generation and subroutine call Table 5 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.01 Oct 15, 2003 page 8 of 89 3851 Group (Built-in 24 KB or more ROM) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “ 0 ” , arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _ Rev.1.01 Oct 15, 2003 page 9 of 89 3851 Group (Built-in 24 KB or more ROM) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 1 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 7 Structure of CPU mode register Rev.1.01 Oct 15, 2003 page 10 of 89 3851 Group (Built-in 24 KB or more ROM) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 000016 SFR area 004016 010016 Zero page 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 RAM XXXX16 Not used 0FF016 0FFF16 SFR area (Note) Not used ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 YYYY16 Reserved ROM area (128 bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Fig. 8 Memory map diagram F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Note: Flash memory version only Rev.1.01 Oct 15, 2003 page 11 of 89 3851 Group (Built-in 24 KB or more ROM) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C start/stop condition control register (S2D) Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH) Reserved ✽ MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FFD16 Reserved 0FFE16 0FFF16 Flash memory control register 1 (FMCR) Reserved ✽ Reserved : Do not write any data to this addresses, because these areas are reserved. Fig. 9 Memory map of special function register (SFR) Rev.1.01 Oct 15, 2003 page 12 of 89 3851 Group (Built-in 24 KB or more ROM) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “ 0 ” i s written to the bit corresponding to a pin, that pin becomes an input pin. When “ 1 ” i s written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 7 I/O port function Pin P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10–P17 P20/XCOUT P21/XCIN P22/SDA1 P23/SCL1 Port P0 CMOS compatible input level CMOS 3-state output Port P1 Sub-clock generating circuit CMOS compatible input level CMOS/SMBUS input level (when selecting I2CBUS interface function) N-channel open-drain output P24/SDA2/RxD P25/SCL2/TxD Port P2 Input/output, individual bits CMOS compatible input level CMOS/SMBUS input level (when selecting I2CBUS interface function) CMOS 3-state output N-channel open-drain output (when selecting I2CBUS interface function) I2C-BUS interface function I/O I2C control register (8) (9) CPU mode register Name Input/Output I/O Structure Non-Port Function Related SFRs Ref.No. (1) (2) (3) (4) (5) (6) (7) Serial I/O2 function I/O Serial I/O2 control register I2C-BUS interface function I/O Serial I/O1 function I/O I2C control register Serial I/O1 control register (10) (11) P26/SCLK1 P27/CNTR0/SRDY1 P30/AN0–P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM Note: When reading bit 5, 6, or 7 of ports P3 and P4, the contents are undefined. Serial I/O1 function I/O Serial I/O1 function I/O Timer X function I/O Port P3 A-D conversion input CMOS compatible input level CMOS 3-state output Timer Y function I/O External interrupt input External interrupt input SCMP2 output External interrupt input PWM output Serial I/O1 control register Serial I/O1 control register Timer XY mode register A-D control register Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register (12) (13) (14) (15) (16) (17) (18) Port P4 Rev.1.01 Oct 15, 2003 page 13 of 89 3851 Group (Built-in 24 KB or more ROM) (1) Port P00 Direction register (2) Port P01 P01/SOUT2 P-channel output disable bit Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output (3) Port P02 (4) Port P03 P02/SCLK2 P-channel output disable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Data bus Port latch SRDY2 output enable bit Direction register Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (5) Ports P04-P07,P1 Direction register (6) Port P20 Port XC switch bit Direction register Data bus Port latch Data bus Port latch Oscillator Port P21 (7) Port P21 Port XC switch bit Direction register (8) Port P22 I2C-BUS interface enable bit SDA/SCL pin selection bit Direction register Data bus Port latch Port XC switch bit Data bus Port latch Sub-clock generating circuit input SDA output SDA input Fig. 10 Port block diagram (1) Rev.1.01 Oct 15, 2003 page 14 of 89 3851 Group (Built-in 24 KB or more ROM) (9) Port P23 I C-BUS interface enable bit SDA/SCL pin selection bit Direction register Data bus Port latch 2 (10) Port P24 I2C-BUS interface enable bit SDA/SCL pin selection bit Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch SCL output SCL input SDA output SDA input Serial I/O1 input (11) Port P25 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit I2C-BUS interface enable bit SDA/SCL pin selection bit Direction register (12) Port P26 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O1 output SCL output SCL input Serial I/O1 clock output Serial I/O1 external clock input (13) Port P27 Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register (14) Ports P30-P34 Direction register Data bus Data bus Port latch Port latch Pulse output mode Serial I/O1 ready output Timer output CNTR0 interrupt input A-D converter input Analog input pin selection bit (15) Port P40 Direction register (16) Ports P41,P42 Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output CNTR1 interrupt input Interrupt input Fig. 11 Port block diagram (2) Rev.1.01 Oct 15, 2003 page 15 of 89 3851 Group (Built-in 24 KB or more ROM) (17) Port P43 Serial I/O2 I/O comparison signal control bit Direction register (18) Port P44 PWM output enable bit Direction register Data bus Data bus Port latch Port latch PWM output Serial I/O2 I/O comparison signal output Interrupt input Interrupt input Fig. 12 Port block diagram (3) Rev.1.01 Oct 15, 2003 page 16 of 89 3851 Group (Built-in 24 KB or more ROM) INTERRUPTS Interrupts occur by 17 : seven external, nine internal, and one software. Notes When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register (address 003A16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the corresponding interrupt enable bit to “0” (disabled). (2) Set the interrupt edge select bit or the interrupt source select bit. (3) Set the corresponding interrupt request bit to “ 0 ” a fter 1 or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Rev.1.01 Oct 15, 2003 page 17 of 89 3851 Group (Built-in 24 KB or more ROM) Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Low 1 FFFD16 FFFC16 Reset (Note 2) INT0 SCL, SDA INT1 INT2 INT3 Serial I/O2 I 2C Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 transmission CNTR0 CNTR1 A-D converter BRK instruction 6 7 8 9 10 11 12 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 2 3 4 5 FFFB16 FFF916 FFF716 FFF516 FFFA16 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of SCL or SDA input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At completion of serial I/O2 data reception/transmission At completion of data transfer At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit STP release timer underflow Valid when serial I/O is selected 13 14 15 16 17 FFE516 FFE416 Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt FFE316 FFE116 FFDF16 FFDD16 FFE216 FFE016 FFDE16 FFDC16 Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.01 Oct 15, 2003 page 18 of 89 3851 Group (Built-in 24 KB or more ROM) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns “0” when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit SCL/SDA interrupt request bit INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit I2C interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit SCL/SDA interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit I2C interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers Rev.1.01 Oct 15, 2003 page 19 of 89 3851 Group (Built-in 24 KB or more ROM) TIMERS The 3851 group (built-in 24 KB or more ROM) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode. b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. Fig. 15 Structure of timer XY mode register b7 b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read) Note When switching the count source by the timer 12, X and Y count source bits, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. When timer X/timer Y underflow while executing the instruction which sets “1” to the timer X/timer Y count stop bits, the timer X/ timer Y interrupt request bits are set to “1”. Timer X/Timer Y interrupts are received if these interrupts are enabled at this time. The timing which interrupt is accepted has a case after the instruction which sets “1” to the count stop bit, and a case after the next instruction according to the timing of the timer underflow. When this interrupt is unnecessary, set “0” (disabled) to the interrupt enable bit and then set “1” to the count stop bit. Fig. 16 Structure of timer count source selection register Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Rev.1.01 Oct 15, 2003 page 20 of 89 3851 Group (Built-in 24 KB or more ROM) Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode) Timer X count source selection bit measurement mode Prescaler X latch (8) Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge selection bit “0 ” “1 ” Event counter mode Timer X count stop bit Timer X latch (8) Timer X (8) To timer X interrupt request bit P27/CNTR0/SRDY1 To CNTR0 interrupt request bit CNTR0 active edge selection “1” bit “0 ” Q Q Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P27 direction register Port P27 latch Pulse output mode Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit CNTR1 active edge selection bit “0 ” “1 ” Pulse width measurement mode Prescaler Y latch (8) Timer mode Pulse output mode Prescaler Y (8) Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit P40/CNTR1 Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge selection “1” bit “0 ” Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode Port P40 direction register Port P40 latch Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Timer 12 count source selection bit Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.01 Oct 15, 2003 page 21 of 89 3851 Group (Built-in 24 KB or more ROM) SERIAL I/O SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Address 001816 Receive buffer register P24/RXD Receive shift register Shift clock Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P26/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P25/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 XIN BRG count source selection bit 1/4 P27/CNTR0/SRDY1 F/F Falling-edge detector Fig. 18 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 19 Operation of clock synchronous serial I/O1 function Rev.1.01 Oct 15, 2003 page 22 of 89 3851 Group (Built-in 24 KB or more ROM) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P26/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) UART control register Address 001B16 P24/RXD OE Receive buffer register Character length selection bit ST detector 7 bits Receive shift register 8 bits XIN Fig. 20 Block diagram of UART serial I/O1 Rev.1.01 Oct 15, 2003 page 23 of 89 3851 Group (Built-in 24 KB or more ROM) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST TBE=0 TBE=1 TSC=1 D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 21 Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin. [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.01 Oct 15, 2003 page 24 of 89 3851 Group (Built-in 24 KB or more ROM) b7 b0 Serial I/O1 status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 22 Structure of serial I/O1 control registers Notes on serial I/O1 1. When using the serial I/O1, clear the I2C-BUS interface enable bit to “0” or the SDA/SCL interrupt pin selection bit to “0”. 2. When setting the transmit enable bit of serial I/O1 to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. (1) Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). (2) Set the transmit enable bit to “1”. (3) Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. (4) Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). Rev.1.01 Oct 15, 2003 page 25 of 89 3851 Group (Built-in 24 KB or more ROM) SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P0 1 /S OUT2 , P0 2 /S CLK2 P -channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to “1” automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the transfer direction selection bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H” is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16). b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits b2 b1 b0 0 0 0 0 1 1 0 0 1 1 1 1 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode ) b7 b0 Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance Fig. 23 Structure of Serial I/O2 control registers 1, 2 [Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 23. Rev.1.01 Oct 15, 2003 page 26 of 89 3851 Group (Built-in 24 KB or more ROM) XCIN Main clock division ratio selection bits (Note) 1/8 1/16 Internal synchronous clock selection bits Divider “10” “00” “01” 1/32 1/64 1/128 1/256 Data bus XIN P03 latch “0” Serial I/O2 synchronous clock selection bit SRDY2 “1” SRDY2 output enable bit Synchronous circuit P03/SRDY2 “1” “0” SCLK2 External clock P02 latch “0” Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request P02/SCLK2 “1” Serial I/O2 port selection bit P01 latch “0” P01/SOUT2 “1” Serial I/O2 port selection bit P00/SIN2 Serial I/O2 register (8) P43 latch “0” P43/SCMP2/INT2 Q “1” Serial I/O2 I/O comparison signal control bit D Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig. 24 Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal to serial I/O2 register (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 . D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion. Fig. 25 Timing chart of Serial I/O2 Rev.1.01 Oct 15, 2003 page 27 of 89 3851 Group (Built-in 24 KB or more ROM) SCMP2 SCLK2 SOUT2 SIN2 Judgement of I/O data comparison Fig. 26 SCMP2 output operation Rev.1.01 Oct 15, 2003 page 28 of 89 3851 Group (Built-in 24 KB or more ROM) MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 27 shows a block diagram of the multi-master I2C-BUS interface and Table 9 lists the multi-master I 2 C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I 2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C start/stop condition control register and other control circuits. When using the multi-master I 2 C-BUS interface, set 1 MHz or more to φ. Note: Renesas Technology Corporation assumes no responsibility for infringement of any third-party’s rights or originating in the use of the connection control function between the I2C-BUS interface and the ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control register (002E16). Table 9 Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ= 4 MHz) Format Communication mode SCL clock frequency System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) b7 I2C address register b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB S0D Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I2C data shift register S0 b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 AL circuit S2D I2C start/stop condition control register S1 Internal data bus I2C status register BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 TISS CLK STP 10BIT SAD I2C clock control register S1D b0 ALS ES0 BC2 BC1 BC0 S2 I2C clock control register Clock division S1D I C control register System clock (φ) Bit counter 2 Fig. 27 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of Renesas Technology Corporation's I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Rev.1.01 Oct 15, 2003 page 29 of 89 3851 Group (Built-in 24 KB or more ROM) [I2C Data Shift Register (S0)] 002B16 The I2C data shift register (S0 : address 002B16) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 machine cycles are required from the rising of the SCL clock until input to this register. The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of the I2C control register is “1”. The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 002D16) are “1”, the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. b7 b0 I2C address register (S0D: address 002C16) Read/write bit Slave address SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB Fig. 28 Structure of I2C address register [I2C Address Register (S0D)] 002C16 The I 2C address register (address 002C 16) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. •Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I2C address register. The RWB bit is cleared to “0” automatically when the stop condition is detected. •Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. Rev.1.01 Oct 15, 2003 page 30 of 89 3851 Group (Built-in 24 KB or more ROM) [I2C Clock Control Register (S2)] 002F16 The I2C clock control register (address 002F16) is used to set ACK control, SCL mode and SCL frequency. •Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 10. •Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit is set to “1”, the high-speed clock mode is selected. When connecting the bus of the high-speed mode I2C-BUS standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) and 2 division clock. •Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0”, the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK non-return mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0”, the SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned). ✽ACK clock: Clock for acknowledgment b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE I2C clock control register (S2 : address 002F16) SCL frequency control bits Refer to Table 10. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 29 Structure of I2C clock control register Table 10 Set values of I 2 C clock control register and SCL frequency Setting value of CCR4–CCR0 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 SCL frequency (Note 1) (at φ = 4 MHz, unit : kHz) Standard clock High-speed clock mode mode Setting disabled Setting disabled Setting disabled – (Note 2) – (Note 2) 100 83.3 500/CCR value (Note 3) 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 333 250 400 (Note 3) 166 1000/CCR value (Note 3) 34.5 33.3 32.3 •Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the clock control register during transfer. If data is written during transfer, the I 2C clock generator is reset, so that data cannot be transferred normally. I2 C … … … … 0 1 1 1 1 1 1 1 1 1 1 1 Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration reduction. These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. Rev.1.01 Oct 15, 2003 page 31 of 89 … 1 0 1 3851 Group (Built-in 24 KB or more ROM) [I2C Control Register (S1D)] 002E16 The I2C control register (address 002E16) controls data communication format. •Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of address 002F 16)) have been transferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. •Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0”, the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1”, use of the interface is enabled. When ES0 = “0”, the following is performed. • PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I2C status register at address 002D16 ). • Writing data to the I2C data shift register (address 002B16) is disabled. •Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0”, the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “ I 2C Status Register ” , bit 1) is received, transfer processing can be performed. When this bit is set to “1”, the free data format is selected, so that slave addresses are not recognized. •Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 002C16) are compared with address data. When this bit is set to “1”, the 10-bit addressing format is selected, and all the bits of the I 2C address register are compared with address data. •Bit 6: SDA/SCL pin selection bit (TSEL) This bit selects the input/output pins of SCL and SDA of the multimaster I2C-BUS interface. •Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. TSEL SCL1/P23 SCL SCL2/TxD/P25 Multi-master I2C-BUS interface TSEL TSEL SDA1/P22 SDA SDA2/RxD/P24 TSEL Fig. 30 SDA/SCL pin selection bit b7 TISS TSEL 10 BIT SAD b0 I2C control register ALS ES0 BC2 BC1 BC0 (S1D : address 002E 16) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0:8 0 0 1:7 0 1 0:6 0 1 1:5 1 0 0:4 1 0 1:3 1 1 0:2 1 1 1:1 I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format SDA/SCL pin selection bit 0 : Connect to ports P2 2, P23 1 : Connect to ports P2 4, P25 I2C-BUS interface pin input level selection bit 0 : CMOS input 1 : SMBUS input Fig. 31 Structure of I2C control register Rev.1.01 Oct 15, 2003 page 32 of 89 3851 Group (Built-in 24 KB or more ROM) [I2C Status Register (S1)] 002D16 The I2C status register (address 002D16) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “00002” to the low-order 4 bits, because these bits become the reserved bits at writing. •Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”. Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 002B16). •Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “ 0 ” b y detecting the STOP condition or START condition, or reset. ✽General call: The master transmits the general call address “0016 ” to all slaves. •Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. (1) In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions: • The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 002C16). • A general call is received. (2) In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition: • When the address data is compared with the I2C address register (8 bits consisting of slave address and RWB bit), the first bytes agree. (3) This bit is set to “0” by executing a write instruction to the I2C data shift register (address 002B16) when ES0 is set to “1” or reset. •Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”, so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. ✽Arbitration lost :The status in which communication as a master is disabled. •Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “ 1 ” t o “ 0 ” . At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0”, the SCL is kept in the “0” state and clock generation is disabled. Figure 33 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions: • Executing a write instruction to the I2 C data shift register (address 002B16). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) • When the ES0 bit is “0” • At reset • When writing “1” to the PIN bit by software The conditions in which the PIN bit is set to “0” are shown below: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception •Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0”, this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the start condition, and is set to “0” by detecting the stop condition. The condition of these detecting is set by the start/stop condition setting bits (SSC4–SSC0) of the I2C start/stop condition control register (address 003016). When the ES0 bit of the I 2C control register (address 002E16) is “0” or reset, the BB flag is set to “0”. For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Generating Method” described later. Rev.1.01 Oct 15, 2003 page 33 of 89 3851 Group (Built-in 24 KB or more ROM) •Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is selected and the data of a transmitting device is received. When the bit is “1”, the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied: • When ALS is “0” • In the slave reception mode or the slave transmission mode • When the R/W bit reception is “1” This bit is set to “0” in one of the following conditions: • When arbitration lost is detected. • When a STOP condition is detected. • When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset •Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0”, the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1”, the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to “0” in one of the following conditions. • Immediately after completion of 1-byte data transfer when arbitration lost is detected • When a STOP condition is detected. • Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. b7 b0 I2C status register (S1 : address 002D16) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode MST TRX BB PIN AL AAS AD0 LRB Note: These bits and flags can be read out, but cannot be written. Write “0” to these bits at writing. Fig. 32 Structure of I2C status register SCL PIN IICIRQ Fig. 33 Interrupt request signal generating timing Rev.1.01 Oct 15, 2003 page 34 of 89 3851 Group (Built-in 24 KB or more ROM) START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I2C status register (address 002D16) at the same time after writing the slave address to the I2 C data shift register (address 002B16) with the condition in which the ES0 bit of the I2C control register (address 002E16) and the BB flag are “0”, a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 34, the START condition generating timing diagram, and Table 11, the START condition generating timing table. START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 36, 37, and Table 13. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 13). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 13, the BB flag set/ reset time. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” occurs to the CPU. I C status register write signal SCL SDA Setup time Hold time 2 SCL release time SCL SDA Setup time Hold time BB flag reset time Fig. 34 START condition generating timing diagram BB flag Table 11 START condition generating timing table Standard clock mode High-speed clock mode Item 5.0 µs (20 cycles) 2.5 µs (10 cycles) Setup time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Fig. 36 START condition detecting timing diagram SCL release time SCL SDA Setup time Hold time BB flag reset time STOP Condition Generating Method When the ES0 bit of the control register (address 002E16) is “1”, write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2C status register (address 002D16) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 35, the STOP condition generating timing diagram, and Table 12, the STOP condition generating timing table. I2C BB flag Fig. 37 STOP condition detecting timing diagram Table 13 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode SCL release time Setup time Hold time SSC value + 1 cycle (6.25 µs) 4 cycles (1.0 µs) SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (1.0 µs) 2 SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs) 2 SSC value –1 + 2 cycles (3.375 µs) 3.5 cycles (0.875 µs) 2 I2C status register write signal SCL SDA Setup time Hold time BB flag set/ reset time Note: Unit : Cycle number of system clock φ SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to “1816” at φ = 4 MHz. Fig. 35 STOP condition generating timing diagram Table 12 STOP condition generating timing table Standard clock mode High-speed clock mode Item 5.0 µs (20 cycles) 3.0 µs (12 cycles) Setup time 4.5 µs (18 cycles) 2.5 µs (10 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev.1.01 Oct 15, 2003 page 35 of 89 3851 Group (Built-in 24 KB or more ROM) [I2C START/STOP Condition Control Register (S2D)] 003016 The I2C START/STOP condition control register (address 003016) controls START/STOP condition detection. •Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 13. Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0). Refer to Table 14, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency. •Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. •Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I2 C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1) 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 002E16) to “0”. The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 002C16). At the time of this comparison, address comparison of the RWB bit of the I 2C address register (address 002C 16) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 39, (1) and (2). (2) 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I2 C control register (address 002E16) to “1”. An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C address register (address 002C 16). At the time of this comparison, an address comparison between the RWB bit of the I2C address register (address 002C16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (address 002D16) is set to “1”. After the second-byte address data is stored into the I2C data shift register (address 002B16), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I2C address register (address 002C 16) to “ 1 ” b y software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2 C address register (address 002C16). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 39, (3) and (4). Rev.1.01 Oct 15, 2003 page 36 of 89 3851 Group (Built-in 24 KB or more ROM) b7 b0 SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C START/STOP condition control register (S2D : address 003016) START/STOP condition set bit SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid Reserved Do not write “1” to this bit. Fig. 38 Structure of I2C START/STOP condition control register Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Oscillation frequency f(XIN) (MHz) 8 8 4 2 Main clock divide ratio 2 8 2 2 System clock φ (MHz) 4 1 2 1 START/STOP condition control register XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 SCL release time (µs) 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) Setup time (µs) 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) Hold time (µs) 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0). (1) A master-transmitter transnmits data to a slave-receiver S Slave address R/W 7 bits “0” A Data 1 to 8 bits A Data 1 to 8 bits A/A P (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 7 bits “1” A Data 1 to 8 bits A Data 1 to 8 bits A P (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits 7 bits “0” A Slave address 2nd bytes 8 bits A Data 1 to 8 bits A Data 1 to 8 bits A/A P (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S Slave address R/W 1st 7 bits 7 bits “0” A Slave address 2nd bytes 8 bits A Sr Slave address R/W 1st 7 bits 7 bits “1” A Data 1 to 8 bits A Data 1 to 8 bits A P S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit : Master to slave : Slave to master Fig. 39 Address data communication format Rev.1.01 Oct 15, 2003 page 37 of 89 3851 Group (Built-in 24 KB or more ROM) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. (1) Set a slave address in the high-order 7 bits of the I2 C address register (address 002C16) and “0” into the RWB bit. (2) Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 002F16). (3) Set “0016” in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (address 002E16). (5) Confirm the bus free condition by the BB flag of the I2C status register (address 002D16). (6) Set the address data of the destination of transmission in the high-order 7 bits of the I 2 C data shift register (address 002B16) and set “0” in the least significant bit. (7) Set “F016” in the I2C status register (address 002D16) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. (8) Set transmit data in the I 2 C data shift register (address 002B16). At this time, an SCL and an ACK clock automatically occur. (9) When transmitting control data of more than 1 byte, repeat step (8). (10) Set “D016” in the I2C status register (address 002D16) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends. (8) When receiving control data of more than 1 byte, repeat step (7). (9) When a STOP condition is detected, the communication ends. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. (1) Set a slave address in the high-order 7 bits of the I2 C address register (address 002C16) and “0” in the RWB bit. (2) Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 002F16). (3) Set “0016” in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (address 002E16). (5) When a START condition is received, an address comparison is performed. (6) • When all transmitted addresses are “0” (general call): AD0 of the I2C status register (address 002D16) is set to “1” and an interrupt request signal occurs. • When the transmitted addresses agree with the address set in (1): ASS of the I2C status register (address 002D16) is set to “1” and an interrupt request signal occurs. • In the cases other than the above AD0 and AAS of the I2C status register (address 002D16) are set to “0” and no interrupt request signal occurs. (7) Set dummy data in the I 2 C data shift register (address 002B16). Rev.1.01 Oct 15, 2003 page 38 of 89 3851 Group (Built-in 24 KB or more ROM) Precautions when using multi-master I2CBUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. • I2C data shift register (S0: address 002B16) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. • I2C address register (S0D: address 002C16) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. • I2C status register (S1: address 002D16) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. • I2C control register (S1D: address 002E16) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. • I2C clock control register (S2: address 002F16) The read-modify-write instruction can be executed for this register. • I 2 C START/STOP condition control register (S2D: address 003016) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described in Items 2 to 5 below. • • • 5. Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions for the procedure are described in items 2 to 4 below.) Execute the following procedure when the PIN bit is “0”. • • • LDM #$00, S1 LDA — SEI STA S0 LDM #$F0, S1 CLI • • • (Select slave receive mode) (Take out of slave address value) (Disable interrupt) (Write slave address value) (Trigger RESTART condition generation) (Enable interrupt) 2. Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor “1” is specified as input to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2C data shift register. 4. Disable interrupts during the following two process steps: • Write slave address value • Trigger RESTART condition generation (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. Because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. Because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “ 0 ” a fter generating the STOP condition in the master mode. Because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem. LDA — SEI BBS 5, S1, BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI • • • (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled) BUSBUSY: CLI • • • (Interrupt enabled) 2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag confirming and branch process. 3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page addressing instruction for writing the slave address value to the I2C data shift register. 4. Execute the branch instruction of Item 2 and the store instruction of Item 3 continuously, as shown in the procedure example above. Rev.1.01 Oct 15, 2003 page 39 of 89 3851 Group (Built-in 24 KB or more ROM) PULSE WIDTH MODULATION (PWM) The 3851 group (built-in 24 KB or more ROM) has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2. PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “ 1 ” , operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P4 4 . Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 X (n+1) / f(XIN) = 31.875 X (n+1) µs (when f(XIN) = 8 MHz,count source selection bit = “0”) Output pulse “H” term = PWM period X m / 255 = 0.125 X (n+1) X m µs (when f(XIN) = 8 MHz,count source selection bit = “0”) 31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source selection bit = “0”) Fig. 40 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit (XCIN XIN at low-speed mode) 1/2 “0” “1” PWM prescaler PWM register latch Port P44 PWM register Port P44 latch PWM enable bit Fig. 41 Block diagram of PWM function Rev.1.01 Oct 15, 2003 page 40 of 89 3851 Group (Built-in 24 KB or more ROM) b7 b0 PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read) Fig. 42 Structure of PWM control register A PWM output T PWM register write signal B C B= C T T2 T T2 (Changes “H” term from “A” to “B”.) PWM prescaler write signal (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 43 PWM output timing when PWM register or PWM prescaler is changed Note The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: n+1 2 • f(XIN) n+1 f(XIN) sec (Count source selection bit = 0, where n is the value set in the prescaler) sec (Count source selection bit = 1, where n is the value set in the prescaler) Rev.1.01 Oct 15, 2003 page 41 of 89 3851 Group (Built-in 24 KB or more ROM) A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. b7 b0 A-D control register (ADCON : address 003416) Analog input pin selection bits b2 b1 b0 [A-D Control Register (ADCON)] 003416 The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “ 0 ” d uring an A-D conversion and changes to “ 1 ” w hen an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. 0 0 0 0 1 0 0 1 1 0 0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4 Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 44 Structure of A-D control register Channel Selector The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator. 10-bit reading (Read address 003616 before 003516) b7 Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(XIN ) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit. (Address 003616) b7 b0 b9 b8 (Address 003516) b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : The high-order 6 bits of address 003616 become “0” at reading. 8-bit reading (Read only address 003516) b7 (Address 003516) b0 b9 b8 b7 b6 b5 b4 b3 b2 Fig. 45 Structure of A-D conversion registers Data bus A-D control register (Address 003416) b7 b0 3 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 A-D control circuit A-D interrupt request Channel selector Comparator A-D conversion high-order register (Address 003616) A-D conversion low-order register (Address 003516) 10 Resistor ladder VREF AVSS Fig. 46 Block diagram of A-D converter Rev.1.01 Oct 15, 2003 page 42 of 89 3851 Group (Built-in 24 KB or more ROM) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control register (address 0039 16 ) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L are set to “FF16”. “FF16” is set when watchdog timer control register is written to. “10” Main clock division ratio selection bits (Note) XIN Watchdog timer L (8) 1/16 “00” “01” Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to “ 0 ” , the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after reset. Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “ 1 ” , it cannot be rewritten to “ 0 ” b y program. This bit is cleared to “0” after reset. Data bus “FF16” is set when watchdog timer control register is written to. Watchdog timer H (8) XCIN “0 ” “1 ” Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit Internal reset RESET Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 47 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 003916) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 48 Structure of Watchdog timer control register Rev.1.01 Oct 15, 2003 page 43 of 89 3851 Group (Built-in 24 KB or more ROM) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more of XIN. Then the RESET pin is returned to an “H” level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Poweron Power source voltage 0V Reset input voltage 0V (Note) RESET VCC 0.2VCC Note : Reset release voltage; Vcc = 2.7 V RESET VCC Power source voltage detection circuit Fig. 49 Reset circuit example XIN φ RESET RESETOUT Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals. Fig. 50 Reset sequence Rev.1.01 Oct 15, 2003 page 44 of 89 3851 Group (Built-in 24 KB or more ROM) Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 001516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (36) A-D control register (ADCON) Address Register contents 003416 0 0 0 1 0 0 0 0 (37) A-D conversion low-order register (ADL) 003516 X X X X X X X X (38) A-D conversion high-order register (ADH) 003616 0 0 0 0 0 0 X X (39) MISRG (40) Watchdog timer control register (WDTCON) (41) Interrupt edge selection register (INTEDGE) (42) CPU mode register (CPUM) (43) Interrupt request register 1 (IREQ1) (44) Interrupt request register 2 (IREQ2) (45) Interrupt control register 1 (ICON1) (46) Interrupt control register 2 (ICON2) (47) Processor status register (48) Program counter 003816 0016 003916 0 0 1 1 1 1 1 1 003A16 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) 0016 0016 0016 0016 XXXXX1XX FFFD16 contents FFFC16 contents (10) Port P4 direction register (P4D) (11) Serial I/O2 control register 1 (SIO2CON1) (12) Serial I/O2 control register 2 (SIO2CON2) (13) Serial I/O2 register (SIO2) (14) Transmit/Receive buffer register (TB/RB) (15) Serial I/O1 status register (SIOSTS) (16) Serial I/O1 control register (SIOCON) (17) UART control register (UARTCON) (18) Baud rate generator (BRG) (19) PWM control register (PWMCON) (20) PWM prescaler (PREPWM) (21) PWM register (PWM) (22) Prescaler 12 (PRE12) (23) Timer 1 (T1) (24) Timer 2 (T2) (25) Timer XY mode register (TM) (26) Prescaler X (PREX) (27) Timer X (TX) (28) Prescaler Y (PREY) (29) Timer Y (TY) (30) Timer count source selection register (TCSS) (31) I2C address regiter (S0D) 001616 0 0 0 0 0 1 1 1 001716 X X X X X X X X 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 X X X X X X X X 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 002816 002C16 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016 0016 (32) I2C status register (S1) (33) I2C control register (S1D) (34) I2C clock control register (S2) 002D16 0 0 0 1 0 0 0 X 002E16 002F16 0016 0016 (35) I2C start/stop condition control register (S2D) 003016 0 0 0 X X X X X Fig. 51 Internal status at reset Rev.1.01 Oct 15, 2003 page 45 of 89 3851 Group (Built-in 24 KB or more ROM) CLOCK GENERATING CIRCUIT The 3851 group (built-in 24 KB or more ROM) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between X IN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer ’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. When the oscillator is restarted by reset, apply “ L ” l evel to the RESET pin until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN d ivided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. Note When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. Note If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN). XCIN Rf XCOUT Rd CCOUT XIN XOUT (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillation circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. CCIN CI N COUT Fig. 52 Ceramic resonator circuit Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either X IN or X CIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. XCIN Rf XCOUT Rd CCOUT XIN XOUT Open External oscillation circuit CCIN Vcc Vss Fig. 53 External clock input circuit Rev.1.01 Oct 15, 2003 page 46 of 89 3851 Group (Built-in 24 KB or more ROM) Notes on middle-speed mode automatic switch set bit When the middle-speed mode automatic switch set bit is set to “1” while operating in the low-speed mode, by detecting the rising/falling edge of the SCL or SDA pin, XIN oscillation automatically starts and the mode is automatically switched to the middle-speed mode. The timing which changes from the low-speed mode to the middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5 cycle in the low-speed mode by the middle-speed mode automatic switch waiting time set bit. Select according to the oscillation start characteristic of the XIN oscillator to be used. b7 b0 MISRG (MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return “0” when read) Note: W h e n th e mo d e i s a u t o m a ti c a lly s wi tc h e d fr o m t h e lo w- s p e e d m o d e t o the middle-speed mode, the value of CPU mode register (address 003B16) changes. Fig. 54 Structure of MISRG XCIN XCOUT “1” “0” Port XC switch bit XIN XOUT Main clock division ratio selection bits (Note 1) Low-speed mode Timer 12 count source selection bit 1/2 High-speed or middle-speed mode 1/4 1/2 Prescaler 12 FF16 Timer 1 0116 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode High-speed or low-speed mode Main clock stop bit Timing φ (internal clock) Q S R STP instruction WIT instruction SQ R QS R STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: When bit 0 of MISRG = “0” Fig. 55 System clock generating circuit block diagram (Single-chip mode) Rev.1.01 Oct 15, 2003 page 47 of 89 3851 Group (Built-in 24 KB or more ROM) Reset Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1” ←→ “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) → ” CM ” ← “0 “1 M6 → C ”← “1 4 ” “0 C “0 M4 CM ” ← “1 6 → ”← “1 ” → “0 ” Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM4 “1” ←→ “0” CM6 “1” ←→ “0” CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1” ←→ “0” C “0 M7 CM ” ← “1 6 → “1 ”← ” → “0 ” CM4 “1” ←→ “0” High-speed mode (f(φ) = 4 MHz) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”. (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 56 State transitions of system clock Rev.1.01 Oct 15, 2003 page 48 of 89 CM5 “1” ←→ “0” 3851 Group (Built-in 24 KB or more ROM) FLASH MEMORY MODE The M38517F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 5 V, and 2 power sources when VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and standard serial I/O modes. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Summary Table 15 lists the summary of the M38517F8 (flash memory version). The flash memory of the M38517F8 is divided into User ROM area and Boot ROM area as shown in Figure 57. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 15 Summary of M38517F8 (flash memory version) Item Power source voltage VPP voltage (For Program/Erase) Flash memory mode Erase block division User ROM area Boot ROM area Specifications Vcc = 2.7– 5.5 V (Note 1) Vcc = 2.7–3.6 V (Note 2) 4.5-5.5 V 3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode) 1 block (32 Kbytes) 1 block (4 Kbytes) (Note 3) Byte program Batch erasing Program/Erase control by software command 6 commands 100 times Available in parallel I/O mode and standard serial I/O mode Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation. 2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. Rev.1.01 Oct 15, 2003 page 49 of 89 3851 Group (Built-in 24 KB or more ROM) (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 57 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 57 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P41/INT0 pin high, the CNVss pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC16, FFFD16 fixation). This mode is called the “Boot” mode. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. In case of the M38517F8, it has only one block. Parallel I/O mode 800016 Block 1 : 32 kbyte FFFF16 User ROM area BSEL = 0 CPU rewrite mode, standard serial I/O mode 800016 Block 1 : 32 kbyte Product name M38517F8 Flash memory start address 800016 F00016 4 kbyte FFFF16 Boot ROM area BSEL = 1 F00016 4 kbyte FFFF16 Boot ROM area User area / Boot area selection bit = 1 FFFF16 User ROM area User area / Boot area selection bit = 0 Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 57 Block diagram of built-in flash memory Rev.1.01 Oct 15, 2003 page 50 of 89 3851 Group (Built-in 24 KB or more ROM) Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This rewrite control program must be transferred to the RAM before it can be executed. The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit 1 of address 0FFE16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 58 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing “0”. Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the control circuit. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in the RAM. Figure 59 shows a flowchart for setting/releasing CPU rewrite mode. b7 b0 Flash memory control register (address 0FFE16) (Note 1) FMCR RY/BY status flag 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask ROM version, this address is reserved area. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 58 Structure of flash memory control register Rev.1.01 Oct 15, 2003 page 51 of 89 3851 Group (Built-in 24 KB or more ROM) Start Single-chip mode or Boot mode (Note 1) Set CPU mode register (Note 2) Transfer CPU rewrite mode control program to RAM Setting Jump to control program transferred in RAM (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Check CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Released Write “0” to CPU rewrite mode select bit End Notes 1: When starting the MCU in the single-chip mode, supply 4.5 V to 5.5 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16). 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 59 CPU rewrite mode set/release flowchart Rev.1.01 Oct 15, 2003 page 52 of 89 3851 Group (Built-in 24 KB or more ROM) Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock frequency 4.0 MHz or less using the main clock division ratio selection bits (bit 6, 7 at 003B16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . (3) Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Watchdog timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) Reset Reset is always valid. In case of CNVSS = H when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. Rev.1.01 Oct 15, 2003 page 53 of 89 3851 Group (Built-in 24 KB or more ROM) Software Commands (CPU Rewrite Mode) Table 16 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained intact until another command is written. Read Status Register Command (7016) The read status register mode is entered by writing the command code “7016” in the first bus cycle. The contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR1, SR4, and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. Program Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag of the flash memory control register. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the next command is written. ____ The RY/BY Status Flag is “0” (busy) during write operation and “1” (ready) when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading bit 4 (SR4) of the status register. Start Write 4016 Write Write address Write data Status register read SR7 = 1 ? or RY/BY = 1 ? YES NO S R4 = 0 ? YES Program completed (Read array command “FF16” write) Fig. 60 Program flowchart NO Program error Table 16 List of software commands (CPU rewrite mode) Command Read array Read status register Clear status register Program Erase all blocks Block erase Cycle number 1 2 1 2 2 2 Mode Write Write Write Write Write Write First bus cycle Data Address (D0 to D7) X (Note 1) Second bus cycle Mode Address Data (D0 to D7) F F1 6 7016 5016 4016 2016 2016 Write Write Write BA WA (Note 3) X (Note 4) X X X X X Read X SRD (Note 2) WD (Note 3) 2016 D016 Notes 1: X denotes a given address in the User ROM area . 2: SRD = Status Register Data 3: WA = Write Address, WD = Write Data 4: BA = Block Address to be erased (Input the maximum address of each block.) Rev.1.01 Oct 15, 2003 page 54 of 89 3851 Group (Built-in 24 KB or more ROM) Erase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until another command is written. ____ The RY/BY Status Flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7 (SR7). After the erase all blocks end, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write 2016/D016 Block address 2016:Erase all blocks command D016:Block erase command Status register read SR7 = 1 ? or RY/BY = 1 ? NO YES NO SR5 = 0 ? Erase error YES Erase completed (Read comand “FF16” write) Fig. 61 Erase flowchart Rev.1.01 Oct 15, 2003 page 55 of 89 3851 Group (Built-in 24 KB or more ROM) Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 17 shows the status register. Each bit in this register is explained below. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is set to “0” when it is cleared. If “ 1 ” i s written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Table 17 Definition of each bit in status register (SRD) Symbol SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.1.01 Oct 15, 2003 page 56 of 89 3851 Group (Built-in 24 KB or more ROM) Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 62 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read array, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 62 Full status check flowchart and remedial procedure for errors Rev.1.01 Oct 15, 2003 page 57 of 89 3851 Group (Built-in 24 KB or more ROM) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. qROM Code Protect Function (in Parallel I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFDB 16 ) in parallel I/O mode. Figure 63 shows the ROM code protect control (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits. b7 b0 1 1 ROM code protect control register (address FFDB16) (Note 1) ROMCP Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 4) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 2) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode. Fig. 63 Structure of ROM code protect control Rev.1.01 Oct 15, 2003 page 58 of 89 3851 Group (Built-in 24 KB or more ROM) ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 64 ID code store addresses Rev.1.01 Oct 15, 2003 page 59 of 89 3851 Group (Built-in 24 KB or more ROM) (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 3851 Group (flash memory version). Refer to each programmer maker ’s handling manual for the details of the usage. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 57 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 57. The boot ROM area is 4 Kbytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Renesas factory. Therefore, using the device in standard serial I/O mode, you do not need to write to the boot ROM area. Rev.1.01 Oct 15, 2003 page 60 of 89 3851 Group (Built-in 24 KB or more ROM) (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires the exclusive external equipment (serial programmer). The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P26 (SCLK1) pin and “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas Technology Corporation. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figure 65 shows the pin connection for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins S CLK1, RxD, TxD and SRDY1 (BUSY). The S CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD pin is for CMOS output. The S RDY1 (BUSY) pin outputs “L” level when ready for reception and “H” level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 57 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programmer, etc.) using 4-wire clock-synchronized serial I/O (serial I/O1). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK1 pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY1 (BUSY) pin is “H” level. Accordingly, always start the next transfer after the SRDY1 (BUSY) pin is “L” level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc. Rev.1.01 Oct 15, 2003 page 61 of 89 3851 Group (Built-in 24 KB or more ROM) Table 18 Description of pin function (Standard Serial I/O Mode) Pin VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00 to P07 P10 to P17 P20 to P23 P24 P25 P26 P27 P30 to P34 P40, P42 to P44 P41 Name Power input CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 RxD input TxD output SCLK1 input BUSY output Input port P3 Input port P4 Input port P4 I/O Description Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. I I I O Connect to VCC when VCC = 4.5 V to 5.5 V. Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V. Reset input pin. While reset is “L” level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVSS to VSS . I I I I I O I O I I I Enter the reference voltage for AD from this pin, or open. Input “H” or “L”, or open. Input “H” or “L”, or open. Input “H” or “L”, or open. This pin is for serial data input. This pin is for serial data output. This pin is for serial clock input. This pin is for BUSY signal output. Input “H” or “L”, or open. Input “H” or “L”, or open. Input “H” when RESET is released only. Rev.1.01 Oct 15, 2003 page 62 of 89 3851 Group (Built-in 24 KB or more ROM) VCC VSS VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/TxD P24/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P41 BUSY SCLK1 TxD RxD RXD ✽ 2 VPP RESET ✽1 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) M38517F8SP/FP Mode setup method Signal CNVSS P41 SCLK1 RESET Value 4.5 to 5.5 V VCC ✽ 3 VCC ✽ 3 VSS → VCC Notes 1: Connect oscillator circuit 2: Connect to Vcc when Vcc = 4.5 V to 5.5 V. Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V. 3: It is necessary to apply Vcc only when reset is released. Fig. 65 Pin connection diagram in standard serial I/O mode Rev.1.01 Oct 15, 2003 page 63 of 89 3851 Group (Built-in 24 KB or more ROM) Software Commands (Standard Serial I/O Mode) Table 19 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 19 Software commands (Standard serial I/O mode) Control command 1st byte transfer FF16 2nd byte Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high) commands via the RxD pin. Software commands are explained here below. 4th byte Data output Data input 5th byte Data output Data input 6th byte Data output Data input ..... Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable 1 2 3 4 5 6 Page read Page program Erase all blocks Read status register Clear status register ID code check 4116 A716 7016 5016 F516 Address (low) Size (low) Address (middle) Size (high) Address (high) Checksum ID size Data input ID1 To required number of times Version data output To ID7 Acceptable Not acceptable 7 Download function FA16 8 Version data output function FB16 Version data output Version data output Version data output Version data output Version data output to 9th byte Acceptable Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address high must be “0016”. Rev.1.01 Oct 15, 2003 page 64 of 89 3851 Group (Built-in 24 KB or more ROM) qPage Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0 to D 7) for the page (256 bytes) specified with addresses A8 t o A23 w ill be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK1 RxD FF16 A8 to A15 A16 to A23 TxD data0 data255 SRDY1(BUSY) Fig. 66 Timing for page read qRead Status Register Command This command reads status information. When the “70 16” command code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read. SCLK1 RxD 7016 TxD SRD output SRD1 output SRDY1(BUSY) Fig. 67 Timing for reading status register Rev.1.01 Oct 15, 2003 page 65 of 89 3851 Group (Built-in 24 KB or more ROM) qClear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY1 (BUSY) signal changes from “H” to “L” level. SCLK1 RxD 5016 TxD SRDY1(BUSY) Fig. 68 Timing for clear status register qPage Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0 t o D 7 ) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY1 (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the page program can be known by reading the status register. For more information, see the section on the status register. SCLK1 RxD 4116 A8 to A15 A16 to A23 data0 data255 TxD SRDY1(BUSY) Fig. 69 Timing for page program Rev.1.01 Oct 15, 2003 page 66 of 89 3851 Group (Built-in 24 KB or more ROM) qErase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When erase all blocks end, the S RDY1 ( BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the erase operation can be known by reading the status register. SCLK1 RxD A716 D016 TxD SRDY1(BUSY) Fig. 70 Timing for erase all blocks Rev.1.01 Oct 15, 2003 page 67 of 89 3851 Group (Built-in 24 KB or more ROM) qDownload Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. SCLK1 RxD FA16 Data size Data size (high) (low) Check sum Program data TxD Program data SRDY1(BUSY) Fig. 71 Timing for download Rev.1.01 Oct 15, 2003 page 68 of 89 3851 Group (Built-in 24 KB or more ROM) qVersion Information Output Command This command outputs the version information of the control program stored in the Boot ROM area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. SCLK1 RxD FB16 TxD ‘V’ ‘E’ ‘R’ ‘X’ SRDY1(BUSY) Fig. 72 Timing for version information output Rev.1.01 Oct 15, 2003 page 69 of 89 3851 Group (Built-in 24 KB or more ROM) qID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code. SCLK1 RxD F516 D416 FF16 0016 ID size ID1 ID7 TxD SRDY1(BUSY) Fig. 73 Timing for ID check qID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD416 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 74 ID code storage addresses Rev.1.01 Oct 15, 2003 page 70 of 89 3851 Group (Built-in 24 KB or more ROM) qStatus Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16 ). Also, the status register is cleared by writing the clear status register command (5016). Table 20 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready). This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. If a program error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Table 20 Definition of each bit of status register (SRD) Definition SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.1.01 Oct 15, 2003 page 71 of 89 3851 Group (Built-in 24 KB or more ROM) qStatus Register 1 (SRD1) The status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 21 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is maintained even after the reset. •Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. •Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. •ID check completed bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID code check. •Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command wait state. Table 21 Definition of each bit of status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Definition “1” Update completed Match 00 01 10 11 “0” Not Update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - SR9 (bit1) SR8 (bit0) Data reception time out Reserved Time out - Rev.1.01 Oct 15, 2003 page 72 of 89 3851 Group (Built-in 24 KB or more ROM) Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 75 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (Erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 75 Full status check flowchart and remedial procedure for errors Rev.1.01 Oct 15, 2003 page 73 of 89 3851 Group (Built-in 24 KB or more ROM) Example Circuit Application for Standard Serial I/O Mode Figure 76 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. P41 Clock input BUSY output Data input Data output SCLK1 SRDY1 (BUSY) RXD TXD M38517F8 VPP power source input CNVss Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. 2: In this example, the Vpp power supply is supplied from an external source (writer). To use the user’s power source, connect to 4.5 V to 5.5 V. 3: It is necessary to apply Vcc to SCLK1 pin only when reset is released. Fig. 76 Example circuit application for standard serial I/O mode Rev.1.01 Oct 15, 2003 page 74 of 89 3851 Group (Built-in 24 KB or more ROM) Flash memory Electrical characteristics Table 22 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) 25±5 –40 to 125 Unit V V V V V V V mW °C °C Ta = 25 °C Note: The rating becomes 300 mW at the 42P2R-A/E package. Table 23 Flash memory mode Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Limits Symbol IPP1 IPP2 IPP3 VPP VCC Parameter VPP power source current (read) VPP power source current (program) VPP power source current (erase) VPP power source voltage VCC power source voltage VPP = VCC VPP = VCC VPP = VCC 4.5 Microcomputer mode operation at VCC = 2.7 to 5.5V Microcomputer mode operation at VCC = 2.7 to 3.6V 4.5 3.0 Conditions Min. Typ. Max. 100 60 30 5.5 5.5 3.6 Unit µA mA mA V V V Rev.1.01 Oct 15, 2003 page 75 of 89 3851 Group (Built-in 24 KB or more ROM) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. A-D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP instruction during an A-D conversion. Instruction Execution Time Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. NOTES ON USAGE Differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM) (1) The absolute maximum ratings of 3851 group (built-in 24 KB or more ROM) is smaller than that of 3851 group (built-in 16 KB ROM). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8) VI = –0.3 to 6.5 V (M38517F8) (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC p in) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recommended. Serial I/O In serial I/O1 (clock synchronous mode), if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H”. EPROM Version/One Time PROM Version/ Flash Memory Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. Rev.1.01 Oct 15, 2003 page 76 of 89 3851 Group (Built-in 24 KB or more ROM) Electric Characteristic Differences Among Mask ROM, Flash Memory, and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM, flash memory, and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with the flash memory, One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 20 Programming adapter Package 42P4B, 42S1B 42P2R-A/E Name of Programming Adapter PCA4738S-42A PCA4738F-42A DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form✽ 2. Mark Specification Form✽ 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 77 is recommended to verify programming. DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS The following are necessary when ordering a PROM programming service: 1. ROM Programming Confirmation Form✽ 2. Mark Specification Form✽ (only special mark with customer ’s trade mark logo) 3. Data to be programmed to PROM, in EPROM form (three identical copies) or one floppy disk. ✽For the mask ROM confirmation and the mark specifications, refer to the “ Renesas Technology ” H omepage ROM ordering (http://www.renesas.com/eng/rom). Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 77 Programming and testing of One Time PROM version Rev.1.01 Oct 15, 2003 page 77 of 89 3851 Group (Built-in 24 KB or more ROM) Electrical characteristics Absolute maximum ratings Table 25 Absolute maximum ratings Symbol Parameter VCC Power source voltage Input voltage P00–P07, P10–P17, P20, P21, VI P24–P27, P30–P34, P40–P44, VREF Input voltage P22, P23 VI Input voltage RESET, XIN VI Input voltage CNVSS M38514M6, M38514M8 VI M38514E6 M38517F8 Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VO XOUT Output voltage P22, P23 VO Power dissipation Pd Operating temperature Topr Storage temperature Tstg Note : The rating becomes 300mW at the 42P2R-A/E package. Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) –20 to 85 –40 to 125 Unit V V V V V V V V V mW °C °C All voltages are based on VSS. Output transistors are cut off. Ta = 25 °C Rev.1.01 Oct 15, 2003 page 78 of 89 3851 Group (Built-in 24 KB or more ROM) Recommended operating conditions Table 26 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC Power source voltage Parameter 8 MHz (high-speed mode) 8 MHz (middle-speed mode), 4 MHz(high-speed mode) VSS VREF AVSS VIA VIH VIH Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage “H” input voltage “H” input voltage (when I2C-BUS AN0–AN4 P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 input level is selected) SDA1, SCL1 SDA2, SCL2 VIH “H” input voltage (when SMBUS input level is selected) ____________ Min. 4.0 2.7 Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 Unit V V V 2.0 0 AVSS 0.8VCC 0.7VCC 0.7VCC 1.4 1.4 0.8VCC 0 0 0 0 0 0 VCC V V VCC VCC 5.8 VCC 5.8 VCC VCC 0.2VCC 0.3VCC 0.6 0.2VCC 0.16VCC –80 –80 80 120 80 –40 –40 40 60 40 V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA SDA1, SCL1 SDA2, SCL2 VIH VIL VIL VIL VIL VIL ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) “H” input voltage “L” input voltage “L” input voltage (when I2C-BUS RESET, XIN, CNVSS P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 input level is selected) ____________ SDA1, SDA2, SCL1, SCL2 SDA1, SDA2, SCL1, SCL2 “L” input voltage (when SMBUS input level is selected) “L” input voltage “L” input voltage RESET, CNVSS XIN “H” total peak output current (Note) P00–P07, P10–P17, P30–P34 “H” total peak output current (Note) P20, P21, P24–P27, P40–P44 “L” total peak output current (Note) P00–P07, P30–P34 “L” total peak output current (Note) P10–P17 “L” total peak output current (Note) P20–P27,P40–P44 “H” total average output current (Note) P00–P07, P10–P17, P30–P34 “H” total average output current (Note) P20, P21, P24–P27, P40–P44 “L” total average output current (Note) P00–P07, P30–P34 “L” total average output current (Note) P10–P17 “L” total average output current (Note) P20–P27,P40–P44 Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.1.01 Oct 15, 2003 page 79 of 89 3851 Group (Built-in 24 KB or more ROM) Table 27 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) f(XIN) “H” peak output current (Note 1) Parameter P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 “L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44, P10–P17 “H” average output current (Note 2) P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 “L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44, P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. –10 10 20 –5 5 15 8 4 Unit mA mA mA mA mA mA MHz MHz Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%. Electrical characteristics Table 28 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note) “L” output voltage P00–P07, P20–P27, P30–P34, P40–P44 “L” output voltage P10–P17 Test conditions IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V IOL = 10 mA VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V IOL = 20 mA VCC = 4.0–5.5 V IOL = 10 mA VCC = 2.7–5.5 V Min. VCC–2.0 VCC–1.0 2.0 1.0 2.0 1.0 Typ. Max. Unit V V V V V V VOL VOL Note: P25 is measured when the P25/SCL2/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Rev.1.01 Oct 15, 2003 page 80 of 89 3851 Group (Built-in 24 KB or more ROM) Table 29 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VT+–VT– VT+–VT– VT+–VT– IIH Parameter Hysteresis CNTR0, CNTR1, INT0–INT3 Hysteresis RxD, SCLK1, SIN2, SCLK2 ____________ Hysteresis RESET “H” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 ____________ “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P34, P40–P44 ____________ “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage Test conditions Min. Typ. 0.4 0.5 0.5 VI = VCC 5.0 Max. Unit V V V µA IIH IIH IIL VI = VCC VI = VCC VI = VSS 5.0 4 –5.0 µA µA µA IIL IIL VRAM VI = VSS VI = VSS When clock stopped –5.0 –4 2.0 5.5 µA µA V Rev.1.01 Oct 15, 2003 page 81 of 89 3851 Group (Built-in 24 KB or more ROM) Table 30 Electrical characteristics (3) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Min. High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode Except f(XIN) = stopped M38517F8FP/SP f(XCIN) = 32.768 kHz M38517F8FP/SP Output transistors “off” Low-speed mode Except f(XIN) = stopped M38517F8FP/SP f(XCIN) = 32.768 kHz (in WIT state) M38517F8FP/SP Output transistors “off” Low-speed mode (VCC = 3 V) Except M38517F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz M38517F8FP/SP Output transistors “off” Low-speed mode (VCC = 3 V) Except M38517F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) M38517F8FP/SP Output transistors “off” Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Limits Typ. 6.8 Max. 13 Unit mA 1.6 60 250 20 70 20 150 5.0 20 10.0 55 40 200 mA µA µA µA µA µA µA µA µA ICC Power source current 4.0 7.0 mA 1.5 mA 800 0.1 1.0 10 µA µA µA Rev.1.01 Oct 15, 2003 page 82 of 89 3851 Group (Built-in 24 KB or more ROM) A-D converter characteristics Table 31 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Symbol – – tCONV Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions Limits Min. Typ. Max. 10 ±4 61 Unit bit LSB tc(φ) µs kΩ µA µA High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50 RLADDER IVREF II(AD) Ladder resistor Reference power source input current A-D port input current VREF “on” VREF “off” 40 35 150 0.5 200 5.0 5.0 Rev.1.01 Oct 15, 2003 page 83 of 89 3851 Group (Built-in 24 KB or more ROM) Timing requirements Table 32 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 33 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Parameter Limits Min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART). Rev.1.01 Oct 15, 2003 page 84 of 89 3851 Group (Built-in 24 KB or more ROM) Switching characteristics Table 34 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2–30 tC(SCLK1)/2–30 –30 30 30 tC(SCLK2)/2–160 tC(SCLK2)/2–160 200 0 10 10 30 30 30 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Fig. 79 140 Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded. Table 35 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2–50 tC(SCLK1)/2–50 –30 50 50 tC(SCLK2)/2–240 tC(SCLK2)/2–240 400 0 20 20 50 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Fig. 79 350 Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded. Rev.1.01 Oct 15, 2003 page 85 of 89 3851 Group (Built-in 24 KB or more ROM) MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Table 36 Multi-master I2C-BUS bus line characteristics Standard clock mode High-speed clock mode Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Bus free time Hold time for START condition Hold time for SCL clock = “0” Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition 250 4.7 4.0 Fig. 80 0 4.0 300 Parameter Test conditions Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit µs µs µs ns µs µs ns ns µs µs Note: Cb = total capacitance of 1 bus line SDA tBUF tLOW tR tF Sr p tHD:STA tsu:STO SCL p S tHD:STA tHD:DTA tHIGH tsu:DAT tsu:STA Fig. 78 Timing diagram of multi-master I2C-BUS 1 kΩ Measurement output pin 100 pF Measurement output pin 100 pF CMOS output N-channnel open-drain Fig. 79 Circuit for measuring output switching characteristics (1) Fig. 80 Circuit for measuring output switching characteristics (2) Rev.1.01 Oct 15, 2003 page 86 of 89 3851 Group (Built-in 24 KB or more ROM) tC(CNTR) C N TR 0 C N TR 1 tWH(CNTR) 0.8VCC 0.2VCC tWL(CNTR) tWH(INT) tWL(INT) 0.2VCC INT0 to INT3 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC SCLK1 SCLK2 tf tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC th(SCLK1-RxD), th(SCLK2-SIN2) RX D SIN2 td(SCLK1-TXD), td(SCLK2-SOUT2) 0.8VCC 0.2VCC tv(SCLK1-TXD), tv(SCLK2-SOUT2) TX D SOUT2 Fig. 81 Timing diagram Rev.1.01 Oct 15, 2003 page 87 of 89 3851 Group (Built-in 24 KB or more ROM) PACKAGE OUTLINE 42P4B EIAJ Package Code SDIP42-P-600-1.78 MMP JEDEC Code – Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy Plastic 42pin 600mil SDIP 42 22 1 21 Symbol D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° A 42P2R-A/E EIAJ Package Code SSOP42-P-450-0.80 42 A1 L A2 Plastic 42pin 450mil SSOP JEDEC Code – Weight(g) 0.63 22 Lead Material Alloy 42 e e1 E c b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – Symbol 1 21 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 c z Z1 Detail G Detail F Rev.1.01 Oct 15, 2003 page 88 of 89 L I2 3851 Group (Built-in 24 KB or more ROM) 42S1B-A EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code – Weight(g) Metal seal 42pin 600mil DIP D 42 22 c Symbol A A1 A2 b b1 c D E e e1 L Z A2 Dimension in Millimeters Min Nom Max – – 5.0 – – 1.0 3.44 – – 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 – – 41.1 – 15.8 – – – 1.778 – – 15.24 3.05 – – – – 3.05 A1 e1 E 1 21 L A Z e b b1 SEATING PLANE Rev.1.01 Oct 15, 2003 page 89 of 89 REVISION HISTORY Rev. Date Page 1.00 Jul. 26, 2002 1.01 Oct. 15, 2003 1 5 14-15 15 17 – First edition issued 3851 Group (built-in 24 KB or more ROM) Data Sheet Description Summary 18 22 29 32 77 79 •Mitsubishi, Mitsubishi Electric Corporation → Renesas Technology Corporation •SCLK → SCLK1 qMulti-master I2C-BUS interface (option) → qMulti-master I2C-BUS interface Fig.4 Memory expansion plan Under development M38517M8/F8 → Mass production M38517M8/F8 “SDA input”, “SCL input” “Serial I/O1 input” (12)Port P26 External clock input → Serial I/O1 external clock input (13)Port P27 Serial ready output → Serial I/O1 ready output •Interrupt occur by 17 sources among 17 sources seven external → Interrupt occur by 17 sources : seven external •address 3A16, address 2316 → address 003A16, address 002316 Table 8 Interrupt vector addresses and priority Serial I/O1 reception, Serial I/O transmission : Remarks Valid when serial I/O1 is selected → Valid when serial I/O is selected Fig.18 Block diagram of clock synchronous serial I/O __________ __________ P27/SRDY1 → P27/CNTR0/SRDY1 MITSUBISHI ELECTRIC CORPORATION’S → Renesas Technology Corporation’s •Bit 6: SDA/SCL pin selection bit → Bit 6: SDA/SCL pin selection bit (TSEL) •Bit 7: I2C-BUS interface pin input level selection bit → Bit 7: I2C-BUS interface pin input level selection bit (TISS) “Mitsubishi MCU Technical Information” Homepage (http:// www. infomicom.maec.co.jp/indexe.htm) → “Renesas Technology” Homepage Rom ordering (http:// www. renesas.com/eng/rom) Table 26 Recommended operating conditions (1) Symbol VIH VIH Parameter “H” input voltage (when I2C-BUS input level is selected) SDA2, SCL2 SDA1, SCL1 “H” input voltage (when SMBUS input level is selected) SDA2, SCL2 SDA1, SCL1 Min. 0.7VCC 0.7VCC 1.4 1.4 Limits Typ. Max. VCC 5.8 VCC 5.8 Unit V V V V Symbol VIH VIH Parameter “H” input voltage (when I2C-BUS input level is selected) SDA1, SDA2, “H” input voltage (when SMBUS input level is selected) SDA1, SDA2, SCL1 SCL2 SCL1 SCL2 Min. 0.7VCC 0.7VCC 1.4 1.4 Limits Typ. Max. 5.8 VCC 5.8 VCC Unit V V V V 81 Table 29 Electrical characteristics (2) VT+–VT- Hysterisis RXD, SCLK → RXD, SCLK1, SIN2, SCLK2 (1/1) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. 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