4519

REJ09B0175-0100Z 4 4519 Group User's Manual RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: Aug 06, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. REVISION HISTORY Rev. Date Page 1.00 Aug 06, 2004 – First edition issued 4519 Group User’s Manual Description Summary BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. As for the Mask ROM confirmation form, the ROM programming confirmation form, and the Mark specification form which are to be submitted when ordering, refer to the “Renesas Technology Corp.” Hompage (http:/ /www.renesas.com/en/rom). As for the Development tools and related documents, refer to the Product Info - 4519 Group (http:// www.renesas.com/eng/products/mpumcu/specific/lcd_mcu/expand/e4519.htm) of “Renesas Technology Corp.” Homepage. 4519 Group Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 BLOCK DIAGRAM ......................................................................................................................... 1-3 PERFORMANCE OVERVIEW ....................................................................................................... 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 MULTIFUNCTION ..................................................................................................................... 1-6 DEFINITION OF CLOCK AND CYCLE ................................................................................. 1-6 PORT FUNCTION .................................................................................................................... 1-7 CONNECTIONS OF UNUSED PINS ..................................................................................... 1-8 PORT BLOCK DIAGRAMS ..................................................................................................... 1-9 FUNCTION BLOCK OPERATIONS ........................................................................................... 1-17 CPU .......................................................................................................................................... 1-17 PROGRAM MEMORY (ROM) ............................................................................................... 1-20 DATA MEMORY (RAM) ......................................................................................................... 1-21 INTERRUPT FUNCTION ....................................................................................................... 1-22 EXTERNAL INTERRUPTS .................................................................................................... 1-26 TIMERS ................................................................................................................................... 1-31 WATCHDOG TIMER .............................................................................................................. 1-45 A/D CONVERTER (COMPARATOR) ................................................................................... 1-47 SERIAL I/O .............................................................................................................................. 1-53 RESET FUNCTION ................................................................................................................ 1-58 VOLTAGE DROP DETECTION CIRCUIT ........................................................................... 1-62 RAM BACK-UP MODE .......................................................................................................... 1-63 CLOCK CONTROL ................................................................................................................. 1-68 ROM ORDERING METHOD ....................................................................................................... 1-71 LIST OF PRECAUTIONS ............................................................................................................ 1-72 CONTROL REGISTERS .............................................................................................................. 1-78 INSTRUCTIONS ............................................................................................................................ 1-85 SYMBOL .................................................................................................................................. 1-85 INDEX LIST OF INSTRUCTION FUNCTION ..................................................................... 1-86 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) ....................................................... 1-91 MACHINE INSTRUCTIONS (INDEX BY TYPES) ............................................................ 1-130 INSTRUCTION CODE TABLE ............................................................................................ 1-146 BUILT-IN PROM VERSION ...................................................................................................... 1-148 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z i 4519 Group Table of contents CHAPTER 2 APPLICATION 2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports .......................................................................................................................... 2-2 2.1.2 Related registers ............................................................................................................ 2-6 2.1.3 Port application examples ........................................................................................... 2-12 2.1.4 Notes on use ................................................................................................................ 2-13 2.2 Interrupts ............................................................................................................................... 2-15 2.2.1 Interrupt functions ........................................................................................................ 2-15 2.2.2 Related registers .......................................................................................................... 2-18 2.2.3 Interrupt application examples .................................................................................... 2-21 2.2.4 Notes on use ................................................................................................................ 2-30 2.3 Timers .................................................................................................................................... 2-31 2.3.1 Timer functions ............................................................................................................. 2-31 2.3.2 Related registers .......................................................................................................... 2-32 2.3.3 Timer application examples ........................................................................................ 2-37 2.3.4 Notes on use ................................................................................................................ 2-50 2.4 A/D converter ....................................................................................................................... 2-52 2.4.1 Related registers .......................................................................................................... 2-53 2.4.2 A/D converter application examples .......................................................................... 2-54 2.4.3 Notes on use ................................................................................................................ 2-56 2.5 Serial I/O ................................................................................................................................ 2-58 2.5.1 Serial I/O functions ...................................................................................................... 2-58 2.5.2 Related registers .......................................................................................................... 2-59 2.5.3 Operation description ................................................................................................... 2-60 2.5.4 Serial I/O application example ................................................................................... 2-63 2.5.5 Notes on use ................................................................................................................ 2-66 2.6 Reset ....................................................................................................................................... 2-67 2.6.1 Reset circuit .................................................................................................................. 2-67 2.6.2 Internal state at reset .................................................................................................. 2-68 2.6.3 Notes on use ................................................................................................................ 2-69 2.7 Voltage drop detection circuit .......................................................................................... 2-70 2.8 RAM back-up ........................................................................................................................ 2-71 2.8.1 RAM back-up mode ..................................................................................................... 2-71 2.8.2 Related registers .......................................................................................................... 2-74 2.8.3 Notes on use ................................................................................................................ 2-78 2.9 Oscillation circuit ................................................................................................................ 2-79 2.9.1 Oscillation operation .................................................................................................... 2-79 2.9.2 Related register ............................................................................................................ 2-80 2.9.3 Notes on use ................................................................................................................ 2-81 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z ii 4519 Group Table of contents CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-6 3.1.4 A/D converter recommended operating conditions .................................................... 3-8 3.1.5 Voltage drop detection circuit characteristics ........................................................... 3-10 3.1.6 Basic timing diagram ................................................................................................... 3-10 3.2 Typical characteristics ....................................................................................................... 3-11 3.3 List of precautions .............................................................................................................. 3-12 3.3.1 Program counter ........................................................................................................... 3-12 3.3.2 Stack registers (SKs) ................................................................................................... 3-12 3.3.3 Notes on I/O port ......................................................................................................... 3-12 3.3.4 Notes on interrupt ........................................................................................................ 3-14 3.3.5 Notes on timer .............................................................................................................. 3-15 3.3.6 Notes on A/D conversion ............................................................................................ 3-17 3.3.7 Notes on serial I/O ...................................................................................................... 3-18 3.3.8 Notes on reset .............................................................................................................. 3-19 3.3.9 Notes on RAM back-up ............................................................................................... 3-19 3.3.10 Notes on clock control .............................................................................................. 3-20 3.3.11 Electric characteristic differences between Mask ROM and One Time PROM version MCU .. 3-20 3.3.12 Note on Power Source Voltage ............................................................................... 3-20 3.4 Notes on noise ..................................................................................................................... 3-21 3.4.1 Shortest wiring length .................................................................................................. 3-21 3.4.2 Connection of bypass capacitor across V SS l ine and V DD l ine ............................ 3-23 3.4.3 Wiring to analog input pins ........................................................................................ 3-24 3.4.4 Oscillator concerns ....................................................................................................... 3-24 3.4.5 Setup for I/O ports ....................................................................................................... 3-25 3.4.6 Providing of watchdog timer function by software .................................................. 3-25 3.5 Package outline ................................................................................................................... 3-27 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z iii 4519 Group List of figures List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 AMC instruction execution example ............................................................................... 1-17 2 RAR instruction execution example ............................................................................... 1-17 3 Registers A, B and register E ........................................................................................ 1-17 4 TABP p instruction execution example .......................................................................... 1-17 5 Stack registers (SKs) structure ....................................................................................... 1-18 6 Example of operation at subroutine call ....................................................................... 1-18 7 Program counter (PC) structure ..................................................................................... 1-19 8 Data pointer (DP) structure ............................................................................................. 1-19 9 SD instruction execution example .................................................................................. 1-19 10 ROM map of M34519M8/E8 ......................................................................................... 1-20 11 Page 1 (addresses 0080 16 t o 00FF 16) structure ....................................................... 1-20 12 RAM map ......................................................................................................................... 1-21 13 Program example of interrupt processing ................................................................... 1-23 14 Internal state when interrupt occurs ............................................................................ 1-23 15 Interrupt system diagram ............................................................................................... 1-23 16 Interrupt sequence .......................................................................................................... 1-25 17 External interrupt circuit structure ................................................................................ 1-26 18 External 0 interrupt program example-1 ...................................................................... 1-29 19 External 0 interrupt program example-2 ...................................................................... 1-29 20 External 0 interrupt program example-3 ...................................................................... 1-29 21 External 1 interrupt program example-1 ...................................................................... 1-30 22 External 1 interrupt program example-2 ...................................................................... 1-30 23 External 1 interrupt program example-3 ...................................................................... 1-30 24 Auto-reload function ....................................................................................................... 1-31 25 Timer structure (1) ......................................................................................................... 1-33 26 Timer structure (2) ......................................................................................................... 1-34 27 Period measurement circuit program example ........................................................... 1-39 28 Period measurement circuit program example ........................................................... 1-41 29 Timer 4 operation (reload register R4L: “03 16”, R4H: “02 16”) ................................. 1-42 30 CNTR1 output auto-control function by timer 3 ......................................................... 1-43 31 Timer 4 count start/stop timing .................................................................................... 1-44 32 Watchdog timer function ................................................................................................ 1-45 33 Program example to start/stop watchdog timer ......................................................... 1-46 34 Program example to enter the mode when using the watchdog timer .................. 1-46 35 A/D conversion circuit structure ................................................................................... 1-47 36 A/D conversion timing chart .......................................................................................... 1-50 37 Setting registers .............................................................................................................. 1-50 38 Comparator operation timing chart ............................................................................... 1-51 39 Definition of A/D conversion accuracy ........................................................................ 1-52 40 Serial I/O structure ......................................................................................................... 1-53 41 Serial I/O register state when transferring .................................................................. 1-54 42 Serial I/O connection example ...................................................................................... 1-55 43 Timing of serial I/O data transfer ................................................................................. 1-56 44 Reset release timing ...................................................................................................... 1-58 ____________ 45 RESET pin input waveform and reset operation ....................................................... 1-58 46 Structure of reset pin and its peripherals, and power-on reset operation ............. 1-59 47 Internal state at reset 1 ................................................................................................. 1-60 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z iv 4519 Group List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Internal state at reset 2 ................................................................................................. 1-61 Voltage drop detection reset circuit ............................................................................. 1-62 Voltage drop detection circuit operation waveform .................................................... 1-62 State transition ................................................................................................................ 1-65 Set source and clear source of the P flag ................................................................. 1-65 Start condition identified example using the SNZP instruction ................................ 1-65 Clock control circuit structure ....................................................................................... 1-68 Switch to ceramic resonance/RC oscillation/quartz-crystal oscillation .................... 1-69 Handling of X IN a nd X OUT w hen operating on-chip oscillator .................................. 1-70 Ceramic resonator external circuit ............................................................................... 1-70 External RC oscillation circuit ....................................................................................... 1-70 External quartz-crystal circuit ........................................................................................ 1-70 External clock input circuit ............................................................................................ 1-70 Period measurement circuit program example ........................................................... 1-73 External 0 interrupt program example-1 ...................................................................... 1-74 External 0 interrupt program example-2 ...................................................................... 1-74 External 0 interrupt program example-3 ...................................................................... 1-74 External 1 interrupt program example-1 ...................................................................... 1-75 External 1 interrupt program example-2 ...................................................................... 1-75 External 1 interrupt program example-3 ...................................................................... 1-75 A/D converter program example-3 ............................................................................... 1-76 Analog input external circuit example-1 ...................................................................... 1-76 Analog input external circuit example-2 ...................................................................... 1-76 Pin configuration of built-in PROM version .............................................................. 1-148 PROM memory map ..................................................................................................... 1-149 Flow of writing and test of the product shipped in blank ....................................... 1-149 CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Key input by key scan ............................................................................................... 2-12 2.1.2 Key scan input timing ................................................................................................ 2-12 2.2.1 External 0 interrupt operation example ................................................................... 2-22 2.2.2 External 0 interrupt setting example ....................................................................... 2-23 2.2.3 External 1 interrupt operation example ................................................................... 2-24 2.2.4 External 1 interrupt setting example ....................................................................... 2-25 2.2.5 Timer 1 constant period interrupt setting example ................................................ 2-26 2.2.6 Timer 2 constant period interrupt setting example ................................................ 2-27 2.2.7 Timer 3 constant period interrupt setting example ................................................ 2-28 2.2.8 Timer 4 constant period interrupt setting example ................................................ 2-29 2.3.1 Peripheral circuit example ......................................................................................... 2-37 2.3.2 Timer 4 operation ....................................................................................................... 2-38 2.3.3 Watchdog timer function ............................................................................................ 2-39 2.3.4 Constant period measurement setting example ..................................................... 2-40 2.3.5 CNTR0 output setting example ................................................................................ 2-41 2.3.6 CNTR0 input setting example .................................................................................. 2-42 2.3.7 Timer start by external input setting example ....................................................... 2-43 2.3.8 PWM output control setting example ...................................................................... 2-44 2.3.9 Period measurement of CNTR0 pin input setting example (1) ........................... 2-45 2.3.10 Period measurement of CNTR0 pin input setting example (2) ......................... 2-46 2.3.11 Pulse width measurement of INT0 pin input setting example (1) ..................... 2-47 2.3.12 Pulse width measurement of INT0 pin input setting example (2) ..................... 2-48 2.3.13 Watchdog timer setting example ............................................................................ 2-49 2.3.14 Period measurement circuit program example ..................................................... 2-51 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z v 4519 Group List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.15 Count start time and count time when operation starts (PS, T1, T2 and T3) 2-51 2.3.16 Count start time and count time when operation starts (T4) ............................ 2-51 2.4.1 A/D converter structure ............................................................................................. 2-52 2.4.2 A/D conversion mode setting example .................................................................... 2-55 2.4.3 Analog input external circuit example-1 .................................................................. 2-56 2.4.4 Analog input external circuit example-2 .................................................................. 2-56 2.4.5 A/D converter operating mode program example .................................................. 2-56 2.5.1 Serial I/O block diagram ........................................................................................... 2-58 2.5.2 Serial I/O connection example ................................................................................. 2-60 2.5.3 Serial I/O register state when transfer .................................................................... 2-60 2.5.4 Serial I/O transfer timing ........................................................................................... 2-61 2.5.5 Setting example when a serial I/O of master side is not used .......................... 2-64 2.5.6 Setting example when a serial I/O interrupt of slave side is used .................... 2-65 2.6.1 Structure of reset pin and its peripherals, and power-on reset operation ......... 2-67 2.6.2 Oscillation stabilizing time after system is released from reset .......................... 2-67 2.6.3 Internal state at reset ................................................................................................ 2-68 2.6.4 Internal state at reset ................................................................................................ 2-69 2.7.1 Voltage drop detection circuit ................................................................................... 2-70 2.7.2 Voltage drop detection circuit operation waveform example ............................... 2-70 2.8.1 State transition ............................................................................................................ 2-71 2.8.2 Start condition identified example ............................................................................ 2-73 2.9.1 Structure of clock control circuit .............................................................................. 2-79 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z vi 4519 Group List of figures CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.3.1 Period measurement circuit program example ....................................................... 3-16 3.3.2 Count start time and count time when operation starts (PS, T1, T2 and T3) .. 3-16 3.3.3 Count start time and count time when operation starts (T4) .............................. 3-16 3.3.4 Analog input external circuit example-1 .................................................................. 3-17 3.3.5 Analog input external circuit example-2 .................................................................. 3-17 3.3.6 A/D converter operating mode program example .................................................. 3-17 3.4.1 Selection of packages ............................................................................................... 3-21 ____________ 3.4.2 Wiring for the RESET input pin ............................................................................... 3-21 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-22 3.4.4 Wiring for CNV SS p in ................................................................................................. 3-22 3.4.5 Wiring for the V PP p in of the built-in PROM version ............................................ 3-23 3.4.6 Bypass capacitor across the V SS l ine and the VDD l ine ...................................... 3-23 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-24 3.4.8 Wiring for a large current signal line ...................................................................... 3-24 3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-25 3.4.10 V SS p attern on the underside of an oscillator ..................................................... 3-25 3.4.11 Watchdog timer by software ................................................................................... 3-26 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z vii 4519 Group List of tables List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock .................................................................................................. 1-6 1 ROM size and pages .................................................................................................... 1-20 2 RAM size ........................................................................................................................ 1-21 3 Interrupt sources ............................................................................................................ 1-22 4 Interrupt request flag, interrupt enable bit and skip instruction .............................. 1-22 5 Interrupt enable bit function ......................................................................................... 1-22 6 Interrupt control registers ............................................................................................. 1-24 7 External interrupt activated conditions ........................................................................ 1-26 8 External interrupt control register ................................................................................ 1-28 9 Function related timers ................................................................................................. 1-32 10 Timer related registers ................................................................................................ 1-35 11 A/D converter characteristics ..................................................................................... 1-47 12 A/D control registers ................................................................................................... 1-48 13 Change of successive comparison register AD during A/D conversion .............. 1-49 14 Serial I/O pins .............................................................................................................. 1-53 15 Serial I/O control register ........................................................................................... 1-53 16 Processing sequence of data transfer from master to slave ................................ 1-57 17 Port state at reset ....................................................................................................... 1-59 18 Voltage drop detection circuit operation state ......................................................... 1-62 19 Functions and states retained at RAM back-up ..................................................... 1-63 20 Return source and return condition .......................................................................... 1-64 21 Key-on wakeup control register, pull-up control register ....................................... 1-66 22 Key-on wakeup control register, pull-up control register ....................................... 1-67 23 Clock control registers ................................................................................................ 1-71 24 Product of built-in PROM version ........................................................................... 1-148 25 Programming adapter ................................................................................................ 1-149 CHAPTER 2 APPLICATION Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 Timer control register W4 ........................................................................................ 2-6 2.1.2 Timer control register W6 ........................................................................................ 2-6 2.1.3 Serial I/O control register J1 ................................................................................... 2-7 2.1.4 A/D control register Q2 ............................................................................................ 2-7 2.1.5 Pull-up control register PU0 .................................................................................... 2-8 2.1.6 Pull-up control register PU1 .................................................................................... 2-8 2.1.7 Port output structure control register FR0 ............................................................. 2-9 2.1.8 Port output structure control register FR1 ............................................................. 2-9 2.1.9 Port output structure control register FR2 ........................................................... 2-10 2.1.10 Port output structure control register FR3 ......................................................... 2-10 2.1.11 Key-on wakeup control register K0 .................................................................... 2-11 2.1.12 Key-on wakeup control register K2 .................................................................... 2-11 2.1.13 Connections of unused pins ................................................................................ 2-14 2.2.1 Interrupt control register V1 ................................................................................... 2-18 2.2.2 Interrupt control register V2 ................................................................................... 2-19 2.2.3 Interrupt control register I1 .................................................................................... 2-19 2.2.4 Interrupt control register I2 .................................................................................... 2-20 2.3.1 Interrupt control register V1 ................................................................................... 2-32 2.3.2 Interrupt control register V2 ................................................................................... 2-32 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z viii 4519 Group List of tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.3.3 Interrupt control register I1 .................................................................................... 2-33 2.3.4 Interrupt control register I2 .................................................................................... 2-33 2.3.5 Timer control register PA ....................................................................................... 2-34 2.3.6 Timer control register W1 ...................................................................................... 2-34 2.3.7 Timer control register W2 ...................................................................................... 2-34 2.3.8 Timer control register W3 ...................................................................................... 2-35 2.3.9 Timer control register W4 ...................................................................................... 2-35 2.3.10 Timer control register W5 .................................................................................... 2-36 2.3.11 Timer control register W6 .................................................................................... 2-36 2.4.1 Interrupt control register V2 ................................................................................... 2-53 2.4.2 A/D control register Q1 .......................................................................................... 2-53 2.4.3 A/D control register Q2 .......................................................................................... 2-54 2.4.4 A/D control register Q3 .......................................................................................... 2-54 2.5.1 Interrupt control register V2 ................................................................................... 2-59 2.5.2 Serial I/O mode register J1 ................................................................................... 2-59 2.7.1 Voltage drop detection circuit operation state .................................................... 2-70 2.8.1 Functions and states retained at RAM back-up mode ...................................... 2-72 2.8.2 Return source and return condition ...................................................................... 2-73 2.8.3 Start condition identification ................................................................................... 2-73 2.8.4 Interrupt control register I1 .................................................................................... 2-74 2.8.5 Interrupt control register I2 .................................................................................... 2-74 2.8.6 Pull-up control register PU0 .................................................................................. 2-75 2.8.7 Pull-up control register PU1 .................................................................................. 2-76 2.8.8 Key-on wakeup control register K0 ...................................................................... 2-76 2.8.9 Key-on wakeup control register K1 ...................................................................... 2-77 2.8.10 Key-on wakeup control register K2 .................................................................... 2-77 2.9.1 Clock control register MR ...................................................................................... 2-80 2.9.2 Clock control register RG ...................................................................................... 2-80 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.3.1 Absolute maximum ratings ....................................................................................... 3-2 Recommended operating conditions 1 ................................................................... 3-3 Recommended operating conditions 2 ................................................................... 3-4 Recommended operating conditions 3 ................................................................... 3-5 Electrical characteristics 1 ....................................................................................... 3-6 Electrical characteristics 2 ....................................................................................... 3-7 A/D converter recommended operating conditions ............................................... 3-8 A/D converter characteristics ................................................................................... 3-9 Voltage drop detection circuit characteristics ...................................................... 3-10 Connections of unused pins .................................................................................. 3-13 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z ix CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT-IN PROM VERSION HARDWARE 4519 Group DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION DESCRIPTION The 4519 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has one or two reload registers), a 10-bit A/D converter, interrupts, and oscillation circuit switch function. The various microcomputers in the 4519 Group include variations of the built-in memory size as shown in the table below. FEATURES q Minimum instruction execution time .................................. 0.5 µs (at 6 MHz oscillation frequency, in XIN through-mode) q Supply voltage Mask ROM version ...................................................... 1.8 to 5.5 V One Time PROM version ............................................. 2.5 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) q Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 3 ................................. 8-bit timer with two reload registers Part number M34519M6-XXXFP M34519M8-XXXFP M34519E8FP (Note) Note: Shipped in blank. q Interrupt ........................................................................ 8 sources q Key-on wakeup function pins ................................................... 10 q Serial I/O ....................................................................... 8 bits ✕ 1 q A/D converter .......... 10-bit successive comparison method, 8ch q Voltage drop detection circuit Reset occurrence .................................... Typ. 3.5 V (Ta = 25 °C) Reset release .......................................... Typ. 3.7 V (Ta = 25 °C) q Watchdog timer q Clock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/onchip oscillator) q LED drive directly enabled (port D) APPLICATION Electrical household appliance, consumer electronic products, office automation equipment, etc. ROM (PROM) size (✕ 10 bits) 6144 words 8192 words 8192 words RAM size (✕ 4 bits) 384 words 384 words 384 words Package 42P2R-A 42P2R-A 42P2R-A ROM type Mask ROM Mask ROM One Time PROM PIN CONFIGURATION P13 D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P50 P51 P52 P53 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS 1 2 3 4 5 6 42 41 40 39 38 37 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P12 P11 P10 P03 P02 P01 P00 P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P33 P32 P31/INT1 P30/INT0 VDCE VDD OUTLINE 42P2R-A Pin configuration (top view) (4519 Group) M34519Mx-XXXFP M34519E8FP Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-2 4519 Group 4 4 3 4 4 4 4 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z Block diagram (4519 Group) I/O port Port P1 Port P3 Port P4 Port P5 Port P6 Port P2 Port P0 Internal peripheral functions System clock generation circuit XIN -XOUT (Ceramic/Quartz-crystal/RC) On-chip oscillator Timer Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits) Voltage drop detection circuit Watchdog timer (16 bits) A/D converter (10 bits ✕ 8 ch) Memory ROM 6144, 8192 words ✕ 10 bits Serial I/O (8 bits ✕ 1) 4500 series CPU core ALU(4 bits) Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) RAM 384 words ✕ 4 bits Port D 8 BLOCK DIAGRAM HARDWARE 1-3 HARDWARE 4519 Group PERFORMANCE OVERVIEW PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34519M6 Function 153 0.5 µs (at 6.0 MHz oscillation frequency, in XIN through-mode) 6144 words ✕ 10 bits 8192 words ✕ 10 bits 384 words ✕ 4 bits Input/Output Eight independent I/O ports; Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. ports The output structure is switched by software. 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched by software. P10–P13 I/O 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched by software. P20–P22 I/O 3-bit I/O port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. P30–P33 I/O 4-bit I/O port ; ports P30 and P31 are also used as INT0 and INT1, respectively. P40–P43 I/O 4-bit I/O port ; ports P40–P43 are also used as AIN4–AIN7, respectively. P50–P53 I/O 4-bit I/O port ; the output structure is switched by software. P60–P63 I/O 4-bit I/O port ; ports P60–P63 are also used as AIN0–AIN3, respectively. Timer 1 Timers 8-bit timer with a reload register is also used as an event counter. Also, this is equipped with a period/pulse width measurement function. Timer 2 8-bit timer with a reload register. Timer 3 8-bit timer with a reload register is also used as an event counter. Timer 4 8-bit timer with two reload registers and PWM output function. A/D converter 10-bit wide ✕ 8 ch, This is equipped with an 8-bit comparator function. Serial I/O 8-bit ✕ 1 Sources Interrupt 8 (two for external, four for timer, one for A/D, and one for serial I/O) Nesting 1 level Subroutine nesting 8 levels Device structure CMOS silicon gate Package 42-pin plastic molded SSOP (42P2R-A) Operating temperature range –20 °C to 85 °C Supply voltage Mask ROM version 1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) One Time PROM version 2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) Active mode Power 2.8 mA (Ta=25°C, VDD=5V, f(XIN)=6 MHz, f(STCK)=f(XIN), on-chip oscillator stop) dissipation 70 µA (Ta=25°C, VDD=5V, f(XIN)=32 kHz, f(STCK)=f(XIN), on-chip oscillator stop) (typical value) 150 µA (Ta=25°C, VDD=5V, on-chip oscillator is used, f(STCK)=f(RING), f(XIN) stop) RAM back-up mode 0.1 µA (Ta=25°C, VDD = 5 V, output transistors in the cut-off state) M34519M8/E8 RAM M34519M6/M8/E8 D0–D7 I/O (Input is examined by skip decision) P00–P03 I/O Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-4 HARDWARE 4519 Group PIN DESCRIPTION PIN DESCRIPTION Pin VDD VSS CNVSS VDCE Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output Input/Output — — — Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is input to this pin, the circuit starts operating. When “L“ level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. When using a 32 kHz quartz-crystal oscillator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports D6, D7 is also used as CNTR0 pin and CNTR1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P20–P22 are also used as SCK, SOUT, SIN, respectively. Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P30 and P31 are also used as INT0 pin and INT1 pin, respectively. Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P40–P43 are also used as AIN4–AIN7, respectively. Port P5 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P60–P63 are also used as AIN0–AIN3, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D6 and D7, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports P30 and P31, respectively. A/D converter analog input pins. AIN0–AIN7 are also used as ports P60–P63 and P40– P43, respectively. Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port P20.. Serial I/O data output pin. SOUT pin is also used as port P21. Serial I/O data input pin. SIN pin is also used as port P22. RESET I/O XIN XOUT D 0 – D7 Main clock input Main clock output I/O port D Input is examined by skip decision. I/O port P0 Input Output I/O P00–P03 I/O P10–P13 I/O port P1 I/O P20–P23 I/O port P2 I/O P30–P33 I/O port P3 I/O P40–P43 I/O port P4 I/O P50–P53 I/O port P5 I/O P60–P63 I/O port P6 I/O CNTR0, CNTR1 Timer input/output I/O INT0, INT1 Interrupt input Input AIN0–AIN7 SCK SOUT SIN Analog input Serial I/O data I/O Serial I/O data output Serial I/O clock input Input I/O Output Input Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-5 HARDWARE 4519 Group MULTIFUNCTION/DEFINITION OF CLOCK AND CYCLE MULTIFUNCTION Pin D6 D7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Pin CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Multifunction D6 D7 P20 P21 P22 P30 P31 Pin P60 P61 P62 P63 P40 P41 P42 P43 Multifunction AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pin AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction P60 P61 P62 P63 P40 P41 P42 P43 Notes 1: Pins except above have just single function. 2: The input/output of P30 and P31 can be used even when INT0 and INT1 are selected. 3: The input of ports P20–P22 can be used even when SIN, SOUT and SCK are selected. 4: The input/output of D6 can be used even when CNTR0 (input) is selected. 5: The input of D6 can be used even when CNTR0 (output) is selected. 6: The input/output of D7 can be used even when CNTR1 (input) is selected. 7: The input of D7 can be used even when CNTR1 (output) is selected. DEFINITION OF CLOCK AND CYCLE q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • Clock (f(XIN)) by the external ceramic resonator • Clock (f(XIN)) by the external RC oscillation • Clock (f(XIN)) by the external input • Clock (f(RING)) of the on-chip oscillator which is the internal oscillator • Clock (f(XIN)) by the external quartz-crystal oscillation Table Selection of system clock Register MR System clock MR3 MR2 MR1 MR0 0 0 0 0 f(STCK) = f(XIN) ✕ 1 f(STCK) = f(RING) 0 1 0 0 f(STCK) = f(XIN)/2 ✕ 1 f(STCK) = f(RING)/2 1 0 0 0 f(STCK) = f(XIN)/4 ✕ 1 f(STCK) = f(RING)/4 1 1 0 0 f(STCK) = f(XIN)/8 ✕ 1 f(STCK) = f(RING)/8 ✕: 0 or 1 Note: The f(RING)/8 is selected after system is released from reset. When on-chip oscillator clock is selected for main clock, set the on-chip oscillator to be operating state. q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode XIN through mode On-chip oscillator through mode XIN divided by 2 mode On-chip oscillator divided by 2 mode XIN divided by 4 mode On-chip oscillator divided by 4 mode XIN divided by 8 mode On-chip oscillator divided by 8 mode Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-6 HARDWARE 4519 Group PORT FUNCTION PORT FUNCTION Port Port D Pin D 0– D 5 D6/CNTR0 D7/CNTR1 P00–P03 Input Output I/O (8) I/O (4) Output structure N-channel open-drain/ CMOS N-channel open-drain/ CMOS I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers FR1, FR2 W6 W4 FR0 PU0 K0, K1 FR0 PU1 K0 J1 I1, I2 K2 Q1 Q2 FR3 Q2 Q1 Remark Output structure selection function (programmable) Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions Port P0 4 Port P1 P10–P13 I/O (4) N-channel open-drain/ CMOS 4 OP1A IAP1 Port P2 Port P3 Port P4 Port P5 Port P6 P20/SCK, P21/SOUT P22/SIN P30/INT0, P31/INT1 P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 I/O (3) I/O (4) I/O (4) I/O (4) I/O (4) N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain 3 4 4 4 4 OP2A IAP2 OP3A IAP3 OP4A IAP4 OP5A IAP5 OP6A IAP6 Output structure selection function (programmable) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-7 HARDWARE 4519 Group CONNECTION OF UNUSED PINS CONNECTIONS OF UNUSED PINS Pin XIN XOUT Open. Open. Connection Usage condition Internal oscillator is selected. Internal oscillator is selected. RC oscillator is selected. External clock input is selected for main clock. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. CNTR1 input is not selected for timer 3 count source. N-channel open-drain is selected for the output structure. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. SCK pin is not selected. (Note 1) (Note 1) (Note 2) (Note 3) (Note 4) (Note 4) (Note 4) (Note 6) (Note 5) (Note 4) (Note 6) (Note 7) (Note 5) (Note 4) (Note 7) D 0– D 5 D6/CNTR0 D7/CNTR1 P00–P03 Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. P10–P13 Open. Connect to VSS. P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. SIN pin is not selected. “0” is set to output latch. “0” is set to output latch. N-channel open-drain is selected for the output structure. Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG0=0, MR0=1). 2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution. In order to start oscillation, setting the main clock f(XIN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing wait time by software.) Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN) (MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of software, and then set the main clock (f(XIN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, XIN pin is fixed to “H”. When an external clock is used, insert a 1 kΩ resistor to XIN pin in series for limits of current. 4: Be sure to select the output structure of ports D0–D5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open. 6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on wake-up control register K1, set the unused 1-bit to “H” input (turn pull-up transistor ON and open) or “L” input (connect to VSS, or open and set the output latch to “0”). 7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON and open. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-8 HARDWARE 4519 Group PORT BLOCK DIAGRAM PORT BLOCK DIAGRAMS Skip decision Register Y Decoder SZD instruction (Note 3) FR1i (Note 1) S SD instruction RD instruction RQ D0—D3 (Note 2) (Note 1) CLD instruction Skip decision Register Y Decoder SZD instruction FR20 (Note 1) S SD instruction RD instruction RQ D4 (Note 1) (Note 2) CLD instruction Skip decision Register Y Decoder SZD instruction FR21 (Note 1) S SD instruction RD instruction RQ D5 (Note 1) (Note 2) CLD instruction Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. Port block diagram (1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-9 HARDWARE 4519 Group PORT BLOCK DIAGRAM Register Y Decoder SZD instruction CLD instruction Skip decision FR22 S W60 RQ W23 1/2 1/2 0 1 0 1 (Note 1) D6/CNTR0 (Note 2) SD instruction RD instruction Timer 1 underflow signal Timer 2 underflow signal W62 Clock (input) for timer 1 event count or period measurement signal input 0 1 W10 W11 W50 W51 Register Y Decoder SZD instruction CLD instruction Skip decision FR23 S W43 RQ PWMOD W63 0 0 1 (Note 1) D7/CNTR1 (Note 2) SD instruction RD instruction Clock (input) for timer 3 event count 1 W30 W31 Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (2) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-10 HARDWARE 4519 Group PORT BLOCK DIAGRAM (Note 3) IAP0 instruction Register A Aj FR00 Aj OP0A instruction K11 Key-on wakeup 0 1 Pull-up transistor PU0j (Note 3) (Note 1) P00, P01(Note 2) (Note 1) D TQ K10 Level detection circuit Edge detection circuit (Note 4) IAP0 instruction Register A Ak 0 1 K00 FR01 Ak OP0A instruction K13 Key-on wakeup 0 1 Pull-up transistor PU0k (Note 4) (Note 1) P02, P03(Note 2) (Note 1) D TQ K12 Level detection circuit Edge detection circuit (Note 3) IAP1 instruction Register A Aj 0 1 K01 FR02 Aj OP1A instruction Key-on wakeup D TQ Pull-up transistor PU1j (Note 3) (Note 1) P10, P11(Note 2) (Note 1) Level detection circuit K02 (Note 4) IAP1 instruction Register A Ak FR03 Ak OP1A instruction Key-on wakeup D TQ Pull-up transistor PU1k (Note 4) (Note 1) P12, P13(Note 2) (Note 1) Level detection circuit K03 Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Port block diagram (3) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-11 HARDWARE 4519 Group PORT BLOCK DIAGRAM Register A A0 IAP2 instruction (Note 1) J12 J13 P20/SCK (Note 2) A0 OP2A instruction DQ T Synchronous clock (output) for serial data transfer Synchronous clock (input) for serial data transfer J10 J11 Register A A1 IAP2 instruction (Note 1) P21/SOUT (Note 2) J10 A1 OP2A instruction DQ T 0 1 Serial data output Register A A2 IAP2 instruction (Note 1) P22/SIN (Note 2) A2 OP2A instruction DQ T J11 Serial data input This symbol represents a parasitic diode on the port. Notes 1: 2: Applied potential to these ports must be VDD or less. Port block diagram (4) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-12 HARDWARE 4519 Group PORT BLOCK DIAGRAM Register A A0 IAP3 instruction (Note 1) P30/INT0 (Note 2) A0 OP3A instruction DQ T (Note 3) External 0 interrupt circuit External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input Period measurement circuit input Register A A1 IAP3 instruction (Note 1) P31/INT1 (Note 2) A1 OP3A instruction DQ T (Note 3) External 1 interrupt circuit External 1 interrupt Key-on wakeup input Timer 3 count start synchronous circuit input Register A A2 IAP3 instruction (Note 1) P32 (Note 2) A2 OP3A instruction DQ T Register A A3 IAP3 instruction (Note 1) P33 (Note 2) A3 OP3A instruction DQ T Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the external interrupt circuit structure. Port block diagram (5) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-13 HARDWARE 4519 Group PORT BLOCK DIAGRAM (Note 3) Register A Ai IAP4 instruction (Note 1) Q23 Ai OP4A instruction DQ T Q1 Decoder Analog input P40/AIN4–P43/AIN7 (Note 2) (Note 3) Register A Ai IAP5 instruction (Note 3) FR3i (Note 1) Ai OP5A instruction D T Q P50–P53 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. Port block diagram (6) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-14 HARDWARE 4519 Group PORT BLOCK DIAGRAM (Note 3) Register A Aj (Note 1) Q2j (Note 3) Aj OP6A instruction DQ T Q1 Decoder Analog input P60/AIN0, P61/AIN1 (Note 2) IAP6 instruction (Note 4) Register A Ak IAP6 instruction (Note 1) Q22 Ak OP6A instruction DQ T Q1 Decoder Analog input P62/AIN2, P63/AIN3 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Port block diagram (7) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-15 HARDWARE 4519 Group PORT BLOCK DIAGRAM (Note 1) P30/INT0 I12 Falling 0 1 Rising One-sided edge detection circuit I11 0 EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit 1 I13 K21 0 External 0 interrupt Period measurement circuit input Timer 1 count start synchronous circuit Key-on wakeup 1 Skip decision (SNZI0 instruction) (Note 1) P31/INT1 I22 Falling 0 1 Rising One-sided edge detection circuit I21 0 EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction) 1 External 1 interrupt I23 Timer 3 count start synchronous circuit K23 0 Key-on wakeup 1 This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Port block diagram (8) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-16 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS FUNCTION BLOCK OPERATIONS CPU (CY) (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. (M(DP)) Addition (A) ALU (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. Fig. 1 AMC instruction execution example SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed. Also, when the TABP p instruction is executed, the high-order 2 bits of the reference data in ROM is stored to the low-order 2 bits of register D, and the contents of the high-order 1 bit of register D is “0”. (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig. 3 Registers A, B and register E TABP p instruction Specifying address ROM 8 4 0 p6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) High-order 2 bits Register D (3) High-order 1 bit of register D is “0”. Immediate field value p The contents of The contents of register D register A Fig. 4 TABP p instruction execution example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-17 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. (PC) ← (SK0) (SP) ← 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-18 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H ( most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig. 8 Data pointer (DP) structure Specifying bit position Set D3 D2 D1 D0 0 0 0 1 1 Port D output latch Register Y (4) Fig. 9 SD instruction execution example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-19 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34519M8/E8. Table 1 ROM size and pages Part number M34519M6 M34519M8/E8 ROM (PROM) size (✕ 10 bits) 6144 words 8192 words Pages 48 (0 to 47) 64 (0 to 63) 987 000016 007F16 008016 00FF16 010016 017F16 018016 654 321 0 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction. 1FFF16 Page 63 Fig. 10 ROM map of M34519M8/E8 9 008016 008216 008416 008616 008816 008A16 008C16 008E16 876543210 External 0 interrupt address External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 4 interrupt address A/D interrupt address Serial I/O interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-20 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). Table 2 shows the RAM size. Figure 12 shows the RAM map. • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Table 2 RAM size Part number M34519M6 M34519M8/E8 RAM size 384 words ✕ 4 bits (1536 bits) RAM 384 words ✕ 4 bits (1536 bits) Register Z Register X 0 1 0 ... 6 7 23 1 ... ... 15 0 ... ... 567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 384 words M34519M8/E8 Z=0, X=0 to 15 Z=1, X=0 to 7 Fig. 12 RAM map Register Y Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-21 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 8 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt Serial I/O interrupt Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A/D conversion Completion of serial I/O transmit/receive (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt Serial I/O interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T4F ADF SIOF Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Interrupt enable bit V10 V11 V12 V13 V20 V21 V22 V23 (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “ 1. ” E ach interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0 Skip instruction Invalid Valid Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-22 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). • Program counter (PC) ............................................................... Each interrupt address • Stack register (SK) The address of main routine to be .................................................................................................... executed when returning • Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 • Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Activated condition INT0 pin interrupt waveform input Request flag Enable bit (state retained) Enable flag EXF0 V10 Address 0 in page 1 Address 2 in page 1 INT1 pin interrupt waveform input EXF1 V11 Main routine Interrupt service routine Interrupt occurs Timer 1 underflow T1F V12 Address 4 in page 1 Timer 2 underflow Timer 3 underflow T2F V13 Address 6 in page 1 • • • • T3F V20 Address 8 in page 1 Address A in page 1 EI R TI Interrupt is enabled Timer 4 underflow A/D conversion completed T4F V21 ADF V22 Address C in page 1 Serial I/O transmit/ receive completed SIOF V23 INTE Address E in page 1 : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing Fig. 15 Interrupt system diagram Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-23 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. • Interrupt control register V2 The timer 3, timer 4, A/D and serial I/O interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) Note: “R” represents read enabled, and “W” represents write enabled. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V1 0–V1 3, V20–V23 ), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-24 4519 Group Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z T3 T1 T1 T1 T2 T3 T2 T3 T2 T3 T1 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) The program starts from the interrupt address. Fig. 16 Interrupt sequence q When an interrupt request flag is set after its interrupt is enabled (Note 1) 1 machine cycle T1 T2 System clock (STCK) EI instruction execution cycle Interrupt enable flag (INTE) INT0,INT1 External interrupt EXF0,EXF1 Timer 1, Timer 2, Timer 3, Timer 4, A/D and Serial I/O interrupts T1F,T2F,T3F,T4F, ADF,SIOF Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. HARDWARE F UNCTION BLOCK OPERATIONS 1-25 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS EXTERNAL INTERRUPTS The 4519 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P30/INT0 Activated condition When the next waveform is input to P30/INT0 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms External 1 interrupt P31/INT1 When the next waveform is input to P31/INT1 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms I21 I22 Valid waveform selection bit I11 I12 (Note 1) P30/INT0 I12 Falling 0 1 Rising One-sided edge detection circuit I11 0 EXF0 Both edges detection circuit 1 I13 (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit Skip decision (SNZI0 instruction) K21 0 External 0 interrupt Period measurement circuit input Timer 1 count start synchronous circuit Key-on wakeup 1 (Note 1) P31/INT1 I22 Falling 0 1 Rising One-sided edge detection circuit I21 0 EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction) 1 External 1 interrupt I23 Timer 3 count start synchronous circuit K23 0 Key-on wakeup 1 This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Fig. 17 External interrupt circuit structure Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-26 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. ➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I2. ➂ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-27 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit 0 1 0 1 0 1 0 1 • Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. at reset : 00002 at RAM back-up : state retained R/W TAI1/TI1A INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I12 Interrupt valid waveform for INT0 pin/ return level selection bit I11 I10 INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAI2/TI2A INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) I21 I20 INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-28 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (4) Notes on External 0 interrupt ➀ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18 ➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18 ➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18 ➂). ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the P3 0 /INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂). ••• ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT0 pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. • When the input of INT0 pin is disabled (register I13 = “0”), set the key-on wakeup function to be invalid (register K20 = “0”) before system enters to the RAM back-up mode. (refer to Figure 19➀). ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3 ••• LA 0 TK2A DI EPOF POF ; (✕✕✕02) ; Input of INT0 key-on wakeup invalid .. ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2 ••• ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-29 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (5) Notes on External 1 interrupt ➀ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. • Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 21➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21➂). ➂ Note on bit 2 of register I2 When the interrupt valid waveform of the P3 1 /INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. • Depending on the input state of the P3 1/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 23➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23➂). ••• ••• LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT1 pin input is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 21 External 1 interrupt program example-1 ➁ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. • When the input of INT1 pin is disabled (register I23 = “0”), set the key-on wakeup function to be invalid (register K22 = “0”) before system enters to the RAM back-up mode. (refer to Figure 22➀). ✕ : these bits are not used here. Fig. 23 External 1 interrupt program example-3 ••• LA 0 TK2A DI EPOF POF ; (✕0✕✕2) ; Input of INT1 key-on wakeup invalid .. ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 22 External 1 interrupt program example-2 ••• ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-30 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS TIMERS The 4519 Group has the following timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. FF16 n : Counter initial value Count starts n Reload Reload The contents of counter 1st underflow 2nd underflow 0016 Time n+1 count Timer interrupt “1” “0” request flag An interrupt occurs or a skip instruction is executed. n+1 count Fig. 24 Auto-reload function The 4519 Group timer consists of the following circuits. • Prescaler : 8-bit programmable timer • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Timer 4 : 8-bit programmable timer • Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, and 4 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, and 4 can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-31 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) (period/pulse width measurement function) Timer 2 8-bit programmable binary down counter • System clock (STCK) • Prescaler output (ORCLK) • Timer 1 underflow (T1UDF) • PWM output (PWMOUT) Timer 3 8-bit programmable binary down counter (link to INT1 input) • PWM output (PWMOUT) • Prescaler output (ORCLK) • Timer 2 underflow (T2UDF) • CNTR1 input Timer 4 8-bit programmable binary down counter Watchdog timer • XIN input • Prescaler output (ORCLK) 65534 1 to 256 • Timer 2, 3 count source • CNTR1 output • Timer 4 interrupt • System reset (count twice) • WDF flag decision W4 1 to 256 • CNTR1 output control • Timer 3 interrupt W3 1 to 256 • Timer 3 count source • CNTR0 output • Timer 2 interrupt W2 Count source • Instruction clock (INSTCK) • Instruction clock (INSTCK) • Prescaler output (ORCLK) • XIN input • CNTR0 input Frequency dividing ratio 1 to 256 1 to 256 Use of output signal • Timer 1, 2, 3, amd 4 count sources • Timer 2 count source • CNTR0 output • Timer 1 interrupt Control register PA W1 W2 W5 (PWM output function) • Instruction clock (INSTCK) 16-bit fixed dividing frequency Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-32 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Division circuit Divided by 8 On-chip oscillator Ceramic resonance 1 Multiplexer (CMCK, CRCK, CYCK) (Note 1) 0 MR0 Divided by 4 Divided by 2 MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) XIN RC oscillation Quartz-crystal oscillation PA0 Prescaler (8) ORCLK Reload register RPS (8) (TPSAB) (TABPS) W60 0 1 1 (TPSAB) (TPSAB) (TABPS) Register B Register A Port D6 output W23 0 1/2 1/2 00 01 T1UDF T2UDF W51, W50 On-chip oscillator W62 0 1 I12 1/16 10 11 W52 D6/CNTR0 One-period generation circuit P30/INT0 I13 I10 W13 0 1 One-sided edge detection circuit I11 0 (Note 2) 1 Both edges detection circuit SQ R W52 1 0 I10 1 0 T1UDF W11, W10 (Note 3) INSTCK ORCLK XIN 00 01 10 11 W12 W21, W20 00 01 10 11 W22 (TAB2) (TAB1) W52 1 Timer 1 (8) Reload register R1 (8) (T1AB) (TR1AB) (T1AB) (T1AB) (TAB1) 0 T1F Timer 1 interrupt Register B Register A STCK ORCLK T1UDF PWMOUT Timer 1 underflow signal ( T1UDF) Timer 2 (8) T2F Timer 2 interrupt Reload register R2 (8) (T2AB) (T2AB) (T2AB) (TAB2) Register B Register A TR1AB: This instruction is used to transfer the contents of register A and register B to only reload register R1. PWMOUT: PWM output signal (from timer 4 output unit) Timer 2 underflow signal (T2UDF) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When CYCK instruction is executed, quartz-crystal oscillator is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: XIN cannot be used for the count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. Fig. 25 Timer structure (1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-33 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS I2 2 P31/INT1 I2 3 I2 0 W33 0 1 One-sided edge detection circuit I21 0 1 Both edges detection circuit (Note 4) SQ R I20 1 0 T3UDF W31, W30 00 01 10 11 W32 1 W43 0 1 PWMOD W32 (TAB3) PWMOUT ORCLK T2UDF D7/CNTR1 W63 0 Timer 3 (8) Reload register R3 (8) (T3AB) (TR3AB) (T3AB) (T3AB) (TAB3) T3F Timer 3 interrupt Register B Register A Timer 3 underflow signal (T3UDF) Port D7 output T3UDF W61 QD RT Register B Register A (T4HAB) (Note 3) XIN ORCLK 1/2 W40 0 1 W41 Reload register R4H (8) Reload control circuit W42 1 0 (T4R4L) TQ R T4F PWMOUT W43 Timer 4 interrupt Timer 4 (8) “H” interval expansion Reload register R4L (8) (T4AB) (TAB4) (T4AB) (T4AB) (TAB4) Register B Register A Watchdog timer 1 - - - - - - - - - - - - - - 16 INSTCK (Note 5) S Q WDF1 WRST instruction RESET signal R S Q (Note 7) WEF D Q Watchdog reset signal DWDT instruction R + WRST instruction (Note 6) T R RESET signal TR3AB: This instruction is used to transfer the contents of Notes 3: XIN cannot be used for the count source when bit 1 (MR1) of register A and register B to only reload register R3. register MR is set to “1” and f(XIN) oscillation is stopped. T4R4L: This instruction is used to transfer the contents of 4: Timer 3 count start synchronous circuit is set by the valid edge reload register R4L to timer 4. of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. INSTCK: Instruction clock (system clock divided by 3) 5: Flag WDF1 is cleared to “0” and the next instruction is skipped ORCLK: Prescaler output (instruction clock divided by 1 to 256) Data is set automatically from each reload register when timer underflows (auto-reload function). when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 6: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 7: The WEF flag is set to “1” at system reset or RAM back-up mode. Fig. 26 Timer structure (2) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-34 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state initialized) Operating R/W TAW1/TW1A at RAM back-up : 02 W TPAA Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W11 W10 Count source 0 Instruction clock (INSTCK) 0 0 Prescaler output (ORCLK) 1 1 XIN input 0 1 CNTR0 input 1 R/W TAW2/TW2A Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output signal selection bit (Note 2) Timer 2 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating W21 W20 Count source 0 System clock (STCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 1 underflow signal (T1UDF) 0 1 PWM signal (PWMOUT) 1 Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAW3/TW3A Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating W31 W30 Count source 0 PWM signal (PWMOUT) 0 0 Prescaler output (ORCLK) 1 1 Timer 2 underflow signal (T2UDF) 0 1 CNTR1 input 1 Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-35 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Timer control register W4 W43 W42 W41 W40 D7/CNTR1 pin function selection bit PWM signal “H” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAW4/TW4A D7 (I/O) / CNTR1 (input) CNTR1 (I/O) / D7 (input) PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2 Timer control register W5 W53 W52 W51 Signal for period measurement selection bits W50 Not used Period measurement circuit control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAW5/TW5A This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR0 pin input INT0 pin input Not available R/W TAW6/TW6A W51 W50 0 0 0 1 1 0 1 1 Timer control register W6 W63 W62 W61 W60 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input) Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-36 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (1) Timer control registers • Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. • Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W3 Register W3 controls the selection of the count operation and count source of timer 3 count auto-stop circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. • Timer control register W4 Register W4 controls the D7/CNTR1 output, the expansion of “H” interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. • Timer control register W5 Register W5 controls the period measurement circuit and target signal for period measurement. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. • Timer control register W6 Register W6 controls the count edges of CNTR0 pin and CNTR1 pin, selection of CNTR1 output auto-control circuit and the D6/ CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, and 4 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to “0” and setting bit 0 of register W6 to “1”. The period measurement circuit starts operating by setting bit 2 of register W5 to “1” and timer 1 is used to count the one-period of the target signal for the period measurement. In this time, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-37 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to “1” and setting bit 0 of register W6 to “1”. (6) Timer 4 (interrupt function) Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; ➀ set data in timer 4 ➁ set count source by bit 0 of register W4, and ➂ set the bit 1 of register W4 to “1.” When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4L, and count continues (auto-reload function). The PWM signal generated by timer 4 can be output from CNTR1 pin by setting bit 3 of the timer control register W4 to “1”. Timer 4 can control the PWM output to CNTR1 pin with timer 3 by setting bit 1 of the timer control register W6 to “1”. (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; ➀ set data in timer 3 ➁ set count source by bits 0 and 1 of register W3, and ➂ set the bit 2 of register W3 to “1.” When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to “1.” Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to “1.” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-38 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (7) Period measurement function (Timer 1, period measurement circuit) Timer 1 has the period measurement circuit which performs timer count operation synchronizing with the one cycle of the signal divided by 16 of the on-chip oscillator, D6/CNTR0 pin input, or P30/ INT0 pin input (one cycle, “H”, or “L” pulse width at the case of a P30/INT0 pin input). When the target signal for period measurement is set by bits 0 and 1 of register W5, a period measurement circuit is started by setting the bit 2 of register W5 to “1”. Then, if a XIN input is set as the count source of a timer 1 and the bit 2 of register W1 is set to “1”, timer 1 starts operation. Timer 1 starts operation synchronizing with the falling edge of the target signal for period measurement, and stops count operation synchronizing with the next falling edge (one-period generation circuit). When selecting D6/CNTR0 pin input as target signal for period measurement, the period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register W6 to “1”. When selecting P3 0/INT0 pin input as target signal for period measurement, period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register I1 to “1”. A timer 1 interrupt request flag (T1F) is set to “1” after completing measurement operation. When a period measurement circuit is set to be operating, timer 1 interrupt request flag (T1F) is not set by timer 1 underflow signal, but turns into a flag which detects the completion of period measurement. In addition, a timer 1 underflow signal can be used as timer 2 count source. Once period measurement operation is completed, even if period measurement valid edge is input next, timer 1 is in a stop state and measurement data is held. When a period measurement circuit is used again, stop a period measurement circuit at once by setting the bit 2 of register W5 to “0”, and change a period measurement circuit into a state of operation by setting the bit 2 of register W5 to “1” again. When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 27➀) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 27➁). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 27➂). ••• LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP ; (✕0✕✕2) ; The SNZT1 instruction is valid ........ ➀ ; (✕0✕✕2) ; Period measurement circuit stop ........................................................... ➁ ; The SNZT1 instruction is executed (T1F flag cleared) ........................................................... ➂ ✕ : these bits are not used here. Fig. 27 Period measurement circuit program example When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The X IN input is recommended as timer 1 count source at the time of period measurement circuit use.) (8) Pulse width measurement function (timer 1, period measurement circuit) A period measurement circuit can measure “H” pulse width (from rising to falling) or “L” pulse width (from falling to rising) of P30/ INT0 pin input (pulse width measurement function) when the following is set; • Set the bit 0 of register W5 to “0”, and set a bit 1 to “1” (target for period measurement circuit: 30/INT0 pin input). • Set the bit 1 of register I1 to “1” (INT0 pin edge detection circuit: both edges detection) The measurement pulse width (“H” or “L”) is decided by the period measurement circuit and the P30/INT0 pin input level at the start time of timer operation. At the time of the start of a period measurement circuit and timer operation, “L” pulse width (from falling to rising) when the input level of P30/INT0 pin is “H” or “H” pulse width (from rising to falling) when its level is “L” is measured. When the input of P30/INT0 pin is selected as the target for measurement, set the bit 3 of register I1 to “1”, and set the input of INT0 pin to be enabled. ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-39 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (9) Count start synchronization circuit (timer 1, timer 3) Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to “1” and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (11) Timer input/output pin (D6/CNTR0 pin, D7/CNTR1 pin) CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. The D6/CNTR0 pin function can be selected by bit 0 of register W6. The selection of D7/CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising or falling waveform of CNTR0 input. The count edge is selected by the bit 2 of register W6. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising or falling waveform of CNTR1 input. The count edge is selected by the bit 3 of register W6. (12) PWM output function (D7/CNTR1, timer 3, timer 4) When bit 3 of register W4 is set to “1”, timer 4 reloads data from reload register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R4L, and the “H” interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to “1” at this time, the interval (PWM signal “H” interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R4H. When bit 1 of register W6 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to “0”), this function is canceled. Even when bit 1 of a register W4 is cleared to “0” in the “H” interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. At CNTR1 output vaild, if a timing of timer 4 underflow overlaps with a timing to stop timer 4, a hazard may be generated in a CNTR1 output waveform. Please review sufficiently. (10) Count auto-stop circuit (timer 1, timer 3) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to “1”. It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-40 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (13) Timer interrupt request flags (T1F, T2F, T3F, T4F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. The timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 28➀) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 28➁). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 28➂). ••• (14) Precautions Note the following for the use of timers. • Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. • Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source. • Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. • Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data. • Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. • Timer 4 At CNTR1 output vaild, if a timing of timer 4 underflow overlaps with a timing to stop timer 4, a hazard may be generated in a CNTR1 output waveform. Please review sufficiently. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H. • Period measurement function When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP ; (✕0✕✕2) ; The SNZT1 instruction is valid ........ ➀ ; (✕0✕✕2) ; Period measurement circuit stop ........................................................... ➁ ; The SNZT1 instruction is executed (T1F flag cleared) ........................................................... ➂ ✕ : these bits are not used here. Fig. 28 Period measurement circuit program example While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The X IN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled. ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-41 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS q CNTR1 output: invalid (W43 = “0”) Timer 4 count source 0316 (R4L) (R4L) (R4L) (R4L) (R4L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal (output invalid) Timer 4 start PWM signal “L” fixed q CNTR1 output: valid (W43 = “1”) PWM signal “H” interval extension function: invalid (W42 = “0”) Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal 3 clock Timer 4 start PWM period 7 clock 3 clock PWM period 7 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 q CNTR1 output: valid (W43 = “1”) PWM signal “H” interval extension function: valid (W42 = “1”) (Note) Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H. Fig. 29 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-42 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS CNTR1 output auto-control circuit by timer 3 is selected. q CNTR1 output: valid (W43 = “1”) CNTR1 output auto-control circuit selected (W61 = “1”) PWM signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start q CNTR1 output auto-control function PWM signal Timer 3 underflow signal Timer 3 start Register W61 ➀ ➁ Timer 3 stop ➂ CNTR1 output CNTR1 output start CNTR1 output stop ➀ ➁ ➂ When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. Fig. 30 CNTR1 output auto-control function by timer 3 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-43 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS ●Waveform extension function of CNTR1 output “H” interval: Invalid (W42 = “0”), CNTR1 output: valid (W43 = “1”), Count source: XIN input selected (W40 = “0”), Reload register R4L: “0316” Reload register R4H: “0216” Timer 4 count start timing Machine cycle Mi Mi+1 Mi+2 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal TW4A instruction execution cycle (W41) ← 1 0316 (R4L) 0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4H) (R4L) Timer 4 count start timing Timer 4 count stop timing Machine cycle Mi Mi+1 Mi+2 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal TW4A instruction execution cycle (W41) ← 0 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L) 0216 (R4H) (Note 1) Timer 4 count stop timing Notes 1: At CNTR1 output vaild, if a timing of timer 4 underflow overlaps with a timing to stop timer 4, a hazard may be generated in a CNTR1 output waveform. Please review sufficiently. 2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output. Fig. 31 Timer 4 count start/stop timing Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-44 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “ 000016, ” t he next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “ 0 ” a nd the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag ➁ ➁ 65534 count (Note) WDF2 flag ➃ RESET pin output ➀ Reset released ➂ WRST instruction executed (skip executed) ➄ System reset ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock. Fig. 32 Watchdog timer function Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-45 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 33). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 34). The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. WRST ••• ; WDF1 flag cleared DI DWDT WRST ••• ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig. 33 Program example to start/stop watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ↓ Oscillation stop Fig. 34 Program example to enter the mode when using the watchdog timer ••• ••• ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-46 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS A/D CONVERTER (Comparator) The 4519 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Table 11 A/D converter characteristics Characteristics Parameter Conversion format Successive comparison method Resolution 10 bits Relative accuracy Linearity error: ±2LSB (2.7 V ≤ VDD ≤ 5.5V) Differential non-linearity error: ±0.9LSB (2.2 V ≤ VDD ≤ 5.5V) Conversion speed 31 µs (f(X IN ) = 6 MHz, STCK = f(XIN) (XIN through-mode), ADCK = INSTCK/6) Analog input pin 8 Register B (4) Register A (4) 4 4 IAP4 (P40–P43) IAP6 (P60–P63) OP4A (P40–P43) OP6A (P60–P63) TAQ1 TQ1A 4 TAQ2 TQ2A 4 TAQ3 TQ3A 2 TALA Division circuit Divided by 48 4 4 4 Q13 Q12 Q11 Q10 Q23 Q22 Q21 Q20 Q33 Q32 Q31 Q30 8 TABAD 8 TADAB Q31, Q30 11 10 01 00 Q32 3 Instruction clock On-chip oscillator 1 clock 0 Divided by 24 Divided by 12 Divided by 6 A/D conversion clock (ADCK) Q13 0 8-channel multi-plexed analog switch A/D control circuit 1 P60/AIN0 P61/AIN1 P62/AIN2 P63/AIN3 P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7 ADF (1) A/D interrupt 1 Comparator 0 Q13 DAC operation signal Successive comparison register (AD) (10) 10 0 1 Q13 10 8 0 1 1 Q13 8 DA converter (Note 1) 8 VDD 8 VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. Fig. 35 A/D conversion circuit structure Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-47 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Table 12 A/D control registers A/D control register Q1 Q13 A/D operation mode selection bit at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 at RAM back-up : state retained R/W TAQ1/TQ1A Analog input pins Q12 Q11 Analog input pin selection bits Q10 A/D control register Q2 Q23 Q22 Q21 Q20 P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7 pin function selection bit P62/AIN2, P63/AIN3 pin function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAQ2/TQ2A P40, P41, P42, P43 AIN4, AIN5, AIN6, AIN7 P62, P63 AIN2, AIN3 P61 AIN1 P60 AIN0 A/D control register Q3 Q33 Q32 Q31 A/D converter operation clock division ratio selection bits Not used A/D converter operation clock selection bit 0 1 0 1 Q31 0 0 1 1 at reset : 00002 at RAM back-up : state retained R/W TAQ3/TQ3A This bit has no function, but read/write is enabled. Q30 Instruction clock (INSTCK) On-chip oscillator (f(RING)) Division ratio Q30 0 Frequency divided by 6 1 Frequency divided by 12 0 Frequency divided by 24 1 Frequency divided by 48 Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-48 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (1) A/D control register • A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. • A/D control register Q2 Register Q2 controls the selection of P4 0/A IN4–P43/A IN7, P60/ AIN0–P63/AIN3. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. • A/D control register Q3 Register Q3 controls the selection of A /D converter operation clock. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A. (4) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “00016.” ➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage V ref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4519 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 2 machine cycles + A/D conversion clock (31 µs when f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/ 6) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 36). (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in D/A converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = V DD ✕n 1024 n: The value of register AD (n = 0 to 1023) Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼1: 1st comparison result ✼3: 3rd comparison result ✼9: 9th comparison result Change of successive comparison register AD ------------- Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4 ○ ○ ○ ○ 1 ✼1 ✼1 0 1 ✼2 0 0 1 ----------------------------------------------------------------- 0 0 0 0 0 0 0 0 0 --------- ± ± ± ± ± 8 VDD 1024 A/D conversion result ------------- ✼1 ✼2 ✼3 ------------- ----- ✼8 ✼9 ✼A 2 ✼2: 2nd comparison result ✼8: 8th comparison result ✼A: 10th comparison result Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-49 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (7) A/D conversion timing chart Figure 36 shows the A/D conversion timing chart. ADST instruction 2 machine cycles + 10/f(ADCK) A/D conversion completion flag (ADF) DAC operation signal Fig. 36 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P60/AIN0 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Instruction clock/6 is selected as the A/D converter operation clock. ➀ Select the AIN0 pin function with the bit 0 of the register Q2. Select the A IN0 p in function and A/D conversion mode with the register Q1. Also, the instruction clock divided by 6 is selected with the register Q3. (refer to Figure 37) ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). (Bit 3) (Bit 0) ✕ ✕ ✕ 1 A/D control register Q2 A IN0 p in function selected (Bit 3) (Bit 0) 0 0 0 0 A/D control register Q1 A IN0 p in selected A/D conversion mode (Bit 3) (Bit 0) ✕ 0 0 0 A/D control register Q3 Frequency divided by 6 Instruction clock ✕ : Set an arbitrary value. Fig. 37 Setting registers Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-50 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” Below, the operation at comparator mode is described. (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operating. The comparator stops 2 machine cycles + A/D conversion clock f(ADCK) 1 clock after it has started (4 µs at f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/6). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” (10) Comparator register In comparator mode, the built-in D/A comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in D/A converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 ✕n (13) Notes for the use of A/D conversion • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” • Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. n: The value of register AD (n = 0 to 255) (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. ADST instruction 2 machine cycles + 1/f(ADCK) Comparison result store flag(ADF) DAC operation signal Comparator operation completed. (The value of ADF is determined) Fig. 38 Comparator operation timing chart → 1-51 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (14) Definition of A/D converter accuracy The A/D conversion accuracy is defined below (refer to Figure 39). • Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. ➃ Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. • Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022) • 1LSB at relative accuracy → VFST–V0T (V) 1022 VDD 1024 • 1LSB at absolute accuracy → (V) Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error = Linearity error = c a n+1 n b –a a [LSB] b a [LSB] Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn and actual Vn Ideal line of A/D conversion between V0–V1022 1 0 V0 V1 Vn Vn+1 V1022 Analog voltage VDD Zero transition voltage (V0T) Fig. 39 Definition of A/D conversion accuracy Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-52 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS SERIAL I/O The 4519 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O control register J1 • serial I/O transmit/receive completion flag (SIOF) • serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. Table 14 Serial I/O pins Pin P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN) Note: Even when the SCK, S OUT, SIN pin functions are used, the input of P20, P21, P22 are valid. 1/8 1/4 INSTCK SCK 1/2 J13J12 00 01 10 11 Synchronous circuit Serial I/O counter (3) SIOF Serial I/O interrupt P20/SCK Q S R SST instruction Internal reset signal P21/SOUT SOUT P22/SIN SIN MSB Serial I/O register (8) LSB TABSI J11 J10 TSIAB TABSI Register B (4) Register A (4) Fig. 40 Serial I/O structure Table 15 Serial I/O control register Serial I/O control register J1 at reset : 00002 at RAM back-up : state retained R/W TAJ1/TJ1A J13 J12 J11 J10 J13 J12 Synchronous clock 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 J11 J10 Port function 0 P20, P21,P22 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, P22 selected/P20, P21, SIN not selected 0 0 SCK, P21, SIN selected/P20, SOUT, P22 not selected 1 1 SCK, SOUT, SIN selected/P20, P21,P22 not selected 1 Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-53 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS At transmit (D7–D0: transfer data) SIN pin At receive SOUT pin Serial I/O register (SI) D7 D6 D5 D4 D3 D2 D1 D0 SOUT pin SIN pin Serial I/O register (SI) * ** ** ** * Transfer data set D7 D6 D5 D4 D3 D2 D1 D0 * ** ** ** * D0 *D 7 D6 D5 D4 D3 D2 D1 Transfer start ** ** ** * ****** * *D 7 D6 D5 D4 D3 D2 D1 D0 * ** ** ** * Fig. 41 Serial I/O register state when transferring Transfer complete D7 D6 D5 D4 D3 D2 D1 D0 (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, do not select the SCK pin. (3) Serial I/O start instruction (SST) When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started. (4) Serial I/O control register J1 Register J1 controls the synchronous clock, P2 0/S CK, P21/S OUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. (2) Serial I/O transmit/receive completion flag (SIOF) Serial I/O transmit/receive completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-54 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (5) How to use serial I/O Figure 42 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the wiring between each pin with a resistor. Figure 42 shows the data transfer timing and Table 16 shows the data transfer sequence. Master (clock control) Slave (external clock) D3 SCK SOUT SI N SRDY signal D3 SCK SIN SOUT (Bit 3) 0 0 1 (Bit 0) 1 (Bit 3) Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN Instruction clock/8 selected as synchronous clock (Bit 0) 1 1 1 Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN External clock selected as synchronous clock 1 (Bit 3) 0 ✕ ✕ (Bit 0) ✕ Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid) (Bit 3) 0 ✕ ✕ (Bit 0) ✕ Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid) ✕: Set an arbitrary value. Fig. 42 Serial I/O connection example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-55 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Master SOUT SIN SST instruction M7’ S7 ’ M0 S0 M1 S1 M2 S2 M3 S3 M4 S4 M5 S5 M6 S6 M7 S7 SCK Slave SST instruction SRDY signal SOUT SIN S7 ’ M7’ S0 M0 S1 M1 S2 M2 S3 M3 S4 M4 S5 M5 S6 M6 S7 M7 M0–M7: Contents of master serial I/O register S0–S7: Contents of slave serial I/O register Rising of SCK: Serial input Falling of SCK: Serial output Fig. 43 Timing of serial I/O data transfer Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-56 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS Table 16 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] • Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 42. TJ1A and TV2A instructions • S etting the port received the reception enable signal (SRDY) to the input mode. (Port D3 is used in this example) SD instruction * [Transmission enable state] • Storing transmission data to serial I/O register SI. TSIAB instruction [Initial setting] • Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 42. TJ1A and TV2A instructions • Setting the port transmitted the reception enable signal (SRDY) and outputting “H” level (reception impossible). (Port D3 is used in this example) SD instruction *[Reception enable state] • The SIOF flag is cleared to “0.” SST instruction • “L” level (reception possible) is output from port D3. RD instruction [Transmission] •Check port D3 is “L” level. SZD instruction •Serial transfer starts. SST instruction •Check transmission completes. SNZSI instruction •Wait (timing when continuously transferring) • Check reception completes. SNZSI instruction • “H” level is output from port D3. SD instruction [Data processing] 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to “1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to “H.” [Reception] Slave (reception) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-57 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. f(RING) RESET On-chip oscillator (internal oscillator) is counted 120 to 144 times. Program starts (address 0 in page 0) Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed. Fig. 44 Reset release timing Reset input = On-chip oscillator (internal oscillator) is 1 machine cycle or more counted 120 to 144 times. 0.85VDD RESET 0.3VDD Program starts (address 0 in page 0) (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 45 RESET pin input waveform and reset operation Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-58 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (1) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V until the value of supply voltage reaches the minimum operating voltage must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. 100 µs or less VDD (Note 3) Pull-up transistor (Note 1) (Note 2) Power-on reset circuit output RESET pin Internal reset signal Power-on reset circuit (Note 1) SRST instruction Voltage drop detection circuit Watchdog reset signal WEF Internal reset signal Reset state Power-on Reset released Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 46 Structure of reset pin and its peripherals, and power-on reset operation Table 17 Port state at reset Name D0–D5 D6/CNTR0 D7/CNTR1 P00–P03 P10–P13 P20/SCK, P21/SOUT, P22/SIN P30/INT0, P31/INT1, P32, P33 P40/AIN4–P43/AIN7 P50–P53 P60/AIN0–P63/AIN3 Notes 1: Output latch is set to “1.” 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D0–D5 D6 D7 P00–P03 P10–P13 P20–P22 P30–P33 P40–P43 P50–P53 P60–P63 High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) State High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Notes 1, 2) High-impedance (Note 1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-59 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS (2) Internal state at reset Figure 47 and 48 show internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure are undefined, so set the initial value to them. • Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) .................................................................................................. 0 • Power down flag (P) ............................................................................................................. 0 • External 0 interrupt request flag (EXF0) .............................................................................. 0 • External 1 interrupt request flag (EXF1) .............................................................................. 0 • Interrupt control register V1 .................................................................................................. 0 000 • Interrupt control register V2 .................................................................................................. 0 000 • Interrupt control register I1 ................................................................................................... 0 000 • Interrupt control register I2 ................................................................................................... 0 000 • Timer 1 interrupt request flag (T1F) ..................................................................................... 0 • Timer 2 interrupt request flag (T2F) ..................................................................................... 0 • Timer 3 interrupt request flag (T3F) ..................................................................................... 0 • Timer 4 interrupt request flag (T4F) ..................................................................................... 0 • Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 • Watchdog timer enable flag (WEF) ...................................................................................... 1 • Timer control register PA ...................................................................................................... 0 • Timer control register W1 ..................................................................................................... 0 000 • Timer control register W2 ..................................................................................................... 0 000 • Timer control register W3 ..................................................................................................... 0 000 • Timer control register W4 ..................................................................................................... 0 000 • Timer control register W5 ..................................................................................................... 0 000 • Timer control register W6 ..................................................................................................... 0 000 • Clock control register MR ..................................................................................................... 1 111 • Clock control register RG ..................................................................................................... 0 • Serial I/O transmit/receive completion flag (SIOF) .............................................................. 0 • Serial I/O mode register J1 .................................................................................................. 0 000 ✕✕✕✕✕✕✕ • Serial I/O register SI ............................................................................................................. ✕ • A/D conversion completion flag (ADF) ................................................................................. 0 • A/D control register Q1 ......................................................................................................... 0 000 • A/D control register Q2 ......................................................................................................... 0 000 • A/D control register Q3 ......................................................................................................... 0 000 ✕ ✕✕✕✕✕✕✕✕ • Successive comparison register AD .................................................................................... ✕ ✕✕✕✕✕✕✕ • Comparator register .............................................................................................................. ✕ • Key-on wakeup control register K0 ...................................................................................... 0 000 • Key-on wakeup control register K1 ...................................................................................... 0 000 • Key-on wakeup control register K2 ...................................................................................... 0 000 • Pull-up control register PU0 ................................................................................................. 0 000 • Pull-up control register PU1 ................................................................................................. 0 000 0 0 0 0 0 0 0 0 (Interrupt disabled) (Interrupt disabled) (Interrupt disabled) (Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped) (Period measurement circuit stopped) (On-chip oscillator operating) (External clock selected, serial I/O port not selected) “✕ ” r epresents undefined. Fig. 47 Internal state at reset 1 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-60 HARDWARE 4519 Group F UNCTION BLOCK OPERATIONS • Port output structure control register FR0 ........................................................................... 0000 • Port output structure control register FR1 ........................................................................... 0000 • Port output structure control register FR2 ........................................................................... 0000 • Port output structure control register FR3 ........................................................................... 0000 • Carry flag (CY) ...................................................................................................................... 0 • Register A ............................................................................................................................. 0000 • Register B ............................................................................................................................. 0000 • Register D ............................................................................................................................. ✕✕✕ • Register E ............................................................................................................................. ✕✕✕✕✕✕✕✕ • Register X ............................................................................................................................. 0000 • Register Y ............................................................................................................................. 0000 • Register Z ............................................................................................................................. ✕✕ • Stack pointer (SP) ................................................................................................................ 111 • Operation source clock .......................................................... On-chip oscillator (operating) • Ceramic resonator circuit .............................................................................................. Stop • RC oscillation circuit ...................................................................................................... Stop • Quartz-crystal oscillation circuit .................................................................................... Stop “✕ ” r epresents undefined. Fig. 48 Internal state at reset 2 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-61 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. VDCE VRST + VRST - – + Voltage drop detection circuit Reset signal Voltage drop detection circuit Fig. 49 Voltage drop detection reset circuit VRST (reset release voltage) VRST -(reset voltage) + VDD Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 120 to 144 times. RESET pin Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ). Fig. 50 Voltage drop detection circuit operation waveform Table 18 Voltage drop detection circuit operation state VDCE pin “L” “H” At CPU operating Invalid Valid At RAM back-up Invalid Valid Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-62 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS RAM BACK-UP MODE The 4519 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 18 shows the function and states retained at RAM back-up. Figure 51 shows the state transition. Table 19 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selection of oscillation circuit Clock control register MR Timer 1 function Timer 2 function Timer 3 function Timer 4 function Watchdog timer function Timer control register PA, W4 Timer control registers W1 to W3, W5, W6 Serial I/O function Serial I/O mode register J1 A/D conversion function A/D control registers Q1 to Q3 Voltage drop detection circuit Port level Key-on wakeup control register K0 to K2 Pull-up control registers PU0, PU1 Port output direction registers FR0 to FR3 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) A/D conversion completion flag (ADF) Serial I/O transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) ✕ ✕ (Note 4) ✕ (Note 4) RAM back-up ✕ O ✕ O O ✕ (Note 3) (Note 3) (Note 3) (Note 3) ✕ (Note 4) ✕ O ✕ O ✕ O O (Note 5) O O O O ✕ ✕ (Note 3) (Note 3) (Note 3) (Note 3) ✕ ✕ (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the RAM back-up flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when; • reset pulse is input to RESET pin, or • reset by watchdog timer is performed, or • voltage drop detection circuit detects the voltage drop, or • SRST instruction is executed. In this case, the P flag is “0.” Notes 1: “O” represents that the function can be retained, and “ ✕” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The valid/invalid of the voltage drop detection circuit can be controlled only by VDCE pin. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-63 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 19 shows the return condition for each return source. (5) Related registers • Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. • Key-on wakeup control register K1 Register K1 controls the return condition and valid waveform/ level selection for port P0. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K1 to register A. • Key-on wakeup control register K2 Register K2 controls the INT0 and INT1 key-on wakeup functions and return condition function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 20 Return source and return condition Return source Return condition • Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. • Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU0 to register A. • External interrupt control register I1 Register I1 controls the valid waveform of external 0 interrupt, input control of INT0 pin, and return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. • External interrupt control register I2 Register I2 controls the valid waveform of external 1 interrupt, input control of INT1 pin, and return input level. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Remarks External wakeup signal The key-on wakeup function can be selected with 2 port units. Select the return level ( “ L ” l evel or “ H ” l evel), and return condition (return by level or edge) with the register K1 according to the external state before going into the RAM back-up state. Ports P1 0 – P1 3 Return by an external “L” level in- The key-on wakeup function can be selected with 2 port units. Set the port using the key-on wakeup function to “H” level before going into the RAM put. back-up state. Ports P0 0 – P0 3 Return by an external “H” level or “ L ” l evel input, or rising edge (“L”→“H”) or falling edge (“H”→“L”). INT0 INT1 Return by an external “H” level or Select the return level (“L” level or “H” level) with the registers I1 and I2 ac“ L ” l evel input, or rising edge cording to the external state, and return condition (return by level or edge) ( “ L ” → “ H ” ) o r f a l l i n g e d g e with the register K2 before going into the RAM back-up state. (“H”→“L”). The external interrupt request flags (EXF0, EXF1) are not set. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-64 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS A Operation state Reset (Note 1) • Operation source clock: f(RING) • f(XIN): Stop MR1←1 (Note 5) Key-on wakeup E RAM back-up mode POF instruction execution (Note 4) (Note 2) MR1←0 B Operation state • Operation source clock: f(RING) • f(XIN): Operating (Note 3) MR0←0 MR0←1 POF instruction execution (Note 4) Operation state • Operation source clock: f(XIN) • f(RING): Operating RG0←0 RG0←1 POF instruction execution (Note 4) C D Operation state • Operation source clock: f(XIN) • f(RING): Stop POF instruction execution (Note 4) f(RING): stop f(XIN): stop Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times. 2: The f(XIN) oscillation circuit (ceramic resonance, RC oscillation or quartz-crystal oscillation) is selected by the CMCK, CRCK or CYCK instruction (the start of oscillation and the operation source clock is not switched by these instructions). The start/stop of oscillation and the operation source is switched by register MR. Surely, select the f(XIN) oscillation circuit by executing the CMCK, CRCK or CYCK instruction before clearing MR1 to “0”. MR1 cannot be cleared to “0” when the oscillation circuit is not selected. 3: Generate the wait time by software until the oscillation is stabilized, and then, switch the system clock. 4: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 5: System returns to state A certainly when returning from the RAM back-up mode. However, the selected contents (CMCK, CRCK, CYCK instruction execution state) of f(XIN) oscillation circuit is retained. Fig. 51 State transition POF EPOF instruction + instruction Reset input Power down flag P S Q Program start Yes R P = “1 ” ? No Warm start q Set source ••••••• EPOF instruction + POF instruction Cold start q Clear source • • • • • • Reset input Fig. 52 Set source and clear source of the P flag Fig. 53 Start condition identified example using the SNZP instruction Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-65 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Table 21 Key-on wakeup control register, pull-up control register Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 K13 K12 K11 K10 Ports P02 and P03 return condition selection bit Ports P02 and P03 valid waveform/ level selection bit Ports P01 and P00 return condition selection bit Ports P01 and P00 valid waveform/ level selection bit Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H” level Return by level Return by edge Falling waveform/“L” level Rising waveform/“H” level at reset : 00002 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used at RAM back-up : state retained R/W TAK2/TK2A at RAM back-up : state retained R/W TAK1/TK1A Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-66 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS Table 22 Key-on wakeup control register, pull-up control register Pull-up control register PU0 PU03 PU02 PU01 PU00 P03 pin pull-up transistor control bit P02 pin pull-up transistor control bit P01 pin pull-up transistor control bit P00 pin pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 P13 pin pull-up transistor control bit P12 pin pull-up transistor control bit P11 pin pull-up transistor control bit P10 pin pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained R/W TAPU1/ TPU1A at RAM back-up : state retained R/W TAPU0/ TPU0A Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-67 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS CLOCK CONTROL The clock control circuit consists of the following circuits. • On-chip oscillator (internal oscillator) • Ceramic resonator • RC oscillation circuit • Quartz-crystal oscillation circuit • Multi-plexer (clock selection circuit) • Frequency divider • Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 54 shows the structure of the clock control circuit. The 4519 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator, the RC oscillation or quartz-crystal oscillator can be used for the main clock (f(XIN)) of the 4519 Group. The CMCK instruction, CRCK instruction or CYCK instruction is executed to select the ceramic resonator, RC oscillator or quartz-crystal oscillator respectively. The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. The oscillation start/stop of main clock f(XIN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation start/stop of on-chip oscillator is controlled by register RG. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(X IN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(XIN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped. MR3, MR2 11 10 Division circuit Divided by 8 MR0 1 RG0 0 Divided by 4 Divided by 2 System clock (STCK) Internal clock generating circuit (divided by 3) 01 00 On-chip oscillator (internal oscillator) Instruction clock (INSTCK) S XIN XOUT Ceramic resonance Multiplexer QS RQ CMCK instruction RC oscillation R QS CRCK instruction Quartz-crystal oscillation R QS MR1 QS R EPOF instruction + R Internal reset signal Key-on wakeup signal POF instruction CYCK instruction Fig. 54 Clock control circuit structure Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-68 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS (1) Main clock generating circuit (f(XIN)) The ceramic resonator, RC oscillation or quartz-crystal oscillator can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. When the quartz-crystal oscillator is used, execute the CYCK instruction. The oscillation start/stop of main clock f(XIN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. Execute the CMCK, CRCK or CYCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK, CRCK or CYCK instruction is not executed in program, this MCU operates by the on-chip oscillator. Reset On-chip oscillator operation CMCK instruction CRCKinstruction CYCK instruction • Main clock: ceramic resonance • On-chip oscillator: operating • System clock: on-chip oscillator clock • Main clock: RC oscillation circuit • On-chip oscillator: operating • System clock: on-chip oscillator clock • Main clock: Quartz-crystal circuit • On-chip oscillator: operating • System clock: on-chip oscillator clock • Set the main clock (f(XIN)) oscillation by bit 1 of register MR. • Switch the system clock by bit 0 of register MR. Also, when system clock is switched after main clock oscillation is started, generate the oscillation stabilizing wait time by program if necessary. • Set the on-chip oscillator clock oscillation by register RG. Fig. 55 Switch to ceramic resonance/RC oscillation/quartz-crystal oscillation Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-69 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS (2) On-chip oscillator operation When the MCU operates by the on-chip oscillator as the main clock (f(X IN )) without using the ceramic resonator, RC oscillator or quartz-crystal oscillation, leave XIN pin and XOUT pin open (Figure 56). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that the margin of frequencies when designing application products. M34519 use the CMCK, CRCK * Do not instructions in program.and CYCK XOUT Open XIN Open Fig. 56 Handling of XIN and XOUT when operating on-chip oscillator (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(X IN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 57). M34519 Execute the CMCK instruction in program. XOUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. Rd (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value COUT because constants such as capacitance depend on the resonator. XIN * CIN (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 58). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Fig. 57 Ceramic resonator external circuit M34519 R XIN XOUT Open * Execute the CRCK instruction in program. (5) Quartz-crystal oscillator When a quartz-crystal oscillator is used as the main clock (f(XIN)), connect this external circuit and a quartz-crystal oscillator to pins XIN and XOUT at the shortest distance. Then, execute the CYCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 59). C Fig. 58 External RC oscillation circuit (6) External clock When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to XIN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(XIN)) stop (MR1=1), XIN pin is fixed to “H” in order to avoid the through current by floating of internal logic. The XIN pin is fixed to “H” until main clock (f(XIN)) oscillation starts to be valid (MR 1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to XIN pin in series to limit of current by competitive signal. XIN M34519 * Execute the CYCK instruction in program. XOUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Rd Use the quartz-crystal manufacturer’s recommended value because constants such as caCOUT pacitance depend on the resonator. CIN Fig. 59 External quartz-crystal circuit * Execute the CMCK instruction in program, and set the main clock M34519 f(XIN) to be enabled (MR1=0) XOUT VDD VSS XIN Open R 1kΩ or more External oscillation circuit Fig. 60 External clock input circuit Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-70 HARDWARE 4519 Group FUNCTION BLOCK OPERATIONS (7) Clock control register MR Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 23 Clock control registers Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit (8) Clock control register RG Register RG controls start/stop of on-chip oscillator. Set the contents of this register through register A with the TRGA instruction. at reset : 11112 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1 at RAM back-up : 11112 R/W TAMR/ TMRA Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(XIN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) Main clock (f(RING)) W TRGA Clock control register RG RG0 On-chip oscillator (f(RING)) control bit 0 1 at reset : 02 at RAM back-up : 02 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop Note: “R” represents read enabled, and “W” represents write enabled. ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form✽ 2.Mark Specification Form✽ 3.Data to be written to ROM .................................. one floppy disk. ✽For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-71 HARDWARE 4519 Group LIST OF PRECAUTIONS LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS/ VPP pin as close as possible). ➁ Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. • Register Z (2 bits) • Register D (3 bits) • Register E (8 bits) ➂ Register initial values 2 The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values. • Register Z (2 bits) • Register X (4 bits) • Register Y (4 bits) • Register D (3 bits) • Register E (8 bits) ➃ Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. ➄ Multifunction • The input/output of P30 and P3 1 can be used even when INT0 and INT1 are selected. • The input of ports P2 0–P22 can be used even when S IN, SOUT and SCK are selected. • The input/output of D6 can be used even when CNTR0 (input) is selected. • The input of D6 can be used even when CNTR0 (output) is selected. • The input/output of D7 can be used even when CNTR1 (input) is selected. • The input of D7 can be used even when CNTR1 (output) is selected. ➅ Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. ➆ Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source. ➇ Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. ➈ Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data. 10 Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. Timer 4 In order to stop timer 4 while the PWM output function is used, avoid a timing when timer 4 underflows. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H. 11 12 Watchdog timer • The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function. • The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up state, and stop the watchdog timer function. • When the watchdog timer function and RAM back-up function are used at the same time, execute the WRST instruction before system enters into the RAM back-up state and initialize the flag WDF1. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-72 HARDWARE 4519 Group LIST OF PRECAUTIONS 13 Period measurement circuit When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started. When the edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to “0” to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to “0” (refer to Figure 61➀) and then, stop the bit 2 of register W5 to “0” to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 61➁). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 61➂). While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The X IN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled. ••• LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP ; (✕0✕✕2) ; The SNZT1 instruction is valid ........ ➀ ; (✕0✕✕2) ; Period measurement circuit stop ........................................................... ➁ ; The SNZT1 instruction is executed (T1F flag cleared) ........................................................... ➂ ✕ : these bits are not used here. Fig. 61 Period measurement circuit program example ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-73 HARDWARE 4519 Group LIST OF PRECAUTIONS 14 P30/INT0 pin ❶ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 61 ➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 62 ➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 62 ➂). ❸ Note on bit 2 of register I1 When the interrupt valid waveform of the P3 0 /INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P3 0/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 64➀) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 64➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 64➂). ••• ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ••• ✕ : these bits are not used here. ✕ : these bits are not used here. Fig. 64 External 0 interrupt program example-3 Fig. 62 External 0 interrupt program example-1 ❷ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. • When the input of INT0 pin is disabled (register I13 = “0”), set the key-on wakeup function to be invalid (register K20 = “0”) before system enters to the RAM back-up mode. (refer to Figure 63➀). ••• LA 0 TK2A DI EPOF POF ; (✕✕✕02) ; Input of INT0 key-on wakeup invalid .. ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 63 External 0 interrupt program example-2 ••• ••• ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT0 pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-74 HARDWARE 4519 Group LIST OF PRECAUTIONS 15 P31/INT1 pin ❶ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. ❸ Note on bit 2 of register I2 When the interrupt valid waveform of the P3 1 /INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. • Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 67➀) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 67➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 67➂). • Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 65➀) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to Figure 65➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 65➂). ••• ••• LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT1 pin input is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 65 External 1 interrupt program example-1 ❷ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. • When the input of INT1 pin is disabled (register I23 = “0”), set the key-on wakeup function to be invalid (register K22 = “0”) before system enters to the RAM back-up mode. (refer to Figure 66➀). ✕ : these bits are not used here. Fig. 67 External 1 interrupt program example-3 ••• LA 0 TK2A DI EPOF POF ; (✕0✕✕2) ; Input of INT1 key-on wakeup invalid .. ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 66 External 1 interrupt program example-2 ••• ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-75 HARDWARE 4519 Group LIST OF PRECAUTIONS 16 A/D converter-1 • When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” • Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. • Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. • The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. 18 POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continuously. Program counter Make sure that the PC does not specify after the last page of the built-in ROM. Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the value of supply voltage or more must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Clock control Execute the main clock (f(X IN )) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(XIN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(X IN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. When considering the oscillation stabilize wait time at the switch of clock, be careful that the margin of frequencies of the on-chip oscillator clock. 19 20 ••• LA 8 TV2A LA 0 TQ1A ; (✕0✕✕2) ; The SNZAD instruction is valid ........ ➀ ; (0✕✕✕2) ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode. 21 SNZAD NOP ••• ✕ : these bits are not used here. Fig. 68 A/D converter program example-3 17 A/D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 69). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 70. In addition, test the application products sufficiently. 22 Sensor AI N Apply the voltage withiin the specifications to an analog input pin. Fig. 69 Analog input external circuit example-1 About 1kΩ Sensor AI N Fig. 70 Analog input external circuit example-2 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-76 HARDWARE 4519 Group LIST OF PRECAUTIONS 23 External clock When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to X IN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(XIN)) stop (MR1=1), XIN pin is fixed to “H” in order to avoid the through current by floating of internal logic. The XIN pin is fixed to “H” until main clock (f(XIN)) oscillation start to be valid (MR1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to XIN pin in series to limit of current by competitive signal. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. 24 25 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-77 HARDWARE 4519 Group CONTROL REGISTERS CONTROL REGISTERS Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/W TAI1/TI1A Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I12 Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAI2/TI2A INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) I21 I20 INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to “1”. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-78 HARDWARE 4519 Group CONTROL REGISTERS Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit at reset : 11112 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1 at RAM back-up : 11112 R/W TAMR/ TMRA Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(XIN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) Main clock (f(RING)) W TRGA Clock control register RG RG0 On-chip oscillator (f(RING)) control bit 0 1 at reset : 02 at RAM back-up : 02 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop W TPAA Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state initialized) Operating at RAM back-up : 02 Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAW1/TW1A Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W11 W10 Count source 0 Instruction clock (INSTCK) 0 0 Prescaler output (ORCLK) 1 1 XIN input 0 1 CNTR0 input 1 R/W TAW2/TW2A Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output signal selection bit Timer 2 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating W21 W20 Count source 0 System clock (STCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 1 underflow signal (T1UDF) 0 1 PWM signal (PWMOUT) 1 Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-79 HARDWARE 4519 Group CONTROL REGISTERS Timer control register W3 W33 W32 W31 Timer 3 count source selection bits W30 Timer 3 count auto-stop circuit selection bit (Note 2) Timer 3 control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAW3/TW3A Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating W31 W30 Count source 0 PWM signal (PWMOUT) 0 0 Prescaler output (ORCLK) 1 1 Timer 2 underflow signal (T2UDF) 0 1 CNTR1 input 1 Timer control register W4 W43 W42 W41 W40 D7/CNTR1 pin function selection bit PWM signal “H” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAW4/TW4A D7 (I/O) / CNTR1 (input) CNTR1 (I/O) / D7 (input) PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2 Timer control register W5 W53 W52 W51 Signal for period measurement selection bits W50 Not used Period measurement circuit control bit 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAW5/TW5A This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR0 pin input INT0 pin input Not available R/W TAW6/TW6A W51 W50 0 0 0 1 1 0 1 1 Timer control register W6 W63 W62 W61 W60 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input) Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-80 HARDWARE 4519 Group CONTROL REGISTERS Serial I/O control register J1 at reset : 00002 at RAM back-up : state retained R/W TAJ1/TJ1A J13 J12 J11 J10 Synchronous clock J13 J12 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 Port function J11 J10 0 P20, P21,P22 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, P22 selected/P20, P21, SIN not selected 0 0 SCK, P21, SIN selected/P20, SOUT, P22 not selected 1 1 SCK, SOUT, SIN selected/P20, P21,P22 not selected 1 A/D control register Q1 Q13 A/D operation mode selection bit at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 at RAM back-up : state retained R/W TAQ1/TQ1A Analog input pins Q12 Q11 Analog input pin selection bits Q10 A/D control register Q2 Q23 Q22 Q21 Q20 P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7 pin function selection bit P62/AIN2, P63/AIN3 pin function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAQ2/TQ2A P40, P41, P42, P43 AIN4, AIN5, AIN6, AIN7 P62, P63 AIN2, AIN3 P61 AIN1 P60 AIN0 A/D control register Q3 Q33 Q32 Q31 A/D converter operation clock division ratio selection bits Not used A/D converter operation clock selection bit 0 1 0 1 Q31 0 0 1 1 at reset : 00002 at RAM back-up : state retained R/W TAQ3/TQ3A This bit has no function, but read/write is enabled. Q30 Instruction clock (INSTCK) On-chip oscillator (f(RING)) Division ratio Q30 0 Frequency divided by 6 1 Frequency divided by 12 0 Frequency divided by 24 1 Frequency divided by 48 Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-81 HARDWARE 4519 Group CONTROL REGISTERS Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 K13 K12 K11 K10 Ports P02 and P03 return condition selection bit Ports P02 and P03 valid waveform/ level selection bit Ports P01 and P00 return condition selection bit Ports P01 and P00 valid waveform/ level selection bit Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Return by level Return by edge Falling waveform/“L” level Rising waveform/“H” level Return by level Return by edge Falling waveform/“L” level Rising waveform/“H” level at reset : 00002 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used at RAM back-up : state retained R/W TAK2/TK2A at RAM back-up : state retained R/W TAK1/TK1A Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-82 HARDWARE 4519 Group CONTROL REGISTERS Pull-up control register PU0 PU03 PU02 PU01 PU00 P03 pin pull-up transistor control bit P02 pin pull-up transistor control bit P01 pin pull-up transistor control bit P00 pin pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 P13 pin pull-up transistor control bit P12 pin pull-up transistor control bit P11 pin pull-up transistor control bit P10 pin pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained R/W TAPU0/ TPU0A at RAM back-up : state retained R/W TAPU1/ TPU1A Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-83 HARDWARE 4519 Group CONTROL REGISTERS Port output structure control register FR0 FR03 FR02 FR01 FR00 Ports P12, P13 output structure selection bit Ports P10, P11 output structure selection bit Ports P02, P03 output structure selection bit Ports P00, P01 output structure selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W TFR0A N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output at reset : 00002 at RAM back-up : state retained W TFR1A Port output structure control register FR1 FR13 FR12 FR11 FR10 Port D3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit 0 1 0 1 0 1 0 1 N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR2A Port output structure control register FR2 FR23 FR22 FR21 FR20 Port D7/CNTR1 output structure selection bit Port D6/CNTR0 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR3A Port output structure control register FR3 FR33 FR32 FR31 FR30 Port P53 output structure selection bit Port P52 output structure selection bit Port P51 output structure selection bit Port P50 output structure selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Note: “R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-84 HARDWARE 4519 Group INSTRUCTIONS INSTRUCTIONS The 4519 Group has the 153 instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Symbol A B DR E V1 V2 I1 I2 MR RG PA W1 W2 W3 W4 W5 W6 J1 Q1 Q2 Q3 PU0 PU1 FR0 FR1 FR2 FR3 K0 K1 K2 X Y Z DP PC PCH PCL SK SP CY RPS R1 R2 R3 R4L R4H Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Clock control register MR (4 bits) Clock control register RG (1 bit) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) Serial I/O control register J1 (4 bits) A/D control register Q1 (4 bits) A/D control register Q2 (4 bits) A/D control register Q3 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output format control register FR0 (4 bits) Port output format control register FR1 (4 bits) Port output format control register FR2 (4 bits) Port output format control register FR3 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 3 reload register (8 bits) Timer 4 reload register (8 bits) Timer 4 reload register (8 bits) SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol PS T1 T2 T3 T4 T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D P0 P1 P2 P3 P4 P5 P6 x y z p n i j A 3A 2A 1A 0 Contents Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A/D conversion completion flag Serial I/O transmit/receive completion flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (4 bits) Port P4 (4 bits) Port P5 (4 bits) Port P6 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x ← ↔ ? () — M(DP) a p, a C + x Note : Some instructions of the 4519 Group has the skip function to unexecute the next described instruction. The 4519 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-85 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION GroupMnemonic ing TAB TBA TAY TYA TEAB (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) TABE (B) ← (E7–E4) (A) ← (E3–E0) TDA TAD (DR2–DR0) ← (A2–A0) (A2–A0) ← (DR2–DR0) (A3) ← 0 TAZ (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 TAX TASP (A) ← (X) (A2–A0) ← (SP2–SP0) (A3) ← 0 LXY x, y (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 98, 130 118, 130 AM 116, 130 AMC (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry An (A) ← (A) + n n = 0 to 15 AND OR DEY TAM j (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAM j (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMD j (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8. Function Page 110, 130 GroupMnemonic ing XAMI j Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Page 129, 130 119, 130 119, 130 128, 130 120, 130 RAM to register transfer TMA j (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 122, 130 Register to register transfer LA n 111, 130 TABP p 119, 130 112, 130 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 98, 132 111, 132 119, 130 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 91, 132 91, 132 Arithmetic operation RAM addresses 91, 132 LZ z INY (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 98, 130 98, 130 95, 130 114, 130 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3A 2A 1A 0 92, 132 101, 132 103, 132 102, 132 108, 132 94, 132 101, 132 SC RC SZC CMA RAR RAM to register transfer 128, 130 128, 130 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-86 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing SB j Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Ba (PCL) ← a6–a0 (PCH) ← p (PCL) ← a6–a0 BLA p (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 TV2A TAI1 BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 BMLA p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) TAW1 RTI (PC) ← (SK(SP)) (SP) ← (SP) – 1 102, 134 TW1A (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) 126, 136 117, 136 126, 136 117, 136 127, 136 (A) ← (W1) 117, 136 TPAA (PA0) ← (A0) 123, 136 93, 134 TAI2 TI2A (A) ← (I2) (I2) ← (A) 113, 136 121, 136 93, 134 TI1A (I1) ← (A) 121, 136 (V2) ← (A) (A) ← (I1) 126, 136 113, 136 93, 134 92, 134 92, 134 92, 134 107, 132 SNZ1 Page 103, 132 GroupMnemonic ing DI EI RB j 101, 132 SNZ0 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) ← 0 V11 = 1: NOP SEA n 104, 132 SNZI0 I12 = 1 : (INT0) = “H” ? I12 = 0 : (INT0) = “L” ? 105, 136 104, 136 104, 136 (INTE) ← 0 (INTE) ← 1 Function Page 95, 136 95, 136 Bit operation Comparison operation SEAM 104, 132 Interrupt operation Branch operation SNZI1 I22 = 1 : (INT1) = “H” ? I22 = 0 : (INT1) = “L” ? 105, 136 BL p, a TAV1 TV1A TAV2 (A) ← (V1) (V1) ← (A) (A) ← (V2) 116, 136 126, 136 117, 136 Subroutine operation RT (PC) ← (SK(SP)) (SP) ← (SP) – 1 102, 134 Timer operation TAW2 TW2A TAW3 TW3A Return operation RTS (PC) ← (SK(SP)) (SP) ← (SP) – 1 103, 134 Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-87 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION (continued) Grouping Mnemonic TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS (A) ← (W4) (W4) ← (A) (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS4) (A) ← (TPS3–TPS0) TPSAB (RPS7–RPS4) ← (B) (TPS7–TPS4) ← (B) (RPS3–RPS0) ← (A) (TPS3–TPS0) ← (A) TAB1 (B) ← (T17–T14) (A) ← (T13–T10) 110, 138 SNZT4 108, 138 IAP0 OP0A TAB2 (B) ← (T27–T24) (A) ← (T23–T20) (R27–R24) ← (B) (T27–T24) ← (B) (R23–R20) ← (A) IAP2 (T23–T20) ← (A) TAB3 (B) ← (T37–T34) (A) ← (T33–T30) T3AB (R37–R34) ← (B) (T37–T34) ← (B) (R33–R30) ← (A) (T33–T30) ← (A) TAB4 (B) ← (T47–T44) (A) ← (T43–T40) T4AB (R4L7–R4L4) ← (B) (T47–T44) ← (B) (R4L3–R4L0) ← (A) (T43–T40) ← (A) 109, 138 111, 138 IAP5 OP5A IAP6 OP6A 109, 138 110, 138 110, 138 IAP1 108, 138 OP1A V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V21 = 1: NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A2–A0) ← (P22–P20) (A3) ← 0 (P22–P20) ← (A2–A0) (A) ← (P3) (P3) ← (A) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (A) ← (P6) (P6) ← (A) 107, 140 SNZT3 V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1: NOP 106, 140 123, 138 Function Page 118, 136 127, 136 TR1AB 118, 138 TR3AB 127, 138 T4R4L 118, 138 SNZT1 127, 138 112, 138 (T47–T44) ← (R4L7–R4L4) V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: NOP 109, 140 106, 140 (R37–R34) ← (B) (R33–R30) ← (A) 125, 138 (R17–R14) ← (B) (R13–R10) ← (A) 125, 138 GroupMnemonic ing T4HAB Function (R4H7–R4H4) ← (B) (R4H3–R4H0) ← (A) Page 109, 138 Timer operation SNZT2 106, 140 Timer operation T1AB (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) 96, 140 99, 140 96, 140 99, 140 96, 140 99, 140 97, 140 100, 140 97, 140 100, 140 97, 140 100, 140 97, 140 100, 140 T2AB Input/Output operation OP2A IAP3 OP3A IAP4 OP4A Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-88 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION (continued) Grouping Mnemonic CLD RD (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 SD (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 TAPU0 TPU0A TAPU1 TPU1A (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) Ceramic resonator selected RC oscillator selected Quartz-crystal oscillator selected (RG0) ← (A0) (A) ← (MR) (MR) ← (A) 115, 140 123, 140 115, 140 124, 140 113, 142 122, 142 TALA TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A CMCK CRCK 114, 142 122, 142 114, 142 ADST (ADF) ← 0 A/D conversion starting SNZAD V21 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V21=1: NOP TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A (A) ← (Q1) (Q1) ← (A) (A) ← (Q2) (Q2) ← (A) (A) ← (Q3) (Q3) ← (A) 115, 144 124, 144 116, 144 124, 144 116, 144 124, 144 105, 144 91, 144 122, 142 120, 142 120, 142 120, 142 121, 142 94, 142 94, 142 94, 142 125, 142 110, 142 123, 142 TADAB (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD7–AD4) ← (B) (AD3–AD0) ← (A) 112, 144 114, 144 103, 140 Function Page 93, 140 102, 140 GroupMnemonic ing TABSI TSIAB Function (B) ← (SI7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial I/O starting SNZSI V23=0: (SIOF)=1? After skipping, (SIOF) ← 0 V23=1: NOP TAJ1 TJ1A TABAD (A) ← (J1) (J1) ← (A) In A/D conversion mode , (B) ← (AD9–AD6) (A) ← (AD5–AD2) In comparator mode, (B) ← (AD7–AD4) (A) ← (AD3–AD0) 113, 142 121, 142 111, 144 106, 142 Page 112, 142 125, 142 107, 142 SZD 108, 140 Input/Output operation TAK0 TK0A Clock operation CYCK TRGA TAMR TMRA A/D operation Serial I/O operation SST Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-89 HARDWARE 4519 Group INDEX OF INSTRUCTION FUNCTION INDEX LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing NOP POF EPOF Function (PC) ← (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) ← 0 SRST System reset occurrence Page 99, 144 101, 144 96, 144 105, 144 95, 144 Other operation SNZP DWDT WRST 128, 144 107, 144 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-90 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruction code D9 0 0 0 1 1 0 n n n D0 n 2 0 6 n Number of words 16 Number of cycles 1 Flag CY – Skip condition Overflow = 0 1 Operation: (A) ← (A) + n n = 0 to 15 Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. ADST (A/D conversion STart) Instruction code D9 1 0 1 0 0 1 1 1 1 D0 1 2 2 9 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (ADF) ← 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1) Grouping: A/D conversion operation Description: Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. AM (Add accumulator and Memory) Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0 2 0 0 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (A) + (M(DP)) Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1 2 0 0 B Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-91 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) AND (logical AND between accumulator and memory) Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0 2 0 1 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. B a (Branch to address a) Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0 2 1 8 +a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. BL p, a (Branch Long to address a in page p) Instruction code D9 0 1 Operation: 0 0 1 1 1 D0 p4 p3 p2 p1 p0 2 0 2 E +p p +a p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p5 a6 a5 a4 a3 a2 a1 a0 2 a 16 (PCH) ← p (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. BLA p (Branch Long to address (D) + (A) in page p) Instruction code D9 0 1 Operation: 0 0 0 0 0 1 0 0 0 0 D0 0 2 0 2 1 p 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p5 p4 0 p3 p2 p1 p0 2 p 16 (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR 1 DR 0 A3 A2 A 1 A0 )2 specified by registers D and A in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-92 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BM a (Branch and Mark to address a in page 2) Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0 2 1 a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. BML p, a (Branch and Mark Long to address a in page p) Instruction code D9 0 1 Operation: 0 0 1 1 0 D0 p4 p3 p2 p1 p0 2 0 2 C +p p +a p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p5 a6 a5 a4 a3 a2 a1 a0 2 a 16 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Be careful not to over the stack because the maximum level of subroutine nesting is 8. BMLA p (Branch and Mark Long to address (D) + (A) in page p) Instruction code D9 0 1 Operation: 0 0 0 0 1 1 0 0 0 0 D0 0 2 0 2 3 p 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p5 p4 0 p3 p2 p1 p0 2 p 16 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 47 for M34519M6 and p is 0 to 63 for M34519M8E8. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1 2 0 1 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D) ← 1 Grouping: Input/Output operation Description: Sets (1) to port D. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-93 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) CMA (CoMplement of Accumulator) Instruction code D9 0 0 0 0 0 1 1 1 0 D0 0 2 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (A) Grouping: Arithmetic operation Description: Stores the one ’s complement for register A’s contents in register A. CMCK (Clock select: ceraMic oscillation ClocK) Instruction code D9 1 0 1 0 0 1 1 0 1 D0 0 2 2 9 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Ceramic oscillation circuit selected Grouping: Clock control operation Description: Selects the ceramic oscillation circuit for main clock f(XIN). CRCK (Clock select: Rc oscillation ClocK) Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1 2 2 9 B 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: RC oscillation circuit selected Grouping: Clock control operation Description: Selects the RC oscillation circuit for main clock f(XIN). CYCK (Clock select: crYstal oscillation ClocK) Instruction code D9 1 0 1 0 0 1 1 1 0 D0 1 2 2 9 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Quartz-crystal oscillation circuit selected Grouping: Clock control operation Description: Selects the quartz-crystal oscillation circuit for main clock f(XIN). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-94 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DEY (DEcrement register Y) Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1 2 0 1 7 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (Y) = 15 Operation: (Y) ← (Y) – 1 Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. DI (Disable Interrupt) Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0 2 0 0 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (INTE) ← 0 Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0 2 2 9 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Stop of watchdog timer function enabled Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. EI (Enable Interrupt) Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1 2 0 0 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (INTE) ← 1 Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-95 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EPOF (Enable POF instruction) Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1 2 0 5 B 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: POF instruction valid Grouping: Other operation Description: Makes the immediate after POF instruction valid by executing the EPOF instruction. IAP0 (Input Accumulator from port P0) Instruction code D9 1 0 0 1 1 0 0 0 0 D0 02 2 6 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (P0) Grouping: Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1 2 2 6 1 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (P1) Grouping: Input/Output operation Description: Transfers the input of port P1 to register A. IAP2 (Input Accumulator from port P2) Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0 2 2 6 2 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A2–A0) ← (P22–P20) (A3) ← 0 Grouping: Input/Output operation Description: Transfers the input of port P2 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-96 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP3 (Input Accumulator from port P3) Instruction code D9 1 0 0 1 1 0 0 0 1 D0 1 2 2 6 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (P3) Grouping: Input/Output operation Description: Transfers the input of port P3 to register A. IAP4 (Input Accumulator from port P4) Instruction code D9 1 0 0 1 1 0 0 1 0 D0 0 2 2 6 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (P4) Grouping: Input/Output operation Description: Transfers the input of port P4 to register A. IAP5 (Input Accumulator from port P5) Instruction code D9 1 0 0 1 1 0 0 1 0 D0 1 2 2 6 5 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (P5) Grouping: Input/Output operation Description: Transfers the input of port P5 to register A. IAP6 (Input Accumulator from port P6) Instruction code D9 1 0 0 1 1 0 0 1 1 D0 0 2 2 6 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (P6) Grouping: Input/Output operation Description: Transfers the input of port P6 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-97 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) INY (INcrement register Y) Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1 2 0 1 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 0 1 Operation: (Y) ← (Y) + 1 Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruction code D9 0 0 0 1 1 1 n n n D0 n 2 0 7 n 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition Continuous description Operation: (A) ← n n = 0 to 15 Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. LXY x, y (Load register X and Y with x and y) Instruction code D9 1 1 D0 x3 x2 x1 x0 y3 y2 y1 y0 2 3 x y Number of words 16 Number of cycles 1 Flag CY – Skip condition Continuous description 1 Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruction code D9 0 0 0 1 0 0 1 0 D0 z1 z0 2 0 4 8 +z 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Z) ← z z = 0 to 3 Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-98 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) NOP (No OPeration) Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0 2 0 0 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PC) ← (PC) + 1 Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged. OP0A (Output port P0 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0 2 2 2 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P0) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P0. OP1A (Output port P1 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1 2 2 2 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P1) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P1. OP2A (Output port P2 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 1 D0 0 2 2 2 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P2) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-99 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP3A (Output port P3 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 1 D0 1 2 2 2 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P3) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P3. OP4A (Output port P4 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 1 0 D0 0 2 2 2 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P4) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P4. OP5A (Output port P5 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 1 0 D0 1 2 2 2 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P5) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P5. OP6A (Output port P6 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 1 1 D0 0 2 2 2 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P6) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P6. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-100 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OR (logical OR between accumulator and memory) Instruction code D9 0 0 0 0 0 1 1 0 0 D0 12 0 1 9 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (A) OR (M(DP)) Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. POF (Power OFf) Instruction code D9 0 0 0 0 0 0 0 0 1 D0 0 2 0 0 2 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: Transition to RAM back-up mode Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. RAR (Rotate Accumulator Right) Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1 2 0 1 D Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: → C Y → A 3 A 2A 1A 0 Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instruction code D9 0 0 0 1 0 0 1 1 j D0 j 2 0 4 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-101 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0 2 0 0 6 Number of words 16 Number of cycles 1 Flag CY 0 Skip condition – 1 Operation: (CY) ← 0 Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RD (Reset port D specified by register Y) Instruction code D9 0 0 0 0 0 1 0 1 0 D0 0 2 0 1 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 0 However, (Y) = 0 to 7 Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. RT (ReTurn from subroutine) Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0 2 0 4 4 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 1 Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine. RTI (ReTurn from Interrupt) Instruction code D9 0 0 0 1 0 0 0 1 1 D0 0 2 0 4 6 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-102 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTS (ReTurn from subroutine and Skip) Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1 2 0 4 5 16 Number of words 1 Number of cycles 2 Flag CY – Skip condition Skip at uncondition Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. SB j (Set Bit) Instruction code D9 0 0 0 1 0 1 1 1 j D0 j 2 0 5 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 1 j = 0 to 3 Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). SC (Set Carry flag) Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1 2 0 0 7 Number of words 16 Number of cycles 1 Flag CY 1 Skip condition – 1 Operation: (CY) ← 1 Grouping: Arithmetic operation Description: Sets (1) to carry flag CY. SD (Set port D specified by register Y) Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1 2 0 1 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 1 (Y) = 0 to 7 Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-103 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1 n 2 0 0 2 7 5 Number of words 16 Number of cycles 2 Flag CY – Skip condition (A) = n 2 2 (A) = n ? n = 0 to 15 n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. SEAM (Skip Equal, Accumulator with Memory) Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0 2 0 2 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition (A) = (M(DP)) 1 Operation: (A) = (M(DP)) ? Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0 2 0 3 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition V10 = 0: (EXF0) = 1 1 Operation: V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Grouping: Interrupt operation Description: When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag) Instruction code D9 0 0 0 0 1 1 1 0 0 D0 1 2 0 3 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition V11 = 0: (EXF1) = 1 1 Operation: V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1) Grouping: Interrupt operation Description: When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-104 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZAD (Skip if Non Zero condition of A/D conversion completion flag) Instruction code D9 1 0 1 0 0 0 0 1 1 D0 1 2 2 8 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition V22 = 0: (ADF) = 1 1 Operation: V22 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2) Grouping: A/D conversion operation Description: When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction. SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) Instruction code D9 0 0 0 0 1 1 1 0 1 D0 0 2 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition I12 = 0 : (INT0) = “L” I12 = 1 : (INT0) = “H” Operation: I12 = 0 : (INT0) = “L” ? I12 = 1 : (INT0) = “H” ? (I12 : bit 2 of the interrupt control register I1) Grouping: Interrupt operation Description: When I12 = 0 : S kips the next instruction when the level of INT0 pin is “L.” Executes the next instruction when the level of INT0 pin is “H.” When I12 = 1 : S kips the next instruction when the level of INT0 pin is “H.” Executes the next instruction when the level of INT0 pin is “L.” Number of words 1 Number of cycles 1 Flag CY – Skip condition I22 = 0 : (INT1) = “L” I22 = 1 : (INT1) = “H” SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin) Instruction code D9 0 0 0 0 1 1 1 0 1 D0 12 0 3 B 16 Operation: I22 = 0 : (INT1) = “L” ? I22 = 1 : (INT1) = “H” ? (I22 : bit 2 of the interrupt control register I2) Grouping: Interrupt operation Description: When I22 = 0 : S kips the next instruction when the level of INT1 pin is “L.” Executes the next instruction when the level of INT1 pin is “H.” When I22 = 1 : S kips the next instruction when the level of INT1 pin is “H.” Executes the next instruction when the level of INT1 pin is “L.” Number of words 16 SNZP (Skip if Non Zero condition of Power down flag) Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1 2 0 0 3 Number of cycles 1 Flag CY – Skip condition (P) = 1 1 Operation: (P) = 1 ? Grouping: Other operation Description: Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0.” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-105 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag) Instruction code D9 1 0 1 0 0 0 1 0 0 D0 0 2 2 8 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition V23 = 0: (SIOF) = 1 1 Operation: V23 = 0: (SIOF) = 1 ? After skipping, (SIOF) ← 0 V23 = 1: SNZSI = NOP (V23 = bit 3 of interrupt control register V2) Grouping: Serial I/O operation Description: When V23 = 0 : Skips the next instruction when serial I/O interrupt request flag SIOF is “1.” After skipping, clears (0) to the SIOF flag. When the SIOF flag is “ 0, ” e xecutes the next instruction. When V23 = 1 : This instruction is equivalent to the NOP instruction. SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0 2 2 8 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition V12 = 0: (T1F) = 1 1 Operation: V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Grouping: Timer operation Description: When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “ 1. ” A fter skipping, clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1 2 2 8 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition V13 = 0: (T2F) = 1 1 Operation: V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Grouping: Timer operation Description: When V13 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is “ 1. ” A fter skipping, clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 1 D0 0 2 2 8 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition V20 = 0: (T3F) = 1 1 Operation: V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2) Grouping: Timer operation Description: When V20 = 0 : Skips the next instruction when timer 3 interrupt request flag T3F is “ 1. ” A fter skipping, clears (0) to the T3F flag. When the T3F flag is “0,” executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-106 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 1 D0 1 2 2 8 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition V21 = 0: (T4F) = 1 1 Operation: V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V21 = 1: SNZT4 = NOP (V21 = bit 1 of interrupt control register V2) Grouping: Timer operation Description: When V21 = 0 : Skips the next instruction when timer 4 interrupt request flag T4F is “ 1. ” A fter skipping, clears (0) to the T4F flag. When the T4F flag is “0,” executes the next instruction. When V21 = 1 : This instruction is equivalent to the NOP instruction. SRST (System ReSeT) Instruction code D9 0 0 0 0 0 0 0 0 0 D0 1 2 0 0 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: System reset occurrence Grouping: Other operation Description: System reset occurs. SST (Serial i/o transmission/reception STart) Instruction code D9 1 0 1 0 0 1 1 1 1 D0 0 2 2 9 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (SIOF) ← 0 Serial I/O transmission/reception start Grouping: Serial I/O operation Description: Clears (0) to SIOF flag and starts serial I/O. SZB j (Skip if Zero, Bit) Instruction code D9 0 0 0 0 1 0 0 0 j D0 j 2 0 2 j Number of words 16 Number of cycles 1 Flag CY – Skip condition (Mj(DP)) = 0 j = 0 to 3 1 Operation: (Mj(DP)) = 0 ? j = 0 to 3 Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-107 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag) Instruction code D9 0 0 0 0 1 0 1 1 1 D0 12 0 2 F 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (CY) = 0 Operation: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0.” After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is “1.“ SZD (Skip if Zero, port D specified by register Y) Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0 2 0 0 2 2 4 16 B 16 Number of words 2 Number of cycles 2 Flag CY – Skip condition (D(Y)) = 0 (Y) = 0 to 7 12 (D(Y)) = 0 ? (Y) = 0 to 7 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 0 D0 0 2 2 3 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (T17–T14) ← (B) (R17–R14) ← (B) (T13–T10) ← (A) (R13–R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1 2 2 3 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (T27–T24) ← (B) (R27–R24) ← (B) (T23–T20) ← (A) (R23–R20) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-108 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 1 D0 0 2 2 3 2 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (T37–T34) ← (B) (R37–R34) ← (B) (T33–T30) ← (A) (R33–R30) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 1 D0 12 2 3 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (T47–T44) ← (B) (R4L7–R4L4) ← (B) (T43–T40) ← (A) (R4L3–R4L0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. T4HAB (Transfer data to register R4H from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 1 1 D0 1 2 2 3 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (R4H7–R4H4) ← (B) (R4H3–R4H0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4H. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4H. T4R4L (Transfer data to timer 4 from register R4L) Instruction code D9 1 0 1 0 0 1 0 1 1 D0 1 2 2 9 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (T47–T44) ← (R4L7–R4L4) (T43–T40) ← (R4L3–R4L0) Grouping: Timer operation Description: Transfers the contents of reload register R4L to timer 4. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-109 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB (Transfer data to Accumulator from register B) Instruction code D9 0 0 0 0 0 1 1 1 1 D0 0 2 0 1 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (B) Grouping: Register to register transfer Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0 2 2 7 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T17–T14) (A) ← (T13–T10) Grouping: Timer operation Description: Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. TAB2 (Transfer data to Accumulator and register B from timer 2) Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1 2 2 7 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T27–T24) (A) ← (T23–T20) Grouping: Timer operation Description: Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T23–T20) of timer 2 to register A. TAB3 (Transfer data to Accumulator and register B from timer 3) Instruction code D9 1 0 0 1 1 1 0 0 1 D0 0 2 2 7 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T37–T34) (A) ← (T33–T30) Grouping: Timer operation Description: Transfers the high-order 4 bits (T37–T34) of timer 3 to register B. Transfers the low-order 4 bits (T33–T30) of timer 3 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-110 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB4 (Transfer data to Accumulator and register B from timer 4) Instruction code D9 1 0 0 1 1 1 0 0 1 D0 1 2 2 7 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T47–T44) (A) ← (T43–T40) Grouping: Timer operation Description: Transfers the high-order 4 bits (T47–T44) of timer 4 to register B. Transfers the low-order 4 bits (T43–T40) of timer 4 to register A. TABAD (Transfer data to Accumulator and register B from register AD) Instruction code D9 1 0 0 1 1 1 1 0 0 D0 1 2 2 7 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD6) (A) ← (AD5–AD2) In comparator mode (Q13 = 1), (B) ← (AD7–AD4) (A) ← (AD3–AD0) (Q13 : bit 3 of A/D control register Q1) Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD 9 – AD 6 ) of register AD to register B, and the middle-order 4 bits (AD 5 – AD 2 ) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4 ) of register AD to register B, and the low-order 4 bits (AD3–AD0) of register AD to register A. D0 Number of words 16 TABE (Transfer data to Accumulator and register B from register E) Instruction code D9 0 0 0 0 1 0 1 0 1 0 0 2 A Number of cycles 1 Flag CY – Skip condition – 2 1 Operation: (B) ← (E7–E4) (A) ← (E3–E0) Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E 7–E 4) of register E to register B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruction code D9 0 0 1 0 D0 p5 p4 p3 p2 p1 p0 2 0 8 +p p Number of words 16 Number of cycles 3 Flag CY – Skip condition – 1 Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Arithmetic operation Description: Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p i s 0 to 47 for M34519M6, and p is 0 to 63 for M34519M8E8. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-111 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from PreScaler) Instruction code D9 1 0 0 1 1 1 0 1 0 D0 1 2 2 7 5 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (B) ← (TPS7–TPS4) (A) ← (TPS3–TPS0) Grouping: Timer operation Description: Transfers the high-order 4 bits (TPS 7 – TPS 4 ) of prescaler to register B, and transfers the low-order 4 bits (TPS3–TPS 0) of prescaler to register A. TABSI (Transfer data to Accumulator and register B from register SI) Instruction code D9 1 0 0 1 1 1 1 0 0 D0 0 2 2 7 8 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (B) ← (SI7–SI4) (A) ← (SI3–SI0) Grouping: Serial I/O operation Description: Transfers the high-order 4 bits (SI7–SI4) of serial I/O register SI to register B, and transfers the low-order 4 bits (SI3– SI 0) of serial I/O register SI to register A. TAD (Transfer data to Accumulator from register D) Instruction code D9 0 0 0 1 0 1 0 0 0 D0 1 2 0 5 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A2–A0) ← (DR2–DR0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “ 0 ” i s stored to the bit 3 (A3) of register A. TADAB (Transfer data to register AD from Accumulator from register B) Instruction code D9 1 0 0 0 1 1 1 0 0 D0 1 2 2 3 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (AD7–AD4) ← (B) (AD3–AD0) ← (A) Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q1 3 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-112 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAI1 (Transfer data to Accumulator from register I1) Instruction code D9 1 0 0 1 0 1 0 0 1 D0 1 2 2 5 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (I1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A. TAI2 (Transfer data to Accumulator from register I2) Instruction code D9 1 0 0 1 0 1 0 1 0 D0 0 2 2 5 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (I2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I2 to register A. TAJ1 (Transfer data to Accumulator from register J1) Instruction code D9 1 0 0 1 0 0 0 0 1 D0 0 2 2 4 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (J1) Grouping: Serial I/O operation Description: Transfers the contents of serial I/O control register J1 to register A. TAK0 (Transfer data to Accumulator from register K0) Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0 2 2 5 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K0) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-113 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK1 (Transfer data to Accumulator from register K1) Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1 2 2 5 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K1) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A. TAK2 (Transfer data to Accumulator from register K2) Instruction code D9 1 0 0 1 0 1 1 0 1 D0 0 2 2 5 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K2) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TALA (Transfer data to Accumulator from register LA) Instruction code D9 1 0 0 1 0 0 1 0 0 D0 1 2 2 4 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 Grouping: A/D conversion operation Description: Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the low-order 2 bits (A 1 , A 0 ) of register A. TAM j (Transfer data to Accumulator from Memory) Instruction code D9 1 0 1 1 0 0 j j j D0 j 2 2 C j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-114 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0 2 2 5 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (MR) Grouping: Clock operation Description: Transfers the contents of clock control register MR to register A. TAPU0 (Transfer data to Accumulator from register PU0) Instruction code D9 1 0 0 1 0 1 0 1 1 D0 12 2 5 7 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (PU0) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A. TAPU1 (Transfer data to Accumulator from register PU1) Instruction code D9 1 0 0 1 0 1 1 1 1 D0 02 2 5 E 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (PU1) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. TAQ1 (Transfer data to Accumulator from register Q1) Instruction code D9 1 0 0 1 0 0 0 1 0 D0 0 2 2 4 4 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (Q1) Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q1 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-115 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAQ2 (Transfer data to Accumulator from register Q2) Instruction code D9 1 0 0 1 0 0 0 1 0 D0 1 2 2 4 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (Q2) Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q2 to register A. TAQ3 (Transfer data to Accumulator from register Q3) Instruction code D9 1 0 0 1 0 0 0 1 1 D0 0 2 2 4 6 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (Q3) Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q3 to register A. TASP (Transfer data to Accumulator from Stack Pointer) Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0 2 0 5 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A2–A0) ← (SP2–SP0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0 2 0 5 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (V1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-116 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAV2 (Transfer data to Accumulator from register V2) Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1 2 0 5 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (V2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A. TAW1 (Transfer data to Accumulator from register W1) Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1 2 2 4 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W1) Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A. TAW2 (Transfer data to Accumulator from register W2) Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0 2 2 4 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W2) Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A. TAW3 (Transfer data to Accumulator from register W3) Instruction code D9 1 0 0 1 0 0 1 1 0 D0 1 2 2 4 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W3) Grouping: Timer operation Description: Transfers the contents of timer control register W3 to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-117 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW4 (Transfer data to Accumulator from register W4) Instruction code D9 1 0 0 1 0 0 1 1 1 D0 0 2 2 4 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W4) Grouping: Timer operation Description: Transfers the contents of timer control register W4 to register A. TAW5 (Transfer data to Accumulator from register W5) Instruction code D9 1 0 0 1 0 0 1 1 1 D0 1 2 2 4 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W5) Grouping: Timer operation Description: Transfers the contents of timer control register W5 to register A. TAW6 (Transfer data to Accumulator from register W6) Instruction code D9 1 0 0 1 0 1 0 0 0 D0 0 2 2 5 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W6) Grouping: Timer operation Description: Transfers the contents of timer control register W6 to register A. TAX (Transfer data to Accumulator from register X) Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0 2 0 5 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (X) Grouping: Register to register transfer Description: Transfers the contents of register X to register A. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-118 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAY (Transfer data to Accumulator from register Y) Instruction code D9 0 0 0 0 0 1 1 1 1 D0 1 2 0 1 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (Y) Grouping: Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruction code D9 0 0 0 1 0 1 0 0 1 D0 1 2 0 5 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the high-order 2 bits (A3, A2 ) of register A. TBA (Transfer data to register B from Accumulator) Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0 2 0 0 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register B. TDA (Transfer data to register D from Accumulator) Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1 2 0 2 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (DR2–DR0) ← (A2–A0) Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-119 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0 2 0 1 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (E7–E4) ← (B) (E3–E0) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E. TFR0A (Transfer data to register FR0 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 0 0 D0 0 2 2 2 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (FR0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR0. TFR1A (Transfer data to register FR1 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 0 0 D0 1 2 2 2 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (FR1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR1. TFR2A (Transfer data to register FR2 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 0 1 D0 0 2 2 2 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (FR2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-120 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR3A (Transfer data to register FR3 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 0 1 D0 1 2 2 2 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (FR3) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR3. TI1A (Transfer data to register I1 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 1 D0 1 2 2 1 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (I1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1. TI2A (Transfer data to register I2 from Accumulator) Instruction code D9 1 0 0 0 0 1 1 0 0 D0 0 2 2 1 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (I2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I2. TJ1A (Transfer data to register J1 from Accumulator) Instruction code D9 1 0 0 0 0 0 0 0 1 D0 0 2 2 0 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (J1) ← (A) Grouping: Serial I/O operation Description: Transfers the contents of register A to serial I/O control register J1. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-121 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK0A (Transfer data to register K0 from Accumulator) Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1 2 2 1 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K0. TK1A (Transfer data to register K1 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0 2 2 1 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1. TK2A (Transfer data to register K2 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1 2 2 1 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2. TMA j (Transfer data to Memory from Accumulator) Instruction code D9 1 0 1 0 1 1 j j j D0 j 2 2 B j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-122 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TMRA (Transfer data to register MR from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0 2 2 1 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (MR) ← (A) Grouping: Other operation Description: Transfers the contents of register A to clock control register MR. TPAA (Transfer data to register PA from Accumulator) Instruction code D9 1 0 1 0 1 0 1 0 1 D0 0 2 2 A A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PA0) ← (A0) Grouping: Timer operation Description: Transfers the contents of lowermost bit (A0) register A to timer control register PA. TPSAB (Transfer data to Pre-Scaler from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 1 0 D0 1 2 2 3 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (RPS7–RPS4) ← (B) (TPS7–TPS4) ← (B) (RPS3–RPS0) ← (A) (TPS3–TPS0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. TPU0A (Transfer data to register PU0 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1 2 2 2 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-123 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPU1A (Transfer data to register PU1 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0 2 2 2 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1. TQ1A (Transfer data to register Q1 from Accumulator) Instruction code D9 1 0 0 0 0 0 0 1 0 D0 0 2 2 0 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (Q1) ← (A) Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q1. TQ2A (Transfer data to register Q2 from Accumulator) Instruction code D9 1 0 0 0 0 0 0 1 0 D0 1 2 2 0 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (Q2) ← (A) Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q2. TQ3A (Transfer data to register Q3 from Accumulator) Instruction code D9 1 0 0 0 0 0 0 1 1 D0 0 2 2 0 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (Q3) ← (A) Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q3. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-124 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR1AB (Transfer data to register R1 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1 2 2 3 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (R17–R14) ← (B) (R13–R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13–R10) of reload register R1. TR3AB (Transfer data to register R3 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 1 0 1 D0 1 2 2 3 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (R37–R34) ← (B) (R33–R30) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R37–R34) of reload register R3, and the contents of register A to the low-order 4 bits (R33–R30) of reload register R3. TRGA (Transfer data to register RG from Accumulator) Instruction code D9 1 0 0 0 0 0 1 0 0 D0 1 2 2 0 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (RG0) ← (A0) Grouping: Clock control operation Description: Transfers the contents of register A to register RG. TSIAB (Transfer data to register SI from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 1 0 0 D0 0 2 2 3 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (SI7–SI4) ← (B) (SI3–SI0) ← (A) Grouping: Serial I/O operation Description: Transfers the contents of register B to the high-order 4 bits (SI7–SI4) of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits (SI3–SI0) of serial I/O register SI. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-125 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV1A (Transfer data to register V1 from Accumulator) Instruction code D9 0 0 0 0 1 1 1 1 1 D0 1 2 0 3 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (V1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1. TV2A (Transfer data to register V2 from Accumulator) Instruction code D9 0 0 0 0 1 1 1 1 1 D0 0 2 0 3 E 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (V2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2. TW1A (Transfer data to register W1 from Accumulator) Instruction code D9 1 0 0 0 0 0 1 1 1 D0 0 2 2 0 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (W1) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1. TW2A (Transfer data to register W2 from Accumulator) Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1 2 2 0 F 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W2) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-126 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW3A (Transfer data to register W3 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 0 0 D0 02 2 1 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W3) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3. TW4A (Transfer data to register W4 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 0 0 D0 12 2 1 1 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W4) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W4. TW5A (Transfer data to register W5 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 0 1 D0 0 2 2 1 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (W5) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W5. TW6A (Transfer data to register W6 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 0 1 D0 12 2 1 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W6) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W6. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-127 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TYA (Transfer data to register Y from Accumulator) Instruction code D9 0 0 0 0 0 0 1 1 0 D0 0 2 0 0 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (Y) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register Y. WRST (Watchdog timer ReSeT) Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0 2 2 A 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition (WDF1) = 1 1 Operation: (WDF1) = 1 ? After skipping, (WDF1) ← 0 Grouping: Other operation Description: Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. XAM j (eXchange Accumulator and Memory data) Instruction code D9 1 0 1 1 0 1 j j j D0 j 2 2 D j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruction code D9 1 0 1 1 1 1 j j j D0 j 2 2 F j Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 15 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-128 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruction code D9 1 0 1 1 1 0 j j j D0 j 2 2 E j Number of words 16 Number of cycles 1 Flag CY – Skip Skip condition (Y) = 0 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. D0 2 16 Instruction code D9 Number of words Number of cycles Flag CY Skip condition Instruction code D9 D0 2 16 Number of words Number of cycles Flag CY Skip condition Instruction code D9 D0 2 16 Number of words Number of cycles Flag CY Skip condition Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-129 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR0) ← (A2–A0) (A2–A0) ← (DR2–DR0) (A3) ← 0 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 Register to register transfer TEAB TABE TDA TAD TAZ TAX TASP LXY x, y x3 x2 x1 x0 y3 y2 y1 y0 RAM addresses LZ z INY DEY 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 z1 z0 1 1 1 1 048 +z 013 017 1 1 1 1 1 1 TAM j 1 0 1 1 0 0 j j j j 2Cj 1 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 XAM j 1 0 1 1 0 1 j j j j 2Dj 1 1 RAM to register transfer XAMD j 1 0 1 1 1 1 j j j j 2Fj 1 1 XAMI j 1 0 1 1 1 0 j j j j 2Ej 1 1 TMA j 1 0 1 0 1 1 j j j j 2Bj 1 1 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-130 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – – – – – – – – – – Continuous description – (Y) = 0 (Y) = 15 – – – – – – – – – – – – Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. – – – – – – – (Y) = 15 – (Y) = 0 – – – Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-131 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n 07n 1 1 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (SK(SP)) ← (PC) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 TABP p 0 0 1 0 p5 p4 p3 p2 p1 p0 08p +p 1 3 AM 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 n 0 0 n 1 1 n 0 1 n 00A 00B 06n 1 1 1 1 1 1 Arithmetic operation AMC An AND OR SC RC SZC CMA RAR SB j 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 j j j 0 1 1 0 1 0 1 j j j 018 019 007 006 02F 01C 01D 05C +j 04C +j 02j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3A 2A 1A 0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? Bit operation RB j SZB j SEAM 0 0 0 0 1 0 0 1 1 0 026 1 1 Comparison operation SEA n 0 0 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n 1 n 025 07n 2 2 (A) = n ? n = 0 to 15 Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-132 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description Continuous description – – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. – – – Overflow = 0 – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. – Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. – – – – (CY) = 0 – – – – (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) – – 1 0 – – 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. – – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. – (A) = n – Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-133 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0 18a +a 0Ep +p 2pa +a 010 2pp 1aa 1 2 1 2 (PCL) ← a6–a0 (PCH) ← p (Note) (PCL) ← a6–a0 Branch operation p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 0 0 0 2 2 (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) p5 p4 0 0 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 1 1 Subroutine operation (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 BML p, a 0 1 0 0 0 0 1 1 0 p4 p3 p2 p1 p0 0Cp +p 2pa +a 030 2pp 2 2 p5 a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 0 0 0 0 BMLA p 0 1 2 2 p5 p4 0 p3 p2 p1 p0 RTI 0 0 0 1 0 0 0 1 1 0 046 1 1 Return operation RT 0 0 0 1 0 0 0 1 0 0 044 1 2 RTS 0 0 0 1 0 0 0 1 0 1 045 1 2 Note: p is 0 to 47 for M34519M6, p is 0 to 63 for M34519M8/E8. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-134 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – – – Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. – – Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. – – Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-135 HARDWARE 4519 Group M ACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 004 005 038 1 1 1 1 1 1 (INTE) ← 0 (INTE) ← 1 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) ← 0 V11 = 1: SNZ1 = NOP I12 = 1 : (INT0) = “H” ? I12 = 0 : (INT0) = “L” ? SNZ1 0 0 0 0 1 1 1 0 0 1 039 1 1 SNZI0 0 0 0 0 1 1 1 0 1 0 03A 1 1 Interrupt operation SNZI1 0 0 0 0 1 1 1 0 1 1 03B 1 1 I22 = 1 : (INT1) = “H” ? I22 = 0 : (INT1) = “L” ? TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A TAW2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1 054 03F 055 03E 253 217 254 218 2AA 24B 20E 24C 20F 24D 210 24E 211 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W4) (W4) ← (A) Timer operation TW2A TAW3 TW3A TAW4 TW4A Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-136 HARDWARE 4519 Group M ACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – V10 = 0: (EXF0) = 1 – – – Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control register I1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.” V11 = 0: (EXF1) = 1 – (INT0) = “H” However, I12 = 1 (INT0) = “L” However, I12 = 0 (INT1) = “H” However, I22 = 1 (INT1) = “L” However, I22 = 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control register I2) When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-137 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAW5 TW5A TAW6 TW6A TABPS TPSAB 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 24F 212 250 213 275 235 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (W5) (W5) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (TPS7–TPS4) (A) ← (TPS3–TPS0) (RPS7–RPS4) ← (B) (TPS7–TPS4) ← (B) (RPS3–RPS0) ← (A) (TPS3–TPS0) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R24) ← (B) (T27–T24) ← (B) (R23–R20) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R34) ← (B) (T37–T34) ← (B) (R33–R30) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R4L7–R4L4) ← (B) (T47–T44) ← (B) (R4L3–R4L0) ← (A) (T43–T40) ← (A) (R4H7–R4H4) ← (B) (R4H3–R4H0) ← (A) (R17–R14) ← (B) (R13–R10) ← (A) (R37–R34) ← (B) (R33–R30) ← (A) (T47–T40) ← (R4L7–R4L0) TAB1 T1AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 270 230 1 1 1 1 TAB2 T2AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 271 231 1 1 1 1 Timer operation TAB3 T3AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 272 232 1 1 1 1 TAB4 T4AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 273 233 1 1 1 1 T4HAB TR1AB TR3AB T4R4L 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 237 23F 23B 297 1 1 1 1 1 1 1 1 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-138 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – – – – – – – – – – – Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. – – – – – – – – Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. – – – – Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to register A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3. – – – – Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to register A. Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L. – – – – – – – – – – Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the contents of register A to the low-order 4 bits of timer 4 reload register R4H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3. Transfers the contents of timer 4 reload register R4L to timer 4. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-139 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZT1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 TAPU0 TPU0A TAPU1 TPU1A 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 280 281 282 283 260 220 261 221 262 222 263 223 264 224 265 225 266 226 011 014 015 024 02B 257 22D 25E 22E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 0: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 0: NOP V20 = 0: (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 0: NOP V21 = 0: (T4F) = 1 ? After skipping, (T4F) ← 0 V21 = 0: NOP (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A2–A0) ← (P22–P20) (A3) ← 0 (P22–P20) ← (A2–A0) (A1, A0) ← (P31, P30) (P31, P30) ← (A1, A0) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (A) ← (P6) (P6) ← (A) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) Timer operation Input/Output operation SNZT2 SNZT3 SNZT4 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A IAP4 OP4A IAP5 OP5A IAP6 OP6A CLD RD SD SZD Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-140 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description V12 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 V21 = 0: (T4F) =1 – – – – – – – – – – – – – – – – – (D(Y)) = 0 However, (Y)=0 to 7 – – – – – – – – – – – – – – – – – – – – – – – – – – Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the contents of T3F flag is “1.” After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the contents of T4F flag is “1.” After skipping, clears (0) to T4F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Outputs the contents of register A to port P4. Transfers the input of port P5 to register A. Outputs the contents of register A to port P5. Transfers the input of port P6 to register A. Outputs the contents of register A to port P6. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.” Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. – – – – Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-141 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAK0 TK0A TAK1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 256 21B 259 214 25A 215 228 229 22A 22B 278 238 29E 288 242 202 29A 29B 29D 209 252 216 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (FR0) ← (A) (FR1) ← (A) (FR2) ← (A) (FR3) ← (A) (B) ← (SI7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (SIOF) ← 0 Serial I/O starting V23=0: (SIOF)=1? After skipping, (SIOF) ← 0 V23 = 1: NOP (A) ← (J1) (J1) ← (A) Ceramic resonator selected RC oscillator selected Quartz-crystal oscillator selected (RG0) ← (A0) (A) ← (MR) (MR) ← (A) Input/Output operation Serial I/O operation Clock operation TK1A TAK2 TK2A TFR0A TFR1A TFR2A TFR3A TABSI TSIAB SST SNZSI TAJ1 TJ1A CMCK CRCK CYCK TRGA TAMR TMRA Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-142 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – – – – – – – – – – – – V23 = 0: (SIOF) = 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0 . Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output format control register FR0. Transferts the contents of register A to port output format control register FR1. Transferts the contents of register A to port output format control register FR2. Transferts the contents of register A to port output format control register FR3. Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of serial I/O register SI to register A. Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits of serial I/O register SI. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents of SIOF flag is “1.” After skipping, clears (0) to SIOF flag. Transfers the contents of serial I/O control register J1 to register A. Transfers the contents of register A to serial I/O control register J1. Selects the ceramic resonator for main clock f(XIN). Selects the RC oscillation circuit for main clock f(XIN). Selects the quartz-crystal oscillation circuit for main clock f(XIN). Transfers the contents of clock control regiser RG to register A. Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-143 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABAD 1 0 0 1 1 1 1 0 0 1 279 1 1 Q13 = 0: (B) ← (AD9–AD6) (A) ← (AD5–AD2) Q13 = 1: (B) ← (AD7–AD4) (A) ← (AD3–AD0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD7–AD4) ← (B) (AD3–AD0) ← (A) (ADF) ← 0 A/D conversion starting V21 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: NOP (A) ← (Q1) (Q1) ← (A) (A) ← (Q2) (Q2) ← (A) (A) ← (Q3) (Q3) ← (A) (PC) ← (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? (WDF1) = 1 ? After skipping, (WDF1) ← 0 Stop of watchdog timer function enabled System reset occurrence TALA TADAB 1 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 249 239 1 1 1 1 A/D conversion operation ADST 1 0 1 0 0 1 1 1 1 1 29F 1 1 SNZAD 1 0 1 0 0 0 0 1 1 1 287 1 1 TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A NOP POF EPOF SNZP WRST 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 244 204 245 205 246 206 000 002 05B 003 2A0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Other operation DWDT SRST 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 29C 001 1 1 1 1 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-144 HARDWARE 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Skip condition Carry flag CY Datailed description – – In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register B, and the middle-order 4 bits (AD5–AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B, and the low-order 4 bits (AD3–AD0) of register AD to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt control register V2) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Transfers the contents of A/D control register Q2 to register A. Transfers the contents of register A to A/D control register Q2. Transfers the contents of A/D control register Q3 to register A. Transfers the contents of register A to A/D control register Q3. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate after POF instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. System reset occurs. – – – – – – V22 = 0: (ADF) = 1 – – – – – – – – – – (P) = 1 (WDF1) = 1 – – – – – – – – – – – – – – – Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-145 HARDWARE 4519 Group INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111 D3–D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Hex. 010000 011000 010111 011111 00 NOP 01 BLA 02 03 04 – – – – RT 05 TASP TAD TAX TAZ TAV1 06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 08 09 0A 0B 0C 0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML 0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 10–17 18–1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM – – – – – – – – – SNZ0 TABP TABP TABP TABP BML 48* 32 0 16 TABP TABP TABP TABP BML 49* 33 1 17 TABP TABP TABP TABP BML 50* 34 2 18 TABP TABP TABP TABP BML 51* 35 3 19 TABP TABP TABP TABP BML 36 52* 4 20 TABP TABP TABP TABP BML 53* 37 5 21 TABP TABP TABP TABP BML 38 54* 6 22 TABP TABP TABP TABP BML 55* 39 7 23 TABP TABP TABP TABP BML 40 56* 8 24 TABP TABP TABP TABP BML 57* 41 9 25 TABP TABP TABP TABP BML 42 58* 10 26 TABP TABP TABP TABP BML 59* 43 11 27 TABP TABP TABP TABP BML 60* 44 12 28 TABP TABP TABP TABP BML 61* 45 13 29 TABP TABP TABP TABP BML 62* 46 14 30 TABP TABP TABP TABP BML 47 63* 15 31 SRST CLD POF – SNZP INY DI EI RC SC – – AM AMC TYA – TBA – RD SD – DEY AND OR RTS TAV2 RTI – LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 – – – – – EPOF SB 0 SB 1 SB 2 SB 3 TDA SNZ1 TEAB TABE SNZI0 – CMA RAR TAB TAY – – – – SNZI1 – – TV2A SZC TV1A The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 • * cannot be used in the M34519M6. BL BML BLA BMLA SEA SZD Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-146 HARDWARE 4519 Group INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (continued) D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3–D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Hex. 110000 111111 20 – – 21 22 23 24 – – 25 26 27 28 29 – – – – – – – 2A WRST – – – – – – – – – 2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15 2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15 2D 2E 2F 30–3F TW3A OP0A T1AB TW4A OP1A T2AB TAW6 IAP0 TAB1 SNZT1 – IAP1 TAB2 SNZT2 XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15 TJ1A TW5A OP2A T3AB TAJ1 TAMR IAP2 TAB3 SNZT3 – TW6A OP3A T4AB – – TAI1 IAP3 TAB4 SNZT4 IAP4 – – – – TQ1A TK1A OP4A TAQ1 TAI2 – TQ2A TK2A OP5A TPSAB TAQ2 TQ3A TMRA OP6A – – TRGA – – – – TW1A TW2A TI1A – – T4HAB IAP5 TABPS – – TAQ3 TAK0 IAP6 – – TAPU0 – – – – – – – – – – SNZAD T4R4L – – TI2A TFR0A TSIAB – – TABSI SNZSI TABAD – – – – – – – – – – – – – TFR1ATADAB TALA TAK1 TFR2A – – TAK2 – – – CMCK TPAA CRCK DWDT CYCK SST ADST – – – – – TK0A TFR3ATR3AB TAW1 – – – – – TPU0A TPU1A – – – – TAW2 TAW3 TAW4 TAPU1 – TR1AB TAW5 The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 BL BML BLA BMLA SEA SZD Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-147 HARDWARE 4519 Group BUILT-IN PROM VERSION BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4519 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 23 shows the product of built-in PROM version. Figure 73 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Table 24 Product of built-in PROM version PROM size Part number (✕ 10 bits) M34519E8FP 8192 words RAM size (✕ 4 bits) 384 words Package 42P2R-A ROM type One Time PROM [shipped in blank] PIN CONFIGURATION (TOP VIEW) P13 D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P50 P51 P52 P53 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P12 P11 P10 P03 P02 P01 P00 P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P33 P32 P31/INT1 P30/INT0 VDCE VDD M34519E8FP Fig. 71 Pin configuration of built-in PROM version Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-148 HARDWARE 4519 Group B UILT-IN PROM VERSION (1) PROM mode The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 24. Contact addresses at the end of this data sheet for the appropriate PROM programmer. • Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 73. Table 25 Programming adapter Microcomputer Name of Programming Adapter M34519E8FP PCA7441 Address 000016 1 1 1 D4 D3 D2 D1 D0 Low-order 5 bits (2) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version shipped in blank, Renesas Technology Corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 74 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped). 3FFF16 400016 1 1 1 D4 D3 D2 D1 D0 High-order 5 bits 7FFF16 Fig. 72 PROM memory map (3) E l e c t r i c C h a r a c t e r i s t i c D i f f e r e n c e s Between Mask ROM and One TIme PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One Time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Fig. 73 Flow of writing and test of the product shipped in blank Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 1-149 CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 I/O pins Interrupts Timers A/D converter Serial I/O Reset Voltage drop detection circuit RAM back-up Oscillation circuit APPLICATION 4519 Group 2.1 I/O pins 2.1 I/O pins The 4519 Group has thirty-five I/O pins. Port P2 is also used as Serial I/O pins S CK, S OUT, S IN. Port P3 0 i s also used as INT0 input pin. Port P3 1 i s also used as INT1 input pin. Port P4 is also used as analog input pins A IN4–A IN7 . Port P6 is also used as analog input pins A IN0–A IN3 . Port D6 i s also used as CNTR0 I/O pin. Port D7 i s also used as CNTR1 I/O pin. This section describes each port I/O function, related registers, application example using each port function and notes. 2.1.1 I/O ports (1) Port P0 Port P0 is a 4-bit I/O port. Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor which turns ON/OFF with register PU0. q I nput In the following conditions, the pin state of port P0 is transferred as input data to register A when the I AP0 i nstruction is executed. • Set bit FR0 0 o r bit FR0 1 o f register FR0 to “0” according to the port to be used. • Set the output latch of specified port P0i (i=0, 1, 2 or 3) to “1” with the O P0A i nstruction. If FR0 0 o r FR0 1 i s “0” and the output latch is “0”, “0” is output to specified port P0. If FR0 0 o r FR0 1 i s “1”, the output latch value is output to specified port P0. q O utput The contents of register A is set to the output latch with the OP0A instruction, and is output to port P0. N-channel open-drain or CMOS can be selected as the output structure of port P0 in 2 bits unit by setting FR0 0 o r FR0 1. (2) Port P1 Port P1 is a 4-bit I/O port. Port P1 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor which turns ON/OFF with register PU1. q I nput In the following conditions, the pin state of port P1 is transferred as input data to register A when the I AP1 i nstruction is executed. • Set bit FR0 2 o r bit FR0 3 o f register FR0 to “0” according to the port to be used. • Set the output latch of specified port P1i (i=0, 1, 2 or 3) to “1” with the O P1A i nstruction. If FR0 2 o r FR0 3 i s “0” and the output latch is “0”, “0” is output to specified port P1. If FR0 2 o r FR0 3 i s “1”, the output latch value is output to specified port P1. q O utput The contents of register A is set to the output latch with the OP1A instruction, and is output to port P1. N-channel open-drain or CMOS can be selected as the output structure of port P1 in 2 bits unit by setting FR0 2 o r FR0 3. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-2 APPLICATION 4519 Group 2.1 I/O pins (3) Port P2 Port P2 is a 3-bit I/O port. P2 0 –P2 3 a re also used as serial I/O pins S CK , S OUT , S IN . q I nput In the following condition, the pin state of port P2 is transferred as input data to register A when the I AP2 i nstruction is executed. • Set the output latch of specified port P2i (i=0, 1 or 2) to “1” with the O P2A i nstruction. If the output latch is “0”, “0” is output to specified port P2. q O utput The contents of register A is set to the output latch with the O P2A i nstruction, and is output to port P2. The output structure is an N-channel open-drain. Notes 1: P ort P2 0 i s also used as the serial I/O pin SCK. Accordingly, when port P20 i s used as an input/output port, set bits J1 1 a nd J1 0 o f register J1 to “00 2”. Also, set bits J1 3 a nd J12 of register J1 to “00 2 ”, “01 2 ” or “10 2 ”. 2: P ort P2 1 i s also used as the serial I/O pin S OUT. Accordingly, when port P2 1 i s used as an input/output port, set bits J1 1 a nd J1 0 o f register J1 to “00 2 ” or “10 2 ”. 3: P ort P22 i s also used as the serial I/O pin S IN. Accordingly, when port P2 2 i s used as an input/output port, set bits J1 1 a nd J1 0 o f register J1 to “00 2” or “10 2 ”. (4) Port P3 Port P3 is a 4-bit I/O port. P3 0 i s also used as INT0 input pin and P3 1 i s also used as INT1 input pin. Also, the key-on wakeup function of INT0 and INT1 can be turned ON/OFF by setting bits K2 0 a nd K2 2 o f register K2. q I nput In the following condition, the pin state of port P3 is transferred as input data to register A when the I AP3 i nstruction is executed. • Set the output latch of specified port P3i (i=0, 1, 2 or 3) to “1” with the O P3A i nstruction. If the output latch is “0”, “0” is output to specified port P3. q O utput The contents of register A is set to the output latch with the O P3A i nstruction, and is output to port P3. The output structure is an N-channel open-drain. (5) Port P4 Port P4 is a 4-bit I/O port. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-3 APPLICATION 4519 Group 2.1 I/O pins Port P4 0–P4 3 a re also used as analog input pins A IN4 –A IN7 . q I nput In the following conditions, the pin state of port P4 is transferred as input data to register A when the I AP4 i nstruction is executed. • Set the output latch of specified port P4i (i=0, 1, 2 or 3) to “1” with the O P4A i nstruction. If the output latch is “0”, “0” is output to specified port P4. q O utput The contents of register A is set to the output latch with the O P4A i nstruction, and is output to port P4. The output structure is an N-channel open-drain. (6) Port P5 Port P5 is a 4-bit I/O port. q I nput In the following conditions, the pin state of port P5 is transferred as input data to register A when the I AP5 i nstruction is executed. • Set bit FR3 i ( i=0, 1, 2 or 3) of register FR3 to “0” according to the port to be used. • Set the output latch of specified port P5i (i=0, 1, 2 or 3) to “1” with the O P5A i nstruction. If FR3 i i s “0” and the output latch is “0”, “0” is output to specified port P5. If FR3 i i s “1”, the output latch value is output to specified port P5. q O utput The contents of register A is set to the output latch with the O P5A i nstruction, and is output to port P5. N-channel open-drain or CMOS can be selected as the output structure of port P5 in 2 bits unit by setting FR3 i. (7) Port P6 Port P6 is a 4-bit I/O port. Port P6 0–P6 3 a re also used as analog input pins A IN0 –A IN3 . q I nput In the following conditions, the pin state of port P6 is transferred as input data to register A when the I AP6 i nstruction is executed. • Set the output latch of specified port P6i (i=0, 1, 2 or 3) to “1” with the O P6A i nstruction. If the output latch is “0”, “0” is output to specified port P6. q O utput The contents of register A is set to the output latch with the O P6A i nstruction, and is output to port P6. The output structure is an N-channel open-drain. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-4 APPLICATION 4519 Group 2.1 I/O pins (8) Port D Ports D0–D7 are eight independent I/O ports. Port D6 is also used as CNTR0 I/O pin. Port D 7 is also used as CNTR1 I/O pin. s I nput/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D7, select one of port D with the register Y of the data pointer first. q I nput The pin state of port D can be obtained with the S ZD i nstruction. In the following conditions, if the pin state of port Dj (j=0, 1, 2, 3, 4, 5, 6 or 7) is “0” when the SZD i nstruction is executed, the next instruction is skipped. If it is “1” when the S ZD i nstruction is executed, the next instruction is executed. • Set bit i (i=0,1,2 or 3) of register FR1 or FR2 to “0” according to the port to be used. • Set the output latch of specified port Dj to “1” with the S D i nstruction. If FR1 i o r FR2 i i s “0” and the output latch is “0”, “0” is output to specified port D. If FR1i o r FR2 i i s “1”, the output latch value is output to specified port D. q O utput Set the output level to the output latch with the S D, C LD a nd R D i nstructions. The state of pin enters the high-impedance state when the S D i nstruction is executed. All port D enter the high-impedance state or “H” level state when the CLD instruction is executed. The state of pin becomes “L” level when the R D i nstruction is executed. N-channel open-drain or CMOS can be selected as the output structure of ports D0–D7 in 1 bit unit by setting registers FR1, FR2. Notes 1: W hen the S D a nd R D i nstructions are used, do not set “1000 2 ” or more to register Y. 2: P ort D6 i s also used as CNTR0 pin. Accordingly, when using port D 6, set bit 0 (W6 0 ) of register W6 to “0.” 3: P ort D7 i s also used as CNTR1 pin. Accordingly, when using port D 7, set bit 3 (W4 3 ) of register W4 to “0.” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-5 APPLICATION 4519 Group 2.1 I/O pins 2.1.2 Related registers (1) Timer control register W4 Table 2.1.1 shows the timer control register W4. Set the contents of this register through register A with the T W4A i nstruction. The contents of register W4 is transferred to register A with the T AW4 i nstruction. Table 2.1.1 Timer control register W4 Timer control register W4 W43 W42 W41 W40 D7/CNTR1 pin function selection bit PWM signal “H” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W D 7 ( I/O) / CNTR1 (input) CNTR1 (I/O) / D 7 ( input) PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN i nput Prescaler output (ORCLK) divided by 2 Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: W hen setting the port, W4 2 –W4 0 a re not used. (2) Timer control register W6 Table 2.1.2 shows the timer control register W6. Set the contents of this register through register A with the T W6A i nstruction. The contents of register W6 is transferred to register A with the T AW6 i nstruction. Table 2.1.2 Timer control register W6 Timer control register W6 W6 3 W6 2 W6 1 W6 0 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit (Note 2 ) at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O)/CNTR0 input CNTR0 input/output/D 6 (input) Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: W hen setting the port, W6 3–W6 1 a re not used. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-6 APPLICATION 4519 Group 2.1 I/O pins (3) Serial I/O control register J1 Table 2.1.3 shows the serial I/O control register J1. Set the contents of this register through register A with the T J1A i nstruction. The contents of register J1 is transferred to register A with the T AJ1 i nstruction. Table 2.1.3 Serial I/O control register J1 Serial I/O control register J1 at reset : 0000 2 J1 2 0 1 0 1 J1 0 0 1 0 1 at RAM back-up : state retained Synchronous clock Instruction clock (INSTCK) divided by 8 Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S CK i nput) Port function P2 0, P2 1, P2 2 s elected/S CK, SOUT , S IN n ot selected S CK, SOUT , P2 2 s elected/P20 , P2 1, S IN n ot selected S CK, P2 1, S IN s elected/P20, S OUT, P2 2 n ot selected S CK, SOUT , S IN s elected/P20, P2 1, P2 2 n ot selected R/W J1 3 J1 2 J1 1 J1 0 J1 3 0 Serial I/O synchronous clock 0 selection bits 1 1 J1 1 Serial I/O port function selection 0 0 bits 1 1 Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: W hen setting the port, J1 3–J1 2 a re not used. (4) A/D control register Q2 Table 2.1.4 shows the A/D control register Q2. Set the contents of this register through register A with the T Q2A i nstruction. The contents of register Q2 is transferred to register A with the T AQ2 i nstruction. Table 2.1.4 A/D control register Q2 A/D control register Q2 Q23 Q22 Q21 Q20 P40/AIN4, P41/AIN5, P42/AIN6, P43/ AIN7 p in function selection bit P6 2/A IN2, P6 3 /A IN3 p in function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W P4 0, P4 1, P4 2, P4 3 A IN4, A IN5, A IN6 , AIN7 P6 2, P63 A IN2, AIN3 P6 1 AIN1 P6 0 AIN0 Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: I n order to select A IN3–A IN0, set register Q1 after setting register Q2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-7 APPLICATION 4519 Group 2.1 I/O pins (5) Pull-up control register PU0 Table 2.1.5 shows the pull-up control register PU0. Set the contents of this register through register A with the T PU0A i nstruction. The contents of register PU0 is transferred to register A with the T APU0 i nstruction. Table 2.1.5 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 P0 3 p in pull-up transistor control bit P0 2 p in pull-up transistor control bit P0 1 p in pull-up transistor control bit P0 0 p in at reset : 0000 2 0 1 0 1 0 1 0 at RAM back-up : state retained R/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF pull-up transistor control bit Pull-up transistor ON 1 Note: “ R” represents read enabled, and “W” represents write enabled. (6) Pull-up control register PU1 Table 2.1.6 shows the pull-up control register PU1. Set the contents of this register through register A with the T PU1A i nstruction. The contents of register PU1 is transferred to register A with the T APU1 i nstruction. Table 2.1.6 Pull-up control register PU1 Pull-up control register PU1 PU1 3 PU1 2 PU1 1 PU1 0 P13 p in pull-up transistor control bit P12 p in pull-up transistor control bit P11 p in pull-up transistor control bit P10 p in at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON pull-up transistor control bit 1 Note: “ R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-8 APPLICATION 4519 Group 2.1 I/O pins (7) Port output structure control register FR0 Table 2.1.7 shows the port output structure control register FR0. Set the contents of this register through register A with the T FR0A i nstruction. Table 2.1.7 Port output structure control register FR0 Port output structure control register FR0 FR0 3 FR0 2 FR0 1 FR0 0 Ports P1 2, P1 3 output structure selection bit Ports P1 0, P1 1 output structure selection bit Ports P0 2, P0 3 output structure selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained W N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Ports P0 1, P0 0 output structure selection bit Note: “ W” represents write enabled. (8) Port output structure control register FR1 Table 2.1.8 shows the port output structure control register FR1. Set the contents of this register through register A with the T FR1A i nstruction. Table 2.1.8 Port output structure control register FR1 Port output structure control register FR1 FR13 FR12 FR11 FR10 Port D 3 output structure selection bit Port D 2 output structure selection bit Port D 1 output structure selection bit Port D 0 at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained W N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output output structure selection bit Note: “ W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-9 APPLICATION 4519 Group 2.1 I/O pins (9) Port output structure control register FR2 Table 2.1.9 shows the port output structure control register FR2. Set the contents of this register through register A with the T FR2A i nstruction. Table 2.1.9 Port output structure control register FR2 Port output structure control register FR2 FR2 3 FR2 2 FR2 1 FR2 0 Port D 7/CNTR1 output structure selection bit Port D 6/CNTR0 output structure selection bit Port D 5 output structure selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained W N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Port D 4 output structure selection bit Note: “ W” represents write enabled. (10) Port output structure control register FR3 Table 2.1.10 shows the port output structure control register FR3. Set the contents of this register through register A with the T FR3A i nstruction. Table 2.1.10 Port output structure control register FR3 Port output structure control register FR3 FR3 3 FR3 2 FR3 1 FR3 0 Port P5 3 output structure selection bit Port P5 2 output structure selection bit Port P5 1 output structure selection bit Port P5 0 at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained W N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output output structure selection bit Note: “ W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-10 APPLICATION 4519 Group 2.1 I/O pins (11) Key-on wakeup control register K0 Table 2.1.11 shows the key-on wakeup control register K0. Set the contents of this register through register A with the T K0A i nstruction. The contents of register K0 is transferred to register A with the T AK0 i nstruction. Table 2.1.11 Key-on wakeup control register K0 Key-on wakeup control register K0 K0 3 K0 2 K0 1 K0 0 Pins P1 2, P1 3 key-on wakeup control bit Pins P1 0, P1 1 key-on wakeup control bit Pins P0 2, P0 3 key-on wakeup control bit Pins P0 0, P0 1 at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used 0 Key-on wakeup used key-on wakeup control bit 1 Note: “ R” represents read enabled, and “W” represents write enabled. (12) Key-on wakeup control register K2 Table 2.1.12 shows the key-on wakeup control register K2. Set the contents of this register through register A with the T K2A i nstruction. The contents of register K2 is transferred to register A with the T AK2 i nstruction. Table 2.1.12 Key-on wakeup control register K2 Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W Return by level Return by edge Key-on wakeup invalid Key-on wakeup valid Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid Note: “ R” represents read enabled, and “W” represents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-11 APPLICATION 4519 Group 2.1 I/O pins 2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor. Outline: T he connecting required external part is just keys. Specifications: P ort D is used to output “L” level and port P0 is used to input 16 keys. Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing. M34519 D0 SW4 SW3 SW2 SW1 SW8 SW7 SW6 SW5 D1 SW12 SW11 SW10 SW9 D2 SW16 SW15 SW14 SW13 D3 P00 P01 P02 P03 Fig. 2.1.1 Key input by key scan Switching key input selection port (D 0 →D 1) Stabilizing wait time for input Reading port (key input) Key input period D0 D1 D2 D3 “H ” “L ” “H ” “L ” “H ” “L ” “H ” “L ” IAP0 Input to SW1–SW4 IAP0 Input to SW5–SW8 IAP0 Input to SW9–SW12 IAP0 Input to SW13–SW16 IAP0 Input to SW1–SW4 Note: “H” output of port D becomes high-impedance state. Fig. 2.1.2 Key scan input timing Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-12 APPLICATION 4519 Group 2.1 I/O pins 2.1.4 Notes on use (1) Note when an I/O port is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0”, “L” level can be input. As for the port which has the output structure selection function, select the N-channel open-drain output structure. (2) Noise and latch-up prevention Connect an approximate 0.1 µF bypass capacitor directly to the V SS l ine and the V DD l ine with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the V PP pin (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNVSS/VPP pin to V SS through an approximate 5 k Ω resistor which is connected to the CNV SS/V PP p in at the shortest distance. (3) Multifunction • Be careful that the output of ports P30 and P31 can be used even when INT0 and INT1 pins are selected. • Be careful that the input of ports P20–P22 can be used even when SIN, SOUT and S CK pins are selected. • Be careful that the input/output of port D6 can be used even when input of CNTR0 pin is selected. • Be careful that the input of port D 6 c an be used even when output of CNTR0 pin is selected. • Be careful that the input/output of port D7 can be used even when input of CNTR1 pin is selected. • Be careful that the input of port D 7 c an be used even when output of CNTR1 pin is selected. (4) Connection of unused pins Table 2.1.13 shows the connections of unused pins. (5) SD, RD, SZD instructions When the S D , R D , or S ZD i nstructions is used, do not set “1000 2 ” or more to register Y. (6) Port P3 0/INT0 pin When the RAM back-up mode is used by clearing the bit 3 of register I1 to “0” and setting the input of INT0 pin to be disabled, be careful about the following note. • When the input of INT0 pin is disabled (register I1 3 = “ 0”), clear bit 0 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. (7) Port P3 1/INT1 pin When the RAM back-up mode is used by clearing the bit 3 of register I2 to “0” and setting the input of INT1 pin to be disabled, be careful about the following note. • When the input of INT1 pin is disabled (register I2 3 = “ 0”), clear bit 2 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-13 APPLICATION 4519 Group 2.1 I/O pins Table 2.1.13 Connections of unused pins Pin XIN XOUT Connection Open. Open. Usage condition Internal oscillator is selected. Internal oscillator is selected. RC oscillator is selected. External clock input is selected for main clock. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. CNTR1 input is not selected for timer 3 count source. N-channel open-drain is selected for the output structure. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. S CK p in is not selected. ( Note ( Note ( Note ( Note 1) 1) 2) 3) D0–D5 D6/CNTR0 D7/CNTR1 P00–P03 Open. Connect Open. Connect Open. Connect Open. Connect to VSS. to VSS. to VSS. to VSS. ( Note 4) ( Note 4) ( Note ( Note ( Note ( Note ( Note ( Note ( Note ( Note ( Note 4) 6) 5) 4) 6) 7) 5) 4) 7) P10–P13 Open. Connect to VSS. Open. Connect Open. P21/SOUT Connect Open. P22/SIN Connect Open. P30/INT0 Connect Open. P31/INT1 Connect Open. P3 2, P3 3 Connect P4 0 /A IN4 –P4 3 / Open. Connect AIN7 Open. P50–P53 Connect P6 0 /A IN0 –P6 3 / Open. AIN3 Connect P20/SCK to VSS. to VSS. S IN p in is not selected. to VSS. “0” is set to output latch. to Vss. “0” is set to output latch. to Vss. to Vss. to Vss. to Vss. to Vss. N-channel open-drain is selected for the output structure. Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG 0=0, MR0=1). 2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution. In order to start oscillation, setting the main clock f(X IN) oscillation to be valid (MR 1=0) is required. (If necessary, generate the oscillation stabilizing wait time by software.) Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN) (MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of software, and then set the main clock (f(X IN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, X IN pin is fixed to “H”. When an external clock is used, insert a 1 kΩ resistor to XIN pin in series for limits of current. 4: Be sure to select the output structure of ports D0–D5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open. 6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on wake-up control register K1, set the unused 1-bit to “H” input (turn pull-up transistor ON and open) or “L” input (connect to VSS, or open and set the output latch to “0”). 7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON and open. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-14 APPLICATION 4519 Group 2.2 Interrupts 2.2 Interrupts The 4519 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A/ D and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt functions (1) External 0 interrupt (INT0) The interrupt request occurs by the change of input level of INT0 pin. The interrupt valid waveform can be selected by the bits 1 and 2, and the INT0 pin input is controlled by the bit 3 of the interrupt control register I1. s E xternal 0 interrupt INT0 processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to “ 1. ” W hen the external 0 interrupt occurs, the interrupt processing is executed from address 0 in page 1. q W hen the interrupt is not used The interrupt is disabled and the S NZ0 i nstruction is valid when the bit 0 of register V1 is set to “ 0. ” (2) External 1 interrupt (INT1) The interrupt request occurs by the change of input level of INT1 pin. The interrupt valid waveform can be selected by the bits 1 and 2, and the INT1 pin input is controlled by the bit 3 of the interrupt control register I2. s E xternal 1 interrupt INT1 processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the interrupt enable flag INTE are set to “ 1. ” W hen the external 1 interrupt occurs, the interrupt processing is executed from address 2 in page 1. q W hen the interrupt is not used The interrupt is disabled and the S NZ1 i nstruction is valid when the bit 1 of register V1 is set to “ 0. ” (3) Timer 1 interrupt The interrupt request occurs by the timer 1 underflow. s T imer 1 interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. q W hen the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to “ 0. ” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-15 APPLICATION 4519 Group 2.2 Interrupts (4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. s T imer 2 interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. q W hen the interrupt is not used The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to “ 0. ” (5) Timer 3 interrupt The interrupt request occurs by the timer 3 underflow. s T imer 3 interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.” When the timer 3 interrupt occurs, the interrupt processing is executed from address 8 in page 1. q W hen the interrupt is not used The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set to “ 0. ” (6) Timer 4 interrupt The interrupt request occurs by the timer 4 underflow. s T imer 4 interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.” When the timer 4 interrupt occurs, the interrupt processing is executed from address A in page 1. q W hen the interrupt is not used The interrupt is disabled and the SNZT4 instruction is valid when the bit 1 of register V2 is set to “ 0. ” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-16 APPLICATION 4519 Group 2.2 Interrupts (7) A/D interrupt The interrupt request occurs by the completion of A/D conversion. s A /D interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.” When the A/D interrupt occurs, the interrupt processing is executed from address C in page 1. q W hen the interrupt is not used The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set to “ 0. ” (8) Serial I/O interrupt The interrupt request occurs by the completion of serial I/O transmit/receive. s S erial I/O interrupt processing q W hen the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the interrupt enable flag INTE are set to “ 1. ” W hen the serial I/O interrupt occurs, the interrupt processing is executed from address E in page 1. q W hen the interrupt is not used The interrupt is disabled and the S NZSI i nstruction is valid when the bit 3 of register V2 is set to “ 0. ” Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-17 APPLICATION 4519 Group 2.2 Interrupts 2.2.2 Related registers (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “ 1 ” w ith the E I i nstruction and disabled when INTE flag is cleared to “ 0 ” w ith the D I i nstruction. When any interrupt occurs while the INTE flag is “ 1 ” , the INTE flag is automatically cleared to “ 0, ” so that other interrupts are disabled until the E I i nstruction is executed. Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction. (2) Interrupt request flag The activated condition for each interrupt is examined. Each interrupt request flag is set to “1” when the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Each interrupt request flag is cleared to “ 0 ” w hen either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. (3) Interrupt control register V1 Table 2.2.1 shows the interrupt control register V1. Set the contents of this register through register A with the T V1A i nstruction. In addition, the T AV1 i nstruction can be used to transfer the contents of register V1 to register A. Table 2.2.1 Interrupt control register V1 Interrupt control register V1 V1 3 V1 2 V1 1 V1 0 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 0000 2 R/W Interrupt disabled ( SNZT2 i nstruction is valid) Interrupt enabled (SNZT2 instruction is invalid) ( Note 2) Interrupt disabled ( SNZT1 i nstruction is valid) Interrupt enabled (SNZT1 instruction is invalid) ( Note 2) Interrupt disabled ( SNZ1 i nstruction is valid) Interrupt enabled ( SNZ1 i nstruction is invalid) (Note 2) Interrupt disabled ( SNZ0 i nstruction is valid) Interrupt enabled ( SNZ0 i nstruction is invalid) (Note 2) Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-18 APPLICATION 4519 Group 2.2 Interrupts (4) Interrupt control register V2 Table 2.2.2 shows the interrupt control register V2. Set the contents of this register through register A with the T V2A i nstruction. In addition, the T AV2 i nstruction can be used to transfer the contents of register V2 to register A. Table 2.2.2 Interrupt control register V2 Interrupt control register V2 V2 3 V2 2 V2 1 V2 0 Serial I/O interrupt enable bit (Note 2 ) A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit at reset : 0000 2 0 1 0 1 0 1 0 1 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt at RAM back-up : 0000 2 R/W disabled ( SNZSI i nstruction is valid) enabled ( SNZSI i nstruction is invalid) (Note disabled ( SNZAD i nstruction is valid) enabled ( SNZAD instruction is invalid) (Note disabled ( SNZT4 i nstruction is valid) enabled ( SNZT4 instruction is invalid) (Note disabled ( SNZT3 i nstruction is valid) enabled ( SNZT3 instruction is invalid) (Note 2) 2) 2) 2) Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. (5) Interrupt control register I1 Table 2.2.3 shows the interrupt control register I1. Set the contents of this register through register A with the T I1A i nstruction. In addition, the T AI1 i nstruction can be used to transfer the contents of register I1 to register A. Table 2.2.3 Interrupt control register I1 Interrupt control register I1 I13 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/return level selection bit ( Note 2) I11 I10 INT0 pin edge detection circuit control bit at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W INT0 pin input disabled INT0 pin input enabled Falling waveform /“L” level (“L” level is recognized with the S NZI0 i nstruction) Rising waveform /“H” level (“H” level is recognized with the S NZI0 i nstruction) One-sided edge detected Both edges detected I12 Timer 1 count start synchronous circuit not selected INT0 pin Timer 1 count start 0 synchronous circuit selection bit Timer 1 count start synchronous circuit selected 1 Notes 1: “ R” represents read enabled, and “W” represents write enabled. 2: W hen the contents of I1 2 a nd I1 3 a re changed, the external interrupt request flag EXF0 may be set to “1”. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V1 0) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the S NZ0 i nstruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-19 APPLICATION 4519 Group 2.2 Interrupts (6) Interrupt control register I2 Table 2.2.4 shows the interrupt control register I2. Set the contents of this register through register A with the T I2A i nstruction. In addition, the T AI2 i nstruction can be used to transfer the contents of register I2 to register A. Table 2.2.4 Interrupt control register I2 Interrupt control register I2 I23 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/return level selection bit (Note 2 ) I21 I20 INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W INT1 pin input disabled INT1 pin input enabled Falling waveform / “L” level (“L” level is recognized with the S NZI1 i nstruction) Rising waveform /“H” level (“H” level is recognized with the S NZI1 i nstruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected I22 Timer 3 count start synchronous circuit selected synchronous circuit selection bit 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: W hen the contents of I2 2 a nd I23 a re changed, the external interrupt request flag EXF1 may be set to “1”. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V1 1) of register V1 to “0”. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is performed with the S NZ1 i nstruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-20 APPLICATION 4519 Group 2.2 Interrupts 2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of falling edge ( “ H ” →“ L ” ), rising edge ( “ L ” → “ H ” ) and both edges ( “ H ”→ “ L ” o r “L”→“H”). Outline: An external 0 interrupt can be used by dealing with the falling edge (“H” →“L”), rising edge ( “ L ” →“ H ” ) and both edges ( “ H ” →“ L ” o r “ L ” → “ H ” ) as a trigger. Specifications: An interrupt occurs by the change of an external signal edge (both edges: “H” →“L” or “ L ”→ “ H ” ). Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting example of an external 0 interrupt. (2) External 1 interrupt The INT1 pin is used for external 1 interrupt, of which valid waveforms can be chosen, which can recognize the change of falling edge ( “ H ” →“ L ” ), rising edge ( “ L ” → “ H ” ) and both edges ( “ H ”→ “ L ” o r “L”→“H”). Outline: An external 1 interrupt can be used by dealing with the falling edge (“H” →“L”), rising edge ( “ L ” →“ H ” ) and both edges ( “ H ” →“ L ” o r “ L ” → “ H ” ) as a trigger. Specifications: An interrupt occurs by the change of an external signal edge (falling edge: “H”→ “L”). Figure 2.2.3 shows an operation example of an external 1 interrupt, and Figure 2.2.4 shows a setting example of an external 1 interrupt. (3) Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used. Outline: T he constant period interrupts by the timer 1 underflow signal can be used. Specifications: T imer 1 divides the system clock frequency = 2.0 MHz, and the timer 1 interrupt occurs every 0.25 ms. Figure 2.2.5 shows a setting example of the timer 1 constant period interrupt. (4) Timer 2 interrupt Constant period interrupts by a setting value to timer 2 can be used. Outline: T he constant period interrupts by the timer 2 underflow signal can be used. Specifications: Timer 2 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer 2 interrupt occurs every 1 ms. Figure 2.2.6 shows a setting example of the timer 2 constant period interrupt. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-21 APPLICATION 4519 Group 2.2 Interrupts (5) Timer 3 interrupt Constant period interrupts by a setting value to timer 3 can be used. Outline: T he constant period interrupts by the timer 3 underflow signal can be used. Specifications: Prescaler and timer 3 divide the system clock frequency = 6.0 MHz, and the timer 3 interrupt occurs every 1 ms. Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt. (6) Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used. Outline: T he constant period interrupts by the timer 4 underflow signal can be used. Specifications: Timer 4 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer 4 interrupt occurs every 50 ms. Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt. P30/INT0 “H” “L” P30/INT0 “H” “L” An interrupt occurs after the valid waveform “falling” is detected. An interrupt occurs after the valid waveform “rising” is detected. Fig. 2.2.1 External 0 interrupt operation example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-22 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts External 0 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] ✕ 0 b0: External 0 interrupt occurrence disabled [ TV1A ] ✕✕ ↓ ➁ S et Port Port used for external 0 interrupt is set to input port. b3 b0 Port P3 0 o utput latch ✕✕ ✕ 1 Set to input [ OP3A ] ↓ ➂ S et Valid Waveform Valid waveform of INT0 pin is selected. b3 b0 Interrupt control register I1 1 ✕ 1 ✕ [ TI1A ] b3: INT0 pin input enabled b1: Both edges detection selected ↓ ➃ E xecute NOP Instruction [ NOP ] ↓ ➄ C lear Interrupt Request External 0 interrupt activated condition is cleared. External 0 interrupt request flag EXF0 0 External 0 interrupt activated condition cleared [SNZ0 ] ↓ ( Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the N OP i nstruction after the S NZ0 i nstruction. ) ↓ ➅ E nable Interrupts The External 0 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕✕ 1 ✕ 1 b0: External 0 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ External 0 interrupt enabled state “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.2 External 0 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-23 APPLICATION 4519 Group 2.2 Interrupts P31/INT1 “H” “L” P31/INT1 “H” “L” An interrupt occurs after the valid waveform “falling” is detected. Fig. 2.2.3 External 1 interrupt operation example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-24 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts External 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ b1: External 1 interrupt occurrence disabled [ TV1A ] ✕✕ ↓ ➁ S et Port Port used for external 1 interrupt is set to input port. b3 b0 Port P3 1 o utput latch ✕✕ 1 ✕ Set to input [ OP3A ] ↓ ➂ S et Valid Waveform Valid waveform of INT1 pin is selected. b3 b0 Interrupt control register I2 1 0 0 ✕ [ TI2A ] b3: INT1 pin input enabled b2, b1: One-sided edge detection and falling waveform selected ↓ ➃ E xecute NOP Instruction [ NOP ] ↓ ➄ C lear Interrupt Request External 1 interrupt activated condition is cleared. External 1 interrupt request flag EXF1 0 External 1 interrupt activated condition cleared [SNZ1 ] ↓ ( Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag EXF1, insert the N OP i nstruction after the S NZ1 i nstruction. ↓ b3 b0 ) ➅ E nable Interrupts The External 1 interrupt which is temporarily disabled is enabled. Interrupt control register V1 Interrupt enable flag INTE ✕✕ 1 1 ✕ b1: External 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ External 1 interrupt enabled state “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.4 External 1 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-25 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ✕ ↓ ➁ S top Timer Operation Timer 1 is temporarily stopped. Timer 1 count source is selected. b3 b0 Timer control register W1 0 0 0 0 [ TW1A ] b3: Timer 1 count auto-stop circuit not selected b2: Timer 1 stop b1, b0: Instruction clock (INSTCK) selected for Timer 1 count source ↓ ➂ S et Timer Value Timer 1 count time is set. (The formula is shown *A below.) Timer 1 reload register R1 “ A6 16” Timer count value 166 set [ T1AB ] ↓ ➃ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [ SNZT1 ] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ) ↓ ➄ S tart Timer Operation Timer 1 temporarily stopped is restarted. b3 b0 Timer control register W1 0 1 0 0 b2: Timer 1 operation start [ TW1A ] ↓ ➅ E nable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕ 1 1 ✕ ✕ b2: Timer 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Constant period interrupt execution started *A: The timer 1 count value to make the interrupt occur every 0.25 ms is set as follows. 0.25 ms ≅ ( 2.0 MHz) -1 ✕ 3 ✕ ( 166+1) System clock Instruction clock Timer 1 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.5 Timer 1 constant period interrupt setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-26 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] ✕ ✕ ✕ b3: Timer 2 interrupt occurrence disabled [ TV1A ] 0 ↓ ➁ S top Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped. Timer 2 count source is selected. b3 b0 Timer control register W2 Timer control register PA ✕ 0 0 1 b0 0 [ TW2A ] b2: Timer 2 stop b1, b0: Prescaler output (ORCLK) selected for T imer 2 count source Prescaler stop [ TPAA ] ↓ ➂ S et Timer Value and Prescaler Value Timer 2 and prescaler count times are set. (The formula is shown *A below.) Timer 2 reload register R2 “ 52 16” Timer count value 82 set [ T2AB ] Prescaler reload register RPS “ 0F 16” Prescaler count value 15 set [ TPSAB ] ↓ ➃ C lear Interrupt Request Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared [SNZT2 ] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the N OP i nstruction after the S NZT2 i nstruction. ) ↓ ➄ S tart Timer Operation and Prescaler Operation Timer 2 and prescaler temporarily stopped are restarted. b3 b0 Timer control register W2 Timer control register PA ✕ 1 0 1 b0 b2: Timer 2 operation start [ TW2A ] Prescaler start [ TPAA ] 1 ↓ ➅ E nable Interrupts The Timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE 1 1 ✕ ✕ ✕ b3: Timer 2 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Constant period interrupt execution started *A: The prescaler count value and timer 2 count value to make the interrupt occur every 1 ms are set as follows. 1 ms ≅ ( 4.0 MHz) -1 ✕ 3 ✕ ( 15 +1) ✕ ( 82 +1) System clock Instruction clock Prescaler count value Timer 2 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.6 Timer 2 constant period interrupt setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-27 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts Timer 3 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 0 b3 b0 All interrupts disabled [ DI ] ✕ ✕ 0 b0: Timer 3 interrupt occurrence disabled [ TV2A ] ✕ ↓ ➁ S top Timer Operation Timer 3 and prescaler are temporarily stopped. Timer 3 count source is selected. b3 b0 Timer control register W3 0 0 0 1 b0 Timer control register PA 0 [ TW3A ] b3: Timer 3 count auto-stop circuit not selected b2: Timer 3 stop b1, b0: Prescaler output (ORCLK) selected for T imer 3 count source Prescaler stop [ TPAA ] ↓ ➂ S et Timer Value and Prescaler Value Timer 3 and prescaler count times are set. (The formula is shown *A below.) Timer 3 reload register R3 “ EF 16” Timer count value 239 set [ T3AB ] Prescaler count value 249 set [ TPSAB ] Prescaler reload register RPS “ F9 16” ↓ ➃ C lear Interrupt Request Timer 3 interrupt activated condition is cleared. Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared [SNZT3] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag T3F, insert the N OP i nstruction after the S NZT3 i nstruction. ) ↓ ➄ S tart Timer Operation and Prescaler Operation Timer 3 and prescaler temporarily stopped are restarted. b3 b0 Timer control register W3 Timer control register PA 0 1 0 1 b0 b2: Timer 3 operation start [ TW3A ] Prescaler start [ TPAA ] 1 ↓ ➅ E nable Interrupts The Timer 3 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V2 Interrupt enable flag INTE ✕ 1 ✕ ✕ 1 b0: Timer 3 interrupt occurrence enabled [ TV2A ] All interrupts enabled [ EI ] ↓ Constant period interrupt execution started *A: The prescaler count value and timer 3 count value to make the interrupt occur every 30 ms are set as follows. 30 ms ≅ ( 6.0 MHz) -1 ✕ 3 ✕ ( 249 +1) ✕ ( 239 +1) System clock Instruction clock Prescaler count value Timer 3 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.7 Timer 3 constant period interrupt setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-28 APPLICATION 4519 Group 2.2 Interrupts ➀ D isable Interrupts Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ b1: Timer 4 interrupt occurrence disabled [ TV2A ] ✕✕ ↓ ➁ S top Timer and Prescaler Operation Timer 4 and prescaler are temporarily stopped. Timer 4 count source is selected. b3 b0 Timer control register W4 Timer control register PA 0 0 0 1 b0 0 [ TW4A ] b3: CNTR1 input b2: PWM signal “H” interval expansion function invalid b1: Timer 4 stop b0: Prescaler output (ORCLK) divided by 2 selected f or Timer 4 count source Prescaler stop [ TPAA ] ↓ ➂ S et Timer Value and Prescaler Value Timer 4 and prescaler count times are set. (The formula is shown *A below.) Timer 4 reload register R4L “ DD 16” Timer count value 221 set [ T4AB ] Prescaler reload register RPS “ 95 16” Prescaler count value 149 set [ TPSAB ] ↓ ➃ C lear Interrupt Request Timer 4 interrupt activated condition is cleared. Timer 4 interrupt request flag T4F 0 Timer 4 interrupt activated condition cleared [SNZT4 ] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag T4F, insert the N OP i nstruction after the S NZT4 i nstruction. ) ↓ ➄ S tart Timer Operation and Prescaler Operation Timer 4 and prescaler temporarily stopped are restarted. b3 b0 Timer control register W4 Timer control register PA 0 0 1 1 b0 b1: Timer 4 operation start [ TW4A ] Prescaler start [ TPAA ] 1 ↓ ➅ E nable Interrupts The Timer 4 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V2 Interrupt enable flag INTE ✕✕ 1 1 ✕ b1: Timer 4 interrupt occurrence enabled [ TV2A ] All interrupts enabled [ EI ] ↓ Constant period interrupt execution started *A: The prescaler count value and timer 4 count value to make the interrupt occur every 50 ms are set as follows. 50 ms ≅ ( 4.0 MHz) -1 ✕ 3 ✕ ( 149 +1) ✕ 2 ✕ ( 221 +1) System clock Instruction clock Prescaler count value Timer 4 count source Timer 4 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.2.8 Timer 4 constant period interrupt setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-29 APPLICATION 4519 Group 2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Set a value to the bit 2 of register I1, and execute the S NZ0 i nstruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P30/INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the bit 2 of register I1 is changed. (2) Setting of INT0 pin input control Set a value to the bit 3 of register I1, and execute the S NZ0 i nstruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P30/INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the bit 3 of register I1 is changed. (3) Setting of INT1 interrupt valid waveform Set a value to the bit 2 of register I2, and execute the S NZ1 i nstruction to clear the EXF1 flag to “0” after executing at least one instruction. Depending on the input state of P31/INT1 pin, the external interrupt request flag (EXF1) may be set to “1” when the bit 2 of register I2 is changed. (4) Setting of INT1 pin input control Set a value to the bit 3 of register I2, and execute the S NZ1 i nstruction to clear the EXF1 flag to “0” after executing at least one instruction. Depending on the input state of P31/INT1 pin, the external interrupt request flag (EXF1) may be set to “1” when the bit 3 of register I2 is changed. (5) Multiple interrupts Multiple interrupts cannot be used in the 4519 Group. (6) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write E I a nd R TI i nstructions continuously. (7) P30/INT0 pin When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to “1”. Even in this case, port P30 I /O function is valid. Also, the EXF0 flag is set to “1” when bit 3 of register I1 is set to “1” by input of a valid waveform (valid waveform causing external 0 interrupt) even if it is used as an I/O port P3 0. The input threshold characteristics (VIH/VIL) are different between INT0 pin input and port P3 0 input. Accordingly, note this difference when INT0 pin input and port P3 0 input are used at the same time. (8) P3 1/INT1 pin When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to “1”. Even in this case, port P31 I /O function is valid. Also, the EXF1 flag is set to “1” when bit 3 of register I2 is set to “1” by input of a valid waveform (valid waveform causing external 1 interrupt) even if it is used as an I/O port P3 1. The input threshold characteristics (VIH/VIL) are different between INT1 pin input and port P3 1 input. Accordingly, note this difference when INT1 pin input and port P3 1 input are used at the same time. (9) POF instruction When the P OF i nstruction is executed continuously after the E POF i nstruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the P OF i nstruction. Be sure to disable interrupts by executing the D I i nstruction before executing the E POF i nstruction and the P OF i nstruction continuously. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2.2 Interrupts 2-30 APPLICATION 4519 Group 2.3 Timers 2.3 Timers The 4519 Group has four 8-bit timers (each has a reload register) and the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Timer functions (1) Timer 1 s T imer operation (Timer 1 has the timer 1 count start trigger function from P30 /INT0 pin input) (2) Timer 2 s T imer operation (3) Timer 3 s T imer operation (Timer 3 has the timer 3 count start trigger function from P31 /INT1 pin input) (4) Timer 4 s T imer operation (Timer 4 has the PWM output function) (5) Watchdog timer s W atchdog function Watchdog timer provides a method to reset the system when a program run-away occurs. System operates after it is released from reset. When the timer count value underflows, the WDF1 flag is set to “ 1. ” T hen, if the W RST i nstruction is never executed until timer WDT counts 65534, WDF2 flag is set to “ 1, ” a nd system reset occurs. When the DWDT instruction and the WRST instruction are executed continuously, the watchdog timer function is invalid. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “ 1 ” , the next instruction is skipped and then, the WDF1 flag is cleared to “ 0 ” . Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-31 APPLICATION 4519 Group 2.3 Timers 2.3.2 Related registers (1) Interrupt control register V1 Table 2.3.1 shows the interrupt control register V1. Set the contents of this register through register A with the T V1A i nstruction. In addition, the T AV1 i nstruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 Interrupt control register V1 Interrupt control register V1 V1 3 V1 2 V1 1 V1 0 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : 0000 2 R/W Interrupt disabled ( SNZT2 i nstruction is valid) Interrupt enabled (SNZT2 instruction is invalid) ( Note 2) Interrupt disabled ( SNZT1 i nstruction is valid) Interrupt enabled (SNZT1 instruction is invalid) ( Note 2) Interrupt disabled ( SNZ1 i nstruction is valid) Interrupt enabled ( SNZ1 i nstruction is invalid) (Note 2) Interrupt disabled ( SNZ0 i nstruction is valid) Interrupt enabled ( SNZ0 i nstruction is invalid) (Note 2) 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. 3: W hen timer is used, V1 1 a nd V1 0 a re not used. (2) Interrupt control register V2 Table 2.3.2 shows the interrupt control register V2. Set the contents of this register through register A with the T V2A i nstruction. In addition, the T AV2 i nstruction can be used to transfer the contents of register V2 to register A. Table 2.3.2 Interrupt control register V2 Interrupt control register V2 V2 3 V2 2 V2 1 V2 0 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit at reset : 00002 0 1 0 1 0 1 at RAM back-up : 0000 2 R/W Interrupt disabled ( SNZSI i nstruction is valid) Interrupt enabled ( SNZSI instruction is invalid) (Note 2) Interrupt disabled ( SNZAD i nstruction is valid) Interrupt enabled ( SNZTAD instruction is invalid) ( Note 2) Interrupt disabled ( SNZT4 i nstruction is valid) Interrupt enabled (SNZT4 instruction is invalid) ( Note 2) Interrupt disabled ( SNZT3 i nstruction is valid) 0 Interrupt enabled (SNZT3 instruction is invalid) ( Note 2) 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. 3: W hen timer is used, V2 3 a nd V2 2 i s not used. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-32 APPLICATION 4519 Group 2.3 Timers (3) Interrupt control register I1 Table 2.3.3 shows the interrupt control register I1. Set the contents of this register through register A with the T I1A i nstruction. In addition, the T AI1 i nstruction can be used to transfer the contents of register I1 to register A. Table 2.3.3 Interrupt control register I1 Interrupt control register I1 I13 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/return level selection bit ( Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W INT0 pin input disabled INT0 pin input enabled Falling waveform/ “ L ” l evel ( “ L ” l evel is recognized with the S NZI0 i nstruction) Rising waveform/ “ H ” l evel ( “ H ” l evel is recognized with the S NZI0 i nstruction) One-sided edge detected Both edges detected I12 Timer 1 count start synchronous circuit not selected 0 synchronous circuit selection bit Timer 1 count start synchronous circuit selected 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: W hen the contents of I1 2 a nd I1 3 a re changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to “ 0 ” . In this time, set the N OP i nstruction after the S NZ0 i nstruction, for the case when a skip is performed with the S NZ0 i nstruction. (4) Interrupt control register I2 Table 2.3.4 shows the interrupt control register I2. Set the contents of this register through register A with the T I2A i nstruction. In addition, the T AI2 i nstruction can be used to transfer the contents of register I2 to register A. Table 2.3.4 Interrupt control register I2 Interrupt control register I2 I23 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/return level selection bit ( Note 2) I21 I20 INT1 pin edge detection circuit control bit at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W INT1 pin input disabled INT1 pin input enabled Falling waveform/ “ L ” l evel ( “ L ” l evel is recognized with the S NZI1 i nstruction) Rising waveform/ “ H ” l evel ( “ H ” l evel is recognized with the S NZI1 i nstruction) One-sided edge detected Both edges detected I22 Timer 3 count start synchronous circuit not selected INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit selected synchronous circuit selection bit 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: W hen the contents of I2 2 a nd I2 3 a re changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V1 1) of register V1 to “ 0 ” . In this time, set the N OP i nstruction after the S NZ1 i nstruction, for the case when a skip is performed with the S NZ1 i nstruction. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-33 APPLICATION 4519 Group 2.3 Timers (5) Timer control register PA Table 2.3.5 shows the timer control register PA. Set the contents of this register through register A with the T PAA i nstruction. Table 2.3.5 Timer control register PA Timer control register PA PA0 Prescaler control bit at reset : 0 2 0 1 at RAM back-up : state retained W Stop (state initialized) Operating Note: “ W ” r epresents write enabled. (6) Timer control register W1 Table 2.3.6 shows the timer control register W1. Set the contents of this register through register A with the T W1A i nstruction. In addition, the TAW1 instruction can be used to transfer the contents of register W1 to register A. Table 2.3.6 Timer control register W1 Timer control register W1 W1 3 W1 2 Timer 1 count auto-stop circuit control bit ( Note 2 ) Timer 1 control bit at reset : 0000 2 0 1 0 at RAM back-up : state retained R/W Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating 1 W11 W10 Count source W1 1 0 0 Instruction clock (INSTCK) Timer 1 count source selection 0 1 Prescaler output (ORCLK) bits 1 0 XIN i nput W1 0 1 1 CNTR0 input Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T his function is valid only when the timer 1 count start synchronous circuit is selected (I1 0= “ 1 ” ). (7) Timer control register W2 Table 2.3.7 shows the timer control register W2. Set the contents of this register through register A with the T W2A i nstruction. In addition, the TAW2 instruction can be used to transfer the contents of register W2 to register A. Table 2.3.7 Timer control register W2 Timer control register W2 W2 3 W2 2 CNTR0 output selection bit Timer 2 control bit at reset : 0000 2 0 1 0 at RAM back-up : state retained R/W Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT) W2 1 W2 0 1 W21 W20 0 Timer 2 count source selection 0 0 1 bits 1 0 1 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-34 APPLICATION 4519 Group 2.3 Timers (8) Timer control register W3 Table 2.3.8 shows the timer control register W3. Set the contents of this register through register A with the T W3A i nstruction. In addition, the TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.3.8 Timer control register W3 Timer control register W3 W33 W32 Timer 3 count auto-stop circuit control bit ( Note 2 ) Timer 3 control bit at reset : 0000 2 0 1 at RAM back-up : state retained R/W Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input W31 W30 0 1 W31 W30 0 Timer 3 count source selection 0 0 1 bits 1 0 1 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T his function is valid only when the timer 3 count start synchronous circuit is selected (I20= “ 1 ” ). (9) Timer control register W4 Table 2.3.9 shows the timer control register W4. Set the contents of this register through register A with the T W4A i nstruction. In addition, the TAW4 instruction can be used to transfer the contents of register W4 to register A. Table 2.3.9 Timer control register W4 Timer control register W4 W4 3 W4 2 W4 1 W4 0 D7/CNTR1 pin function selection bit PWM signal “H” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : 0000 2 R/W D 7 ( I/O) / CNTR1 (input) CNTR1 (I/O) / D 7 ( input) PWM signal “ H ” i nterval expansion function invalid PWM signal “ H ” i nterval expansion function valid Stop (state retained) Operating X IN i nput Prescaler output (ORCLK) divided by 2 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-35 APPLICATION 4519 Group 2.3 Timers (10) Timer control register W5 Table 2.3.10 shows the timer control register W5. Set the contents of this register through register A with the T W5A i nstruction. In addition, the TAW5 instruction can be used to transfer the contents of register W5 to register A. Table 2.3.10 Timer control register W5 Timer control register W5 W5 3 W5 2 Not used Period measurement circuit control bit at reset : 0000 2 0 1 0 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR 0 p in input INT0 pin input Not available W5 1 W5 0 1 W51 W50 0 0 Signal for period measurement 0 1 selection bits 1 0 1 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. (11) Timer control register W6 Table 2.3.11 shows the timer control register W6. Set the contents of this register through register A with the T W6A i nstruction. In addition, the TAW6 instruction can be used to transfer the contents of register W6 to register A. Table 2.3.11 Timer control register W6 Timer control register W6 W6 3 W6 2 W6 1 W6 0 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O)/CNTR0 input CNTR0 input/output/D 6 (input) at RAM back-up : state retained R/W Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-36 APPLICATION 4519 Group 2.3 Timers 2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: T he constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divide the system clock frequency f(XIN ) = 4.0 MHz, and the timer 1 interrupt occurs every 3 ms. Figure 2.3.4 shows the setting example of the constant period measurement. (2) CNTR0 output operation: buzzer output Outline: S quare wave output from timer 2 can be used for buzzer output. Specifications: 4 kHz square wave is output from the CNTR0 pin at system clock frequency f(XIN) = 4.0 MHz. Also, timer 2 interrupt occurs simultaneously. Figure 2.3.1 shows the peripheral circuit example, and Figure 2.3.5 shows the setting example of CNTR0 output. In order to reduce the current dissipation, output is high-impedance state during buzzer output stop. 4519 125 µs 125 µs In order to set the timer 2 underflow cycle to 125 µs, set the dividing ratio. Fig. 2.3.1 Peripheral circuit example (3) CNTR0 input operation: event count CNTR0 Outline: Count operation can be performed by using the signal (rising waveform) input from CNTR0 pin as the event. Specifications: The low-frequency pulse from external as the timer 1 count source is input to CNTR0 pin, and the timer 1 interrupt occurs every 100 counts. Figure 2.3.6 shows the setting example of CNTR0 input. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-37 APPLICATION 4519 Group 2.3 Timers (4) Timer operation: timer start by external input Outline: T he constant period can be measured by external input. Specifications: T imer 3 operates by INT1 input as a trigger and an interrupt occurs after 1 ms. Figure 2.3.7 shows the setting example of timer start. (5) CNTR1 output control: PWM output control Outline: T he PWM output from CNTR1 pin can be performed by timer 4. Specifications: Timer 4 divides the main clock frequency f(XIN) = 4.0 MHz and the waveform, which “ H ” p eriod is 0.875 µ s of the 1.875 µ s PWM periods, is output from CNTR1 pin. Figure 2.3.2 shows the timer 4 operation and Figure 2.3.8 shows the setting example of PWM output control. q CNTR1 output: valid (W43 = “1”) PWM signal “H” interval extension function: valid (W42 = “1”) (Note) Reload register R4L = “0316” Reload register R4H = “0216” Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H. Fig. 2.3.2 Timer 4 operation (6) Period measurement Outline: T he period of the followings can be measured by timer 1. • o n-chip oscillator divided by 16 • C NTR0 pin input • I NT0 pin input Specifications: Timer 1 count is performed during one period from the rise of a CNTR0 input to the next rise. Timer 1 count source is X IN i nput. Figure 2.3.9 and Figure 2.3.10 show the setting example of period measurement of a CNTR0 pin input. (7) Pulse width measurement Outline: “ H ” p ulse width or “ L ” p ulse width of INT0 pin input can be measured by Timer 1. Specifications: T imer 1 count is performed during “ H ” p ulse input from the rise of an INT0 input to the next rise. Timer 1 count source is X IN i nput. Figure 2.3.11 and Figure 2.3.12 show the setting example of pulse width measurement of an INT0 pin input. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-38 APPLICATION 4519 Group 2.3 Timers (8) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. Accordingly, when the watchdog timer function is set to be valid, execute the W RST i nstruction at a certain period which consists of 16-bit timers’ 65534 counts or less (execute WRST instruction at less than 65534 machine cycles). Outline: E xecute the W RST i nstruction in 16-bit timer ’ s 65534 counts at the normal operation. If a program runs incorrectly, the W RST i nstruction is not executed and system reset occurs. Specifications: System clock frequency f(XIN) = 4.0 MHz is used, and program run-away is detected by executing the W RST i nstruction in 49 ms. Figure 2.3.3 shows the watchdog timer function, and Figure 2.3.13 shows the example of watchdog timer. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag ➁ ➁ 65534 count (Note) WDF2 flag ➃ RESET pin output ➀ Reset released ➂ WRST instruction executed (skip executed) ➄ System reset ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock. Fig. 2.3.3 Watchdog timer function Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-39 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ✕ ↓ ➁ S top Timer and Prescaler Operation Timer 1 and prescaler are temporarily stopped. Timer 1 count source is selected. b3 b0 Timer control register W1 Timer control register PA 0 0 0 1 b0 0 [ TW1A ] b3: Timer 1 count auto-stop circuit not selected b2: Timer 1 stop b1, b0: Prescaler output (ORCLK) selected for T imer 1 count source Prescaler stop [ TPAA ] ↓ ➂ S et Timer and Prescaler Values Timer 1 and prescaler count times are set. (The formula is shown *A below.) Timer 1 reload register R1 “ F9 16” Timer count value 249 set [ T1AB ] Prescaler reload register RPS “ 0F 16” Prescaler count value 15 set [ TPSAB ] ↓ ➃ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ) ↓ ➄ S tart Timer and Prescaler Operation Timer 1 and prescaler temporarily stopped are restarted. b3 b0 Timer control register W1 Timer control register PA 0 1 0 1 b0 b2: Timer 1 operation start [ TW1A ] Prescaler operation start [ TPAA ] 1 ↓ ➅ E nable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕ 1 1 ✕ ✕ b2: Timer 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Constant period interrupt execution started *A: The prescaler count value and timer 1 count value to make the interrupt occur every 3 ms is set as follows. 3 ms = (4.0 MHz) -1 ✕ 3 ✕ ( 15+1) ✕ ( 249+1) System clock Instruction clock Prescaler count value Timer 1 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.4 Constant period measurement setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-40 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] ✕ ✕ ✕ b3: Timer 2 interrupt occurrence disabled [ TV1A ] 0 ↓ ➁ S top Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped. Timer 2 count source and CNTR0 output are selected. b3 b0 Timer control register W2 Timer control register PA 1 0 0 1 b0 0 [ TW2A ] b3: Timer 2 underflow signal divided by 2 selected for C NTR0 output b2: Timer 2 stop b1, b0: Prescaler output (ORCLK) selected for T imer 2 count source Prescaler stop [ TPAA ] ↓ ➂ S et CNTR0 Output The output structure of the CNTR0 pin is set to N-channel open-drain output. b3 b0 Port output structure control register FR2 Timer control register W6 ✕ b3 0 ✕ ✕ ✕ b0 b2: N-channel open-drain output selected [ TFR2A ] b0: CNTR0 output port set [ TW6A ] ✕✕ 1 ↓ ➃ S et Timer Value and Prescaler Value Timer 2 and prescaler count times are set. (The formula is shown *A below.) Timer 2 reload register R2 “ 29 16” Timer count value 41 set [ T2AB ] Prescaler reload register RPS “ 03 16” Prescaler count value 3 set [ TPSAB ] ↓ ➄ C lear Interrupt Request Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared [ SNZT2 ] ( ↓ ↓ b3 b0 Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the N OP i nstruction after the S NZT2 i nstruction. ) ➅ S tart Timer Operation and Prescaler Operation Timer 2 and prescaler temporarily stopped are restarted. Timer control register W2 Timer control register PA 1 1 0 1 b0 b2: Timer 2 operation start [ TW2A ] Prescaler start [ TPAA ] 1 ↓ ~ E nable Interrupts The Timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE 1 1 ✕ ✕ ✕ b3: Timer 2 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Buzzer output start . . . ↓ ➇ S top CNTR0 Output CNTR0 I/O port is set to CNTR0 input port and is set to be high-impedance state. b3 b0 Register Y Port D 6 o utput latch Timer control register W6 0 1 b3 1 1 ✕ 0 b0 Specify bit position of port D [ TYA ] Set to input [ SD ] b0: Set to CNTR0 input port [ TW6A ] ✕✕ 0 *A: The prescaler count value and timer 2 count value to make the underflow occur every 125 µ s are set as follows. 125 µ s ≅ ( 4.0 MHz) -1 ✕ 3 ✕ ( 3 +1) ✕ ( 41 +1) System clock Instruction clock Presclaer count value Timer 2 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.5 CNTR0 output setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-41 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ✕ ↓ ➁ S top Timer Operation Timer 1 is temporarily stopped. Timer 1 count source is selected. b3 b0 Timer control register W1 0 0 1 1 [ TW1A ] b2: Timer 1 stop b1, b0: CNTR0 input for Timer 1 count source ↓ ➂ S et Port CNTR0 I/O port is set to CNTR0 input port. b3 b0 Register Y Port D 6 o utput latch Port output structure control register FR2 Timer control register W6 0 1 b3 1 1 0 b0 Specify bit position of port D [ TYA ] Set to input [ SD ] b2: N-channel open-drain output selected [ TFR2A ] b2: Set count edge to rising [ TW6A ] b0: Set to CNTR0 input port ✕ b3 0 1 ✕ ✕ ✕ b0 ✕ 0 ↓ ➃ S et Timer Values Timer 1 count time is set. Timer 1 reload register R1 “ 6316 ” Timer count value 99 set [ T1AB ] ↓ ➄ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [ SNZT1 ] ↓ ( Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ) ↓ ➅ S tart Timer Operation Timer 1 temporarily stopped is restarted. b3 b0 Timer control register W1 0 1 1 1 b2: Timer 1 operation start [ TW1A ] ↓ ~ E nable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕ 1 1 ✕ ✕ b2: Timer 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Input signal count started “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.6 CNTR0 input setting example However, specify the pulse width input to CNTR0 pin, CNTR1 pin. Refer to section “3.1 Electrical characteristics” for the timer external input period condition. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-42 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 3 interrupt and external interrupt are temporarily disabled. Interrupt enable flag INTE 0 All interrupts disabled [ DI ] b3 b0 Interrupt control register V1 Interrupt control register V2 ➁ I nitialize Valid Waveform INT1 pin is initialized. ✕✕ b3 0 ✕ ✕ b0 b1: External 1 interrupt occurrence disabled [ TV1A ] b0: Timer 3 interrupt occurrence disabled [ TV2A ] [ TI2A ] b3: INT1 pin input disabled b2: Rising waveform b1: One-sided edge detected b0: Timer 3 count start synchronous circuit not selected ✕✕ 0 ↓ b3 b0 Interrupt control register I2 0 1 0 0 ↓ ➂ S top Timer 3 and Prescaler Operation Timer 3 and prescaler are temporarily stopped. Timer 3 count source is selected. b3 b0 Timer control register W3 Timer control register PA 0 0 0 1 b0 0 [ TW3A ] b3: Timer 3 count auto-stop circuit not selected b2: Timer 3 stop b1, b0: Prescaler output (ORCLK) selected for T imer 3 count source Prescaler stop [ TPAA ] ↓ ➃ S et Port INT1 pin is set to input. b3 b0 Port P3 1 o utput latch ✕✕ 1 ✕ Set to input [ OP3A ] ↓ ➄ S et Timer Value and Prescaler Value Timer 3 and prescaler count times are set. (The formula is shown *A below.) Timer count value 82 set [ T3AB ] Timer 3 reload register R3 “ 52 16” Prescaler reload register RPS “ 0F 16” Prescaler count value 15 set [ TPSAB ] ↓ ➅ C lear Interrupt Request Timer 3 interrupt activated condition is cleared. Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared [SNZT3] ↓ ( Note when the interrupt request is cleared When ➅ i s executed, considering the skip of the next instruction according to the interrupt request flag T3F, insert the N OP i nstruction after the S NZT3 i nstruction. ↓ ~ S et INT1 Input INT1 pin input is set to be valid. b3 b0 ) Interrupt control register I2 1 1 0 1 b3: INT1 pin input enabled [ TI2A ] b0: T imer 3 count start synchronous circuit selected ↓ ➇ S tart Timer Operation and Prescaler Operation Timer 3 and prescaler temporarily stopped are restarted. Timer 3 count auto-stop circuit is selected. b3 b0 Timer control register W3 1101 b0 [ TW3A ] b3: Timer 3 count auto-stop circuit selected b2: Timer 3 operation start Prescaler start [ TPAA ] Timer control register PA 1 ↓ ➈ E nable Interrupts The Timer 3 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V2 Interrupt enable flag INTE ✕✕ 1 ✕ 1 b0: Timer 3 interrupt occurrence enabled [ TV2A ] All interrupts enabled [ EI ] ↓ Ready for timer start by external input completed *A: The prescaler count value and timer 3 count value to make the interrupt occur every 1 ms are set as follows. 1 ms ≅ ( 4.0 MHz) -1 ✕ 3 ✕ ( 15 +1) ✕ ( 82 +1) System clock Instruction clock Presclaer count value Timer 3 count value “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.7 Timer start by external input setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-43 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts ( Note 1 ) Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 0 b3 b0 All interrupts disabled [ DI ] ✕ 0 ✕ b1: Timer 4 interrupt occurrence disabled [ TV2A ] ✕ ↓ ➁ S top Timer Operation Timer 4 is temporarily stopped. Timer 4 count source is selected. PWM signal “ H ” i nterval expansion function control is set. b3 b0 Timer control register W4 0 1 0 0 [ TW4A ] b2: PWM signal “ H ” i nterval expansion function valid b1: Timer 4 stop b0: X IN s elected for Timer 4 count source ↓ ➂ S et Port PWM signal output from CNTR1 pin is set. b3 b0 Timer control register W6 Register Y Port D 7 o utput latch Port output structure control register FR2 ✕ b3 ✕ 0 0 1 ✕ b0 b1: CNTR1 output auto-control circuit not selected [TW6A] Specify bit position of port D [ TYA ] Set to “ L ” o utput [ RD ] b3: Port D 7 C MOS output selected [ TFR2A ] 0 0 b3 1 b0 1 ✕ ✕ ✕ ↓ ➃ S et Timer Value Timer 4 count time is set. Timer 4 reload register R4L Timer 4 reload register R4H “ 0316 ” “ 0216 ” Timer count value 3 set [ T4AB ] Timer count value 2 set [ T4HAB ] ↓ ➄ S tart Timer Operation Timer 4 temporarily stopped is restarted. CNTR1 output control is set to be valid. Timer control register W4 b3 b0 1 1 1 0 [ TW4A ] b3: CNTR1 output valid b1: Timer 4 operation start ↓ ➅ S et Interrupts ( Note 1 ) Interrupts except Timer 4 interrupt is enabled. [ EI ] ↓ PWM output started “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.8 PWM output control setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-44 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ✕ ↓ ➁ S top Timer Operation Timer 1 interrupt is temporarily disabled. Timer 1 count time is set. b3 b0 Timer control register W1 0 0 1 0 [ TW1A ] b2: Timer 1 stop b1, b0: X IN i nput for Timer 1 count source ↓ ➂ S elect Period Measurement signal CNTR I/O port is set as a CNTR input port. CNTR0 pin input is selected as the period measurement signal. b3 b0 Register Y Port D 6 o utput latch Port output structure control register FR2 Timer control register W6 Timer control register W5 0 1 b3 0 0 1 0 1 ✕ ✕ 0 1 b0 ✕ b3 ✕ b0 ✕ b3 0 b0 ✕ 1 Specify bit position of port D [ TYA ] Set to “ H ” i nput [ SD ] [ TFR2A ] b2: Port D 6 N -channel open-drain output selected [ TW6A ] b2: Select rising edge b0: Set CNTR0 input port [ TW5A ] b2: Period measurement circuit stop b1, b0: CNTR0 pin input for period measurement signal ↓ ➃ N o select Timer 1 Count Start Synchronous Circuit Timer 1 count start synchronous circuit is set to be “ not selected ” . b3 b0 [ TI1A ] Interrupt control register I1 ✕✕✕0 b0: Timer 1 count start synchronous circuit not selected ↓ ➄ S et Timer Value Timer 1 count time is set. Timer 1 reload register R1 “ FF 16” Timer count value 255 set [ T1AB ] ↓ ➅ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1 ] ( ↓ Note when the interrupt request is cleared When ➅ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ↓ b3 b0 ) ➆ S tart Period Measurement Circuit The period measurement circuit operation is started. Timer control register W5 ✕ 1 0 1 b2: period measurement circuit operating [ TW5A ] ↓ ➇ S tart Timer Operation Timer 1 temporarily stopped is restarted. b3 b0 Timer control register W1 0 1 1 0 b2: Timer 1 operation start [ TW1A ] ↓ ➈ E nable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕ 1 1 ✕ ✕ b1: Timer 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] ↓ Timer 1 count started, synchronizing with a fall of CNTR0 pin input “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.9 Period measurement of CNTR0 pin input setting example (1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-45 APPLICATION 4519 Group 2.3 Timers Timer 1 interrupt occurrence (period measurement completed) ↓ ➀ S top Timer Operation Timer 1 interrupt is disabled. b3 b0 Timer control register W1 0 0 1 0 [TW1A ] b2: Timer 1 stop ↓ ➁ D isable Interrupts Timer 1 interrupt is disabled. Interrupt control register V1 b3 b0 ✕ 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ↓ ➂ S top Period Measurement circuit Period measurement circuit is stopped. b3 b0 Timer control register W5 ✕ 0 0 1 b2: Period measurement circuit stop [ TW5A ] ↓ ➃ E xecute NOP Instruction [NOP ] ↓ ➄ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1] ↓ ( Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ) ↓ ➅ M easurement data processing Timer 1 count value is read out. Timer 1 “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction → Register A, Register B [ TAB1 ] Fig. 2.3.10 Period measurement of CNTR0 pin input setting example (2) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-46 APPLICATION 4519 Group 2.3 Timers ➀ D isable Interrupts Timer 1 interrupt and External 0 interrupt are temporarily disabled. Interrupt enable flag INTE 0 All interrupts disabled [ DI ] b3 b0 Interrupt control register V1 ✕ 0 ✕ 0 ↓ ➁ S top Timer Operation Timer 1 interrupt is temporarily disabled. Timer 1 count source is set. b3 b0 b2, b0: Timer 1 interrupt and External 0 interrupt occurrence disabled [ TV1A ] Timer control register W1 0 0 1 ↓ 0 [ TW1A ] b2: Timer 1 stop b1, b0: X IN i nput for Timer 1 count source ➂ S elect Period Measurement signal P3 0 /INT0 pin is set as an input port. INT0 pin input is enabled and both edges detection are set. INT0 pin input is selected for period measurement signal.. b3 b0 Port P3 0 o utput latch Interrupt control register I1 ✕ b3 ✕ 0 ✕ 1 1 b0 1 0 Set to input [ OP3A ] [ TI1A ] b3: INT0 pin input enabled b2: “ L ” l evel is recognized with the SNZI0 instruction b1: Both edges selected b0: Timer 1 count start synchronous circuit not selected b2: Period measurement circuit stop [ TW5A ] b1, b0: INT0 pin input for period measurement signal b3 b0 Timer control register W5 ✕ 0 1 0 ↓ ↓ ➃ C lear Interrupt Request (execute this after executing at least one instruction from ➂ i s executed.) External 0 interrupt activated condition is cleared. External 0 interrupt request flag EXF0 0 External 0 interrupt activated condition cleared [ SNZ0] ( ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the N OP i nstruction after the S NZ0 i nstruction. ↓ ↓ ↓ ) ) ➄ S et Timer Value Timer 1 count time is set. Timer 1 reload register R1 “ FF 16” Timer count value 255 set [ T1AB ] ➅ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1 ] Note when the interrupt request is cleared When ➅ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ↓ ↓ ➆ C heck Input level of INT0 Pin to Measure “ H ” P ulse Width Whether an input level of INT0 pin is “ L ” i s checked. [SNZI0 ] ➇ S tart Period Measurement Circuit If an input level of INT0 pin is “ L ” , the period measurement circuit operation is started. b3 b0 Timer control register W5 ➈ S tart Timer Operation Timer 1 temporarily stopped is restarted. ✕ 1 1 ↓ 0 b2: period measurement circuit operating [ TW5A ] b3 b0 Timer control register W1 0 1 1 ↓ 0 b2: Timer 1 operation start [ TW1A ] ➉ E nable Interrupts The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 Interrupt enable flag INTE ✕ 1 1 ✕ ✕ ↓ b2: Timer 1 interrupt occurrence enabled [ TV1A ] All interrupts enabled [ EI ] Timer 1 count started, synchronizing with a rise of INT0 pin input “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.3.11 Pulse width measurement of INT0 pin input setting example (1) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-47 APPLICATION 4519 Group 2.3 Timers Timer 1 interrupt occurrence (period measurement completed) ↓ ➀ S top Timer Operation Timer 1 interrupt is disabled. b3 b0 Timer control register W1 0 0 1 0 [TW1A ] b2: Timer 1 stop ↓ ➁ D isable Interrupts Timer 1 interrupt is disabled. Interrupt control register V1 b3 b0 ✕ 0 ✕ ✕ b2: Timer 1 interrupt occurrence disabled [ TV1A ] ↓ ➂ S top Period Measurement circuit Period measurement circuit is stopped. b3 b0 Timer control register W5 ✕ 0 1 0 b2: Period measurement circuit stop [ TW5A ] ↓ ➃ E xecute NOP Instruction [NOP ] ↓ ➄ C lear Interrupt Request Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared [SNZT1] ↓ ( Note when the interrupt request is cleared When ➄ i s executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the N OP i nstruction after the S NZT1 i nstruction. ) ↓ ➅ M easurement Data Processing Timer 1 count value is read out. Timer 1 “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction → Register A, Register B [ TAB1 ] Fig. 2.3.12 Pulse width measurement of INT0 pin input setting example (2) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-48 APPLICATION 4519 Group 2.3 Timers Main Routine (every 20 ms) ➀ R eset Flag WDF1 Watchdog timer flag WDF1 is reset. 0 Watchdog timer flag WDF1 cleared. [ WRST ] ( ↓ Note when the watchdog timer flag is cleared When ➀ i s executed, considering the skip of the next instruction according to the watchdog timer flag WDF1, insert the N OP i nstruction after the W RST i nstruction. ↓ Main Routine Execution ) ↓ Repeat In the interrupt service routine, do not clear watchdog timer flag WDF1. Interrupt may be executed even if program run-away occurs. When going to RAM back-up mode : : WRST ; WDF flag cleared NOP DI ; Interrupt disabled EPOF ; P OF i nstruction enabled POF ↓ Oscillation stop (RAM back-up mode) In the RAM back-up mode, WEF, WDF1 and WDF2 flags are initialized. However, when WDF2 flag is set to “ 1 ” , at the same time, system goes into RAM back-up mode, microcomputer may be reset. When watchdog timer and RAM back-up mode are used, execute the W RST i nstruction to initialize WDF1 flag before system goes into the RAM back-up mode. Fig. 2.3.13 Watchdog timer setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-49 APPLICATION 4519 Group 2.3 Timers 2.3.4 Notes on use (1) Prescaler Stop counting and then execute the T ABPS i nstruction to read from prescaler data. Stop counting and then execute the T PSAB i nstruction to set prescaler data. (2) Count source Stop timer 1, 2, 3, 4 or LC counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3 or 4 counting and then execute the T AB1 , T AB2 , T AB3 o r T AB4 i nstruction to read its data. (4) Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the T 1AB , T 2AB , T 3AB , T 4AB o r T LCA instruction to write its data. (5) Writing to reload register R1, reload register R3 and reload register R4H When writing data to reload register R1 while timer 1 is operating respectively, avoid a timing when timer 1 underflows. When writing data to reload register R3 while timer 3 is operating respectively, avoid a timing when timer 3 underflows. When writing data to reload register R4H while timer 4 is operating respectively, avoid a timing when timer 4 underflows. (6) Timer 4 • A t CNTR1 output vaild, if a timing of timer 4 underflow overlaps with a timing to stop timer 4, a hazard may be generated in a CNTR1 output waveform. Please review sufficiently. • When “H” interval extension function of the PWM signal is set to be “valid”, set “01 16” or more to reload register R4H. (7) Watchdog timer • The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the WRST i nstruction continuously, and clear the WEF flag to “0”. • The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction and the W RST i nstruction continuously every system is returned from the RAM back-up state. • When the watchdog timer function and RAM back-up function are used at the same time, initialize the flag WDF1 with the W RST i nstruction before system enters into the RAM back-up state. (8) Pulse width input to CNTR0 pin, CNTR1 pin Refer to section “3.1 Electrical characteristics” for rating value of pulse width input to CNTR0 pin, CNTR1 pin. (9) Period measurement circuit ● When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. ● While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. ● When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-50 APPLICATION 4519 Group 2.3 Timers ● When the signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) ●When the input of P3 0/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled. ● S tart timer operation immediately after operation of a period measurement circuit is started. ● Even when the edge for measurement is input by timer operation is started from the operation of period measurement circuit is started, timer 1 is not operated. ● W hen data is read from timer 1, stop the timer 1 and the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, disable the timer 1 interrupt, and then, stop the period measurement circuit. Figure 2.3.14 shows the setting example to read measurement data of period measurement circuit. (10) Prescaler, timer 1, timer 2 and timer 3 count start time and count time when operation starts Count starts from the first rising edge of the count source ➁ in Fig.2.3.15 after prescaler, timer 1, timer 2 and timer 3 operations start ➀ i n Fig.2.3.15. Time to first underflow ➂ in Fig.2.3.15 is shorter (for up to 1 period of the count source) than time among next underflow ➃ in Fig.2.3.15 by the timing to start the timer and count source operations after count starts. (11) Timer 4 count start time and count time when operation starts Count starts from the rising edge ➁ in Fig.2.3.16 after the first falling edge of the count source, after timer 4 operation starts ➀ in Fig.2.3.16. Time to first underflow ➂ i n Fig.2.3.16 is different from time among next underflow ➃ in Fig.2.3.16 by the timing to start the timer and count source operations after count starts. ••• Timer 1 operation is stopped (bit 2 of register W1 is cleared to “0”) ↓ Timer 1 interrupt is disabled (bit 2 of register V1 is cleared to “0”) ↓ Period measurement circuit is stopped. (bit 2 of register W5 is cleared to “0”) ↓ Execute at least one Instruction [ NOP] ↓ Timer 1 interrupt request flag (T1F) is cleared to “0”. [ SNZT1 ] ↓ Considering the skip of the S NZT1 i nstruction, insert the N OP i nstruction. ↓ Measurement data is read. [ TAB1 ] Fig. 2.3.14 Period measurement circuit program example ➁ Count source Timer value 3 2 1 0 3 2 1 0 3 2 Timer underflow signal ➂ ➃ ➀ Timer start Fig. 2.3.15 Count start time and count time when operation starts (PS, T1, T2 and T3) ➁ Count source Timer value 3 2 1 0 3 2 1 0 3 Timer underflow signal ➂ ➃ ➀ Timer start Fig. 2.3.16 Count start time and count time when operation starts (T4) → → ••• Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-51 APPLICATION 4519 Group 2.4 A/D converter 2.4 A/D converter The 4519 Group has an 8-channel A/D converter with the 10-bit successive comparison method. This A/D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values. This section describes the related registers, application examples using the A/D converter and notes. Figure 2.4.1 shows the A/D converter block diagram. Register B (4) Register A (4) 4 4 IAP4 (P40–P43) IAP6 (P60–P63) OP4A (P40–P43) OP6A (P60–P63) TAQ1 TQ1A 4 TAQ2 TQ2A 4 TAQ3 TQ3A 2 TALA Division circuit Divided by 48 4 4 4 Q13 Q12 Q11 Q10 Q23 Q22 Q21 Q20 Q33 Q32 Q31 Q30 8 TABAD 8 TADAB Q31, Q30 11 10 01 00 Q32 3 Instruction clock On-chip oscillator 1 clock 0 Divided by 24 Divided by 12 Divided by 6 A/D conversion clock (ADCK) Q13 0 8-channel multi-plexed analog switch A/D control circuit 1 P60/AIN0 P61/AIN1 P62/AIN2 P63/AIN3 P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7 ADF (1) A/D interrupt 1 Comparator 0 Q13 DAC operation signal Successive comparison register (AD) (10) 10 0 1 Q13 10 8 0 1 1 Q13 8 D/A converter (Note 1) 8 VDD 8 VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. Fig. 2.4.1 A/D converter structure Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-52 APPLICATION 4519 Group 2.4 A/D converter 2.4.1 Related registers (1) Interrupt control register V2 Table 2.4.1 shows the interrupt control register V2. Set the contents of this register through register A with the T V2A i nstruction. In addition, the T AV2 i nstruction can be used to transfer the contents of register V2 to register A. Table 2.4.1 Interrupt control register V2 Interrupt control register V2 V2 3 V2 2 V2 1 V2 0 Serial I/O interrupt enable bit (Note 2 ) A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit at reset : 0000 2 0 1 0 1 0 1 0 1 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt at RAM back-up : 0000 2 R/W disabled ( SNZSI i nstruction is valid) enabled ( SNZSI i nstruction is invalid) disabled ( SNZAD i nstruction is valid) enabled (SNZAD instruction is invalid) disabled ( SNZT4 i nstruction is valid) enabled ( SNZT4 instruction is invalid) disabled ( SNZT3 i nstruction is valid) enabled ( SNZT3 instruction is invalid) (Note 2 ) (Note 2) (Note 2) (Note 2) Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. 3: W hen setting the A/D converter, V2 3 , V2 1 a nd V2 0 a re not used. (2) A/D control register Q1 Table 2.4.2 shows the A/D control register Q1. Set the contents of this register through register A with the T Q1A i nstruction. In addition, the T AQ1 i nstruction can be used to transfer the contents of register Q1 to register A. Table 2.4.2 A/D control register Q1 A/D control register Q1 Q13 A/D operation mode control bit at reset : 0000 2 0 at RAM back-up : state retained R/W A/D conversion mode Analog input pins Q12 1 Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 Q11 Analog input pin selection bits 0 1 1 Q10 1 1 1 1 AIN7 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: I n order to select A IN7 – A IN0 , set register Q1 after setting regsiter Q2. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-53 APPLICATION 4519 Group 2.4 A/D converter (3) A/D control register Q2 Table 2.4.3 shows the A/D control register Q2. Set the contents of this register through register A with the T Q2A i nstruction. The contents of register Q2 is transferred to register A with the T AQ2 i nstruction. Table 2.4.3 A/D control register Q2 A/D control register Q2 Q23 Q22 Q21 Q20 P23/AIN3 pin function selection bit P6 2/A IN2, P6 3 /A IN3 p in function selection bit P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W P4 0, P 4 1, P 4 2 , P 43 A IN4, A IN5, A IN6, A IN7 P6 2, P63 A IN2, AIN3 P6 1 AIN1 P6 0 AIN0 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. (4) A/D control register Q3 Table 2.4.4 shows the A/D control register Q3. Set the contents of this register through register A with the T Q3A i nstruction. The contents of register Q3 is transferred to register A with the T AQ3 i nstruction. Table 2.4.4 A/D control register Q3 A/D control register Q3 Q33 Q32 Not used A/D converter operation clock selection bit at reset : 0000 2 0 1 0 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Instruction clock (INSTCK) Q31 Q3 0 1 0 Frequency divided by 24 1 1 Frequency divided by 48 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: I n order to select A IN7– A IN4, set register Q1 after setting regsiter Q3. 2.4.2 A/D converter application examples (1) A/D conversion mode Outline: A nalog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 p in for this analog input. Figure 2.4.2 shows the A/D conversion mode setting example. A/D converter operation clock division ratio selection bits On-chip oscillator (f(RING)) 1 Q31 Q30 Division ratio 0 0 Frequency divided by 6 0 1 Frequency divided by 12 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-54 APPLICATION 4519 Group 2.4 A/D converter ➀ D isable Interrupts A/D interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 0 b3 b0 All interrupts disabled [ DI ] 0 ✕ ✕ b2: A/D interrupt occurrence disabled [ TV2A ] ✕ ↓ ➁ S et A/D Converter A/D conversion mode is selected to A/D operation mode. Analog input pin A IN0 i s selected. Instruction clock/6 is selected for A/D converter operation clock. b3 b0 A/D control register Q2 A/D control register Q1 A/D control register Q3 ✕ b3 ✕ 0 0 ✕ 0 0 1 b0 b0: A IN0 p in function selected [ TQ2A ] b3: A/D conversion selected b2-b0: A IN0 s elected [ TQ1A ] [ TQ3A ] b2: A/D converter operation clock: Instruction clock b1, b0: Frequency divided by 6 is selected for A/D converter operation clock 0 b3 0 b0 ✕ 0 ↓ ➂ C lear Interrupt Request A/D interrupt activated condition is cleared. A/D conversion completion flag ADF 0 A/D interrupt activated condition cleared [ SNZAD ] ↓ ( Note when the interrupt request is cleared When ➂ i s executed, considering the skip of the next instruction according to the flag ADF, insert the N OP i nstruction after the S NZAD i nstruction. ↓ When interrupt is not used ➃ S et Interrupt Interrupts except A/D conversion is enabled. [ EI ] ↓ ) ↓ When interrupt is used ➃ S et Interrupt A/D interrupt temporarily disabled is enabled. b3 b0 Interrupt control register V2 ✕ 1 ✕ ✕ b2: A/D interrupt occurrence enabled [ TV2A ] Interrupt enable flag INTE All interrupt enabled [ EI ] 1 ↓ ↓ ➄ S tart A/D Conversion A/D conversion operation is started [ ADST ] ↓ ↓ When interrupt is not used ➅ C heck A/D Interrupt Request A/D conversion completion flag is checked [SNZAD] ↓ When interrupt is used ➅ A /D Interrupt Occurs ↓ ↓ ➆ E xecute A/D Conversion High-order 8 bits of register AD Low-order 2 bits of register AD → → ↓ ↓ Register A and register B [ TABAD ] High-order 2 bits of register A [ TALA ] “ 0 ” i s set to low-order 2 bits of register A ↓ When A/D conversion is executed by the same channel, repeat ➄ t o ➆ . When A/D conversion is executed by another channel, repeat ➀ t o ➆ . “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.4.2 A/D conversion mode setting example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-55 APPLICATION 4519 Group 2.4 A/D converter 2.4.3 Notes on use (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µ F) to analog input pins. Figure 2.4.3 shows the analog input external circuit example-1. When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 2.4.4. In addition, test the application products sufficiently. Sensor AIN Sensor About 1kΩ AIN Apply the voltage withiin the specifications to an analog input pin. Fig. 2.4.4 Analog input external circuit example-2 Fig. 2.4.3 Analog input external circuit example-1 (3) Notes for the use of A/D conversion 2 Do not change the operating mode of the A/D converter by bit 3 of register Q1 during A/D conversion (A/D conversion mode and comparator mode). (4) Notes for the use of A/D conversion 3 When the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode with bit 3 of register Q1 in a program, be careful about the following notes. • C lear bit 2 of register V2 to “ 0 ” t o change the operating mode of the A/D converter from the comparator mode to the A/D conversion mode (refer to Figure 2.4.5 ➀). • T he A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to bit 3 of register Q1, and execute the S NZAD i nstruction to clear the ADF flag to “ 0 ” . • • • Clear bit 2 of register V2 to “ 0 ” ....... ➀ ↓ Change of the operating mode of the A/D converter from the comparator mode to the A/D conversion mode ↓ Clear the ADF flag to “ 0 ” w ith the S NZAD i nstruction ↓ Execute the N OP i nstruction for the case when a skip is performed with the S NZAD i nstruction • • • Fig. 2.4.5 A/D converter operating mode program example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-56 APPLICATION 4519 Group 2.4 A/D converter (5) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “ 0, ” n ot set to “ 1. ” In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 2 machine cycles + A/D conversion clock (ADCK) 1 clock. (6) Analog input pins When P4 0/AIN4–P43/AIN7, P60/AIN0–P63/AIN3 are set to pins for analog input, they cannot be used as I/O ports P4 and P6. (7) TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “ 0. ” (8) Recommended operating conditions when using A/D converter As for the supply voltage when A/D converter is used and the recommended operating condition of the A/D convesion clock frequency, refer to the “ 3.1 Electrical characteristics ” . Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-57 APPLICATION 4519 Group 2.5 Serial I/O 2.5 Serial I/O The 4519 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes. 2.5.1 Serial I/O functions Serial I/O consists of the serial I/O register SI, serial I/O control register J1, serial I/O transmit/receive completion flag SIOF and serial I/O counter. A clock-synchronous serial I/O uses the shift clock generated by the clock control circuit as a synchronous clock. Accordingly, the data transmit and receive operations are synchronized with this shift clock. In transmit operation, data is transmitted bit by bit from the SOUT pin synchronously with the falling edges of the shift clock. In receive operation, data is received bit by bit from the SIN pin synchronously with the rising edges of the shift clock. Note: 4 519 Group only supports LSB-first transmit and receive. s Shift clock When using the internal clock of 4519 Group as a synchronous clock, eight shift clock pulses are output from the S CK pin when a transfer operation is started. Also, when using some external clock as a synchronous clock, the clock that is input from the S CK p in is used as the shift clock. Data transfer rate (baudrate) When using the internal clock, the data transfer rate can be determined by selecting the instruction clock divided by 2, 4 or 8. When using an external clock, the clock frequency input to the SCK pin determines the data transfer rate. s Figure 2.5.1 shows the serial I/O block diagram. 1/8 1/4 INSTCK SCK 1/2 J13J12 00 01 10 11 Synchronous circuit Serial I/O counter (3) SIOF Serial I/O interrupt P20/SCK Q S R SST instruction Internal reset signal P21/SOUT SOUT P22/SIN SIN MSB Serial I/O register (8) LSB TABSI J11 J10 TSIAB TABSI Register B (4) Register A (4) Fig. 2.5.1 Serial I/O block diagram Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-58 APPLICATION 4519 Group 2.5 Serial I/O 2.5.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the T SIAB i nstruction. Also, the low-order 4 bits of register SI is transferred to register A, and the high-order 4 bits of register SI is transferred to register B with the T ABSI i nstruction. (2) Serial I/O transmit/receive completion flag (SIOF) Serial I/O transmit/receive completion flag (SIOF) is set to “ 1 ” w hen serial data transmit or receive operation completes. The state of SIOF flag can be examined with the skip instruction ( SNZSI ). (3) Interrupt control register V2 Table 2.5.1 shows the interrupt control register V2. Set the contents of this register through register A with the T V2A i nstruction. In addition, the T AV2 i nstruction can be used to transfer the contents of register V2 to register A. Table 2.5.1 Interrupt control register V2 Interrupt control register V2 V23 V22 V21 V20 Notes Timer 4, serial I/O interrupt enable bit at reset : 00002 0 1 at RAM back-up : 0000 2 R/W Interrupt disabled ( SNZSI i nstruction is valid) Interrupt enabled ( SNZSI i nstruction is invalid) (Note 0 Interrupt disabled ( SNZAD i nstruction is valid) A/D interrupt enable bit 1 Interrupt enabled (SNZAD instruction is invalid) (Note 0 Interrupt disabled ( SNZT4 i nstruction is valid) Timer 4 interrupt enable bit Interrupt enabled ( SNZT4 instruction is invalid) (Note 1 Interrupt disabled ( SNZT3 i nstruction is valid) 0 Timer 3 interrupt enable bit Interrupt enabled ( SNZT3 instruction is invalid) (Note 1 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: T hese instructions are equivalent to the N OP i nstruction. 3: W hen setting the serial I/O, V2 2, V2 1 a nd V2 0 a re not used. 2) 2) 2) 2) (4) Serial I/O mode register J1 Table 2.5.2 shows the serial I/O mode register J1. Set the contents of this register through register A with the T J1A i nstruction. In addition, the T AJ1 i nstruction can be used to transfer the contents of register J1 to register A. Table 2.5.2 Serial I/O mode register J1 Serial I/O control register J1 at reset : 00002 at RAM back-up : state retained R/W J13 J12 J1 1 J1 0 Note: J13 J1 2 Synchronous clock 0 0 Instruction clock (INSTCK) divided by 8 Serial I/O synchronous clock 0 1 Instruction clock (INSTCK) divided by 4 selection bits 1 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (S CK i nput) J11 J1 0 Port function Serial I/O port function selection 0 0 P20, P2 1, P2 2 s elected/SCK, SOUT, S IN n ot 0 1 SCK, SOUT, P2 2 s elected/P20, P2 1, S IN n ot bits 1 0 SCK, P2 1, S IN s elected/P2 0, S OUT, P2 2 n ot 1 1 SCK, SOUT, S IN s elected/P20, P2 1, P2 2 n ot “ R ” r epresents read enabled, and “ W ” r epresents write enabled. selected selected selected selected Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-59 APPLICATION 4519 Group 2.5 Serial I/O 2.5.3 Operation description Figure 2.5.2 shows the serial I/O connection example, Figure 2.5.3 shows the serial I/O register state, and Figure 2.5.4 shows the serial I/O transfer timing. Master (internal clock selected) 4519 D3 SCK SOUT SIN Slave (external clock selected) 4519 Control signal D3 SCK SIN SOUT Note: The control signal is used to inform the master by the pin level that the slave is in a ready state to receive. The 4524 Group does not have a control pin exclusively used for serial I/O. Accordingly, if a control signal is required, use the normal input/output ports. Fig. 2.5.2 Serial I/O connection example Master (M7–M0 : transmit data) SIN pin Slave (S7–S0: transmit data) SOUT pin Serial I/O register (SI) M7 M6 M5 M4 M3 M2 M1 M0 SOUT pin SIN pin Serial I/O register (SI) S7 S6 S5 S4 S3 S2 S1 S0 Transmit data set Transfer start S7 S6 S5 S4 S3 S2 S1 S0 * M7 M6 M5 M4 M3 M2 M1 Falling of clock * S7 S6 S5 S4 S3 S2 S1 S0 M7 M6 M5 M4 M3 M2 M1 Rising of clock M0 S7 S6 S5 S4 S3 S2 S1 * S0 M7 M6 M5 M4 M3 M2 Falling of clock * M0 S7 S6 S5 S4 S3 S2 S7 S6 S5 S4 S3 S2 S1 S0 Transfer complete M7 M6 M5 M4 M3 M2 M1 M0 Fig. 2.5.3 Serial I/O register state when transfer Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-60 APPLICATION 4519 Group 2.5 Serial I/O Master SOUT SIN SST instruction M7’ S7’ M0 S0 M1 S1 M2 S2 M3 S3 M4 S4 M5 S5 M6 S6 M7 S7 SCK Slave SST instruction Control signal SOUT SIN S7’ M7’ S0 M0 S1 M1 S2 M2 S3 M3 S4 M4 S5 M5 S6 M6 S7 M7 M0–M7: Contents of master serial I/O register S0–S7: Contents of slave serial I/O register Rising of SCK: Serial input Falling of SCK: Serial output M7’, S7’: Contents of previous master, slave MSB Fig. 2.5.4 Serial I/O transfer timing Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-61 APPLICATION 4519 Group 2.5 Serial I/O The full duplex communication of master and slave is described using the connection example shown in Figure 2.5.2. (1) Transmit/receive operation of master ➀ S et the transmit data to the serial I/O register SI with the T SIAB i nstruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order 4 bits of register SI and the contents of register B are transferred to the high-order 4 bits of register SI. ➁ C heck whether the microcomputer on the slave side is ready to transmit/receive or not. In the connection example in Figure 2.5.2, check that the input level of control signal is “L” level. ➂ S tart serial transmit/receive with the S ST i nstruction. When the S ST i nstruction is executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to “ 0. ” ➃ T he transmit data is output from the S OUT p in synchronously with the falling edges of the shift clock. ➄ T he transmit data is output bit by bit beginning with the LSB of register SI. Each time one bit is output, the contents of register SI is shifted one bit position toward the LSB. ➅ A lso, the receive data is input from the S IN p in synchronously with the rising edges of the shift clock. ➆ T he receive data is input bit by bit to the MSB of register SI. ➇ A s erial I/O interrupt request occurs when the transmit/receive data is completed, and the SIOF flag is set to “ 1. ” ➈ The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in after examining the completion of the transmit/receive operation with the SNZSI instruction without using an interrupt. Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed. Notes 1: R epeat steps ➀ t hrough ➈ t o transmit/receive multiple data in succession. 2: F or the program on the master side, start to transmit the next data at the next timing (control signal turns “ L ” ). Do not start to transmit the next data during the previous data transfer (control signal = “ L ” ). Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-62 APPLICATION 4519 Group 2.5 Serial I/O (2) Transmit/receive operation of slave ➀ S et the transmit data into the serial I/O register SI with the T SIAB i nstruction. When the T SIAB i nstruction is executed, the contents of register A are transferred to the loworder bits of register SI and the contents of register B are transferred to the high-order bits of register SI. At this time, the S CK p in must be at the “ H ” l evel. ➁ Start serial transmit/receive with the SST instruction. However, in Figure 2.5.2 where an external clock is selected, transmit/receive is not started until the clock is input. When the SST instruction is executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to “ 0. ” ➂ T he microcomputer on the master side is informed that the receiving side is ready to receive. In the connection example in Figure 2.5.2, the control signal “ L ” l evel is output. ➃ T he transmit data is output from the SOUT p in synchronously with the falling edges of the shift clock. ➄ T he transmit data is output bit by bit beginning with the LSB of register SI. Each time one bit is output, the contents of register SI are shifted to one bit position toward the LSB. ➅ A lso, the receive data is input from the S IN p in synchronously with the rising edges of the shift clock. ➆ T he receive data is input bit by bit to the MSB of register SI. ➇ A s erial I/O interrupt request occurs when the transmit/receive is completed, and the SIOF flag is set to “ 1. ” ➈ Read the receive data within the serial I/O interrupt service routine; or read the data after examining the completion of the transmit/receive operation with the SNZSI instruction without using an interrupt. Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed. ➉ S et the control signal pin level to “ H ” a fter the receive operation is completed. Note: R epeat steps ➀ t hrough ➉ t o transmit/receive multiple data in succession. 2.5.4 Serial I/O application example (1) Serial I/O Outline: T he 4519 Group can communicate with peripheral ICs. Specifications: F igure 2.5.2 Serial I/O connection example. Figure 2.5.5 shows the setting example when a serial I/O interrupt of master side is not used, and Figure 2.5.6 shows the slave serial I/O setting example. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-63 APPLICATION 4519 Group 2.5 Serial I/O ➀ D isable Interrupts ( Note ) Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 ➁ S et Port Port for control signal is set to input. 0 b3 b0 All interrupts disabled [ DI ] ✕ ✕ ✕ b3: Serial I/O interrupt occurrence disabled [ TV2A ] 0 ↓ b3 b0 Register Y Port D 3 o utput latch Port output structure control register FR1 ➂ S et Serial I/O 0 1 b3 0 1 1 b0 0 ✕ ✕ ✕ Specify bit position of port D [ TYA ] Set to input [ SD ] [ TFR1A ] b3: Port D 3 N -channel open-drain output selected ↓ b3 b0 Serial I/O control regsiter JI 0 1 1 1 [ TJ1A ] b3, b2: Instruction clock divided by 4 is selected for synchronous clock b1, b0: Serial I/O ports S CK , S OUT , S IN s elected ↓ ➃ C lear Interrupt Request Serial I/O interrupt activated condition is cleared. Serial I/O transmit/receive completion flag SIOF 0 Serial I/O interrupt activated condition cleared [ SNZSI] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the flag SIOF, insert the N OP i nstruction after the S NZSI i nstruction. ↓ ➄ S et Interrupts ( Note ) Interrupts except serial I/O interrupt is enabled. [ EI ] ) ↓ ➅ S et Transmit Data Transmit data is set to serial I/O register. Serial I/O register SI ✕✕ 16 [ TSIAB ] ↓ ~ C heck Start Condition of Serial I/O Operation Whether the transmit/receive of the slave side can be performed (pin level of control signal = “ L ” ) or not is checked. b3 b0 Register Y Port D 3 o utput latch Port D 3 i nput level check 0 1 0 1 1 Specify bit position of port D [ TYA ] Set to input [ SD ] [ SZD ] ↓ ➇ S tart Serial I/O Operation If the transmit/receive of the slave side can be performed, serial transfer is started. [ SST ] ↓ ➈ C heck Serial I/O Interrupt Request SIOF flag is checked. [ SNZSI ] ↓ ➉ R eceive Data Processing Data processing received by serial transfer is executed. Register SI → r egister A, register B [ TABSI ] ↓ When serial communication is executed, repeat ➅ t o ➉ . “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.5.5 Setting example when a serial I/O of master side is not used Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-64 APPLICATION 4519 Group 2.5 Serial I/O ➀ D isable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 ➁ S et Port Port for control signal is set to “ H ” o utput. 0 b3 b0 All interrupts disabled [ DI ] ✕ ✕ ✕ b3: Serial I/O interrupt occurrence disabled [ TV2A ] 0 ↓ b3 b0 Register Y Port D 3 o utput latch Port output structure control register FR1 ➂ S et Serial I/O 0 1 b3 0 1 1 b0 Specify bit position of port D [ TYA ] Set to “ H ” o utput [ SD ] b3: Port D 3 C MOS output selected 1 ✕ ✕ ✕ ↓ b3 b0 Serial I/O control regsiter JI 1 1 1 1 [ TJ1A ] b3, b2: External clock is selected for synchronous clock b1, b0: Serial I/O ports S CK , S OUT , S IN s elected ↓ ➃ C lear Interrupt Request Serial I/O interrupt activated condition is cleared. Serial I/O transmit/receive completion flag SIOF 0 Serial I/O interrupt activated condition cleared [ SNZSI] ↓ ( Note when the interrupt request is cleared When ➃ i s executed, considering the skip of the next instruction according to the flag SIOF, insert the N OP i nstruction after the S NZSI i nstruction. ↓ ➄ S et Interrupts The Serial I/O interrupt which is temporarily disabled is enabled. b3 b0 ) Interrupt control register V2 Interrupt enable flag INTE 1 1 ✕ ✕ ✕ b3: Serial I/O interrupt occurrence enabled [ TV2A ] All interrupts enabled [ EI ] ↓ ➅ S et Transmit Data Transmit data is set to serial I/O register. Serial I/O register SI ✕✕16 [ TSIAB ] ↓ ~ S et Start of Serial I/O Operation Serial I/O operation enabled state (serial transfer started, control signal “ L ” l evel output) is set. Serial transfer start [ SST ] b3 b0 Register Y Port D 3 o utput latch 0 0 0 1 1 Specify bit position of port D [ TYA ] Set to “ L ” o utput [ RD ] ↓ Serial transmit/receive by clock of master side : : ↓ ➇ Receive Data Processing by Serial I/O interrupt Serial I/O operation disabled state (control signal “H” level output) is set and received data processing is performed.. b3 b0 Register Y Port D 3 o utput latch Register SI 00 1 → 1 1 Specify bit position of port D [ TYA ] Set to “ H ” o utput [ SD ] register A, register B [ TABSI ] ↓ When serial communication is executed, repeat ➅ t o ➇ . “ ✕ ” : it can be “ 0 ” o r “ 1. ” “ [ ] ” : instruction Fig. 2.5.6 Setting example when a serial I/O interrupt of slave side is used Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-65 APPLICATION 4519 Group 2.5 Serial I/O 2.5.5 Notes on use (1) Note when an external clock is used as a synchronous clock: • A n external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transmit/receive is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transmit/receive is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally. Note also that the SIOF flag is set to “ 1 ” w hen a clock is counted 8 times. • B e sure to set the initial input level on the external clock pin to “ H ” l evel. • R efer to section “ 3.1 Electrical characteristics ” w hen using serial I/O with an external clock. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-66 APPLICATION 4519 Group 2.6 Reset 2.6 Reset System reset is performed by applying “ L ” l evel to t he RESET p in for 1 machine cycle or more when the following conditions are satisfied: q t he value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “ H ” l evel is applied to R ESET p in, the program starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time (On-chip oscillator (internal oscillator) clock is counted for 120 to 144 times). Figure 2.6.2 shows the structure of reset pin and its peripherals, and power-on reset operation. 2.6.1 Reset circuit The 4519 Group has the voltage drop detection circuit. (1) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “ L ” l evel to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions. 100 µs or less VDD (Note 3) Pull-up transistor (Note 1) (Note 2) Power-on reset circuit output RESET pin Internal reset signal Power-on reset circuit (Note 1) SRST instruction Voltage drop detection circuit Watchdog reset signal WEF Internal reset signal Reset state Power-on Reset released Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 2.6.1 Structure of reset pin and its peripherals, and power-on reset operation Reset input = On-chip oscillator (internal oscillator) is 1 machine cycle or more counted 120 to 144 times. 0.85VDD RESET 0.3VDD Program starts (address 0 in page 0) (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 2.6.2 Oscillation stabilizing time after system is released from reset Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-67 APPLICATION 4519 Group 2.6 Reset 2.6.2 Internal state at reset Figure 2.6.3 and Figure 2.6.4 show the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.6.3 and Figure 2.6.4 are undefined, so that set them to initial values. 000000 • P rogram counter (PC) ................................................................................. 0 0 0 0 0 0 0 0 Address 0 in page 0 is set to program counter. 0 • I nterrupt enable flag (INTE) ....................................................................... (Interrupt disabled) 0 • P ower down flag (P) ................................................................................... 0 • E xternal 0 interrupt request flag (EXF0) .................................................. 0 • E xternal 1 interrupt request flag (EXF1) .................................................. 0000 • I nterrupt control register V1 ....................................................................... (Interrupt disabled) 0000 • I nterrupt control register V2 ....................................................................... (Interrupt disabled) 0000 • I nterrupt control register I1 ......................................................................... 0000 • I nterrupt control register I2 ......................................................................... 0 • I nterrupt control register I3 ......................................................................... 0 • T imer 1 interrupt request flag (T1F) ......................................................... 0 • T imer 2 interrupt request flag (T2F) ......................................................... 0 • T imer 3 interrupt request flag (T3F) ......................................................... 0 • T imer 4 interrupt request flag (T4F) ......................................................... 0 • W atchdog timer flags (WDF1, WDF2) ...................................................... 1 • W atchdog timer enable flag (WEF) ........................................................... 0 • T imer control register PA ........................................................................... (Prescaler stopped) 0000 • T imer control register W1 ........................................................................... (Timer 1 stopped) 0000 • T imer control register W2 ........................................................................... (Timer 2 stopped) 0000 • T imer control register W3 ........................................................................... (Timer 3 stopped) 0000 • T imer control register W4 ........................................................................... (Timer 4 stopped) 0000 • T imer control register W5 ........................................................................... 0000 • T imer control register W6 ........................................................................... (Period measurement circuit) 1111 • C lock control register MR ........................................................................... 0 • S erial I/O transmit/receive completion flag (SIOF) ................................. 0000 • S erial I/O mode register J1 ........................................................................ (External clock selected, serial I/O port not selected) ✕✕✕✕✕✕✕✕ • S erial I/O register SI ................................................................................... 0 • A /D conversion completion flag (ADF) ..................................................... 0000 • A /D control register Q1 ............................................................................... 0000 • A /D control register Q2 ............................................................................... 0000 • A /D control register Q3 ............................................................................... ✕✕✕✕✕✕✕✕✕✕ • S uccessive comparison register AD .......................................................... ✕✕✕✕✕✕✕✕ • C omparator register ..................................................................................... Fig. 2.6.3 Internal state at reset “ ✕ ” r epresents undefined. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-68 APPLICATION 4519 Group 2.6 Reset • K ey-on wakeup control register K0 ........................................................... 0000 • K ey-on wakeup control register K1 ........................................................... 0000 • K ey-on wakeup control register K2 ........................................................... 0000 • P ull-up control register PU0 ....................................................................... 0000 • P ull-up control register PU1 ....................................................................... 0000 • P ort output structure control register FR0 ............................................... 0000 • P ort output structure control register FR1 ............................................... 0000 • P ort output structure control register FR2 ............................................... 0000 • P ort output structure control register FR3 ............................................... 0000 • C arry flag (CY) ............................................................................................. 0 • R egister A ..................................................................................................... 0000 • R egister B ..................................................................................................... 0000 • R egister D ..................................................................................................... ✕✕✕ ✕✕✕ ✕ ✕ ✕ ✕ ✕ • R egister E ..................................................................................................... • R egister X ..................................................................................................... 0000 • R egister Y ..................................................................................................... 0000 • R egister Z ..................................................................................................... ✕✕ • S tack pointer (SP) ....................................................................................... 111 • O peration source clock ............................ On-chip oscillator (operating) • C eramic resonator circuit ........................................................... Operating • Q uartz-crystal oscillation circuit ......................................................... Stop • R C oscillation circuit ............................................................................ Stop “✕ ” r epresents undefined. Fig. 2.6.4 Internal state at reset 2.6.3 Notes on use (1) Register initial value The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. • R egister Z (2 bits) • R egister D (3 bits) • R egister E (8 bits) (2) Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS a t the shortest distance, and input “ L ” l evel to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions. Refer to section “3.1 Electrical characteristics” for the reset voltage of the recommended operating conditions. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-69 APPLICATION 4519 Group 2.7 Voltage drop detection circuit 2.7 Voltage drop detection circuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.7.1 shows the voltage drop detection circuit, and Figure 2.7.2 shows the operation waveform example of the voltage drop detection circuit. Table 2.7.1 shows the voltage drop detection circuit operation state. Refer to section “ 3.1 Electrical characteristics ” for the reset voltage of the voltage drop detection circuit. VDCE VRST + VRST - – + Voltage drop detection circuit Reset signal Voltage drop detection circuit Fig. 2.7.1 Voltage drop detection circuit VRST (reset release voltage) VRST -(reset voltage) + VDD Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 120 to 144 times. RESET pin Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ). Fig. 2.7.2 Voltage drop detection circuit operation waveform example Table 2.7.1 Voltage drop detection circuit operation state VDCE pin At CPU operating At RAM back-up “L” Invalid Invalid “H” Valid Valid Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-70 APPLICATION 4519 Group 2.8 RAM back-up 2.8 RAM back-up The 4519 Group has the RAM back-up mode. Figure 2.8.1 shows the state transition. A Operation state Reset (Note 1) • Operation source clock: f(RING) • f(XIN): Stop MR1←1 (Note 5) Key-on wakeup E RAM back-up mode POF instruction execution (Note 4) (Note 2) MR1←0 B Operation state • Operation source clock: f(RING) • f(XIN): Operating (Note 3) MR0←0 MR0←1 POF instruction execution (Note 4) Operation state • Operation source clock: f(XIN) • f(RING): Operating RG0←0 RG0←1 POF instruction execution (Note 4) C D Operation state • Operation source clock: f(XIN) • f(RING): Stop POF instruction execution (Note 4) f(RING): stop f(XIN): stop Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times. 2: The f(XIN) oscillation circuit (ceramic resonance, RC oscillation or quartz-crystal oscillation) is selected by the CMCK, CRCK or CYCK instruction (the start of oscillation and the operation source clock is not switched by these instructions). The start/stop of oscillation and the operation source is switched by register MR. Surely, select the f(XIN) oscillation circuit by executing the CMCK, CRCK or CYCK instruction before clearing MR1 to “0”. MR1 cannot be cleared to “0” when the oscillation circuit is not selected. 3: Generate the wait time by software until the oscillation is stabilized, and then, switch the system clock. 4: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 5: System returns to state A certainly when returning from the RAM back-up mode. However, the selected contents (CMCK, CRCK, CYCK instruction execution state) of f(XIN) oscillation circuit is retained. Fig. 2.8.1 State transition 2.8.1 RAM back-up mode The system goes into RAM back-up mode when the P OF i nstruction is executed immediately after the EPOF i nstruction is executed. Table 2.8.1 shows the function and state retained at RAM back-up mode. Also, Table 2.8.2 shows the return source from this state. (1) RAM back-up mode As oscillation stops with RAM and the state of reset circuit retained, current dissipation can be reduced without losing the contents of RAM. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-71 APPLICATION 4519 Group 2.8 RAM back-up Table 2.8.1 Functions and states retained at RAM back-up mode Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selected oscillation circuit Clock control register MR Timer 1 to timer 4 functions Watchdog timer function Timer control registers PA, W4 Timer control registers W1 to W3, W5, W6 Serial I/O function Serial I/O control register J1 A/D function A/D control registers Q1 to Q3 Voltage drop detection circuit Port level Pull-up control registers PU0, PU1 Key-on wakeup control registers K0 to K2 Port output format control registers FR0 to FR3 External interrupt request flags (EXF0, EXF1) Timer interrupt request flags (T1F to T4F) A/D conversion completion flag (ADF) Serial I/O transmit/receive completion flag SIOF Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) RAM back-up ✕ O ✕ O O O (Note 3 ) ✕ ( Note 4 ) ✕ O ✕ O ✕ O O (Note 5 ) O O O O ✕ (Note 3 ) ✕ ✕ ✕ ✕ ( Note 4 ) ✕ ( Note 4 ) Notes 1: “O” represents that the function can be retained, and “ ✕” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: T he stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: T he state of the timer is undefined. 4: I nitialize the watchdog timer flag WDF1 with the W RST i nstruction, and then go into the RAM back-up state. 5: T he valid/invalid of the voltage drop detection circuit can be controlled only by VDCE pin. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-72 APPLICATION 4519 Group 2.8 RAM back-up Table 2.8.2 Return source and return condition Return source Return condition Ports P0 0 – P0 3 Return by an external “H” level or “L” level input, or rising edge (“L”→“H”) or falling edge (“H” →“L”). Remarks The key-on wakeup function can be selected with 2 port units. Select the return level (“L” level or “H” level), and return condition (return by level or edge) with the register K1 according to the external state before going into the RAM back-up state. External wakeup signal Ports P1 0 – P1 3 Return by an external “L” level The key-on wakeup function can be selected with 2 input. port units. Set the port using the key-on wakeup function to “H” level before going into the RAM back-up state. INT0 Return by an external “H” level Select the return level (“L” level or “H” level) with the INT1 or “L” level input, or rising edge registers I1 and I2 according to the external state, and ( “ L ” → “ H ” ) o r f a l l i n g e d g e return condition (return by level or edge) with the register (“H” →“L”). K2 before going into the RAM back-up state. The external interrupt request flags (EXF0, EXF1) are not set. (3) Start condition identification When system returns from both RAM back-up mode and reset, program is started from address 0 in page 0. The start condition (warm start or cold start) can be identified by examining the state of the power down flag (P) with the S NZP i nstruction. Table 2.8.3 shows the start condition identification, and Figure 2.8.4 shows the start condition identified example. Table 2.8.3 Start condition identification Warm start Cold start (Reset) Start condition External wakeup signal input Reset pulse input to RESET pin Reset by watchdog timer Reset by voltage drop detection circuit SRST instruction execution P flag 1 0 Timer 5 interrupt request flag 0 0 Program start Yes P = “1” ? No Cold start Warm start Fig. 2.8.2 Start condition identified example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-73 APPLICATION 4519 Group 2.8 RAM back-up 2.8.2 Related registers (1) Interrupt control register I1 Table 2.8.4 shows the interrupt control register I1. Set the contents of this register through register A with the T I1A i nstruction. In addition, the T AI1 i nstruction can be used to transfer the contents of register I1 to register A. Table 2.8.4 Interrupt control register I1 Interrupt control register I1 I1 3 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/return level selection bit (Note 2 ) I1 1 I1 0 INT0 pin edge detection circuit control bit at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W INT0 pin input disabled INT0 pin input enabled Falling waveform/ “ L ” l evel ( “ L ” l evel is recognized with the S NZI0 i nstruction) Rising waveform/ “ H ” l evel ( “ H ” l evel is recognized with the S NZI0 i nstruction) One-sided edge detected Both edges detected I1 2 Timer 1 count start synchronous circuit not selected INT0 pin Timer 1 count start 0 Timer 1 count start synchronous circuit selected synchronous circuit selection bit 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: W hen the contents of I12 a nd I1 3 a re changed, the external interrupt request flag EXF0 may be set to “1”. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the S NZ0 i nstruction. 3: W hen setting the RAM back-up, I11 – I1 0 a re not used. (2) Interrupt control register I2 Table 2.8.5 shows the interrupt control register I2. Set the contents of this register through register A with the T I2A i nstruction. In addition, the T AI2 i nstruction can be used to transfer the contents of register I2 to register A. Table 2.8.5 Interrupt control register I2 Interrupt control register I2 I2 3 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/return level selection bit (Note 2 ) I2 1 I2 0 INT1 pin edge detection circuit control bit at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W INT1 pin input disabled INT1 pin input enabled Falling waveform/ “ L ” l evel ( “ L ” l evel is recognized with the S NZI1 i nstruction) Rising waveform/ “ H ” l evel ( “ H ” l evel is recognized with the S NZI1 i nstruction) One-sided edge detected Both edges detected I2 2 Timer 3 count start synchronous circuit not selected INT1 pin Timer 3 count start 0 Timer 3 count start synchronous circuit selected synchronous circuit selection bit 1 Notes 1: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. 2: W hen the contents of I2 2 a nd I23 a re changed, the external interrupt request flag EXF1 may be set to “1”. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V1 1) of register V1 to “0”. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is performed with the S NZ1 i nstruction. 3: W hen setting the RAM back-up, I21 – I2 0 a re not used. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-74 APPLICATION 4519 Group 2.8 RAM back-up (3) Pull-up control register PU0 Table 2.8.6 shows the pull-up control register PU0. Set the contents of this register through register A with the T PU0A i nstruction. The contents of register PU0 is transferred to register A with the T APU0 i nstruction. Table 2.8.6 Pull-up control register PU0 Pull-up control register PU0 PU0 3 PU0 2 PU0 1 PU0 0 P03 p in pull-up transistor control bit P02 p in pull-up transistor control bit P01 p in pull-up transistor control bit P00 p in at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF pull-up transistor control bit Pull-up transistor ON 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-75 APPLICATION 4519 Group 2.8 RAM back-up (4) Pull-up control register PU1 Table 2.8.7 shows the pull-up control register PU1. Set the contents of this register through register A with the T PU1A i nstruction. The contents of register PU1 is transferred to register A with the T APU1 i nstruction. Table 2.8.7 Pull-up control register PU1 Pull-up control register PU1 PU13 PU12 PU11 PU10 P1 3 p in pull-up transistor control bit P1 2 p in pull-up transistor control bit P1 1 p in pull-up transistor control bit P1 0 p in at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF 0 pull-up transistor control bit Pull-up transistor ON 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. (5) Key-on wakeup control register K0 Table 2.8.8 shows the key-on wakeup control register K0. Set the contents of this register through register A with the T K0A i nstruction. The contents of register K0 is transferred to register A with the T AK0 i nstruction. Table 2.8.8 Key-on wakeup control register K0 Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup at reset : 0000 2 0 1 0 1 0 1 0 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used control bit Key-on wakeup used 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-76 APPLICATION 4519 Group 2.8 RAM back-up (6) Key-on wakeup control register K1 Table 2.8.9 shows the key-on wakeup control register K1. Set the contents of this register through register A with the T K1A i nstruction. The contents of register K1 is transferred to register A with the T AK1 i nstruction. Table 2.8.9 Key-on wakeup control register K1 Key-on wakeup control register K1 K1 3 K1 2 K1 1 K1 0 Ports P02 and P03 return condition selection bit Ports P02 and P03 valid waveform/level selection bit Ports P01 and P00 return condition selection bit at reset : 0000 2 0 1 0 1 0 1 at RAM back-up : state retained R/W Return by level Return by edge Falling waveform/ “L” level Rising waveform/ “H” level Return by level Return by edge Ports P01 and P00 valid Falling waveform/ “L” level 0 waveform/level selection bit Rising waveform/ “H” level 1 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. (7) Key-on wakeup control register K2 Table 2.8.10 shows the key-on wakeup control register K2. Set the contents of this register through register A with the T K2A i nstruction. The contents of register K2 is transferred to register A with the T AK2 i nstruction. Table 2.8.10 Key-on wakeup control register K2 Key-on wakeup control register K2 K2 3 K2 2 K2 1 K2 0 INT1 pin return condition selection bit INT1 pin key-on wakeup control bit INT0 pin return condition selection bit INT0 pin key-on wakeup control bit at reset : 0000 2 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W Return by level Return by edge Key-on wakeup not used Key-on wakeup used Returned by level Returned by edge Key-on wakeup not used Key-on wakeup used Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-77 APPLICATION 4519 Group 2.8 RAM back-up 2.8.3 Notes on use (1) POF instruction Execute the P OF i nstruction immediately after executing the E POF i nstruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the P OF i nstruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the P OF i nstruction. (2) Key-on wakeup function After checking none of the return condition for ports (P0, P1, INT0 and INT1 specified with register K0 – K2) with valid key-on wakeup function is satisfied, execute the P OF i nstruction. If at least one of return condition for ports with valid key-on wakeup function is satisfied, system returns from the RAM back-upn state immediately after the P OF i nstruction is executed. (3) Return from RAM back-up mode After system returns from RAM back-up mode, set the undefined registers and flags. The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up mode, set initial values. • R egister Z (2 bits) • R egister X (4 bits) • R egister Y (4 bits) • R egister D (3 bits) • R egister E (8 bits) (4) Watchdog timer • T he watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and the W RST i nstruction continuously every system is returned from the RAM back-up. • When the watchdog timer function and RAM back-up function are used at the same time, initialize the flag WDF1 with the W RST i nstruction before system goes into the RAM back-up state. (5) Port P30 /INT0 pin When the RAM back-up mode is used by clearing the bit 3 of register I1 to “0” and setting the input of INT0 pin to be disabled, be careful about the following note. • W hen the input of INT0 pin is disabled (register I1 3 = “ 0 ” ), clear bit 0 of register K2 to “ 0 ” t o invalidate the key-on wakeup before system goes into the RAM back-up mode. (6) Port P31 /INT1 pin When the RAM back-up mode is used by clearing the bit 3 of register I2 to “0” and setting the input of INT1 pin to be disabled, be careful about the following note. • W hen the input of INT1 pin is disabled (register I2 3 = “ 0 ” ), clear bit 2 of register K2 to “ 0 ” t o invalidate the key-on wakeup before system goes into the RAM back-up mode. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-78 APPLICATION 4519 Group 2.9 Oscillation circuit 2.9 Oscillation circuit The 4519 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The 4519 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator, the RC oscillation or quartz-crystal oscillator can be used for the main clock (f(XIN )) of the 4519 Group. The CMCK instruction, CRCK instruction or CYCK instruction is executed to select the ceramic resonator, RC oscillator or quartz-crystal oscillator respectively. 2.9.1 Oscillation operation System clock is supplied to CPU and peripheral device as the base clock for the microcomputer operation. The system clock f(XIN ) or f(RING) is selected by bit 0 of register MR. The oscillation start/stop of main clock f(X IN) is controlled by bit 1 of register MR. Also, an operation mode of a selected clock is selected from the followings by bits 3 and 2 of register MR. • t hrough mode (f(X IN)) (not divided), • f requency divided by 2 mode (f(X IN)/2), • f requency divided by 4 mode (f(X IN)/4), or • f requency divided by 8 mode (f(X IN )/8) Figure 2.9.1 shows the structure of the clock control circuit. Division circuit Divided by 8 MR0 1 RG0 0 Divided by 4 Divided by 2 MR3, MR2 11 10 01 00 System clock (STCK) Internal clock generating circuit (divided by 3) On-chip oscillator (internal oscillator) Instruction clock (INSTCK) S XIN XOUT Ceramic resonance Multiplexer QS RQ CMCK instruction RC oscillation R QS CRCK instruction Quartz-crystal oscillation R QS MR1 QS R EPOF instruction + R Internal reset signal Key-on wakeup signal POF instruction CYCK instruction Fig. 2.9.1 Structure of clock control circuit Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-79 APPLICATION 4519 Group 2.9 Oscillation circuit 2.9.2 Related register (1) Clock control register MR Table 2.9.1 shows the clock control register MR. Set the contents of this register through register A with the T MRA i nstruction. The contents of register MR is transferred to register A with the T AMR i nstruction. Table 2.9.1 Clock control register MR Clock control register MR at reset : 1111 2 MR3 MR2 00 01 10 11 0 1 0 1 at RAM back-up : state retained Operation mode Through-mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock oscillation enabled Main clock oscillation stop Main clock (f(XIN) Sub-clock (f(X CIN)) R/W MR3 Operation mode selection bits MR2 Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit MR 1 MR 0 Note: “ R ” r epresents read enabled, and “ W ” r epresents write enabled. (2) Clock control register RG Table 2.9.2 shows the clock control register RG. Set the contents of this register through register A with the T RGA i nstruction. Table 2.9.2 Clock control register RG Clock control register RG RG0 On-chip oscillator (f(RING)) control bit at reset : 02 0 1 at RAM back-up : state retained W On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-80 APPLICATION 4519 Group 2.9 Oscillation circuit 2.9.3 Notes on use (1) Clock control Execute the main clock (f(X IN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the C MCK , C RCK o r C YCK i nstruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. The CMCK, CRCK or CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. When the C MCK , C RCK o r C YCK i nstructions are never executed, main clock (f(X IN )) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(X IN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN )) selected for the system clock cannot be stopped. (2) On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that margin of frequencies when designing application products. When considering the oscillation stabilize wait time at the switch of clock, be careful that the margin of frequencies of the on-chip oscillator clock. (3) External clock When the external clock signal for the main clock (f(X IN)) is used, connect the clock source to XIN pin and XOUT p in open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1 =0). For this product, when RAM back-up mode and main clock (f(XIN )) stop (MR1 =1), XIN pin is fixed to “H” in order to avoid the through current by floating of internal logic. The XIN pin is fixed to “H” until main clock (f(X IN )) oscillation start to be valid (MR1 =0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to XIN pin in series to limit of current by competitive signal. (4) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 2-81 CHAPTER 3 APPENDIX 3.1 3.2 3.3 3.4 3.5 Electrical characteristics Typical characteristics List of precautions Notes on noise Package outline APPENDIX 4519 Group 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, P6, D0–D7, RESET, XIN, VDCE Input voltage SCK, SIN, CNTR0, CNTR1, INT0, INT1 Input voltage AIN0–AIN7 Output voltage P0, P1, P2, P3, P4, P5, P6, D 0–D7, RESET Output voltage SCK, SOUT, CNTR0, CNTR1 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Ratings –0.3 to 6.5 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V mW °C °C Output transistors in cut-off state Output transistors in cut-off state Ta = 25 °C 42P2R-A Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-2 APPENDIX 4519 Group 3.1 Electrical characteristics 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (when ceramic resonator/on-chip oscillator is used) Conditions Mask ROM version f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz f(STCK) ≤ 1.1 MHz One Time PROM version f(STCK) ≤ 6 MHz f(STCK) ≤ 4.4 MHz f(STCK) ≤ 2.2 MHz VDD VDD VRAM VSS VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOL(avg) ΣIOH(avg) ΣIOL(avg) Supply voltage (when RC oscillation is used) Supply voltage (when quartz-crystal oscillator is used) RAM back-up voltage Supply voltage “H” level input voltage “H” level input voltage “H” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “H” level peak output current “H” level average output current (Note) “L” level peak output current “L” level peak output current “L” level peak output current “L” level peak output current “L” level average output current (Note) “L” level average output current (Note) “L” level average output current (Note) “L” level average output current (Note) “H” level total average current “L” level total average current D 6 , D7 CNTR0, CNTR1 P0, P1, P2, P3, P4, P5, P6, D0–D7, VDCE, XIN RESET Limits Min. 4.0 2.7 2.0 1.8 4.0 2.7 2.5 2.7 2.0 2.5 1.6 2.0 0 0.8VDD 0.85VDD 0.85VDD 0 0 0 VDD VDD VDD 0.2VDD 0.3VDD 0.15VDD –20 –10 –10 –5 24 12 10 4 24 12 40 30 12 6 5 2 15 7 30 15 –60 –60 80 80 Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V f(STCK) ≤ 4.4 MHz Mask ROM version f(XIN) ≤ 50 kHz V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA One Time PROM version f(XIN) ≤ 50 kHz at RAM back-up mode Mask ROM version One Time PROM version at RAM back-up mode SCK, SIN, CNTR0, CNTR1, INT0, INT1 P0, P1, P2, P3, P4, P5, P6, D0–D7, VDCE, XIN RESET SCK, SIN, CNTR0, CNTR1, INT0, INT1 VDD = 5 V P0, P1, P5, D0–D7 CNTR0, CNTR1 P0, P1, P5, D0–D7 CNTR0, CNTR1 P0, P1, P2, P4, P5, P6 SCK, SOUT P3, RESET D0–D5 D 6 , D7 CNTR0, CNTR1 P0, P1, P2, P4, P5, P6 SCK, SOUT P3, RESET D0–D5 VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V P5, D0–D7, CNTR0, CNTR1 P0, P1 P2, P5, D0–D7, RESET, CNTR0, CNTR1 P0, P1, P3, P4, P6 Note: The average output current is the average value during 100 ms. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-3 APPENDIX 4519 Group 3.1 Electrical characteristics Table 3.1.3 Recommended operating conditions 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Mask ROM version Conditions Through mode VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4, 8 mode VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V One Time PROM Through mode version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V f(XIN) f(XIN) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic resonator selected, external clock input) VDD = 2.7 to 5.5 V Mask ROM version Through mode VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4, 8 mode VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V One Time PROM Through mode version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. When ceramic resonance is used f(STCK) [MHz] 6 When RC oscillation is used f(STCK) [MHz] When external clock is used f(STCK) [MHz] Min. Limits Typ. Max. 6.0 4.4 2.2 1.1 6.0 4.4 2.2 6.0 4.4 6.0 4.4 2.2 6.0 4.4 6.0 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 3.2 1.6 4.8 3.2 4.8 Unit MHz MHz MHz 4.8 4.4 4.4 3.2 2.2 Recommended operating operation Recommended operating operation 1.6 Recommended operating operation 1.1 0.8 VDD[V] VDD[V] 1.8 2 2.7 (2.5) 4 5.5 VDD 1.8 2 2.7 (2.5) 4 5.5 2.7 5.5 ( ): One Time PROM version Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-4 APPENDIX 4519 Group 3.1 Electrical characteristics Table 3.1.4 Recommended operating conditions 3 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a quartz-crystal oscillator) f(CNTR) Timer external input frequency tw(CNTR) Timer external input period (“H” and “L” pulse width) f(SCK) tw(SCK) TPON Serial I/O external input frequency Serial I/O external input frequency (“H” and “L“ pulse width) Power-on reset circuit valid supply voltage rising time Mask ROM version One Time PROM version VDD = 0 → 1.8 V VDD = 0 → 2.5 V 100 100 µs SCK SCK 3/f(STCK) f(STCK)/6 Hz s Mask ROM version One Time PROM version CNTR0, CNTR1 CNTR0, CNTR1 3/f(STCK) Conditions VDD = 2.0 to 5.5 V VDD = 2.5 to 5.5 V Min. Limits Typ. Max. 50 50 f(STCK)/6 Hz s Unit kHz Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-5 APPENDIX 4519 Group 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.5 Electrical characteristics 1 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VOH Parameter “H” level output voltage P0, P1, P5, D0–D7, CNTR0, CNTR1 VDD = 3 V VOL “L” level output voltage P0, P1, P2, P4, P5, P6 SCK, SOUT VOL “L” level output voltage P3, RESET VOL “L” level output voltage D0–D5 VDD = 3 V VOL “L” level output voltage D6, D7, CNTR0, CNTR1 VDD = 5 V VDD = 3 V IIH “H” level input current P0, P1, P2, P3, P4, P5, P6, D0–D7, VDCE, RESET, SCK, SIN, CNTR0, CNTR1, INT0, INT1 IIL “L” level input current P0, P1, P2, P3, P4, P5, P6, D0–D7, VDCE, SCK, SIN, CNTR0, CNTR1, INT0, INT1 RPU Pull-up resistor value VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Mask ROM version ∆f(XIN) Frequency error (with RC oscillation, error of external R, C not included ) (Note) Note: When RC oscillation is used, use the external 30 pF or 33 pF capacitor (C). Test conditions VDD = 5 V IOH = –10 mA IOH = –3 mA IOH = –5 mA IOH = –1 mA IOL = 12 mA IOL = 4 mA VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V IOL = 6 mA IOL = 2 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5 mA VI = VDD Ports P4, P6 selected Limits Min. 3 4.1 2.1 2.4 2 0.9 0.9 0.6 2 0.9 0.9 2 0.9 1.4 0.9 2 0.9 2 0.9 2 Typ. Max. Unit V VDD = 5 V V V V V µA VI = 0 V P0, P1 No pull-up Ports P4, P6 selected –2 µA VDD = 5 V VDD = 3 V 30 50 P0, P1, RESET VT+ – VT– Hysteresis SCK, SIN, CNTR0, CNTR1, INT0, INT1 VT+ – VT– Hysteresis RESET f(RING) On-chip oscillator clock frequency 60 120 0.2 0.2 1 0.4 125 250 kΩ V V 200 100 VDD = 1.8 V 30 500 250 120 700 400 200 ±17 ±17 kHz VDD = 5 V ± 10 %, Ta = 25 °C VDD = 3 V ± 10 %, Ta = 25 °C % % Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-6 APPENDIX 4519 Group 3.1 Electrical characteristics Table 3.1.6 Electrical characteristics 2 (Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol IDD Parameter Supply current at active mode VDD = 5 V (with a ceramic resonator, f(XIN) = 6 MHz on-chip oscillator stop) VDD = 5 V f(XIN) = 4 MHz Test conditions f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 3 V f(XIN) = 4 MHz f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) at active mode (with a quartz-crystal oscillator, on-chip oscillator stop) VDD = 3 V f(XIN) = 32 kHz VDD = 5 V f(XIN) = 32 kHz f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) at active mode (with an on-chip oscillator, f(XIN) stop) VDD = 3 V VDD = 5 V f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) at RAM back-up mode (POF instruction execution) Ta = 25 °C VDD = 5 V VDD = 3 V Limits Min. Typ. 1.4 1.6 2.0 2.8 1.1 1.2 1.5 2.0 0.4 0.5 0.6 0.8 55 60 65 70 12 13 14 15 50 70 100 150 10 15 20 35 0.1 Max. 2.8 3.2 4.0 5.6 2.2 2.4 3.0 4.0 0.8 1.0 1.2 1.6 110 120 130 140 24 26 28 30 100 140 200 300 20 30 40 70 3 10 6 mA mA Unit mA µA µA µA µA µA Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-7 APPENDIX 4519 Group 3.1 Electrical characteristics 3.1.4 A/D converter recommended operating conditions Table 3.1.7 A/D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VDD VIA f(ADCK) Parameter Supply voltage Analog input voltage A/D conversion clock frequency (Note) One Time PROM version Note: Definition of A/D conversion clock (ADCK) Mask ROM version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.0 to 5.5 V VDD = 4.0 to 5.5 V VDD = 3.0 to 5.5 V Conditions Mask ROM version One Time PROM version Min. 2.0 3.0 0 0.8 0.8 0.8 0.8 0.8 0.8 Limits Typ. Max. 5.5 5.5 VDD 334 245 3.9 1.8 334 123 Unit V V kHz On-chip oscillator clock (RING) Division circuit Divided by 8 On-chip oscillator Ceramic resonance Divided by 4 MR0 1 Multiplexer (CMCK, CRCK, CYCK) Division circuit Divided by 48 Q32 Instruction clock (INSTCK) On-chip oscillator clock(RING) 0 1 Divided by 24 Divided by 12 Divided by 6 Q31, Q30 11 10 01 00 A/D conversion clock (ADCK) 0 Divided by 2 MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) XIN RC oscillation Quartz-crystal oscillation f(ADCK) [kHz] 334 245 (123) Recommended operating operation 3.9 (15.3) 1.8 0.8 2 2.2 2.7 (3.0) ( ): One Time PROM version 4 5.5 VDD[V] Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-8 APPENDIX 4519 Group 3.1 Electrical characteristics Table 3.1.8 A/D converter characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol – – – V0T Parameter Resolution Linearity error 2.7 (3.0) V ≤ VDD ≤ 5.5 V((): One Time PROM version) Mask ROM version 2.2 V ≤ VDD < 2.7 V 0 0 0 0 3 5105 3064.5 2552.5 5100 3065 10 7.5 7.5 15 13 5115 3072 2560 5115 3075 Test conditions Min. Limits Typ. Max. 10 ±2 ±4 ±0.9 20 15 15 30 23 5125 3079.5 2567.5 5130 3085 ±8 150 75 450 225 31 LSB µA mV Unit bits LSB LSB mV Differential non-linearity error 2.2 (3.0) V ≤ VDD ≤ 5.5 V ((): One Time PROM version) VDD = 5.12 V Mask ROM version Zero transition voltage VDD = 3.072 V VDD = 2.56 V One Time PROM version VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V One Time PROM version VDD = 2.56 V VDD = 5.12 V VDD = 3.072 V 2.0 V ≤ VDD < 2.2 V VFST Full-scale transition voltage Mask ROM version – IADD TCONV Absolute accuracy (Quantization error excluded) A/D operating current (Note 1) A/D conversion time Mask ROM version VDD = 5 V VDD = 3 V f(XIN) = 6 MHz µs f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6 – – Comparator resolution Comparator error (Note 2) Mask ROM version VDD = 5.12 V VDD = 3.072 V VDD = 2.56 V One Time PROM version – VDD = 5.12 V VDD = 3.072 V Comparator comparison time f(XIN) = 6 MHz f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6 Notes 1: When the A/D converter is used, IADD is added to IDD (supply current). 2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in D/A converter can be obtained by the following formula. 8 ±20 ±15 ±15 ±30 ±23 4 bits mV µs Logic value of comparison voltage Vref Vref = VDD 256 ✕n n = Value of register AD (n = 0 to 255) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-9 APPENDIX 4519 Group 3.1 Electrical characteristics 3.1.5 Voltage drop detection circuit characteristics Table 3.1.9 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VRST– Parameter Detection voltage (reset occurs) (Note 1) VRST+ Detection voltage (reset release) (Note 2) Detection voltage hysteresis Operation current (Note 3) Detection time VDD = 5 V VDD = 3 V VDD → (VRST– – 0.1 V) (Note 4) Ta = 25 °C Ta = 25 °C Test conditions Limits Typ. 3.5 Unit V Min. 3.3 2.7 2.6 3.5 2.9 2.8 Max. 3.7 4.2 4.2 3.7 3.9 4.4 4.4 V VRST+ – VRST– IRST TRST 0.2 50 30 0.2 100 60 1.2 V µA ms Notes 1: The detected voltage (V RST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 2: The detected voltage (V RST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. 3: When the voltage drop detection circuit is used (VDCE pin = “H”), IRST is added to IDD (power current). 4: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V]. 3.1.6 Basic timing diagram Machine cycle Parameter Pin (signal) name Mi Mi+1 System clock STCK Port D output D0–D 7 Port D input D 0–D 7 Ports P0, P1, P2, P3, P00–P03 P10–P13 P4, P5, P6 output P20–P23 P30–P33 P40–P43 P50–P53 P60–P63 Ports P0, P1, P2, P3, P00–P03 P10–P13 P4, P5, P6 input P20–P23 P30–P33 P40–P43 P50–P53 P60–P63 Interrupt input INT0, INT1 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-10 APPENDIX 4519 Group 3.2 Typical characteristics 3.2 Typical characteristics As for the standard characteristics, refer to “Renesas Technology Corp.” Homepage. http://www.renesas.com/en/720 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-11 APPENDIX 4519 Group 3.3 List of precautions 3.3 List of precautions 3.3.1 Program counter Make sure that the PCH d oes not specify after the last page of the built-in ROM. 3.3.2 Stack registers (SK S) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. 3.3.3 Notes on I/O port (1) Note when an I/O port is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0”, “L” level can be input. As for the port which has the output structure selection function, select the N-channel open-drain output structure. (2) Noise and latch-up prevention Connect an approximate 0.1 µ F bypass capacitor directly to the V SS l ine and the V DD l ine with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNV SS p in is also used as the V PP p in (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNV SS/V PP p in to V SS t hrough an approximate 5 k Ω r esistor which is connected to the CNV SS/V PP p in at the shortest distance. (3) Multifunction • Be careful that the output of ports P30 and P31 can be used even when INT0 and INT1 pins are selected. • Be careful that the input of ports P2 0–P2 2 c an be used even when S IN, S OUT a nd S CK p ins are selected. • Be careful that the input/output of port D 6 can be used even when input of CNTR0 pin is selected. • Be careful that the input of port D 6 c an be used even when output of CNTR0 pin is selected. • Be careful that the input/output of port D 7 can be used even when input of CNTR1 pin is selected. • Be careful that the input of port D 7 c an be used even when output of CNTR1 pin is selected. (4) Connection of unused pins Table 3.3.1 shows the connections of unused pins. (5) SD, RD, SZD instructions When the S D , R D , or S ZD i nstructions is used, do not set “1000 2” or more to register Y. (6) Port P3 0/INT0 pin When the RAM back-up mode is used by clearing the bit 3 of register I1 to “0” and setting the input of INT0 pin to be disabled, be careful about the following note. • When the input of INT0 pin is disabled (register I1 3 = “ 0”), clear bit 0 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. (7) Port P3 1/INT1 pin When the RAM back-up mode is used by clearing the bit 3 of register I2 to “0” and setting the input of INT1 pin to be disabled, be careful about the following note. • When the input of INT1 pin is disabled (register I2 3 = “ 0”), clear bit 2 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-12 APPENDIX 4519 Group 3.3 List of precautions Table 3.3.1 Connections of unused pins Pin X IN X OUT Connection Open. Open. Usage condition Internal oscillator is selected. Internal oscillator is selected. RC oscillator is selected. External clock input is selected for main clock. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. CNTR1 input is not selected for timer 3 count source. N-channel open-drain is selected for the output structure. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. S CK p in is not selected. ( Note ( Note ( Note ( Note 1) 1) 2) 3) D 0–D5 D 6/CNTR0 D 7/CNTR1 P00–P03 Open. Connect Open. Connect Open. Connect Open. Connect to V SS. to V SS. to V SS. to V SS. ( Note 4) ( Note 4) ( Note ( Note ( Note ( Note ( Note ( Note ( Note ( Note ( Note 4) 6) 5) 4) 6) 7) 5) 4) 7) P10–P13 Open. Connect to V SS. Open. Connect Open. P21/SOUT Connect Open. P22/SIN Connect Open. P30/INT0 Connect Open. P31/INT1 Connect Open. P3 2, P3 3 Connect P 4 0 / A I N 4 – P 4 3 / Open. Connect AIN7 Open. P50–P53 Connect P 6 0 / A I N 0 – P 6 3 / Open. AIN3 Connect P20/SCK to V SS. to V SS. S IN p in is not selected. to V SS. “0” is set to output latch. to Vss. “0” is set to output latch. to Vss. to Vss. to Vss. to Vss. to Vss. N-channel open-drain is selected for the output structure. Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG 0=0, MR0=1). 2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution. In order to start oscillation, setting the main clock f(X IN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing wait time by software.) Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN) (MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of software, and then set the main clock (f(X IN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, X IN pin is fixed to “H”. When an external clock is used, insert a 1 k Ω resistor to XIN pin in series for limits of current. 4: Be sure to select the output structure of ports D0–D5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open. 6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on wake-up control register K1, set the unused 1-bit to “H” input (turn pull-up transistor ON and open) or “L” input (connect to VSS, or open and set the output latch to “0”). 7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON and open. (Note when connecting to VSS and VDD) ● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-13 APPENDIX 4519 Group 3.3 List of precautions 3.3.4 Notes on interrupt (1) Setting of INT0 interrupt valid waveform Set a value to the bit 2 of register I1, and execute the S NZ0 i nstruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P30/INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the bit 2 of register I1 is changed. (2) Setting of INT0 pin input control Set a value to the bit 3 of register I1, and execute the S NZ0 i nstruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P30/INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the bit 3 of register I1 is changed. (3) Setting of INT1 interrupt valid waveform Set a value to the bit 2 of register I2, and execute the S NZ1 i nstruction to clear the EXF1 flag to “0” after executing at least one instruction. Depending on the input state of P31/INT1 pin, the external interrupt request flag (EXF1) may be set to “1” when the bit 2 of register I2 is changed. (4) Setting of INT1 pin input control Set a value to the bit 3 of register I2, and execute the S NZ1 i nstruction to clear the EXF1 flag to “0” after executing at least one instruction. Depending on the input state of P31/INT1 pin, the external interrupt request flag (EXF1) may be set to “1” when the bit 3 of register I2 is changed. (5) Multiple interrupts Multiple interrupts cannot be used in the 4519 Group. (6) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write E I a nd R TI i nstructions continuously. (7) P3 0/INT0 pin When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to “1”. Even in this case, port P3 0 I /O function is valid. Also, the EXF0 flag is set to “1” when bit 3 of register I1 is set to “1” by input of a valid waveform (valid waveform causing external 0 interrupt) even if it is used as an I/O port P3 0. The input threshold characteristics (VIH/VIL) are different between INT0 pin input and port P3 0 input. Accordingly, note this difference when INT0 pin input and port P3 0 input are used at the same time. (8) P3 1/INT1 pin When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to “1”. Even in this case, port P3 1 I /O function is valid. Also, the EXF1 flag is set to “1” when bit 3 of register I2 is set to “1” by input of a valid waveform (valid waveform causing external 1 interrupt) even if it is used as an I/O port P3 1. The input threshold characteristics (VIH/VIL) are different between INT1 pin input and port P3 1 input. Accordingly, note this difference when INT1 pin input and port P3 1 input are used at the same time. (9) POF instruction When the P OF i nstruction is executed continuously after the E POF i nstruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the P OF i nstruction. Be sure to disable interrupts by executing the D I i nstruction before executing the E POF i nstruction and the P OF i nstruction continuously. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-14 APPENDIX 4519 Group 3.3 List of precautions 3.3.5 Notes on timer (1) Prescaler Stop counting and then execute the T ABPS i nstruction to read from prescaler data. Stop counting and then execute the T PSAB i nstruction to set prescaler data. (2) Count source Stop timer 1, 2, 3, 4 or LC counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3 or 4 counting and then execute the T AB1 , T AB2 , T AB3 o r T AB4 i nstruction to read its data. (4) Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the T 1AB , T 2AB , T 3AB , T 4AB o r T LCA instruction to write its data. (5) Writing to reload register R1, reload register R3 and reload register R4H When writing data to reload register R1 while timer 1 is operating respectively, avoid a timing when timer 1 underflows. When writing data to reload register R3 while timer 3 is operating respectively, avoid a timing when timer 3 underflows. When writing data to reload register R4H while timer 4 is operating respectively, avoid a timing when timer 4 underflows. (6) Timer 4 • A t CNTR1 output vaild, if a timing of timer 4 underflow overlaps with a timing to stop timer 4, a hazard may be generated in a CNTR1 output waveform. Please review sufficiently. • When “H” interval extension function of the PWM signal is set to be “valid”, set “0116” or more to reload register R4H. (7) Watchdog timer • The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the WRST i nstruction continuously, and clear the WEF flag to “0”. • The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction and the W RST i nstruction continuously every system is returned from the RAM back-up state. • When the watchdog timer function and RAM back-up function are used at the same time, initialize the flag WDF1 with the W RST i nstruction before system enters into the RAM back-up state. (8) Pulse width input to CNTR0 pin, CNTR1 pin Refer to section “3.1 Electrical characteristics” for rating value of pulse width input to CNTR0 pin, CNTR1 pin. (9) Period measurement circuit ● When a period measurement circuit is used, clear bit 0 of register I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. ● While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. ● When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-15 APPENDIX 4519 Group 3.3 List of precautions ● When the signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) ● When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled. ● S tart timer operation immediately after operation of a period measurement circuit is started. ● Even when the edge for measurement is input by timer operation is started from the operation of period measurement circuit is started, timer 1 is not operated. ● W hen data is read from timer 1, stop the timer 1 and the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to “1” when the period measurement circuit is stopped by clearing bit 2 of register W5 to “0”. In order to avoid the occurrence of an unexpected interrupt, disable the timer 1 interrupt, and then, stop the period measurement circuit. Figure 3.3.1 shows the setting example to read measurement data of period measurement circuit. (10) Prescaler, timer 1, timer 2 and timer 3 count start time and count time when operation starts Count starts from the first rising edge of the count source ➁ i n Fig. 3.3.2 after prescaler, timer 1, timer 2 and timer 3 operations start ➀ i n Fig. 3.3.2. Time to first underflow ➂ in Fig. 3.3.2 is shorter (for up to 1 period of the count source) than time among next underflow ➃ in Fig. 3.3.2 by the timing to start the timer and count source operations after count starts. (11) Timer 4 count start time and count time when operation starts Count starts from the rising edge ➁ i n Fig. 3.3.3 after the first falling edge of the count source, after timer 4 operation starts ➀ in Fig. 3.3.3. Time to first underflow ➂ in Fig. 3.3.3 is different from time among next underflow ➃ in Fig. 3.3.3 by the timing to start the timer and count source operations after count starts. ••• Timer 1 operation is stopped (bit 2 of register W1 is cleared to “0”) ↓ Timer 1 interrupt is disabled (bit 2 of register V1 is cleared to “0”) ↓ Period measurement circuit is stopped. (bit 2 of register W5 is cleared to “0”) ↓ Execute at least one Instruction [ NOP ] ↓ Timer 1 interrupt request flag (T1F) is cleared to “0”. [ SNZT1 ] ↓ Considering the skip of the S NZT1 i nstruction, insert the N OP i nstruction. ↓ Measurement data is read. [ TAB1 ] Fig. 3.3.1 Period measurement circuit program example ➁ Count source Timer value 3 2 1 0 3 2 1 0 3 2 Timer underflow signal ➂ ➃ ➀ Timer start Fig. 3.3.2 Count start time and count time when operation starts (PS, T1, T2 and T3) ➁ Count source Timer value 3 2 1 0 3 2 1 0 3 Timer underflow signal ➂ ➃ ➀ Timer start Fig. 3.3.3 Count start time and count time when operation starts (T4) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z → → ••• 3-16 APPENDIX 4519 Group 3.3 List of precautions 3.3.6 Notes on A/D conversion (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µ F to 1 µF) to analog input pins. Figure 3.3.4 shows the analog input external circuit example-1. When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 3.3.5. In addition, test the application products sufficiently. Sensor AIN Sensor About 1kΩ AIN Apply the voltage withiin the specifications to an analog input pin. Fig. 3.3.5 Analog input external circuit example-2 Fig. 3.3.4 Analog input external circuit example-1 (3) Notes for the use of A/D conversion 2 Do not change the operating mode of the A/D converter by bit 3 of register Q1 during A/D conversion (A/D conversion mode and comparator mode). (4) Notes for the use of A/D conversion 3 When the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode with bit 3 of register Q1 in a program, be careful about the following notes. • Clear bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to the A/D conversion mode (refer to Figure 3.3.6 ➀). • The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to bit 3 of register Q1, and execute the S NZAD i nstruction to clear the ADF flag to “0”. • • • Clear bit 2 of register V2 to “0”....... ➀ ↓ Change of the operating mode of the A/D converter from the comparator mode to the A/D conversion mode ↓ Clear the ADF flag to “0” with the S NZAD i nstruction ↓ Execute the N OP i nstruction for the case when a skip is performed with the S NZAD i nstruction • • • Fig. 3.3.6 A/D converter operating mode program example Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-17 APPENDIX 4519 Group 3.3 List of precautions (5) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.” In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 2 machine cycles + A/D conversion clock (ADCK) 1 clock. (6) Analog input pins When P40/AIN4–P43/AIN7, P60/AIN0–P63/AIN3 are set to pins for analog input, they cannot be used as I/O ports P4 and P6. (7) TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.” (8) Recommended operating conditions when using A/D converter As for the supply voltage when A/D converter is used and the recommended operating condition of the A/D convesion clock frequency, refer to the “3.1 Electrical characteristics”. 3.3.7 Notes on serial I/O (1) Note when an external clock is used as a synchronous clock: • An external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transmit/receive is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transmit/receive is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally. Note also that the SIOF flag is set to “1” when a clock is counted 8 times. • Be sure to set the initial input level on the external clock pin to “H” level. • Refer to section “3.1 Electrical characteristics” when using serial I/O with an external clock. 3.3.8 Notes on reset (1) Register initial value The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. • Register Z (2 bits) • Register D (3 bits) • Register E (8 bits) (2) Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum rating value of the recommended operating conditions. Refer to section “3.1 Electrical characteristics” for the reset voltage of the recommended operating conditions. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-18 APPENDIX 4519 Group 3.3 List of precautions 3.3.9 Notes on RAM back-up (1) POF instruction Execute the P OF i nstruction immediately after executing the E POF i nstruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the P OF i nstruction. Be sure to disable interrupts by executing the D I i nstruction before executing the E POF i nstruction and the P OF i nstruction. (2) Key-on wakeup function After checking none of the return condition for ports (P0, P1, INT0 and INT1 specified with register K0–K2) with valid key-on wakeup function is satisfied, execute the P OF i nstruction. If at least one of return condition for ports with valid key-on wakeup function is satisfied, system returns from the RAM back-upn state immediately after the P OF i nstruction is executed. (3) Return from RAM back-up mode After system returns from RAM back-up mode, set the undefined registers and flags. The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up mode, set initial values. • Register D (3 bits) • Register Z (2 bits) • Register E (8 bits) • Register X (4 bits) • Register Y (4 bits) (4) Watchdog timer • The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and the W RST i nstruction continuously every system is returned from the RAM back-up. • When the watchdog timer function and RAM back-up function are used at the same time, initialize the flag WDF1 with the W RST i nstruction before system goes into the RAM back-up state. (5) Port P30/INT0 pin When the RAM back-up mode is used by clearing the bit 3 of register I1 to “0” and setting the input of INT0 pin to be disabled, be careful about the following note. • When the input of INT0 pin is disabled (register I1 3 = “ 0”), clear bit 0 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. (6) Port P31/INT1 pin When the RAM back-up mode is used by clearing the bit 3 of register I2 to “0” and setting the input of INT1 pin to be disabled, be careful about the following note. • When the input of INT1 pin is disabled (register I2 3 = “ 0”), clear bit 2 of register K2 to “0” to invalidate the key-on wakeup before system goes into the RAM back-up mode. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-19 APPENDIX 4519 Group 3.3 List of precautions 3.3.10 Notes on clock control (1) Clock control Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the C MCK , C RCK o r C YCK i nstruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. The CMCK, CRCK or CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. When the CMCK, CRCK or CYCK instructions are never executed, main clock (f(XIN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(X IN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(X IN)) selected for the system clock cannot be stopped. (2) On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that margin of frequencies when designing application products. When considering the oscillation stabilize wait time at the switch of clock, be careful that the margin of frequencies of the on-chip oscillator clock. (3) External clock When the external clock signal for the main clock (f(X IN)) is used, connect the clock source to XIN pin and X OUT p in open. In program, after the CMCK instruction is executed, set main clock (f(X IN)) oscillation start to be enabled (MR 1=0). For this product, when RAM back-up mode and main clock (f(X IN)) stop (MR 1=1), X IN p in is fixed to “H” in order to avoid the through current by floating of internal logic. The X IN pin is fixed to “H” until main clock (f(X IN)) oscillation start to be valid (MR 1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 kΩ or more resistor to XIN pin in series to limit of current by competitive signal. (4) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator. 3.3.11 Electric characteristic differences between Mask ROM and One Time PROM version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. 3.3.12 Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-20 APPENDIX 4519 Group 3.4 Notes on noise 3.4 Notes on noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Package Select the smallest possible package to make the total wiring length short. q R eason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. (2) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the V SS p in with the shortest possible wiring. q R eason In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS N.G. RESET VSS DIP SDIP SOP QFP O.K. Reset circuit VSS RESET VSS Fig. 3.4.2 Wiring for the RESET input pin Fig. 3.4.1 Selection of packages Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-21 APPENDIX 4519 Group 3.4 Notes on noise (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • M ake the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the V SS p in of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other V SS p atterns. (4) Wiring to CNV SS p in Connect the CNV SS p in to the V SS p in with the shortest possible wiring. q R eason The operation mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNV SS a nd V SS, the operation mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Noise Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. CNVSS VSS CNVSS VSS Fig. 3.4.3 Wiring for clock I/O pins q R eason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS l evel of a microcomputer and the V SS l evel of an oscillator, the correct clock will not be input in the microcomputer. N.G. O.K. Fig. 3.4.4 Wiring for CNV SS p in Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-22 APPENDIX 4519 Group 3.4 Notes on noise (5) Wiring to VPP pin of built-in PROM version In the built-in PROM version of the 4524 Group, the CNV SS p in is also used as the built-in PROM power supply input pin V PP. q W hen the V PP p in is also used as the CNV SS p in Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the V PP p in and the V SS pin the shortest possible (refer to F igure 3.4.5) Note: E ven when a circuit which included an approximately 5 k Ω r esistor is used in the Mask ROM version, the microcomputer operates correctly. q R eason The V PP p in of the built-in PROM version is the power source input pin for the builtin PROM. When programming in the builtin PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. When the VPP pin is also used as the CNVSS pin Approximately 5kΩ CNVSS/VPP VSS 3.4.2 Connection of bypass capacitor across VSS line and VDD l ine Connect an approximately 0.1 µF bypass capacitor across the V SS l ine and the V DD l ine as follows: • C onnect a bypass capacitor across the V SS p in and the V DD p in at equal length. • C onnect a bypass capacitor across the V SS p in and the VDD pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for V SS l ine and V DD l ine. • C onnect the power source wiring via a bypass capacitor to the V SS p in and the V DD p in. VDD VDD VSS VSS N.G. O.K. Fig. 3.4.6 Bypass capacitor across the V SS l ine and the V DD l ine In the shortest distance Fig. 3.4.5 Wiring for the V PP p in of the built-in PROM version Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-23 APPENDIX 4519 Group 3.4 Notes on noise 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the V SS p in and the analog input pin. Besides, connect the capacitor to the V SS p in as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. q Reason Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise (Note) 3.4.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q R eason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Microcomputer Analog input pin N.G. O.K. Large current GND XIN XOUT VSS Thermistor Fig. 3.4.8 Wiring for a large current signal line VSS Note : The resistor is used for dividing resistance with a thermistor. Fig. 3.4.7 Analog signal line and a resistor and a capacitor Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-24 APPENDIX 4519 Group 3.4 Notes on noise (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q R eason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: • Connect a resistor of 100 Ω or more to an I/O port in series. • A s for an input port, read data several times by a program for checking whether input levels are equal or not. • A s for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. • R ewrite data to pull-up control registers at fixed periods. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.4.9 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using V SS p attern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer V SS p in with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 3.4.10 V SS p attern on the underside of an oscillator Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-25 APPENDIX 4519 Group 3.4 Notes on noise • A ssigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • D etects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • D ecrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • D etects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT)← N EI Main processing ≠N (SWDT) =N? N Interrupt processing routine (SWDT) ← (SWDT)—1 Interrupt processing (SWDT) ≤0? ≤0 >0 RTI Return Main routine errors Interrupt processing routine errors Fig. 3.4.11 Watchdog timer by software Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-26 APPENDIX 4519 Group 3.5 Package outline 3.5 Package outline 42P2R-A EIAJ Package Code SSOP42-P-450-0.80 42 Recommended JEDEC Code – Weight(g) 0.63 22 Plastic 42pin 450mil SSOP Lead Material Alloy 42/Cu Alloy e b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – Symbol 1 21 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 c z Z1 Detail G Detail F L I2 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z 3-27 R ENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER USER’S MANUAL 4519 Group Publication Data : Published by : Rev.1.00 Aug 08, 2004 Sales Strategic Planning Div. Renesas Technology Corp. © 2 004. Renesas Technology Corp., All rights reserved. Printed in Japan. 4519 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan