4571

4571 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0179-0102 Rev.1.02 May 25, 2007 • • • • • • Interrupt ..................................................................... 6 sources Key-on wakeup function pins .............................................. 12 I/O port ................................................................................. 17 Output port ............................................................................. 1 Input port ................................................................................ 1 Voltage drop detection circuit Reset occurrence................................Typ. 1.65 V (Ta = 25 °C) Reset release ......................................Typ. 1.75 V (Ta = 25 °C) Interrupt occurrence...........................Typ. 1.85 V (Ta = 25 °C) • Watchdog timer • Power-on reset circuit • Clock generating circuit (ceramic resonator) APPLICATION Remote control transmitter DESCRIPTION The 4571 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with three 8-bit timers (each timer has one or two reload registers), interrupts, and voltage drop detection circuit. The various microcomputers in the 4571 Group include variations of the built-in memory size as shown in the table below. FEATURES • Minimum instruction execution time..............................0.5 µs (at 6 MHz oscillation frequency, in through-mode) • Supply voltage .......................................................1.8 to 5.5 V (It depends on oscillation frequency and operation mode) • Timers Timer 1..................................8-bit timer with a reload register and carrier wave output auto-control function Timer 2..................................8-bit timer with a reload register Timer 3..................... 8-bit timer with two reload registers and carrier wave generation circuit Table 1 Support Product ROM size (× 10 bits) 4096 words 4096 words 6144 words 6144 words 16384 words 16384 words Part number M34571G4FP (Note 1) M34571G4-XXXFP M34571G6FP (Note 1) M34571G6-XXXFP M34571GDFP (Note 1) M34571GD-XXXFP Note 1.Shipped in blank RAM size (× 4 bits) 128 words 128 words 128 words 128 words 128 words 128 words Package PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A QzROM QzROM QzROM QzROM QzROM QzROM ROM type Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 1 of 124 4571 Group PIN CONFIGURATION Pin configuration (top view) VDD VSS XIN XOUT K RESET P00 P01 P02 P03 P10 P11 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 C/CNTR1 D4/CNTR0 D3 D2 D1 D0 P31 P30 P21/INT1 P20/INT0 P13 P12 Outline: PRSP0024GA-A (24P2Q-A) Fig 1. Pin configuration (PRSP0024GA-A type) M 34571G x-XXXFP M 34571G xFP Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 2 of 124 4571 Group Fig 2. 4 2 4 2 5 FUNCTIONAL BLOCK Rev.1.02 May 25, 2007 REJ03B0179-0102 Port P0 Port P1 Port P3 Port P2 Port D System clock generating circuit X IN -X OUT(ceramic) Power-on reset circuit Voltage drop detection circuit I/O Port Internal peripheral functions Timer Functional block diagram (PRSP0024GA-A type) Page 3 of 124 Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (8 bits) Memory 4500 series CPU core ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) Watchdog timer (16 bits) ROM 4096, 6144, 16384 words × 1 0 bits RAM 128 words × 4 b its Port K Port C 1 1 4571 Group PERFORMANCE OVERVIEW Table 2 Performance overview Parameter Number of basic instructions M34571G4/G6 126 M34571GD Minimum instruction execution time Memory sizes ROM M34571G4 M34571G6 M34571GD RAM I/O port D0–D4 I/O (Input is examined by skip decision) I/O I/O I/O I/O Output Input Timer I/O Timer output 128 0.5 µs (Oscillation frequency 6 MHz: through mode) 4096 words × 10 bits 6144 words × 10 bits 16384 words × 10 bits 128 words × 4 bits Five independent I/O ports; The output structure of ports D0–D3 is switched by software. Port D4 is also used as CNTR0, respectively. 4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. 4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. 2-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. Ports P20 and P21 are also used as INT0 and INT1, respectively. 2-bit I/O port ; the output structure is switched by software. 1-bit output port (CMOS output only); port C is also used as CNTR1 pin. 1-bit input port ; a key-on wakeup function can be switched by software. 1-bit I/O port ; CNTR0 pin is also used as port D4. 1-bit output port ; CNTR1 pin is also used as port C. 1-bit input port ; INT0 and INT1 are also used as ports P20 and P21, respectively. 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. 8-bit timer with a reload register. 8-bit timer with two reload registers and carrier wave generation function. 16-bit timer, fixed dividing frequency (timer for monitor) Built-in Typ. 1.65 V (Ta=25 °C) Typ. 1.75 V (Ta=25 °C) Typ. 1.85 V (Ta=25 °C) 6 sources (two for external, three for timers, voltage drop detection circuit) 1 level 8 levels CMOS sillicon gate 24-pin plastic molded SSOP (PRSP0024GA-A) -20 to 85 °C 1.8 to 5.5 V (It depends on oscillation frequency and operation mode) 0.3 mA (Ta = 25 °C, VDD = 3.0 V, f(XIN)=4 MHz, f(STCK)=f(XIN)/8) 0.1 µA (Ta = 25 °C, output transistor is cut-off state) Function P00−P03 P10−P13 P20, P21 P30, P31 C K CNTR0 CNTR1 Timer Timer 1 Timer 2 Timer 3 INT0, INT1 Interrupt input Watchdog timer Power-on reset circuit Voltage drop detection circuit Interrupt Subroutine nesting Device structure Package Operating temperature range Power source voltage At active mode Power dissipation At RAM back-up (Typ. value) Reset occurrence Reset release Interrupt occurrence Source Nesting Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 4 of 124 4571 Group PIN DESCRIPTION Table 3 Pin VDD VSS RESET Pin description Name Power source Power source Reset I/O Input/Output − − I/O Connected to a plus power supply. Connected to a 0 V power supply. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, or the built-in power-on reset causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. Connect a ceramic resonator between pins XIN and XOUT. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. The output structure of ports D0–D3 can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D4 is also used as CNTR0 pin. Port P0 serves as a 4-bit I/O port. The output structure is N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure is N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 2-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P20 and P21 are also used as INT0 pin and INT1 pin, respectively. Port P3 serves as a 2-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1”. Port C serves as a 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1. Port K serves as a 1-bit input port. It has the key-on wakeup function which can be switched by software. When port K is used for the input of key matrix, connect a pull-up resistor to it externally. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to output the PWM signal generated by timer 3. CNTR0 pin and CNTR1 pin are also used as Ports D4 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports P20 and P21, respectively. Function XIN XOUT D0−D4 Main clock input Main clock output I/O port D (Input is examined by skip decision.) Input Output I/O P00−P03 I/O port P0 I/O P10−P13 I/O port P1 I/O P20, P21 I/O port P2 I/O P30, P31 I/O port P3 I/O C K Output port C Input port K Output Input CNTR0, CNTR1 Timer I/O I/O INT0, INT1 Interrupt input Input MULTIFUNCTION Table 4 Pin C D4 Pin description Multifunction CNTR1 CNTR0 P20 P21 Pin Multifunction INT0 INT1 Pin CNTR1 CNTR0 Multifunction C D4 INT0 INT1 Pin Multifunction P20 P21 Note 1.Pins except above have just single function. Note 2.The input of D4 can be used even when CNTR0 (output) is selected. The input/output of D4 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and D4 since the input threshold value of CNTR0 pin is different from that of port D4. Note 3.“H” output function of port C can be used even when the CNTR1 (output) is used. Note 4.The input/output of P20 can be used even when INT0 is used. Be careful when using inputs of both INT0 and P20 since the input threshold value of INT0 pin is different from that of port P20. Note 5.The input/output of P21 can be used even when INT1 is used. Be careful when using inputs of both INT1 and P21 since the input threshold value of INT1 pin is different from that of port P21. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 5 of 124 4571 Group PORT FUNCTION Table 5 Port Port D Port function Pin D0−D3 Input Output I/O (5) Output structure N-channel open-drain/ CMOS N-channel open-drain I/O (4) N-channel open-drain 4 bits OP0A IAP0 I/O unit 1 bit Control instructions SD, RD SZD, CLD Control registers FR1 Remark Programmable output structure selection function − D4/CNTR0 W1 W2 W5 PU0 K0 Port P0 P00 P01 P02 P03 P10 P11 P12 P13 P20/INT0 P21/INT1 P30 P31 C/CNTR1 K Programmable pull-up and key-on wakeup function Port P1 I/O (4) N-channel open-drain 4 bits OP1A IAP1 PU1 K1 Programmable pull-up and key-on wakeup function Port P2 Port P3 I/O (2) I/O (2) Output (1) Input (1) N-channel open-drain N-channel open-drain/ CMOS CMOS - 2 bits 2 bits OP2A IAP2 OP3A IAP3 RCP SCP IAK PU2 K2, I1, I2, L1 FR0 Programmable pull-up and key-on wakeup function Programmable output structure selection function − Programmable key-on wakeup function Port C Port K 1 bit 1 bit W1, W3, W5 K2 DEFINITION OF CLOCK AND CYCLE • Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • Clock (f(XIN)) by the external ceramic resonator • Clock (f(XIN)) by the external input • System clock The system clock is the basic clock for controlling this product. The system clock is selected by the register MR. • Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. • Machine cycle The machine cycle is the standard cycle required to execute the instruction. Table 6 MR3 1 1 0 0 Table Selection of system clock System clock f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) Operation mode Frequency divided by 8 mode Frequency divided by 4 mode Frequency divided by 2 mode Frequency through mode Register MR MR2 1 0 1 0 Note 1.The frequency divided by 8 is selected after system is released from reset. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 6 of 124 4571 Group CONNECTIONS OF UNUSED PINS Table 7 Pin D0−D3 P30, P31 Port function Usage condition Connection Open. Connect to VSS. Output structure N-channel open-drain CMOS N-channel open-drain CMOS Connect to VDD. N-channel open-drain CMOS Pull-up transistor − − − − − − − − − OFF ON Connect to VSS. N-channel open-drain N-channel open-drain N-channel open-drain CMOS CMOS − OFF ON/OFF OFF ON Connect to VSS. OFF ON/OFF − − − − Connect to VDD. N-channel open-drain Connect to VDD. N-channel open-drain Key-on wakeup − − − − − − − − − Invalid Invalid Invalid Valid/Invalid Invalid Invalid Invalid Valid/Invalid − − Invalid Valid/Invalid Value of output latch 0/1 0/1 0/1 0 1 1 0/1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 0 − − Others (Note 1) − − − − − (Notes 1, 2) (Note 2) (Note 2) (Note 1) − − − (Notes 1, 3) (Note 3) (Note 3) (Note 3) − (Note 4) − − D4/CNTR0 Open. Connect to VSS. N-channel open-drain N-channel open-drain N-channel open-drain Connect to VDD. N-channel open-drain P00−P03, P10−P13 Open. P20/INT0 P21/INT1 Open. C/CNTR1 K Open. Connect to VSS. Connect to VSS. Connect to VDD. − Note 1.If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed when the output latch is 1, the supply voltage may be increased in the instruction execution cycle by the through current. Note 2.Do not select the CNTR0 input as the timer 1 count source. (W11 W10≠11) Note 3.Set the input of INT0 pin or INT1 pin to be disabled. (I13=0, I23=0) Note 4.Set the output of the CNTR1 pin to be invalid. (W33=0) (Note when connecting to VSS or VDD) Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 7 of 124 4571 Group PORT BLOCK DIAGRAM Skip decision Register Y Decoder SZD instruction CLD instruction SD instruction RD instruction RQ (Note 3) FR1i (Note 1) S D0-D3 (Note 2) (Note 1) Skip decision Register Y Decoder SZD instruction CLD instruction S SD instruction RD instruction Timer 1 underflow signal Timer 2 underflow signal RQ W23 0 1/2 1 W52 0 1 W10 W11 W50 0 1 (Note 1) D4/CNTR0 (Note 2) (Note 1) Clock input for timer 1 event count (Note 4) Key-on wakeup input (Note 3) Register A Ai Edge detection circuit K0i (Note 3) Pull-up transistor PU0i (Note 3) IAP0 instruction (Note 1) Ai OP0A instruction D T Q P00-P03 (Note 2) (Note 1) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. i represents bits 0 to 3. 4. A falling edge of port input is detected. Fig 3. Port block diagram (1) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 8 of 124 4571 Group (Note 4) Key-on wakeup input (Note 3) Register A Ai Edge detection circuit IAP1 instruction K1i (Note 3) Pull-up transistor PU1i (Note 3) (Note 1) Ai OP1A instruction D T Q P10-P13(Note 2) (Note 1) (Note 4) Key-on wakeup input Edge detection circuit IAP2 instruction Register A A0 K20 Pull-up transistor PU20 (Note 1) A0 OP2A instruction D T Q P20/INT0(Note 2) (Note 1) External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input External 0 interrupt (Notes 5, 6) (Note4) Key-on wakeup input Edge detection circuit IAP2 instruction Register A A1 K21 Pull-up transistor PU21 (Note 1) A1 OP2A instruction External 1 interrupt Key-on wakeup input D T Q P21/INT1(Note 2) (Note 1) External 1 interrupt (Notes 5, 6) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be V DD or less. 3. i represents bits 0 to 3. 4. Falling edge of port input is detected. 5. As for details, refer to the external interrupt structure. 6. The threshold value of port input is different from that of external interrupt input. Fig 4. Port block diagram (2) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 9 of 124 4571 Group (Note 3) Register A Aj IAP3 instruction (Note 3) FR0j (Note 1) Aj OP3A instruction D T Q P3 0, P 31(Note 2) (Note 1) PWMOUT SCP instruction RCP instruction PWMOD Timer 1 underflow signal W51 T R W12 (Note 4) Key-on wakeup input Edge detection circuit IAK instruction Register A A0 K(Note 2) (Note 1) K22 Q Carrier wave output auto-control signal S R Q (Note 1) C/CNTR1(Note 2) (Note1) D Notes 1. This symbol represents a parasitic diode on the port. 2. A pplied potential to these ports must be V DD or less. 3. j represents bits 0 or 1. 4. Falling edge of port input is detected. Fig 5. Port block diagram (3) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 10 of 124 4571 Group (Note 1) P20/INT0 (Note 1) I12 Falling 0 1 Rising I13 One-sided edge detection circuit I11 0 EXF0 External 0 interrupt 1 Timer 1 count start synchronization circuit input (Note 2) L11 0 1 Both edges detection circuit SNZI0 instruction Skip Level detection circuit L10 Edge detection circuit (Note 3) Key-on wakeup input (Note 1) P21/INT1 (Note 1) I22 Falling 0 1 Rising I23 One-sided edge detection circuit I21 0 EXF1 External 1 interrupt 1 Both edges detection circuit SNZI1 instruction Skip (Note 2) Level detection circuit L12 Edge detection circuit (Note 3) L13 0 1 Key-on wakeup input Note 1: This symbol represents a parasitic diode on the port. 2: When IX2= 0(X=0 or 1) is 0, “L” level is detected. When IX2 is 1, “H” level is detected. 3: When IX2 is 0, falling edge is detected. When IX2 is 1, rising edge is detected. Fig 6. Port block diagram (4) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 11 of 124 4571 Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 7). It is unchanged with both A n instruction and AM instruction. The value of A 0 i s stored in carry flag CY with the RAR instruction (Figure 8). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 9). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 10). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “0”. When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”. Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. (CY) (M(DP)) Addition (A) ALU Fig 7. AMC instruction execution example SC instruction RC instruction CY A3 A2 A1 A 0 RAR instruction A0 CY A3 A2 A1 Fig 8. RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig 9. Registers A, B and register E TABP p instruction Specifying address 8 ROM 4 0 p 6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1 DR0 A3 A2 A1 A0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) High-order 2 bits Immediate field value p The contents of register D The contents of register A Register D (3) * Flag UPTF = 1; High-order 2 bits of reference data is transferred to the low-order 2 bits of register D. “0” is stored to the high-order 1 bit of register D. Flag UPTF = 0; Data is not transferred to register D. Fig 10. TABP p instruction execution example Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 12 of 124 4571 Group (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 11 shows the stack registers (SKs) structure. Figure 12 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first B M i nstruction, and the contents of program counter is stored in SK 0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK 0 is destroyed. Fig 11. Stack registers (SKs) structure (SP) (SK0) (PC) Main program Address 000016 NOP 000116 BM SUB1 000216 NOP 0 0001 16 SUB1 Subroutine SUB1: NOP · · · RT (PC) (SP) (SK0) 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig 12. Example of operation at subroutine call Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 13 of 124 4571 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL ( bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 13). Make sure that the PCH does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 14). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 15). • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Program counter p 6 p5 p4 p3 p2 p 1 p0 a 6 a 5 a4 a3 a2 a1 a 0 PCH Specifying page PCL Specifying address Fig 13. Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig 14. Data pointer (DP) structure Specifying bit position Set D3 0 0 0 1 Register Y (4) D 2 D1 1 D0 Port D output latch Fig 15. SD instruction execution example Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 14 of 124 4571 Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 16 shows the ROM map of M34571G6. Table 8 ROM size and pages ROM (PROM) size (× 10 bits) 4096 words 6144 words 16384 words Pages 32 (0 to 31) 48 (0 to 47) 128 (0 to 127) 98 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 1 0 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 Part number M34571G4 M34571G6 M34571GD Note 1.Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 17). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 t o 017F 16 ) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction. ROM Code Protect Address When selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp., reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, whether the ROM code protect is used or not can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering. 3FFF16 Page 127 Fig 16. ROM map of M34571GD 9 008016 008216 008416 008616 008816 008A16 008C16 8 7 6 5 4 3 2 1 0 External 0 interrupt address External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address 008E16 Voltage drop detection circuit interrupt address 00FF16 Fig 17. Page 1 (addresses 008016 to 00FF16) structure Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 15 of 124 4571 Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). Table 9 shows the RAM size. Figure 18 shows the RAM map. • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Table 9 RAM size and pages RAM size 128 words × 4 bits (512 bits) Part number M34571G4 M34571G6 M34571GD RAM 128 words × 4 bits (512 bits) Register Z Register X 0 0 1 2 3 4 5 Register Y 0 1 2 3 ... 6 7 6 7 8 9 10 11 12 13 14 15 Z=0 X=0 to 7 Y=0 to 15 128 words × 4 bits (512 bits) M34571G4 M34571G6 M34571GD Fig 18. RAM map Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 16 of 124 4571 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 10 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 11 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 12 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag except the voltage drop detection circuit interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. The voltage drop detection circuit interrupt request flag cannot be cleared to “0” at the state that the activated condition is satisfied. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 10. Table 10 Interrupt sources Priority level 1 2 3 4 5 6 Interrupt source Activated Interrupt name condition Voltage drop when supply detection circuit voltage goes interrupt lower than specified value External 0 Level change of interrupt INT0 pin External 1 Level change of interrupt INT1 pin Timer 1 interrupt Timer 1 underflow Timer 2 interrupt Timer 2 underflow Timer 3 interrupt Timer 3 underflow Interrupt address Address E in page 1 Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Table 11 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name Voltage drop detection circuit interrupt External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Interrupt request flag VDF Skip instruction SNZVD Interrupt enable bit V23 EXF0 EXF1 T1F T2F T3F SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 V10 V11 V12 V13 V20 Table 12 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 17 of 124 4571 Group (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 20). • Program counter (PC) An interrupt address is set in program counter. The address to b e e x e c u t e d w h e n r e t u r n i ng t o t h e m a i n r o u t i n e i s automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0” (the voltage drop detection circuit interrupt request flag is excluded) • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 19) • Program counter (PC) Each interrupt address • Stack register (SK) The address of main routine to be executed when returning • Interrupt enable flag (INTE) 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) 0 (excluding voltage drop detection interrupt request flag) • Data pointer, carry flag, registers A and B, skip flag Stored in the interrupt stack register (SDP) automatically Fig 20. Internal state when interrupt occurs Activated condition when supply voltage goes lower than specified value Request flag (state retained) Enable bit Enable flag Address E in page 1 VDF V23 INT0 pin interrupt waveform input Address 0 in page 1 EXF0 V10 Main routine Interrupt service routine Interrupt occurs INT1 pin interrupt waveform input Address 2 in page 1 EXF1 V11 Timer 1 underflow T1F V12 Address 4 in page 1 Timer 2 underflow T2F V13 Address 6 in page 1 Timer 3 underflow T3F V20 INTE Address 8 in page 1 EI RTI Interrupt is enabled Fig 21. Interrupt system diagram : Interrupt enabled state : Interrupt disabled state Fig 19. Program example of interrupt processing Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 18 of 124 4571 Group (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 13 Interrupt control registers Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 External 1 interrupt enable bit V10 External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A • Interrupt control register V2 The voltage drop detection circuit interrupt enable bit and timer 3 interrupt enable bit are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V2 V23 Voltage drop detector interrupt enable bit at reset : 00002 at RAM back-up : 00002 R/W TAV2/TV2A 0 Interrupt disabled (SNZVD instruction is valid) 1 Interrupt enabled (SNZVD instruction is invalid) 0 V22 Not used This bit has no function, but read/write is enabled. 1 0 This bit has no function, but read/write is enabled. V21 Not used 1 0 Interrupt disabled (SNZT3 instruction is valid) V20 Timer 3 interrupt enable bit 1 Interrupt enabled (SNZT3 instruction is invalid) Note 1.“R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 19 of 124 4571 Group (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10−V13, V20, V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 22). When an interrupt request flag is set after its interrupt is enabled 1 machine cycle System clock (STCK) T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 Interrupt enable flag (INTE) EI instruction execution cycle Interrupt enabled state Interrupt disabled state External 0, External 1 interrupt INT0 INT1 EXF0 EXF1 Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Timer 1 Timer 2 Timer 3 interrupt T1F T2F T3F Flag cleared Voltage drop detection circuit VDF interrupt Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. 2 to 3 machine cycles (Notes 1, 2) The program starts from the interrupt address. Fig 22. Interrupt sequence Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 20 of 124 4571 Group EXTERNAL INTERRUPTS The 4571 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 14 External interrupt activated conditions Name External 0 interrupt Input pin P20/INT0 Activated condition When the next waveform is input to P20/INT0 pin • Falling waveform (“H” → “L”) • Rising waveform (“L” → “H”) • Both rising and falling waveforms When the next waveform is input to P21/INT1 pin • Falling waveform (“H” → “L”) • Rising waveform (“L” → “H”) • Both rising and falling waveforms Valid waveform selection bit I11 I12 External 1 interrupt P21/INT1 I21 I22 (Note 1) P20/INT0 (Note 1) I12 Falling 0 1 Rising I13 One-sided edge detection circuit I11 0 EXF0 External 0 interrupt 1 Timer 1 count start synchronization circuit input (Note 2) L11 0 1 Both edges detection circuit SNZI0 instruction Skip Level detection circuit L10 Edge detection circuit (Note 3) Key-on wakeup input (Note 1) P21/INT1 (Note 1) I22 Falling 0 1 Rising I23 One-sided edge detection circuit I21 0 EXF1 External 1 interrupt 1 Both edges detection circuit SNZI1 instruction Skip (Note 2) Level detection circuit L12 Edge detection circuit (Note 3) L13 0 1 Key-on wakeup input Note 1: This symbol represents a parasitic diode on the port. 2: When IX2= 0(X=0 or 1) is 0, “L” level is detected. When IX2 is 1, “H” level is detected. 3: When IX2 is 0, falling edge is detected. When IX2 is 1, rising edge is detected. Fig 23. External interrupt circuit structure Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 21 of 124 4571 Group (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P20/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 22). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P20/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. (1) Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I1. (3) Clear the EXF0 flag to “0” with the SNZ0 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. (5) Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the P20/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P21/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 22). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P21/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. (1) Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I2. (3) Clear the EXF1 flag to “0” with the SNZ1 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. (5) Set both the external 1 interrupt enable bit (V11) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid waveform is input to the P21/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 22 of 124 4571 Group (3) External interrupt control registers (1) Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 15 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAI1/TI1A (2) Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. I12 Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit INT0 pin input disabled INT0 pin input enabled Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Timer 1 disabled Timer 1 enabled R/W TAI2/TI2A Interrupt control register I2 I23 INT1 pin input control bit (Note 3) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) I21 I20 INT1 pin edge detection circuit control bit Not used INT0 pin input disabled INT0 pin input enabled Falling waveform (“L” level of INT0 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected This bit has no function, but read/write is enabled. Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 23 of 124 4571 Group (4) Notes on interrupts (1) Bit 3 of register I1 When the input of the P20/INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the P20/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 24) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 24). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 24). (3) Bit 2 of register I1 When the interrupt valid waveform of the P20/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P20/INT0 pin, the external 1 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 26) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 26). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 26). • • • LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP • • • ; (×××02) ; The SNZ0 instruction is valid ...... (1) ; (1×××2) ; Control of INT0 pin input is changed ...................................................... (2) ; The SNZ0 instruction is executed (EXF0 flag cleared) ...................................................... (3) • • • LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP • • • ; (×××02) ; The SNZ0 instruction is valid ......(1) ; (1×××2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ0 instruction is executed (EXF0 flag cleared) .......................................................(3) ×: these bits are not used here. ×: these bits are not used here. Fig 24. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. • When the INT0 pin input is disabled (register I13 = “0”), set the key-on wakeup of INT0 pin to be invalid (register L10 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 25). Fig 26. External 0 interrupt program example-3 • • • LA 0 TL1A DI EPOF POF • • • ; (×××02) ; INT0 key-on wakeup disabled .....(1) ; RAM back-up ×: these bits are not used here. Fig 25. External 0 interrupt program example-2 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 24 of 124 4571 Group (4) Bit 3 of register I2 When the input of the P21/INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. • Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 27) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 27). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to (3) in Figure 27). • Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 29) and then, change the bit 2 of register I2 is changed. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 29). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to (3) in Figure 29). • • • LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP • • • ; (××0×2) ; The SNZ1 instruction is valid ......(1) ; (1×××2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ1 instruction is executed (EXF1 flag cleared) .......................................................(3) • • • LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP • • • ; (××0×2) ; The SNZ1 instruction is valid ...... (1) ; (1×××2) ; Control of INT1 pin input is changed ...................................................... (2) ; The SNZ1 instruction is executed (EXF1 flag cleared) ...................................................... (3) ×: these bits are not used here. Fig 29. External 1 interrupt program example-3 ×: these bits are not used here. Fig 27. External 1 interrupt program example-1 (5) Bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. • When the INT1 pin input is disabled (register I23 = “0”), set the key-on wakeup of INT1 pin to be invalid (register L20 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 28) . • • • LA 0 TL1A DI EPOF POF • • • ; (×0××2) ; INT1 key-on wakeup disabled .....(1) ; RAM back-up ×: these bits are not used here. Fig 28. External 1 interrupt program example-2 (6) Bit 2 of register I2 When the interrupt valid waveform of the P21/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 25 of 124 4571 Group TIMERS The 4571 Group has the following timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. FF16 n : Counter initial value Count starts n The contents of counter Reload Reload 1st underflow 2nd underflow 0016 n+1 count Timer interrupt request flag “1” “0” An interrupt occurs or a skip instruction is executed. n+1 count Time Fig 30. Auto-reload function Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 26 of 124 4571 Group The 4571 Group timer consists of the following circuits. • Prescaler : 8-bit programmable timer • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Watchdog timer: 16-bit fixed frequency timer (Timers 1, 2 and 3 have the interrupt function, respectively) Table 16 Function related timers Circuit Prescaler Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) (carrier wave output autocontrol function) 8-bit programmable binary down counter Count source • Instruction clock (INSTCK) • Instruction clock divided by 4 (INSTCK/4) • PWM signal (PWMOUT) • Prescaler output (ORCLK) • CNTR0 input (CNTR0IN) • System clock (STCK) • • • • • • PWM signal (PWMOUT) Timer 1 underflow (T1UDF) Prescaler output (ORCLK) System clock (STCK) XIN input Prescaler output divided by 2 (ORCLK/2) Frequency dividing ratio 1 to 256 • • • 1 to 256 • • • Use of output signal Control register PA Prescaler, timer 1, timer 2 and timer 3 can be controlled with the timer control registers PA, W1, W2, W3 and W5. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Timer 1 Timer 2 1 to 256 Timer 1 count source Timer 2 count source Timer 3 count source Timer 2 count source CNTR0 output Carrier wave output autocontrol • Timer 1 interrupt • CNTR0 output • Timer 2 interrupt W1 W5 W2 W5 8-bit programmable binary down counter (with carrier wave generation function) Watchdog 16-bit fixed dividing timer frequency Timer 3 1 to 256 • Instruction clock (INSTCK) 65536 • • • • • • Timer 1 count source Timer 2 count source CNTR1 output Timer 3 interrupt System reset (counting twice) Decision of flag WDF1 W1 W3 W5 - Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 27 of 124 4571 Group Division circuit Divided by 8 Divided by 4 Divided by 2 XIN MR3,MR2 11 10 01 00 System clock (STCK) Internal clock generating circuit (divided by 3) Instruction clock (INSTCK) PA1 0 1/4 1 PA0 Prescaler (8) ORCLK Reload register RPS (8) (TPSAB) (TABPS) W11, W10 00 01 10 11 W12 (Note 1) INT0SNC I10 W13 T1UDF W21, W20 00 01 10 11 T2UDF W22 (TAB2) Reload register R2 (8) (T2AB) (T2AB) (T2AB) Register B Register A Timer 2 (8) T2F Timer 2 interrupt R S Q (TAB1) Reload register R1 (8) (T1AB) (T1AB) (TR1AB) (T1AB) Register B Register A W53 0 1 (TPSAB) (TPSAB) (TABPS) Register B Register A PWMOUT ORCLK STCK CNTR0IN Timer 1 (8) T1F Timer 1 interrupt T1UDF (TAB1) PWMOUT ORCLK STCK T1UDF (TAB2) P20/INT0 I13 I12 0 1 One-sided edge detection circuit Both edges detection circuit I11 0 INTSNC 1 W50 0 D4/CNTR0 1 Port D4 output W23 0 1/2 1 W52 0 CNTR0IN 1 T1UDF T2UDF PWMOUT: PWM signal (output from timer 3) Data is set automatically from each reload register when timer underflows (auto-reload function). Note 1: Timer 1 count start synchronous circuit is synchronized with the valid edge of INT pin selected by bits 1 (I11) and 2 (I12) of register I1. Fig 31. Timers structure (1) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 28 of 124 4571 Group Register B Register A T (Note 1) Reload control circuit “H” interval expansion (T3HAB) Reload Register R3H (8) XIN ORCLK 1/2 W30 0 1 W31 (TAB3) Timer 3 (8) (T3R3L) Reload Register R3L (8) (T3AB) (T3AB) (T3AB) Register B Register A Q R PWMOD W32 1 0 W33 T3F Timer 3 interrupt (TAB3) PWMOUT C/CNTR1 PWMOD Port C output T1UDF W51 W12 R T Q D INSTCK Watchdog timer (16) 1 - - - - - - - - - - - - - 16 (Note 2) S WRST instruction Reset signal (Note 4) DWDT instruction + WRST instruction Q WDF1 R S Q D Q Watchdog reset signal reset signal WEF R (Note 3) T R T2UDF: Timer 2 underflow signal ORCLK: Prescaler output Data is set automatically from each reload register when timer underflows (auto-reload function). Note 1: When the CNTR1 output function is valid (W3 3=“1”), the value is auto-reloaded alternately from reload register R3L and R3H every timer 3 underflow. When the CNTR1 function is invalid (W3 3=“0”), the value is auto-reloaded from reload register R3L only. 2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”. 3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 4: The WEF flag is set to “1” at system reset or RAM back-up mode. Fig 32. Timers structure (2) Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 29 of 124 4571 Group Table 17 Timer control registers Timer control register PA PA1 Prescaler count source selection bit PA0 Prescaler control bit 0 1 0 1 at reset : 002 at RAM back-up : 002 W TPAA Instruction clock (INSTCK) Instruction clock divided by 4 (INSTCK/4) Stop (state initialized) Operating R/W TAW1/TW1A Timer control register W1 W13 Timer 1 count auto-stop circuit selection bit (Note 2) 0 1 0 1 W11 0 Timer 1 count source selection bits W10 0 1 1 at reset : 00002 at RAM back-up : state retained W12 Timer 1 control bit Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W10 Count source 0 1 0 1 PWM signal (PWMOUT) Prescaler output (ORCLK) System clock (STCK) CNTR0 input R/W TAW2/TW2A W11 Timer control register W2 W23 CNTR0 pin function selection bit W22 Timer 2 control bit 0 1 0 1 W21 0 Timer 2 count source selection bits W20 0 1 1 at reset : 00002 at RAM back-up : state retained Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating W20 Count source 0 1 0 1 PWM signal (PWMOUT) Prescaler output (ORCLK) System clock (STCK) Timer 1 underflow signal (T1UDF) R/W TAW3/TW3A W21 Timer control register W3 W33 CNTR1 pin output control bit W32 PWM signal “H” interval expansion function control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 W31 Timer 3 control bit W30 Timer 3 count source selection bit CNTR1 pin output invalid CNTR1 pin output valid PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 R/W TAW5/TW5A Timer control register W5 W53 Timer 1 count start synchronous circuit selection bit (Note 3) at reset : 00002 at RAM back-up : state retained 0 Count start synchronous circuit not selected 1 Count start synchronous circuit selected 0 Falling edge W52 CNTR0 pin input count edge selection bit 1 Rising edge 0 Output auto-control circuit not selected CNTR 1 pin output auto-control circuit W51 selection bit 1 Output auto-control circuit selected 0 D4 (I/O) / CNTR0 (input) W50 D4/CNTR0 pin function selection bit 1 D4 (input) /CNTR0 (I/O) Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is selected (W53 =“1”). Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”). Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 30 of 124 4571 Group (1) Timer control registers • Timer control register PA Register PA controls the count operation and count source of prescaler. Set the contents of this register through register A with the TPAA instruction. • Timer control register W1 Register W1 controls the count operation and count source of timer 1, and timer 1 count auto-stop circuit. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the count operation and count source of timer 2, and CNTR0 pin output signal function. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W3 Register W3 controls timer 3 count source, timer 3 count operation, CNTR1 pin output and PWM signal “H” interval expansion function. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. • Timer control register W5 Register W5 controls the input count edge of CNTR0 pin, the timer 1 count start synchronous circuit, CNTR1 pin output auto-control circuit and the D4/CNTR1 pin function. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler can be selected the instruction clock (INSTCK) or the instruction clock (INSTCK)/4. Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1 and 2 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with a timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register R1 with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; (1) set data in timer 1 (2) set count source by bits 0 and 1 of register W1, and (3) set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). After timer 1 control by INT0 pin is enabled by setting the bit 0 of register I1 to “1”, INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 3 of register W5 to “1”. Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” The timer 1 underflow signal divided by 2 can be output from the CNTR0 pin by setting the bit 0 of register W5 to “1” and bit 3 of register W2 to “0”. (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register R2 with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; (1) set data in timer 2 (2) set count source by bits 0 and 1 of register W2, and (3) set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). The timer 2 underflow signal divided by 2 can be output from the CNTR0 pin by setting the bit 0 of register W5 to “1” and bit 3 of register W2 to “1”. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 31 of 124 4571 Group (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with two timer 3 reload registers (R3L, R3H). Data can be set simultaneously in timer 3 and the reload register R3L with the T3AB instruction. Data can be set in the reload register R3H with the T3HAB instruction. The contents of reload register R3L set with the T3AB instruction can be set to timer 3 again with the T3R3L instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the T3HAB instruction to set data to reload register R3H while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; (1) set data in timer 3 (2) set count source by bit 0 of register W3, and (3) set the bit 1 of register W3 to “1.” When a value set in reload register R3L is n and a value set in reload register R3H is m, timer 3 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3L, and count continues (autoreload function). Timer 3 generates the PWM signal of the “L” interval set as reload register R3L, and the “H” interval set as reload register R3H. The PWM (PWMOD) signal generated by timer 3 is output from CNTR1 pin. When bit 2 of register W3 is set to “1” at this time, timer 3 extends the interval set to reload register R3H for a half period of count source. When a value set in reload register R3H is n, timer 3 divides the count source signal by m + 1.5 (m = 1 to 255). When this function is used, set “1” or more to reload register R3H. When bit 1 of register W5 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 1 underflow. However, when timer 3 is stopped, this function is canceled. Even when bit 1 of a register W3 is cleared to “0” in the “H” interval of PWM signal, timer 3 does not stop until it next timer 3 underflow. When bit 1 of register W3 is cleared to “0” in order to stop timer 3 while the PWM output is used, avoid a timing when timer 3 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. (6) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT0 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function can be selected after timer 1 control by INT0 pin is enabled by setting the bit 0 of register I1 to “1” and its function is selected by setting the bit 3 of register W5 to “1”. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to timer by inputting valid waveform to INT0 pin. The valid waveform of INT0 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to “0” or system reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (7) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop circuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. (8) Timer input/output pin (D4/CNTR0) CNTR0 pin is used to input the timer 1 count source and output the timer 1 or timer 2 underflow signal/2. The D4/CNTR0 pin function can be selected by bit 0 of register W5. The output signal can be selected by bit 0 of register W2. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the falling or rising waveform of CNTR0 input. The count edge is selected by bit 2 of register W5. (9) PWM signal output function (C/CNTR1, timer 1, timer 2) The C/CNTR1 pin is also used to output the PWM signal generated by timer 3. When the bit 3 of register W3 is set to “1”, the PWM signal can be output from the C/CNTR1 pin. In this time, set the output latch of port C to “1.” (10)Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 32 of 124 4571 Group (11) Precautions • Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. Stop prescaler counting to change its count source. • Timer count source Stop timer 1, 2 or 3 counting to change its count source. • Reading the count value Stop timer 1, 2 or 3 counting and then execute the TAB1, TAB2 or TAB3 instruction to read its data. • Writing to the timer Stop timer 1, 2 or 3 counting and then execute the T1AB, T2AB, T3AB or T3R3L instruction to write data to timer. • Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R3H while the timer 3 is operating, execute the T3HAB instruction except a timing of the timer 3 underflow. • PWM signal If the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When “H” interval expansion function of the PWM signal is used, set “1” or more to reload register R3H. Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin. • Prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 33 after prescaler and timer operations start (1) in Figure 33. Time to first underflow (3) in Figure 33 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 33 by the timing to start the timer and count source operations after count starts. When selecting CNTR0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of CNTR0 input selected by software. (2) Count source Count source (When falling edge of CNTR0 input is selected) Timer 1 value 3 2 1 0 3 2 1 0 3 2 Timer 1 underflow signal (3) (1) Timer start (4) Fig 33. Timer count start timing and count time when operation starts Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 33 of 124 4571 Group - CNTR1 pin output invalid (W33=0) Timer 3 count source Timer 3 count value (Reload register) 0316 (R3L) (R3L) Timer 3 underflow signal (R3L) (R3L) (R3L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 PWM signal PWM1 signal “L” fixed Timer 3 start - CNTR1 pin output valid (W33=1), PWM signal “H” interval expansion function invalid (W32=0) Timer 3 count source Timer 3 count value (Reload register) 0316 (R3L) (R3H) Timer 3 underflow signal 4 clock Timer 3 start 3 clock 4 clock 3 clock 4 clock (R3L) (R3H) (R3L) (R3H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 PWM signal PWM period 7 clock PWM period 7 clock - CNTR1 pin output valid (W33=1), PWM signal “H” interval expansion function valid (W32=1) (Note) Timer 3 count source Timer 3 count value (Reload register) 0316 (R3L) (R3H) Timer 3 underflow signal 4 clock Timer 3 start 3.5 clock 4 clock 3.5 clock 4 clock (R3L) (R3H) (R3L) (R3H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 PWM signal PWM period 7.5 clock PWM period 7.5 clock * : “0316” is set to reload register R3L and “02 16” is set to reload register R3H. Note: When the PWM signal “H” interval expansion function is valid, set “1” or more to reload register R3H. Fig 34. Timer 3 operation example Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 34 of 124 4571 Group • CNTR1 output auto-control circuit operation example 1 (W33 = “1”, W51 = “1”) PWM signal Timer 1 underflow signal Timer 1 start CNTR1 output CNTR1 output start * When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows. • CNTR1 output auto-control circuit operation example 2 (W33 = “1”, W51 = “1”) PWM signal Timer 1 underflow signal Register W51 Timer 1 start (1) (2) Timer 1 stop (3) CNTR1 output CNTR1 output start CNTR1 output stop (1) When the CNTR1 output auto-control function is not selected while the CNTR1 output is invalid, CNTR1 output invalid state is retained. (2) When the CNTR1 output auto-control function is not selected while the CNTR1 output is valid, CNTR1 output valid state is retained. (3) When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid. Fig 35. CNTR1 output auto-control function by timer 1 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 35 of 124 4571 Group Timer 3 count start timing (R3L = “0216”, R3H = “0216”, W33 = “1”) Machine cycle Timer 3 count source (XIN input) Register W31 Timer 3 count value (reload register) Timer 3 underflow signal PWM signal Timer 3 count start timing 0216 (R3L) 0116 0016 0216 (R3H) 0116 0016 0216 (R3L) Mi TW3A instruction execution (W3 1←1) Mi + 1 Mi + 2 Mi + 3 Timer 3 count stop timing (R3L = “0216”, R3H = “0216”, W33 = “1”) Machine cycle Timer 3 count source (XIN input) Register W31 Timer 3 count value (reload register) Timer 3 underflow signal PWM signal (Note 1) Timer 3 count stop timing 0216 (R3H) 0116 0016 0216 (R3L) 0116 0016 (R3H) 0216 Mi Mi + 1 TW3A instruction execution (W3 1←0) Mi + 2 Mi + 3 Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR1 pin output is valid (W33=“1”), a hazard may occur in the PWM signal waveform. 2: When timer count is stopped during “H” interval of the PWM signal, timer is stopped after the end of the “H” output interval. Fig 36. Timer count start/stop timing Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 36 of 124 4571 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “000016,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is initialized to “1” at system reset or RAM backup mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF16 Value of 16-bit timer (WDT) 000016 (2) WDF1 flag (2) 65534 count (Note) WDF2 flag RESET pin output (4) (1) Reset released (3) WRST instruction executed (skip executed) (5) System reset (1) After system is released from reset (= after program is started), timer WDT starts count down. (2) When timer WDT underflow occurs, WDF1 flag is set to “1”. (3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0”, the next instruction is skipped. (4) When timer WDT underflow occurs while WDF1 flag is “1”, WDF2 flag is set to “1” and the watchdog reset signal is output. (5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. Fig 37. Watchdog timer function Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 37 of 124 4571 Group When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 38). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction (refer to Figure 39). • • • WRST • • • DI DWDT WRST • • • ; WDF1 flag cleared ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig 38. Program example to start/stop watchdog timer • • • WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ; RAM back-up mode ↓ Oscillation stop • • • Fig 39. Program example when using the watchdog timer Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 38 of 124 4571 Group RESET FUNCTION System reset is performed by the followings: • “L” level is applied to the RESET pin externally, • System reset instruction (SRST) is executed, • Reset occurs by watchdog timer, • Reset occurs by built-in power-on reset • Reset occurs by voltage drop detection circuit Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. (1) RESET pin input System reset is performed certainly by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. (Note 1) RESET pin (Note 2) Pull-up transistor Voltage drop detection circuit Internal reset signal Power-on reset circuit (Note 1) SRST instruction Watchdog reset signal WEF Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be V DD or less. Fig 40. Structure of reset pin and its peripherals Reset input 1 machine cycle or more = 0.85VDD RESET 0.3VDD (Note 1) f(RING) Program starts (address 0 in page 0) XIN input is counted 5400 to 5424 times (Note 2). Notes 1: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: It depends on the internal state at reset. Fig 41. RESET pin input waveform and reset release timing Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 39 of 124 4571 Group (2) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, “L” level is output to RESET pin and system reset is performed. 100µs or less VDD (Note 1) Power-on reset circuit output Internal reset signal Power-on Reset Reset state released Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig 42. Power-on reset operation Table 18 Port state at reset Name D0−D3 D0−D3 D4 D4/CNTR0 P00−P03 P00−P03 P10−P13 P10−P13 P20, P21 P20/INT0, P21/INT1 P30, P31 P30, P31 C/CNTR1 C/CNTR1 K K Note 1.Output latch is set to “1.” Note 2.The output structure is N-channel open-drain. Note 3.Pull-up transistor is turned OFF. Function State High-impedance (Notes 1, 2) High-impedance (Note 1) High-impedance (Notes 1, 3) High-impedance (Notes 1, 3) High-impedance (Notes 1, 3) High-impedance (Notes 1, 2) (VSS) High-impedance Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 40 of 124 4571 Group (4) Internal state at reset Figure 43 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 43 are undefined, so set the initial value to them. • Program counter (PC) Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) • Power down flag (P) • External 0 interrupt request flag (EXF0) • External 1 interrupt request flag (EXF1) • Interrupt control register V1 • Interrupt control register V2 • Interrupt control register I1 • Interrupt control register I2 • Timer 1 interrupt request flag (T1F) • Timer 2 interrupt request flag (T2F) • Timer 3 interrupt request flag (T3F) • Watchdog timer flags (WDF1, WDF2) • Watchdog timer enable flag (WEF) • Timer control register PA • Timer control register W1 • Timer control register W2 •Timer control register W3 • Timer control register W5 • Clock control register MR • Key-on wakeup control register K0 • Key-on wakeup control register K1 • Key-on wakeup control register K2 • Key-on wakeup control register L1 • Pull-up control register PU0 • Pull-up control register PU1 • Pull-up control register PU2 • Port output structure control register FR0 • Port output structure control register FR1 • Carry flag (CY) • Register A • Register B • Register D • Register E • Register X • Register Y • Register Z • Stack pointer (SP) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Interrupt disabled) (Interrupt disabled) (Interrupt disabled) (Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) × × × × × × 0 0 × × 0 0 × × 0 0 × 0 0 × 1 1 × 1 “X” represents undefined. Fig 43. Internal state at reset Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 41 of 124 4571 Group VOLTAGE DROP DETECTION CIRCUIT T he built-in voltage drop detection circuit is used to set the voltage drop detection circuit interrupt request flag (VDF) or to perform system reset. The voltage drop detection circuit stops at RAM back-up mode. EPOF instruction + POF instruction Key-on wakeup signal S R Q Q Oscillation stop signal VINT + VDF Voltage drop detection circuit interrupt Interrupt occurrence V Pull-up transistor RST- /V RST+ + Reset occurrence Voltage drop detection circuit Internal reset signal (Note 1) RESET pin (Note 2) Power-on reset circuit (Note 1) SRST instruction Watchdog reset signal WEF Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be V DD or less. Fig 44. Voltage drop detection reset circuit Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 42 of 124 4571 Group (1) Voltage drop detection circuit interrupt request flag (VDF) Voltage drop detection circuit interrupt request flag (VDF) is set to “1” when the supply voltage goes the defined value (VINT) or less. Moreover, voltage drop detection circuit interrupt request flag (VDF) is cleared to “0” when the supply voltage goes the defined value (VINT) or more. The state of the interrupt request flag can be examined with the skip instruction (SNZVD). Use the interrupt control register V2 to select an interrupt or a skip instruction. Unlike other interrupt request flags, even when the interrupt occurs or the skip instruction is executed, the voltage drop detection circuit interrupt request flag is not cleared to “0”. VDD VINT (interrupt occurrence voltage) VRST+(reset release voltage) VRST-(reset occurrence voltage) Voltage drop detection circuit interrupt request flag (VDF) (Note 3) (2) Voltage drop detection circuit reset System reset is performed when the supply voltage goes the defined value (VRST-) or less (“L” level is not output to RESET pin.). However, unlike the normal system reset, the oscillation circuit is stopped. When the supply voltage goes the defined value (VRST-) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released. Voltage drop detection circuit reset signal (Note 2) (Note 1) Notes 1: Microcomputer starts operation after input clock is counted 5400 to 5424 times. 2: “L” level is not output from RESET pin. The oscillation circuit is stopped. 3: After microcomputer starts operation, the detection of the interrupt occurrence voltage is performed. Fig 45. Voltage drop detection circuit operation waveform VDD Recommended operating condition min.value VRST+ VRSTNo reset Program failure may occur. Normal operation VDD Recommended operating condition min.value VRST+ VRSTReset (3) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and rises again, depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 46); supply voltage does not fall below to VRST-, and its voltage rises again with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that. Fig 46. VDD and VRST- Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 43 of 124 4571 Group RAM BACK-UP MODE The 4571 Group has the RAM back-up mode. When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 19 shows the function and states retained at RAM back-up. Figure 47 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF instruction and POF instruction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when; • “L” level is applied to RESET pin, • system reset (SRST) is performed, • reset by watchdog timer is performed, • reset by the built-in power-on reset circuit is performed, or • reset by the voltage drop detection circuit is performed. In this case, the P flag is “0.” Table 19 Functions and states retained at RAM back-up Function Program counter (PC), stack pointer (SP) (Table 2), carry flag (CY), registers A, B Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Clock control register MR Timer 1, Timer 2, Timer 3 function Watchdog timer function Timer control registers PA, W3 Timer control registers W1, W2, W5 Voltage drop detection circuit Port level Key-on wakeup control registers K0 to K2, L1 Pull-up control registers PU0 to PU2 Port output structure control registers FR0, FR1 External interrupt request flags (EXF0, EXF1) Timer interrupt request flags (T1F, T2F, T3F) Voltage drop detection circuit interrupt request flag (VDF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) RAM back-up × O × O × (Note 3) × (Note 4) × O (Note 5) (Note 6) O O O × (Note 3) × × × (Note 4) × (Note 4) Note 1.“O” represents that the function can be retained, and “×” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. Note 2.The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. Note 3.The state of the timer is undefined. Note 4.Initialize the watchdog timer flag WDF1 with the WRST instruction, and then set the system to be in the RAM back-up mode. Note 5.The voltage drop detection circuit is invalid. Note 6.C/CNTR pin outputs “L” level. Other ports retain their output levels. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 44 of 124 4571 Group (4) Return signal An external wakeup signal is used to return from the RAM backup mode because the oscillation is stopped. Table 20 shows the return condition for each return source. (5) Control registers • Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. • Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K1 to register A. • Key-on wakeup control register K2 Register K2 controls the ports K and P2 key-on wakeup function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. • Key-on wakeup control register L1 Register L1 controls the selection of the selection of the INT0 pin return condition and INT0 pin key-on wakeup function and the selection of the INT1 pin return condition and INT1 pin key-on wakeup function. Set the contents of this register through register A with the TL1A instruction. In addition, the TAL1 instruction can be used to transfer the contents of register L1 to register A. Table 20 Return source and return condition Return source Port P00−P03 Port P10−P13 Port P20, P21 Port K INT pin Return condition Return by an external falling edge (“H” → “L”) input. Remarks The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to “H” level before going into the RAM back-up state. The key-on wakeup function can be selected by one port unit. Select the return level (“L” level or “H” level) with the register I1 and return condition (level or edge) with the register L1 according to the external state before going into the RAM back-up state. • Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. • Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A. • Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P2 pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. In addition, the TAPU2 instruction can be used to transfer the contents of register PU2 to register A. • Interrupt control register I1 Register I1 controls the valid waveform/level of the INT0 pin and the input control of INT0 pin. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. External wakeup signal Return by an external “H” level or “L” level input, or falling edge (“H” → “L”) or rising edge (“L” → “H”). When the return level is input, the EXF0 flag is not set. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 45 of 124 4571 Group State A Reset (Note 1) Operating state POF instruction execution (Note 2) State D RAM back-up mode f(XIN) : operating Key-on wakeup (Notes 1, 3) f(XIN) : Stop Notes 1: Microcomputer starts its operation after counting f( XIN) 5400 to 5424 times from system is released from reset. 2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 3: The operation mode also returns to the initial state (internal frequency divided by 4 mode) (register MR initialized). Fig 47. State transition Power down flag (P) EPOF instruction POF + instruction S Q Software start P = “1” ? No Cold start Yes Internal reset signal R SNZP instruction - Set source ... EPOF instruction + POF instruction - Clear source ... Reset Warm start Fig 48. Set source and clear source of the P flag Fig 49. Start condition identified example using the SNZP instruction Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 46 of 124 4571 Group Table 21 Key-on wakeup control registers Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/TK1A Key-on wakeup control register K1 K13 K12 K11 K10 Port P13 key-on wakeup control bit Port P12 key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK2/TK2A Key-on wakeup control register K2 K23 Not used K22 K21 K20 Port K key-on wakeup control bit Port P21 key-on wakeup control bit Port P20 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained This bit has no function, but read/write is enabled. Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAL1/TL1A Key-on wakeup control register L1 L13 INT1 pin return condition selection bit at reset : 00002 at RAM back-up : state retained 0 Return by level 1 Return by edge 0 Key-on wakeup not used INT1 pin valid waveform/ L12 level selection bit 1 Key-on wakeup used 0 Return by level INT0 pin L11 return condition selection bit 1 Return by edge 0 Key-on wakeup not used INT0 pin L10 key-on wakeup control bit 1 Key-on wakeup used Note 1.“R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 47 of 124 4571 Group Table 22 Pull-up control registers Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON R/W TAPU1/TPU1A at RAM back-up : state retained R/W TAPU0/TPU0A Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained Pull-up control register PU2 PU23 Not used at reset : 00002 at RAM back-up : state retained R/W TAPU2/TPU2A 0 This bit has no function, but read/write is enabled. 1 0 PU22 Not used This bit has no function, but read/write is enabled. 1 0 Pull-up transistor OFF Port P21 pull-up transistor PU21 control bit 1 Pull-up transistor ON 0 Pull-up transistor OFF Port P20 pull-up transistor PU20 control bit 1 Pull-up transistor ON Note 1.“R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 48 of 124 4571 Group CLOCK CONTROL The clock control circuit consists of the following circuits. • Ceramic oscillation circuit • Frequency divider • Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 50 shows the structure of the clock control circuit. Division circuit divided by 8 divided by 4 XIN Ceramic oscillation circuit divided by 2 MR3, MR2 11 10 01 00 System clock (STCK) Internal clock generation circuit (divided by 3) Instruction clock (INSTCK) Voltage drop detection circuit (reset occurs) Oscillation stop signal Q S R EPOF instruction + POF instruction Key-on wakeup signal RESET Fig 50. Clock control circuit structure Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 49 of 124 4571 Group (1) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT (Figure 51). (2) External clock When the external signal clock is used for the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 52). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (3) Clock control register MR Register MR controls the selection of operation mode. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. XIN 4571 XOUT Rd CIN COUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. Fig 51. Ceramic resonator external circuit 4571 XIN XOUT VDD External oscillation circuit VSS Fig 52. External clock input circuit Table 23 Return source and return condition Clock control register MR MR3 at reset : 11112 at RAM back-up : 11112 R/W TAMR/TMRA Operation mode MR3 MR2 0 0 Through mode (frequency not divided) 0 1 Frequency divided by 2 mode Operation mode selection bits MR2 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode 0 This bit has no function, but read/write is enabled. MR1 Not used 1 0 MR0 Not used This bit has no function, but read/write is enabled. 1 Note 1.“R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 50 of 124 4571 Group QzROM Writing Mode In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is applicable for this microcomputer. Table 24 lists the pin description (QzROM writing mode) and Figure 53 shows the pin connections. Refer to Figure 54 for examples of a connection with a serial programmer. Contact the manufacturer of your serial programmer for serial pro-grammer. Refer to the user ’s manual of your serial programmer for details on how to use it. Table 24 Pin description (QzROM writing mode) Pin VDD VSS K P01 P00 P10 RESET Name Power source GND VPP input SDA input/output SCLK input PGM input Reset input I/O − − − I/O Input Input Input − − I/O • • • • • • Function Power supply voltage pin. GND pin. QzROM programmable power source pin. QzROM serial data I/O pin. QzROM serial clock input pin. QzROM read/program pulse input pin. Clock input XIN Clock output XOUT I/O port P02, P03, P11−P13, P20/INT0, P21/INT1, P30, P31, D0−D3, D4/CNTR0, C/CNTR1 • Reset input pin. • Input “L” level signal. • Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. • Input “H” or “L” level signal or leave the pin open. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 51 of 124 4571 Group VDD VSS (Note) VDD VSS XIN XOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 C/CNTR1 D4/CNTR0 D3 D2 D1 D0 P31 P30 P21/INT1 P20/INT0 P13 P12 M34571Gx-XXXFP M34571GxFP VPP RESET SCLK SDA K RESET P00 P01 P02 P03 PGM P10 P11 Package code: PRSP0024GA-A (24P2Q-A) Note: Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. : QzROM pin Fig 53. Pin connection diagram Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 52 of 124 4571 Group 4571 Group T_VDD VDD T_VPP K T_TXD T_RXD T_SCLK T_BUSY T_PGM/OE/MD RESET circuit T_RESET GND N.C. 1 kΩ P01 (SDA) P00 (SCLK) P10 (PGM) RESET Vss XIN XOUT Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 54. When using programmer of Suisei Electronics System Co., LTD, connection example Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 53 of 124 4571 Group DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 54 of 124 4571 Group LIST OF PRECAUTIONS (1) Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. Port K is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS or VDD. Do not leave this pin open. When port is used for key matrix, connect it to VDD through a pull-up resistor. (2) Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. • Register Z (2 bits) • Register D (3 bits) • Register E (8 bits) (4) Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. • Register Z (2 bits) • Register X (4 bits) • Register Y (4 bits) • Register D (3 bits) • Register E (8 bits) (5) Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. (6) Stack registers (SKS) S tack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. (7) Multifunction • The input of D4 can be used even when CNTR0 (output) is selected. The input/output of D 4 c an be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and D4 since the input threshold value of CNTR0 pin is different from that of port D4. • “H” output function of port C can be used even when the CNTR1 (output) is used. • The input/output of P20 can be used even when INT0 is used. Be careful when using inputs of both INT0 and P20 since the input threshold value of INT0 pin is different from that of port P20. • The input/output of P21 can be used even when INT1 is used. Be careful when using inputs of both INT1 and P21 since the input threshold value of INT1 pin is different from that of port P21. (8) Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (9) POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continuously. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 55 of 124 4571 Group (10)P20/INT0 pin (1) Bit 3 of register I1 When the input of the P20/INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the P20/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 55) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 55). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 55). (3) Bit 2 of register I1 When the interrupt valid waveform of the P20/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P20/INT0 pin, the external 1 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 57) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 57). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 57). • • • LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP • • • ; (×××02) ; The SNZ0 instruction is valid ...... (1) ; (1×××2) ; Control of INT0 pin input is changed ...................................................... (2) ; The SNZ0 instruction is executed (EXF0 flag cleared) ...................................................... (3) • • • LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP • • • ; (×××02) ; The SNZ0 instruction is valid ......(1) ; (1×××2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ0 instruction is executed (EXF0 flag cleared) .......................................................(3) ×: these bits are not used here. ×: these bits are not used here. Fig 55. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. • When the INT0 pin input is disabled (register I13 = “0”), set the key-on wakeup of INT0 pin to be invalid (register L10 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 56). Fig 57. External 0 interrupt program example-3 • • • LA 0 TL1A DI EPOF POF • • • ; (×××02) ; INT0 key-on wakeup disabled .....(1) ; RAM back-up ×: these bits are not used here. Fig 56. External 0 interrupt program example-2 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 56 of 124 4571 Group (11)P21/INT1 pin (1) Bit 3 of register I2 When the input of the P21/INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. • Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 58) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 58). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to (3) in Figure 58). (3) Bit 2 of register I2 When the interrupt valid waveform of the P21/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. • Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 60) and then, change the bit 2 of register I2 is changed. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 60). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to (3) in Figure 60). • • • LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP • • • ; (××0×2) ; The SNZ1 instruction is valid ...... (1) ; (1×××2) ; Control of INT1 pin input is changed ...................................................... (2) ; The SNZ1 instruction is executed (EXF1 flag cleared) ...................................................... (3) • • • LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP • • • ; (××0×2) ; The SNZ1 instruction is valid ......(1) ; (1×××2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ1 instruction is executed (EXF1 flag cleared) .......................................................(3) ×: these bits are not used here. ×: these bits are not used here. Fig 58. External 1 interrupt program example-1 (2) Bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. • When the INT1 pin input is disabled (register I23 = “0”), set the key-on wakeup of INT1 pin to be invalid (register L20 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 59) . • • • LA 0 TL1A DI EPOF POF • • • ; (×0××2) ; INT1 key-on wakeup disabled .....(1) Fig 60. External 1 interrupt program example-3 ; RAM back-up ×: these bits are not used here. Fig 59. External 1 interrupt program example-2 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 57 of 124 4571 Group (12)Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. (13)Timer count source Stop timer 1, 2 or 3 counting to change its count source. (14)Reading the count value Stop timer 1, 2 or 3 counting and then execute the TAB1, TAB2 or TAB3 instruction to read its data. (15)Writing to the timer Stop timer 1, 2 or 3 counting and then execute the T1AB, T2AB, T3AB or T3R3L instruction to write data to timer. (16)Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R3H while the timer 3 is operating, execute the T3HAB instruction except a timing of the timer 3 underflow. (17)PWM signal If the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When “H” interval expansion function of the PWM signal is used, set “1” or more to reload register R3H. Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin. (18)Prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 61 after prescaler and timer operations start (1) in Figure 61. Time to first underflow (3) in Figure 61 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 61 by the timing to start the timer and count source operations after count starts. When selecting CNTR0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of CNTR0 input selected by software. (19)Watchdog timer • The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function. • The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. • When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. (20)External clock Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (21)QzROM (1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritten because of overvoltage. Take care especially at turning on the power. (2) As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. (22)Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “0016” for protect enabled or “FF16” for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than “0016” and “FF 16” can not be accepted. (2) Count source Count source (When falling edge of CNTR0 input is selected) Timer 1 value 3 2 1 0 3 2 1 0 3 2 Timer 1 underflow signal (3) (1) Timer start (4) Fig 61. Timer count start timing and count time when operation starts Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 58 of 124 4571 Group NOTES ON NOISE Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1. Shortest wiring length (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring. In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET p in is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. (2) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Noise Noise XIN XOUT VSS XIN XOUT VSS Reset circuit VSS RESET VSS N.G. Fig 63. Wiring for clock I/O pins O.K. N.G. Reset circuit VSS RESET VSS (3) Port K Wiring Do not leave port K open. Always connect it to the VDD pin or VSS pin using the thickest wire at the shortest distance. When port K is used for key matrix, connect it to the VDD pin through a pull-up resistor. In that case too, place a pull-up resistor close to port K and connect it to port K or the VDD pin using the thickest wire at the shortest distance as above. Port K is also used as the power source input pin (VPP pin) for the built-in QzROM. When programming to the QzROM, the impedance of port K is low so that the electric writing current will flow into the QzROM. This allows noise to enter easily. If noise enters from port K, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. (Note) O.K. Fig 62. Wiring for the RESET pin VDD VSS VDD (Note) Shortest distance VSS Shortest distance K (Note) K (Note) (Note) VDD VSS Shortest distance A pull-up resistor K (Note) Note: This indicates pin. Shortest distance Fig 64. Wiring for port K Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 59 of 124 4571 Group 2. Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VDD line as follows: • Connect a bypass capacitor across the VSS pin and the VDD pin at equal length. • Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VDD line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. 3. Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. VDD VDD VSS VSS Noise (Note) N.G. O.K. Thermistor Microcomputer Analog input pin Fig 65. Bypass capacitor across the VSS line and the VDD line N.G. O.K. VSS Note : The resistor is used for dividing resistance with a thermistor. Fig 66. Analog signal line and a resistor and a capacitor Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 60 of 124 4571 Group 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig 69. Vss pattern on the underside of an oscillator 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: • Connect a resistor of 100 Ω or more to an I/O port in series. • As for an input port, read data several times by a program for checking whether input levels are equal or not. • As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. • Rewrite data to pull-up control registers at fixed periods. 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Microcomputer Mutual inductance M Large current GND Fig 67. Wiring for a large current signal line XIN XOUT VSS Do not cross N.G. CNTR XIN XOUT VSS Fig 68. Wiring to a signal line where potential levels change frequently Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 61 of 124 4571 Group • Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and deter-mines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • Decrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT) ← N EI Main processing ≠N (SWDT) =N? N Interrupt processing routine (SWDT) ← (SWDT)−1 Interrupt processing >0 RTI Return Main routine errors (SWDT) ≤0? ≤0 Interrupt processing routine errors Fig 70. Watchdog timer by software Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 62 of 124 4571 Group CONTROL REGISTERS Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at RAM back-up : 00002 R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Voltage drop detector interrupt enable bit Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 Interrupt disabled (SNZVD instruction is valid) Interrupt enabled (SNZVD instruction is invalid) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) at reset : 00002 at RAM back-up : state retained R/W TAI1/TI1A Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 I12 Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit INT0 pin input disabled INT0 pin input enabled Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Timer 1 disabled Timer 1 enabled R/W TAI2/TI2A Interrupt control register I2 I23 INT1 pin input control bit (Note 3) 0 1 0 1 at reset : 00002 at RAM back-up : state retained I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) 0 1 0 I20 Not used This bit has no function, but read/write is enabled. 1 Note 1.”R” represents read enabled, and “W” represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set. I21 INT1 pin edge detection circuit control bit INT0 pin input disabled INT0 pin input enabled Falling waveform (“L” level of INT0 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 63 of 124 4571 Group Timer control register PA PA1 PA0 Prescaler count source selection bit Prescaler control bit 0 1 0 1 at reset : 002 at RAM back-up : 002 W TPAA Instruction clock (INSTCK) Instruction clock divided by 4 (INSTCK)/4 Stop (state initialized) Operating R/W TAW1/TW1A Timer control register W1 W13 Timer 1 count auto-stop circuit selection bit (Note 2) 0 1 0 1 0 Timer 1 count source selection bits W10 0 1 1 at reset : 00002 at RAM back-up : state retained W12 Timer 1 control bit Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM output (PWMOUT) Prescaler output (ORCLK) System clock (STCK) CNTR0 input R/W TAW2/TW2A 0 1 0 1 W11 W10 W11 Timer control register W2 W23 CNTR0 pin function selection bit W22 Timer 2 control bit 0 1 0 1 0 Timer 2 count source selection bits W20 0 1 1 at reset : 00002 at RAM back-up : state retained Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source PWM output (PWMOUT) Prescaler output (ORCLK) System clock (STCK) Timer 1 underflow signal (T1UDF) R/W TAW3/TW3A 0 1 0 1 W21 W20 W21 Timer control register W3 W33 CNTR1 pin output control bit W32 PWM signal “H” interval expansion function control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 W31 Timer 3 control bit W30 Timer 3 count source selection bit CNTR1 pin output invalid CNTR1 pin output valid PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output/2 at reset : 00002 at RAM back-up : state retained R/W TAW5/TW5A Timer control register W5 W53 Timer 1 count start synchronous circuit selection bit (Note 3) 0 1 0 1 W52 CNTR0 pin input count edge selection bit CNTR 1 pin output auto-control circuit selection bit Count start synchronous circuit not selected Count start synchronous circuit selected Falling edge Rising edge 0 Output auto-control circuit not selected W51 1 Output auto-control circuit selected 0 D4 (I/O) / CNTR0 (input) W50 D4/CNTR0 pin function selection bit 1 D4 (input) /CNTR0 (I/O) Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is selected (W53 =“1”). Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”). Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 64 of 124 4571 Group Clock control register MR at reset : 11112 MR3 MR2 at RAM back-up : 11112 Operation mode R/W TAMR/TMRA MR3 Operation mode selection bits MR2 MR1 Not used MR0 Not used 0 0 1 1 0 1 0 1 0 1 0 1 Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/TK1A Key-on wakeup control register K1 K13 K12 K11 K10 Port P13 key-on wakeup control bit Port P12 key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK2/TK2A Key-on wakeup control register K2 K23 K22 K21 K20 Not used Port K key-on wakeup control bit Port P21 key-on wakeup control bit Port P20 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained This bit has no function, but read/write is enabled. Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAL1/TL1A Key-on wakeup control register L1 L13 INT1 pin return condition selection bit at reset : 00002 at RAM back-up : state retained 0 Return by level 1 Return by edge 0 Falling waveform/“L” level INT1 pin valid waveform/ L12 level selection bit 1 Rising waveform/“H” level 0 Return by level INT0 pin L11 return condition selection bit 1 Return by edge 0 Key-on wakeup not used INT0 pin L10 key-on wakeup control bit 1 Key-on wakeup used Note 1.“R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 65 of 124 4571 Group Pull-up control register PU0 PU03 PU02 PU01 PU00 at reset : 00002 0 1 0 1 0 1 0 1 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained R/W TAPU0/TPU0A Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 at reset : 00002 0 1 0 1 0 1 0 1 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained R/W TAPU1/TPU1A Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU2 PU23 Not used PU22 Not used PU21 PU20 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W TAPU2/TPU2A This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON W TFR0A Port P21 pull-up transistor control bit Port P20 pull-up transistor control bit Port output structure control register FR0 FR03 Not used FR02 Not used FR01 Port P31 output structure selection bit FR00 Port P30 output structure selection bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR1A Port output structure control register FR1 FR13 Port D3 output structure selection bit at reset : 00002 at RAM back-up : state retained 0 N-channel open-drain output 1 CMOS output 0 N-channel open-drain output FR12 Port D2 output structure selection bit 1 CMOS output 0 N-channel open-drain output FR11 Port D1 output structure selection bit 1 CMOS output 0 N-channel open-drain output FR10 Port D0 output structure selection bit 1 CMOS output Note 1. “R” represents read enabled, and “W” represents write enabled. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 66 of 124 4571 Group INSTRUCTIONS Each instruction is described as follows; 1. Index list of instruction function 2. Machine instructions (index by alphabet) 3. Machine instructions (index by function) 4. Instruction code table SYMBOL Symbol A B DR E V1 V2 I1 I2 PA W1 W2 W3 W5 MR K0 K1 K2 L1 PU0 PU1 PU2 FR0 FR1 X Y Z DP Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Timer control register PA (2 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W5 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Key-on wakeup control register L1 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Pull-up control register PU2 (4 bits) Port output structure control register FR0 (4 bits) Port output structure control register FR1 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol T1F T2F T3F WDF1 WEF INTE EXF0 EXF1 VDF P D P0 P1 P2 P3 x y z p n i j A3 A2 A1 A0 Contents Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Voltage drop detection circuit interrupt request flag Power down flag Port D (5 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (2 bits) Port P3 (2 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0 ← PC Program counter (14 bits) PCH High-order 7 bits of program counter PCL Low-order 7 bits of program counter SK Stack register (14 bits × 8) SP Stack pointer (3 bits) CY Carry flag RPS Prescaler reload register (8 bits) C Hex. C + Hex. number x (also same for others) R1L Timer 1 reload register (8 bits) + R2 Timer 2 reload register (8 bits) x R3L Timer 3 reload register (8 bits) ? Decision of state shown before “?” R3H Timer 3 reload register (8 bits) ←→ Data exchange between a register and memory PS Prescaler T1 Timer 1 AND Logical multiplication T2 Timer 2 OR Logical addition T3 Timer 3 Note 1.The 4571 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. () − M (DP) a p, a Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 67 of 124 4571 Group INDEX LIST OF INSTRUCTION FUNCTION Group Mnemonic ing TAB TBA TAY TYA Register to register transfer Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7−E4) ← (B) (E3−E0) ← (A) (B) ← (E7−E4) (A) ← (E3−E0) (DR2−DR0) ← (A2−A0) (A2−A0) ← (DR2−DR0) (A3) ← 0 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 (A) ← (X) (A2−A0) ← (SP2−SP0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) − 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Page 88, 103 95, 103 95, 103 101, 103 Group Mnemonic ing LA n TABP p (A) ← n n = 0 to 15 Function Page 76, 105 89, 105 TEAB TABE TDA TAD TAZ TAX TASP LXY x, y 96, 103 89, 103 95, 103 90, 103 95, 103 94, 103 93, 103 OR 77, 103 77, 103 76, 103 74, 103 91, 103 SC RC SZC CMA RAR Arithmetic operation (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (UPTF) = 1, (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A)AND(M(DP)) (A) ← (A)OR(M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) CY A3A2A1A0 AM AMC An AND 71, 105 71, 105 71, 105 71, 105 78, 105 82, 105 80, 105 86, 105 73, 105 79, 105 RAM addresses LZ z INY DEY TAM j SB j Bit operation 102, 103 XAM j RAM to register transfer (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n n = 0 to 15 (PCL) ← a6−a0 (PCH) ← p (PCL) ← a6−a0 (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) 81, 105 79, 105 86, 105 83, 107 83, 107 RB j SZB j SEAM SEA n XAMD j 102, 103 XAMI j 102, 103 Comparison operation TMA j 98, 103 Branch operation Ba BL p, a BLA p 72, 107 72, 107 72, 107 M34571G4: p=0 to 31 M34571G6: p=0 to 47 M34571GD: p=0 to 127 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 68 of 124 4571 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group Mnemonic ing BM a Function (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (PC) ← (SK(SP)) (SP) ← (SP) − 1 (PC) ← (SK(SP)) (SP) ← (SP) − 1 (PC) ← (SK(SP)) (SP) ← (SP) − 1 (INTE) ← 0 (INTE) ← 1 V10 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : NOP I12 = 0 : (INT0) = “L” ? I12 = 1 : (INT0) = “H” ? V11 = 0 : (EXF1) = 1 ? (EXF1) ← 0 V11 = 1 : NOP I22 = 0 : (INT1) = “L” ? I22 = 1 : (INT1) = “H” ? (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) Page 72, 107 Group Mnemonic ing TPAA TAW1 TW1A (PA0) ← (A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W5) (W5) ← (A) Function Page 98, 109 93, 109 100, 109 Subroutine operation BML p, a 73, 107 TAW2 TW2A 94, 109 101, 109 BMLA p 73, 107 TAW3 TW3A TAW5 94, 109 101, 109 94, 109 101, 109 RTI Return operation 81, 107 TW5A 80, 107 81, 107 74, 109 74, 109 83, 109 Timer operation RT RTS DI EI SNZ0 TABPS TPSAB (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) (RPS7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) (B) ← (T17−T14) (A) ← (T13−T10) (R17−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) (R17−R14) ← (B) (R13−R10) ← (A) (B) ← (T27−T24) (A) ← (T23−T20) (R27−R24) ← (B) (T27−T24) ← (B) (R23−R20) ← (A) (T23−T20) ← (A) (B) ← (T37−T34) (A) ← (T33−T30) (R3L7−R3L4) ← (B) (T37−T34) ← (B) (R3L3−R3L0) ← (A) (T33−T30) ← (A) (T37−T30) ← (R3L7−R3L0) (R3H7−R3H4) ← (B) (R3H3−R3H0) ← (A) 89, 111 99, 111 TAB1 T1AB 88, 111 87, 111 SNZI0 SNZ1 Interrupt operation 84, 109 83, 109 TR1AB TAB2 84, 109 T2AB 93, 109 100, 109 100, 111 88, 111 87, 111 SNZI1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAB3 93, 109 100, 109 89, 111 87, 111 T3AB 90, 109 96, 109 90, 109 97, 109 T3R3L T3HAB 88, 111 87, 111 M34571G4: p=0 to 31 M34571G6: p=0 to 47 M34571GD: p=0 to 127 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 69 of 124 4571 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group Mnemonic ing SNZT1 Timer operation Function V12 = 0 : (T1F) = 1 ? (T1F) ← 0 V12 = 1 : SNZT1=NOP V13 = 0 : (T2F) = 1 ? (T2F) ← 0 V13 = 1 : SNZT2=NOP V20 = 0 : (T3F) = 1 ? (T3F) ← 0 V20 = 1 : SNZT3=NOP (A) ← (P0) (P0) ← (A) (A) ←(P1) (P1) ← (A) (A1, A0) ← (P21, P20) (A3, A2) ← 0 (P21, P20) ← (A1, A0) (A1, A0) ← (P31, P30) (A3, A2) ← 0 (P31, P30) ← (A1, A0) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 4 (D(Y)) ← 1 (Y) = 0 to 4 (D(Y)) = 0 ? (Y) = 0 to 4 (C) ← (0) (C) ← (1) (A0) ← (K) (A3−A1) ← 0 (FR0) ← (A) (FR1) ← (A) (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (PU2) (PU2) ← (A) Page 84, 111 Group Mnemonic ing TAK0 TK0A Input/Output operation Function (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (A) ← (L1) (L1) ← (A) (A) ← (MR) (MR) ← (A) (PC) ← (PC)+1 RAM back-up POF instruction valid (P) = 1 ? V23 = 0 : (VDF) = 1? V23 = 0 : NOP (WDF1) = 1 ? (WDF1) ← 0 Stop of watchdog timer function enabled System reset (UPTF) ←0 (UPTF) ←1 p6 ← 0 when TABP p instruction is executed p6 ← 1 when TABP p instruction is executed Page 90, 115 97, 115 91, 115 97, 115 91, 115 97, 115 91, 115 98, 115 92, 115 98, 115 77, 115 79, 115 75, 115 84, 115 85, 115 102, 115 SNZT2 85, 111 TAK1 TK1A TAK2 TK2A TAL1 TL1A TAMR TMRA NOP POF SNZT3 85, 111 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A CLD RD Input/Output operation 75, 113 77, 113 75, 113 78, 113 76, 113 78, 113 76, 113 78, 113 73, 113 80, 113 82, 113 86, 113 80, 113 82, 113 75, 113 96, 113 96, 113 92, 113 99, 113 92, 113 99, 113 92, 113 99, 113 Other operation EPOF SNZP SNZVD WRST DWDT SRST RUPT SUPT RBK SBK 74, 115 85, 115 81, 115 86, 115 79, 115 82, 115 SD SZD RCP SCP IAK TFR0A TFR1A TAPU0 TPU0A TAPU1 TPU1A TAPU2 TPU2A Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 70 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruction D9 code 00 Operation: D0 Number of words 6 n 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition Overflow = 0 0 1 1 0 n n n n20 (A) ← (A) + n n = 0 to 15 Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. AM (Add accumulator and Memory) Instruction D9 code 00 Operation: D0 Number of words 0 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 1 020 (A) ← (A)Å{(M(DP)) Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruction D9 code 00 Operation: D0 Number of words 0 B 16 1 Grouping: Number of cycles 1 Flag CY 0/1 Skip condition - 0 0 0 0 1 0 1 120 (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. AND (logical AND between accumulator and memory) Instruction D9 code 00 Operation: D0 Number of words 1 8 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 0 020 (A) ← (A) AND (M(DP)) Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 71 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) B a (Branch to address a) Instruction D9 code 01 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Branch operation Flag CY - Skip condition - 1 a6 a5 a4 a3 a2 a1 a0 2 1 8 a 16 +a (PCL) ← a6 to a0 Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. BL p,a (Branch Long to address a in page p) Instruction D9 code 00 D0 Number of words 2 Number of cycles 2 Flag CY - Skip condition - 1 1 1 p4 p3 p2 p1 p0 2 0 E p 16 +p a 1 p6 p5 a6 a5 a4 a3 a2 a1 a0 2 2 Operation: (PCH) ← p (PCL) ← a6 to a0 a 16 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 BLA p (Branch Long to address (D)+(A) in page p) Instruction D9 code 00 D0 Number of words 1 p 0 16 2 Number of cycles 2 Flag CY - Skip condition - 0 0 0 1 0 0 0 020 1 p6 p5 p4 0 Operation: 0 p3 p2 p1 p0 2 2 (PCH) ← p (PCL) ← (DR2−R0, A3−A0) p 16 Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 BM a (Branch and Mark to address a in page 2) Instruction D9 code 01 Operation: D0 Number of words a a 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 a6 a5 a4 a3 a2 a1 a0 2 1 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 72 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BML p,a (Branch and Mark Long to address a in page p) Instruction D9 code 00 D0 Number of words 2 Number of cycles 2 Flag CY - Skip condition - 1 1 0 p4 p3 p2 p1 p0 2 0 c p 16 +p a 1 p6 p5 a6 a5 a4 a3 a2 a1 a0 2 2 Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 a 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Be careful not to over the stack because the maximum level of subroutine nesting is 8. BMLA p (Branch and Mark Long to address (D)+(A) in page p) Instruction D9 code 00 D0 Number of words 3 p 0 16 2 Number of cycles 2 Flag CY - Skip condition - 0 0 1 1 0 0 0 020 1 p6 p5 p4 0 Operation: 0 p3 p2 p1 p0 2 2 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) p 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) Instruction D9 code 00 Operation: D0 Number of words 1 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 0 0 120 (D) ← (1) Input/Output operation Description: Sets (1) to port D. CMA (CoMplement of Accumulator) Instruction D9 code 00 Operation: D0 Number of words 1 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 0 020 (A) ←(A) Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 73 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DEY (DEcrement register Y) Instruction D9 code 00 Operation: D0 Number of words 1 7 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition (Y) = 15 0 0 0 1 0 1 1 120 (Y) ← (Y) −1 Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. DI (Disable Interrupt) Instruction D9 code 00 Operation: D0 Number of words 0 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 0 1 0 020 (INTE) ← 0 Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruction D9 code 10 Operation: D0 Number of words 9 C 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 1 0 0 1 1 1 0 022 Stop of watchdog timer function enabled Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. EI (Enable Interrupt) Instruction D9 code 00 Operation: D0 Number of words 0 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 0 1 0 120 (INTE) ← 1 Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 74 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EPOF (Enable POF instruction) Instruction D9 code 00 Operation: D0 Number of words 5 B 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 1 120 POF instruction valid Description: Makes the immediate after POF instruction valid by executing the EPOF instruction. IAK (Input Accumulator from port K) Instruction D9 code 10 Operation: D0 Number of words 6 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 1 1 1 122 (A0) ← (K) (A3−A1) ← 0 Input/Output operation Description: Transfers the input of port K to the least significant bit (A0) of register A. “0” is stored to the high-order 3 bits (A3−A1) of register A. IAP0 (Input Accumulator from port P0) Instruction D9 code 10 Operation: D0 Number of words 6 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 0 022 (A) ← (P0) Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruction D9 code 10 Operation: D0 Number of words 6 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 0 122 (A) ← (P1) Input/Output operation Description: Transfers the input of port P1 to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 75 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP2 (Input Accumulator from port P2) Instruction D9 code 10 Operation: D0 Number of words 6 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 1 022 (A1, A0) ← (P21, P20) (A3, A2) ← 0 Input/Output operation Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. IAP3 (Input Accumulator from port P3) Instruction D9 code 10 Operation: D0 Number of words 6 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 1 122 (A1, A0) ← (P31, P30) (A3, A2) ← 0 Input/Output operation Description: Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. INY (INcrement register Y) Instruction D9 code 00 Operation: D0 Number of words 1 3 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition (Y) = 0 0 0 0 1 0 0 1 120 (Y) ← (Y) + 1 Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruction D9 code 00 Operation: D0 Number of words 7 n 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition Continuous description 0 1 1 1 n n n n20 (A) ← n n = 0 to 15 Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 76 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) LXY x,y (Load register X and Y with x and y) Instruction D9 D0 code 1 1 x3 x2 x1 x0 y3 y2 y1 y0 2 3 Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 Number of words x y 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY Skip condition Continuous description Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruction D9 code 00 Operation: D0 Number of words 4 8 +z 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition - 0 1 0 0 1 0 Z1 Z0 2 0 (Z) ← z z = 0 to 3 Description: Loads the value z in the immediate field to register Z. NOP (No OPeration) Instruction D9 code 00 Operation: D0 Number of words 0 0 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 0 020 (PC) ← (PC) + 1 Description: No operation; Adds 1 to program counter value, and others remain unchanged. OP0A (Output port P0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 0 022 (P0) ← (A) Input/Output operation Description: Outputs the contents of register A to port P0. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 77 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP1A (Output port P1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 0 122 (P1) ← (A) Input/Output operation Description: Outputs the contents of register A to port P1. OP2A (Output port P2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 1 022 (P21, P20) ← (A1, A0) Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. OP3A (Output port P3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 1 122 (P31, P30) ← (A1, A0) Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3. OR (logical OR between accumulator and memory) Instruction D9 code 00 Operation: D0 Number of words 1 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 0 120 (A) ← (A) OR (M(DP)) Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 78 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) POF (Power OFf) Instruction D9 code 00 Operation: D0 Number of words 0 2 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 1 020 RAM back-up Description: Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed just before this instruction, this instruction is equivalent to the NOP instruction. RAR (Rotate Accumulator Right) Instruction D9 code 00 Operation: D0 Number of words 1 D 16 1 Grouping: Number of cycles 1 Flag CY 0/1 Skip condition - 0 0 0 1 1 1 0 120 CY A3A2A1A0 Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instruction D9 code 00 Operation: D0 Number of words 4 C 16 +j 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition - 0 1 0 0 1 1 j j20 (Mj(DP)) ← 0 j = 0 to 3 Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). RBK (Reset BanK flag)) Instruction D9 code 00 Operation: D0 Number of words 4 0 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 0 1 1 0 020 p6 ← 0 when TABP p instruction is executed. Description: Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Note: This instruction cannot be used for the M34571G4/G6. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 79 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) Instruction D9 code 00 Operation: D0 Number of words 0 6 16 1 Grouping: Number of cycles 1 Flag CY 0 Skip condition - 0 0 0 0 0 1 1 020 (CY) ← 0 Arithmetic operation Description: Clears (0) to carry flag CY. RCP (Reset Port C) Instruction D9 code 10 Operation: D0 Number of words 8 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 0 0 1 1 0 022 (C) ← 0 Input/Output operation Description: Clears (0) to port C. RD (Reset port D specified by register Y) Instruction D9 code 00 Operation: D0 Number of words 1 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 020 (D(Y)) ← 0 However, (Y) = 0 to 4 Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y. RT (ReTurn from subroutine) Instruction D9 code 00 Operation: D0 Number of words 4 4 16 1 Grouping: Number of cycles 2 Return operation Flag CY - Skip condition - 0 1 0 0 0 1 0 020 (PC) ← (SK(SP)) (SP) ← (SP) −1 Description: Returns from subroutine to the routine called the subroutine. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 80 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTI (ReTurn from Interrupt) Instruction D9 code 00 Operation: D0 Number of words 4 6 16 1 Grouping: Number of cycles 2 Return operation Flag CY - Skip condition - 0 1 0 0 0 1 1 020 (PC) ← (SK(SP)) (SP) ← (SP) − 1 Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) Instruction D9 code 00 Operation: D0 Number of words 4 5 16 1 Grouping: Number of cycles 2 Return operation Flag CY - Skip condition Skip at uncondition 0 1 0 0 0 1 0 120 (PC) ← (SK(SP)) (SP) ← (SP) − 1 Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. RUPT (Reset UPT flag) Instruction D9 code 00 Operation: D0 Number of words 5 8 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 0 020 (UPTF) ←0 Description: Clears (0) to the high-order bit reference enable flag UPTF. Note: Even when the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is not transferred to register D. SB j (Set Bit) Instruction D9 code 00 Operation: D0 Number of words 5 C 16 +j 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition - 0 1 0 1 1 1 j j20 (Mj(DP)) ← 1 j = 0 to 3 Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 81 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SBK (Set BanK flag) Instruction D9 code 00 Operation: D0 Number of words 4 1 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 0 0 0 0 120 p6 ← 1 when TABP p instruction is executed. Description: Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Note: This instruction cannot be used for the M34571G4/G6. SC (Set Carry flag) Instruction D9 code 00 Operation: D0 Number of words 0 7 16 1 Grouping: Number of cycles 1 Flag CY 1 Skip condition - 0 0 0 0 0 1 1 120 (CY) ← 1 Arithmetic operation Description: Sets (1) to carry flag CY. SCP (Set Port C) Instruction D9 code 10 Operation: D0 Number of words 8 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 0 0 1 1 0 122 (C) ← 1 Input/Output operation Description: Sets (1) to port C. SD (Set port D specified by register Y) Instruction D9 code 00 Operation: D0 Number of words 1 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 120 (D(Y)) ← 1 (Y) = 0 to 4 Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 82 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) Instruction D9 code 00 0 Operation: 0 D0 Number of words 2 7 5 16 2 Number of cycles 2 Flag CY - Skip condition (A) = n n = 0 to 15 0 0 0 1 1 1 0 1 0 n 1 n 0 n 120 n20 (A) = n ? n = 0 to 15 n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. SEAM (Skip Equal, Accumulator with Memory) Instruction D9 code 00 Operation: D0 Number of words 2 6 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (A) = (M(DP)) 0 0 1 0 0 1 1 020 (A) = (M(DP)) ? Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag) Instruction D9 code 00 Operation: D0 Number of words 3 8 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition V10 = 0 : (EXF0) = 1 0 0 1 1 1 0 0 020 V10 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. SNZ1 (Skip if Non Zero condition of external interrupt 1 request flag) Instruction D9 code 00 Operation: D0 Number of words 3 9 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition V11 = 0 : (EXF1) = 1 0 0 1 1 1 0 0 120 V11 = 0 : (EXF1) = 1 ? (EXF1) ← 0 V11 = 1 : SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1) Description: When V11 = 0 : Clears (0) to the EXF1 flag and skips the next instruction when external 1 interrupt request flag EXF1 is “1”. When the EXF1 flag is “0”, executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 83 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin) Instruction D9 code 00 Operation: D0 Number of words 3 A 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition I12 = 0 : (INT0) = “L” I12 = 1 : (INT0) = “H” 0 0 1 1 1 0 1 020 I12 = 0 : (INT0) = “L” ? I12 = 1 : (INT0) = “H” ? (I12 : bit 2 of the interrupt control register I1) Description: When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L”. Executes the next instruction when the level of INT0 pin is “H”. When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” Executes the next instruction when the level of INT0 pin is “L”. SNZI1 (Skip if Non Zero condition of external Interrupt 1 input pin) Instruction D9 code 00 Operation: D0 Number of words 3 B 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition I22 = 0 : (INT1) = “L” I22 = 1 : (INT1) = “H” 0 0 1 1 1 0 1 120 I22 = 0 : (INT1) = “L” ? I22 = 1 : (INT1) = “H” ? Description: When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L”. Executes the next instruction when the level of INT1 pin is “H”. When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H”. Executes the next instruction when the level of INT1 pin is “L”. SNZP (Skip if Non Zero condition of Power down flag) Instruction D9 code 00 Operation: D0 Number of words 0 3 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition (P) = 1 0 0 0 0 0 0 1 120 (P) = 1 ? Description: Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”. SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V12 = 0 : (T1F) = 1 1 0 0 0 0 0 0 022 V12 = 0 : (T1F) = 1 ? (T1F) ← 0 V12 = 1 : SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Description: When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0,” executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 84 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V13 = 0 : (T2F) = 1 1 0 0 0 0 0 0 122 V13 = 0 : (T2F) = 1 ? (T2F) ← 0 V13 = 1 : SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Description: When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 2 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V20 = 0 : (T3F) = 1 1 0 0 0 0 0 1 022 V20 = 0 : (T3F) = 1 ? (T3F) ← 0 V20 = 1 : SNZT3 = NOP Description: When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. SNZVD (Skip if Non Zero condition of Voltage Detector interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 A 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition V23 = 0 : (VDF) = 1 1 0 0 0 1 0 1 022 V23 = 0 : (VDF) = 1? V23 = 1 : SNZVD = NOP Description: When V23 = 0 : Skips the next instruction when voltage detector interrupt request flag VDF is “1”. After skipping, clears (0) to the VDF flag. The VDF flag is not cleared to “0”. When V23 = 1 : This instruction is equivalent to the NOP instruction. SRST (System ReSet) Instruction D9 code 00 Operation: D0 Number of words 0 1 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 0 120 System reset Description: System reset occurs. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 85 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SUPT (Set UPT flag) Instruction D9 code 00 Operation: D0 Number of words 5 9 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 0 120 (UPTF) ←1 Description: Sets (1) to the high-order bit reference enable flag UPTF. Note: When the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is transferred to the low-order 2 bits of register D. SZB j (Skip if Zero, Bit) Instruction D9 code 00 Operation: D0 Number of words 2 j 16 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition (Mj(DP)) = 0 j = 0 to 3 0 0 1 0 0 0 j j20 (Mj(DP)) = 0 ? j = 0 to 3 Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”. SZC (Skip if Zero, Carry flag) Instruction D9 code 00 Operation: D0 Number of words 2 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (CY) = 0 0 0 1 0 1 1 1 120 (CY) = 0 ? Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0”. After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is “1”. SZD (Skip if Zero, port D specified by register Y) Instruction D9 code 00 0 Operation: 0 D0 Number of words 2 4 16 2 Number of cycles 2 Flag CY - Skip condition (D(Y)) = 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 020 120 (D(Y)) = 0 ? (Y) = 0 to 4 2 B 16 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when the bit is “1”. Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 86 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 0 0 022 (T17−T14) ← (B) (R17−R14) ← (B) (T13−T10) ← (A) (R13−R10) ← (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 0 0 122 (T27−T24) ← (B) (R27−R24) ← (B) (T23−T20) ← (A) (R23−R20) ← (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. T3AB (Transfer data to timer 3 and register R3L from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 2 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 0 1 022 (T37−T34) ← (B) (R3L7−R3L4) ← (B) (T33−T30) ← (A) (R3L3−R3L0) ← (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3L. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3L. T3HAB (Transfer data to register R3H from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 D 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 1 1 0 122 (R3H7−R3H4) ← (B) (R3H3−R3H0) ← (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3H. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3H. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 87 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T3R3L (Transfer data to timer 3 from register R3L) Instruction D9 code 10 Operation: D0 Number of words 3 4 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 1 0 022 (T37−T30) ← (R3L7−R3L0) Description: Transfers the contents of reload register R3L to timer 3. TAB (Transfer data to Accumulator from register B) Instruction D9 code 00 Operation: D0 Number of words 1 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 1 020 (A) ← (B) Register to register transfer Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruction D9 code 10 Operation: D0 Number of words 7 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 0 0 022 (B) ← (T17−T14) (A) ← (T13−T10) Description: Transfers the high-order 4 bits (T17−T14) of timer 1 to register B. Transfers the low-order 4 bits (T13−T10) of timer 1 to register A. TAB2 (Transfer data to Accumulator and register B from timer 2) Instruction D9 code 10 Operation: D0 Number of words 7 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 0 0 122 (B) ← (T27−T24) (A) ← (T23−T20) Description: Transfers the high-order 4 bits (T27−T24) of timer 2 to register B. Transfers the low-order 4 bits (T23−T20) of timer 2 to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 88 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB3 (Transfer data to Accumulator and register B from timer 3) Instruction D9 code 10 Operation: D0 Number of words 7 2 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 0 1 022 (B) ← (T37−T34) (A) ← (T33−T30) Description: Transfers the high-order 4 bits (T37−T34) of timer 3 to register B. Transfers the low-order 4 bits (T33−T30) of timer 3 to register A. TABE (Transfer data to Accumulator and register B from register E) Instruction D9 code 00 Operation: D0 Number of words 2 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 1 020 (B) ← (E7−E4) (A) ← (E3−E0) Register to register transfer Description: Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruction D9 code 00 Operation: D0 Number of words 1 Number of cycles 3 Flag CY - Skip condition - 1 0 p5 p4 p3 p2 p1 p0 2 0 8 p 16 +p Grouping: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (UPTF) ← 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the loworder 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. Number of words 7 5 16 1 Grouping: Number of cycles 1 Timer operation TABPS (Transfer data to Accumulator and register B from Prescaler) Instruction D9 code 10 Operation: D0 Flag CY - Skip condition - 0 1 1 1 0 1 0 122 (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) Description: Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 89 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAD (Transfer data to Accumulator from register D) Instruction D9 code 00 Operation: D0 Number of words 5 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 0 120 (A2−A0) ← (DR2−DR0) (A3) ← 0 Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAI1 (Transfer data to Accumulator from register I1) Instruction D9 code 10 Operation: D0 Number of words 5 3 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 0 1 122 (A) ← (I1) Description: Transfers the contents of interrupt control register I1 to register A. TAI2 (Transfer data to Accumulator from register I2) Instruction D9 code 10 Operation: D0 Number of words 5 4 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 1 0 022 (A) ← (I2) Description: Transfers the contents of interrupt control register I2 to register A. TAK0 (Transfer data to Accumulator from register K0) Instruction D9 code 10 Operation: D0 Number of words 5 6 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 1 1 022 (A) ← (K0) Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 90 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK1 (Transfer data to Accumulator from register K1) Instruction D9 code 10 Operation: D0 Number of words 5 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 0 0 122 (A) ← (K1) Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A. TAK2 (Transfer data to Accumulator from register K2) Instruction D9 code 10 Operation: D0 Number of words 5 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 0 1 022 (A) ← (K2) Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TAL1 (Transfer data to Accumulator from register L1) Instruction D9 code 10 Operation: D0 Number of words 4 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 0 1 0 1 022 (A) ← (L1) Input/Output operation Description: Transfers the contents of key-on wakeup control register L1 to register A. TAM j (Transfer data to Accumulator from Memory) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 1 0 0 j j j j22C (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 91 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruction D9 code 10 Operation: D0 Number of words 5 2 16 1 Grouping: Number of cycles 1 Clock operation Flag CY - Skip condition - 0 1 0 1 0 0 1 022 (A) ← (MR) Description: Transfers the contents of clock control register MR to register A. TAPU0 (Transfer data to Accumulator from register PU0) Instruction D9 code 10 Operation: D0 Number of words 5 7 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 1 1 122 (A) ← (PU0) Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A. TAPU1 (Transfer data to Accumulator from register PU1) Instruction D9 code 10 Operation: D0 Number of words 5 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 1 1 022 (A) ← (PU1) Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. TAPU2 (Transfer data to Accumulator from register PU2) Instruction D9 code 10 Operation: D0 Number of words 5 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 1 1 122 (A) ← (PU2) Input/Output operation Description: Transfers the contents of pull-up control register PU2 to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 92 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TASP (Transfer data to Accumulator from Stack Pointer) Instruction D9 code 00 Operation: D0 Number of words 5 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 0 020 (A2−A0) ← (SP2−SP0) (A3) ← 0 Register to register transfer Description: Transfers the contents of stack pointer (SP) to the loworder 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruction D9 code 00 Operation: D0 Number of words 5 4 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 1 0 020 (A) ← (V1) Description: Transfers the contents of interrupt control register V1 to register A. TAV2 (Transfer data to Accumulator from register V2) Instruction D9 code 00 Operation: D0 Number of words 5 5 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 1 0 120 (A) ← (V2) Description: Transfers the contents of interrupt control register V2 to register A. TAW1 (Transfer data to Accumulator from register W1) Instruction D9 code 10 Operation: D0 Number of words 4 B 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 0 1 122 (A) ← (W1) Description: Transfers the contents of timer control register W1 to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 93 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW2 (Transfer data to Accumulator from register W2) Instruction D9 code 10 Operation: D0 Number of words 4 C 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 0 022 (A) ← (W2) Description: Transfers the contents of timer control register W2 to register A. TAW3 (Transfer data to Accumulator from register W3) Instruction D9 code 10 Operation: D0 Number of words 4 D 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 0 122 (A) ← (W3) Description: Transfers the contents of timer control register W3 to register A. TAW5 (Transfer data to Accumulator from register W5) Instruction D9 code 10 Operation: D0 Number of words 4 F 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 1 122 (A) ← (W5) Description: Transfers the contents of timer control register W5 to register A. TAX (Transfer data to Accumulator from register X) Instruction D9 code 00 Operation: D0 Number of words 5 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 1 020 (A) ← (X) Register to register transfer Description: Transfers the contents of register X to register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 94 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAY (Transfer data to Accumulator from register Y) Instruction D9 code 00 Operation: D0 Number of words 1 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 1 120 (A) ← (Y) Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruction D9 code 00 Operation: D0 Number of words 5 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 1 120 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. TBA (Transfer data to register B from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 0 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 1 020 (B) ← (A) Register to register transfer Description: Transfers the contents of register A to register B. TDA (Transfer data to register D from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 2 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 120 (DR2−DR0) ← (A2−A0) Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 95 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruction D9 code 00 Operation: D0 Number of words 1 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 1 020 (E7−E4) ← (B) (E3−E0) ← (A) Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. TFR0A (Transfer data to register FR0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 8 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 022 (FR0) ← (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR0. TFR1A (Transfer data to register FR1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 122 (FR1) ← (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR1. TI1A (Transfer data to register I1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 7 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 0 1 0 1 1 122 (I1) ← (A) Description: Transfers the contents of register A to interrupt control register I1. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 96 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TI2A (Transfer data to register I2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 8 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 0 1 1 0 0 022 (I2) ← (A) Description: Transfers the contents of register A to interrupt control register I2. TK0A (Transfer data to register K0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 1 122 (K0) ← (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K0. TK1A (Transfer data to register K1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 022 (K1) ← (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K1. TK2A (Transfer data to register K2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 122 (K2) ← (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K2. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 97 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TL1A (Transfer data to register L1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 1 022 (L1) ← (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register L1. TMA j (Transfer data to Memory from Accumulator) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 1 1 j j j j22B (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TMRA (Transfer data to register MR from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 6 16 1 Grouping: Number of cycles 1 Clock operation Flag CY - Skip condition - 0 0 0 1 0 1 1 022 (MR) ← (A) Description: Transfers the contents of register A to clock control register MR. TPAA (Transfer data to register PA from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 1 0 1 0 1 0 1 0 2 2 A A 16 (PA0) ← (A0) Description: Transfers the least significant bit of register A (A0) to timer control register PA. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 98 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPSAB (Transfer data to Prescaler and register RPS from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 5 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 1 0 122 (RPS7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. TPU0A (Transfer data to register PU0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 0 122 (PU0) ← (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 1 022 (PU1) ← (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU1. TPU2A (Transfer data to register PU2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 1 122 (PU2) ← (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU2. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 99 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR1AB (Transfer data to register R1 from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 1 1 1 1 122 (R17−R14) ← (B) (R13−R10) ← (A) Input/Output operation Description: Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13−R10) of reload register R1. TV1A (Transfer data to register V1 from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 3 F 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 1 1 1 1 1 120 (V1) ← (A) Description: Transfers the contents of register A to interrupt control register V1. TV2A (Transfer data to register V2 from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 3 E 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 1 1 1 1 1 020 (V2) ← (A) Description: Transfers the contents of register A to interrupt control register V2. TW1A (Transfer data to register W1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 E 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 0 1 1 1 022 (W1) ← (A) Description: Transfers the contents of register A to timer control register W1. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 100 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW2A (Transfer data to register W2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 F 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 0 1 1 1 122 (W2) ← (A) Description: Transfers the contents of register A to timer control register W2. TW3A (Transfer data to register W3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 1 0 0 0 022 (W3) ← (A) Description: Transfers the contents of register A to timer control register W3. TW5A (Transfer data to register W5 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 2 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 1 0 0 1 022 (W5) ← (A) Description: Transfers the contents of register A to timer control register W5. TYA (Transfer data to register Y from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 0 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 0 020 (Y) ← (A) Register to register transfer Description: Transfers the contents of register A to register Y. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 101 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) WRST (Watchdog timer ReSeT) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition (WDF1) = 1 1 0 1 0 0 0 0 0 2 2 A 0 16 (WDF1) = 1 ? (WDF1) ← 0 Description: Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. XAM j (eXchange Accumulator and Memory data) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 1 0 1 j j j j22D (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruction D9 code 10 Operation: D0 Number of words F j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (Y) = 15 1 1 1 1 j j j j22 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) −1 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (Y) = 0 1 1 1 0 j j j j22E (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 102 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 1 0 0 Hexadecim al notation 0 0 0 0 0 1 0 1 0 1 E E F C A Function TAB TBA TAY TYA Register to register transfer 1 1 1 1 1 1 1 1 1 1 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7−E4) ← (B) (E3−E0) ← (A) (B) ← (E7−E4) (A) ← (E3−E0) (DR2−DR0) ← (A2−A0) (A2−A0) ← (DR2−DR0) (A3) ← 0 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 (A) ← (X) (A2−A0) ← (SP2−SP0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 TEAB TABE 0 0 0 0 1 0 1 0 1 0 0 2 A 1 1 TDA TAD 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 2 5 9 1 1 1 1 1 TAZ 0 0 0 1 0 1 0 0 1 1 0 5 3 1 1 TAX TASP 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 5 5 2 0 1 1 1 1 LXY x, y 1 1 x3 x2 x1 x0 y3 y2 y1 y0 3 x y 1 1 RAM addresses LZ z 0 0 0 1 0 0 1 0 z1 z0 0 4 8 +z 3 1 1 (Z) ← z z = 0 to 3 INY 0 0 0 0 0 1 0 0 1 1 0 1 1 1 (Y) ← (Y) + 1 DEY 0 0 0 0 0 1 0 1 1 1 0 1 7 1 1 (Y) ← (Y) − 1 TAM j 1 0 1 1 0 0 j j j j 2 C j 1 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 XAM j RAM to register transfer 1 0 1 1 0 1 j j j j 2 D j 1 1 XAMD j 1 0 1 1 1 1 j j j j 2 F j 1 1 XAMI j 1 0 1 1 1 0 j j j j 2 E j 1 1 TMA j 1 0 1 0 1 1 j j j j 2 B j 1 1 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 103 of 124 4571 Group Skip condition Carry flag CY Detailed description − − − − − − − − − − Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register A. Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. − − − − − − − − − − − − Continuous description − − − (Y) = 0 − Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 − − − − − (Y) = 15 − (Y) = 0 − − − Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 104 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 n n n n Hexadecim al notation 0 7 n Function LA n 1 1 (A) ← n n = 0 to 15 TABP p 0 0 1 0 p5 p4 p3 p2 p1 p0 0 8 +p p 1 3 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7-4 (A) ← (ROM(PC))3-0 (UPTF) = 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 (A) ← (A) + (M(DP)) AM Arithmetic operation 0 0 0 0 0 0 1 0 1 0 0 0 A 1 1 AMC 0 0 0 0 0 0 1 0 1 1 0 0 B 1 1 (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 An 0 0 0 1 1 0 n n n n 0 6 n 1 1 AND OR SC RC SZC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 2 8 9 7 6 F 1 1 1 1 1 1 1 1 1 1 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? CMA RAR 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 C D 1 1 1 1 (A) ← (A) CY A3A2A1A0 SB j Bit operation 0 0 0 1 0 1 1 1 j j 0 5 C +j C +j j 1 1 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 RB j 0 0 0 1 0 0 1 1 j j 0 4 1 1 SZB j 0 0 0 0 1 0 0 0 j j 0 2 1 1 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 105 of 124 4571 Group Skip condition Carry flag CY Detailed description Continuous description − Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. − − − − Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. − 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Overflow = 0 − Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0”. Executes the next instruction when the contents of carry flag CY is “1”. The contents of carry flag CY remains unchanged. Stores the one’s complement for register A’s contents in register A. − − − − − − 1 0 − (CY) = 0 − − − 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. − − Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). − − Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 − Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 106 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 1 1 0 Hexadecim al notation 0 2 6 Function SEAM Comparison operation 1 1 (A) = (M(DP)) ? SEA n 0 0 0 0 1 0 0 1 0 1 0 2 5 2 2 (A) = n n = 0 to 15 0 Ba 0 0 1 0 1 1 1 1 n n n n 0 1 7 8 +a E +p a 1 n a 1 1 (PCL) ← a6−a0 a6 a5 a4 a3 a2 a1 a0 Branch operation BL p, a 0 0 1 1 1 p4 p3 p2 p1 p0 0 p 2 2 (PCH) ←p (Note 1) (PCL) ← a6−a0 1 BLA p 0 p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 1 0 0 0 0 2 0 a 0 2 2 (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) 1 BM a 0 p6 p5 p4 1 0 0 0 p3 p2 p1 p0 2 1 p a p a 1 1 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← a6−a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) (PC) ← (SK(SP)) (SP) ← (SP) − 1 a6 a5 a4 a3 a2 a1 a0 Subroutine operation BML p, a 0 0 1 1 0 p4 p3 p2 p1 p0 0 C +p a 3 p 4 p 2 2 1 BMLA p 0 1 RTI 0 p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 1 0 0 0 0 0 0 2 0 2 0 a 0 p 6 1 1 2 2 p6 p5 p4 0 0 1 p3 p2 p1 p0 0 1 1 0 Return operation RT 0 0 0 1 0 0 0 1 0 0 0 4 4 1 2 (PC) ← (SK(SP)) (SP) ← (SP) − 1 (PC) ← (SK(SP)) (SP) ← (SP) − 1 RTS 0 0 0 1 0 0 0 1 0 1 0 4 5 1 2 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 107 of 124 4571 Group Skip condition Carry flag CY Detailed description (A) = (M(DP)) − Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. (A) = n n = 0 to 15 − − − Branch within a page : Branches to address a in the identical page. − − Branch out of a page : Branches to address a in page p. − − Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. − − Call the subroutine in page 2 : Calls the subroutine at address a in page 2. − − Call the subroutine : Calls the subroutine at address a in page p. − − Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. − − Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. − − No conditional skip − Returns from subroutine to the routine called the subroutine, and skips the next instruction at with no condition. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 108 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 Hexadecim al notation 0 0 0 0 0 3 4 5 8 Function DI EI SNZ0 1 1 1 1 1 1 (INTE) ← 0 (INTE) ← 1 V10 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : SNZ0 = NOP I12 = 0 : (INT0) = “L”? I12 = 1 : (INT0) = “H”? SNZI0 0 0 0 0 1 1 1 0 1 0 0 3 A 1 1 SNZ1 0 0 0 0 1 1 1 0 0 1 0 3 9 1 1 V11 = 0 : (EXF1) = 1 ? (EXF1) ← 0 V11 = 1 : SNZ1 = NOP I22 = 0 : (INT1) = “L” ? I22 = 1 : (INT1) = “H” ? Interrupt operation SNZI1 0 0 0 0 1 1 1 0 1 1 0 3 B 1 1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A Timer operation 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 5 3 5 3 5 1 5 1 A 4 0 4 0 4 1 4 1 4 F 5 E 3 7 4 8 A B E C F D 0 F 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (PA1, PA0) ← (A1, A0) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (A) ← (W5) (W5) ← (A) TAW2 TW2A TAW3 TW3A TAW5 TW5A Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 109 of 124 4571 Group Skip condition Carry flag CY Detailed description − − V10 = 0 : (EXF0) = 1 − − − Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L”. Executes the next instruction when the level of INT0 pin is “H”. When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H”. Executes the next instruction when the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1) (INT0) = “L” However, I12 = 0 (INT0) = “H” However, I12 = 1 V11 = 0 : (EXF1) = 1 − − When V11 = 0 : Clears (0) to the EXF1 flag and skips the next instruction when external 1 interrupt request flag EXF1 is “1”. When the EXF1 flag is “0”, executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L”. Executes the next instruction when the level of INT1 pin is “H”. When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H”. Executes the next instruction when the level of INT1 pin is “L”. (I22: bit 2 of interrupt control register I2) I22 = 0 : (INT1) = “L” I22 = 1 : (INT1) = “H” − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of register A (A1, A0) to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 110 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 1 0 1 0 1 Hexadecim al notation 2 7 5 Function TABPS 1 1 (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) (RPS7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) (B) ← (T17−T14) (A) ← (T13−T10) (R17−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) (R17−R14) ← (B) (R13−R10) ← (A) (B) ← (T27−T24) (A) ← (T23−T20) (R27−R24) ← (B) (T27−T24) ← (B) (R23−R20) ← (A) (T23−T20) ← (A) (B) ← (T37−T34) (A) ← (T33−T30) (R3L7−R3L4) ← (B) (T37−T34) ← (B) (R3L3−R3L0) ← (A) (T33−T30) ← (A) (R3H7−R3H4) ← (B) (R3H3−R3H0) ← (A) (T37) ← (R3L) V12 = 0 : (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1 : SNZT1=NOP TPSAB 1 0 0 0 1 1 0 1 0 1 2 3 5 1 1 TAB1 1 0 0 1 1 1 0 0 0 0 2 7 0 1 1 T1AB 1 0 0 0 1 1 0 0 0 0 2 3 0 1 1 TR1AB 1 0 0 0 1 1 1 1 1 1 2 3 F 1 1 TAB2 1 0 0 1 1 1 0 0 0 1 2 7 1 1 1 T2AB Timer operation 1 0 0 0 1 1 0 0 0 1 2 3 1 1 1 TAB3 T3AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 2 2 7 3 2 2 1 1 1 1 T3HAB T3R3L SNZT1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 0 2 2 2 3 3 8 D 4 0 1 1 1 1 1 1 SNZT2 1 0 1 0 0 0 0 0 0 1 2 8 1 1 1 V13 = 0 : (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1 : SNZT2=NOP SNZT3 1 0 1 0 0 0 0 0 1 0 2 8 2 1 1 V20 = 0 : (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1 : SNZT3=NOP Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 111 of 124 4571 Group Skip condition Carry flag CY Detailed description − − Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. − − − − Transfers the high-order 4 bits (T17−T14) of timer 1 to register B. Transfers the low-order 4 bits (T13−T10) of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. − − − − Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13−R10) of reload register R1. Transfers the high-order 4 bits (T27−T24) of timer 2 to register B. Transfers the low-order 4 bits (T23−T20) of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. − − − − − − − − Transfers the high-order 4 bits (T37−T34) of timer 3 to register B. Transfers the low-order 4 bits (T33−T30) of timer 3 to register A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3L. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3L. − − − − − Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3H. Transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3H. Transfers the contents of timer 3 reload register R3L to timer 3. When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0”, executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2) V12 = 0 : (T1F) = 1 V13 = 0 : (T2F) = 1 − V20 = 0 : (T3F) = 1 − Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 112 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 Hexadecim al notation 2 2 2 2 2 6 2 6 2 6 0 0 1 1 2 Function IAP0 OP0A IAP1 OP1A IAP2 1 1 1 1 1 1 1 1 1 1 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A1, A0) ← (P21, P20) (A3, A2) ← 0 (P21, P20) ← (A1, A0) (A1, A0) ← (P31, P30) (A3, A2) ← 0 (P31, P30) ← (A1, A0) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 4 (D(Y)) ← 1 (Y) = 0 to 4 (D(Y)) = 0 ? (Y) = 0 to 4 OP2A IAP3 OP3A CLD RD Input/Output operation 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 2 2 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 6 2 1 1 1 2 2 8 8 2 2 5 2 5 2 5 2 6 2 3 3 1 4 5 4 B C D 8 9 7 D E E F F F 1 1 1 1 1 1 2 1 1 1 1 1 1 2 SD SZD RCP SCP TFR0A TFR1A TAPU0 TPU0A TAPU1 TPU1A TAPU2 TPU2A IAK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (C) ← (0) (C) ← (1) (FR0) ← (A) (FR1) ← (A) (A) ← (PU0) (PU0) ← (A) (A) ← (PU1) (PU1) ← (A) (A) ← (PU2) (PU2) ← (A) (A0) ← (K) (A3−A1) ← 0 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 113 of 124 4571 Group Skip condition Carry flag CY Detailed description − − − − − − − − − − Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when a bit of port D specified by register Y is “1”. − − − − − − − − − − − − − (D(Y)) = 0 Y = 0 to 4 − − − − − − − − − − − − − − − − − − − − − − Clears (0) to port C. Sets (1) to port C. Transfers the contents of register A to port output structure control register FR0. Transfers the contents of register A to port output structure control register FR1. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of pull-up control register PU2 to register A. Transfers the contents of register A to pull-up control register PU2. Transfers the input of port K to the least significant bit (A0) of register A. “0” is stored to the high-order 3 bits (A3−A1) of register A. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 114 of 124 4571 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAK0 TK0A 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 Hexadecim al notation 2 2 2 2 2 2 2 2 2 2 0 0 5 1 5 1 5 1 4 0 5 1 0 0 6 B 9 4 A 5 A A 2 6 0 2 Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (K0) (K0) ← (A) (A) ← (K1) (K1) ← (A) (A) ← (K2) (K2) ← (A) (A) ← (L1) (L1) ← (A) (A) ← (MR) (MR) ← (A) (PC) ← (PC) + 1 RAM back-up Input/Output operation TAK1 TK1A TAK2 TK2A TAL1 TL1A TAMR TMRA NOP POF EPOF SNZP 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 5 0 B 3 1 1 1 1 POF instruction valid (P) = 1 ? Other operation WRST 1 0 1 0 1 0 0 0 0 0 2 A 0 1 1 (WDF1) = 1 ? (WDF1) ← 0 DWDT SRST RUPT SUPT SNZVD 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 2 0 0 0 2 9 0 5 5 8 C 1 8 9 A 1 1 1 1 1 1 1 1 1 1 Stop of watchdog timer function enabled System reset (UPTF) ← 0 (UPTF) ← 1 V23 = 0 : (VDF) = 1? V23 = 1 : SNZVD = NOP RBK (Note 1) SBK (Note 1) 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 1 1 1 1 1 p6 ← 0 when TABP p instruction is executed. p6 ← 1 when TABP p instruction is executed. Note 1.This instruction cannot be used for the M34571G4/G6. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 115 of 124 4571 Group Skip condition Carry flag CY Detailed description − − − − − − − − − − − − − − − − − − − − − − − − Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transfers the contents of key-on wakeup control register L1 to register A. Transfers the contents of register A to key-on wakeup control register L1. Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Operations of all functions are stopped. Makes the immediate after POF instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”. Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. − − − (P) = 1 (WDF1) = 1 − − − − − − − − − Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. System reset occurs. Clears (0) to the high-order bit reference enable flag UPTF. Sets (1) to the high-order bit reference enable flag UPTF. When V23 = 0 : Skips the next instruction when voltage detector interrupt request flag VDF is “1”. The VDF flag is not cleared to “0“. When the VDF flag is “0”, executes the next instruction. When V23 = 1 : This instruction is equivalent to the NOP instruction. V23 = 0 : (VDF) = 1 − − − − Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 116 of 124 4571 Group INSTRUCTION CODE TABLE 010000 011000 D9− to 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 to D4 010111 011111 D3− H e x , notation D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 NOP 01 BLA 02 03 04 05 06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 08 09 0A 0B 0C 0D 0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 10−17 18−F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B SZB RBK BMLA TASP 0 *** SZB 1 SZB 2 SZB 3 SZD SEAn SEAM TABP TABP TABP TABP BML BML 0 16 32* 48** TABP TABP TABP TABP BML BML 1 17 33* 49** TABP TABP TABP TABP BML BML 2 18 34* 50** TABP TABP TABP TABP BML BML 3 19 35* 51** TABP TABP TABP TABP BML BML 4 20 36* 52** TABP TABP TABP TABP BML BML 5 21 37* 53** TABP TABP TABP TABP BML BML 6 22 38* 54** TABP TABP TABP TABP BML BML 7 23 39* 55** TABP TABP TABP TABP BML BML 8 24 40* 56** TABP TABP TABP TABP BML BML 9 25 41* 57** TABP TABP TABP TABP BML BML 10 26 42* 58** TABP TABP TABP TABP BML BML 11 27 43* 59** TABP TABP TABP TABP BML BML 12 28 44* 60** TABP TABP TABP TABP BML BML 13 29 45* 61** TABP TABP TABP TABP BML BML 14 30 46* 62** TABP TABP TABP TABP BML BML 15 31 47* 63** SRST CLD POF − − − − − − − − SBK *** − − TAD TAX TAZ TAV1 SNZP INY DI EI RC SC − − RD SD − RT RTS TAV2 RTI − − − DEY AND OR − − SNZ0 LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 RUPT SUPT − TDA SNZ1 SNZI 0 SNZI 1 − − AM TEAB TABE AMC TYA − − − − − − EPOF SB 0 SB 1 SB 2 SB 3 CMA RAR TAB TAY TBA − TV2A SZC TV1A The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D 4 s how the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 BL BML BLA BMLA SEA SZD • *, **, and *** cannot be used in the M34571G4. • ** and *** cannot be used in the M34571G6. • A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the M34571GD. The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63. The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 127 (Ex. TABP 0 TABP 64). When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 117 of 124 4571 Group INSTRUCTION CODE TABLE 110000 D9− to 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 D4 111111 D3− D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hex, notation 20 − − − − − − − − − − 21 22 23 24 − − − − − − − − − − 25 − − 26 27 28 SNZT 1 SNZT 2 SNZT 3 − − − − − − − SNZVD 29 − − − − − − − − − − − − 2A WRST − − − − − − − − − 2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15 2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15 2D 2E 2F 30−3F 0 1 2 3 4 5 6 7 8 9 A B C D E F TW3A OP0A T1AB − IAP0 TAB1 IAP1 TAB2 XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15 OP1A T2AB TW5A OP2A T3AB − TAMR IAP2 TAB3 TAI1 TAI2 − OP3A − − − − − T3R3L IAP3 − − − − − − − − − − − − − TABPS TK1A TK2A TMRA TI1A TPSAB − − − − − − − TAK0 TAPU0 − − − − − − − − − − TI2A TFR0A − − TFR1A − TAK1 TL1A − − − − − − TAL1 TAK2 TAW1 TAW2 − − − TAPU1 TPAA − − − − − TK0A − − − − − RCP DWDT SCP − − − − − TPU0A T3HAB TAW3 TPU1A TW1A TW2A − − TPU2A TR1AB TAW5 TAPU2 IAK The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D 4 s how the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 118 of 124 4571 Group Electrical characteristics Absolute maximum ratings Table 25 Absolute maximum ratings Symbol VDD VI VO VO Pd Topr Tstg Supply voltage Input voltage P0, P1, P20/INT0, P21/INT1, P3, D0–D3, D4/CNTR0, K, RESET, XIN Output voltage P0, P1, P2, P3, D0–D3, D4/CNTR0, RESET Output voltage C, XOUT Power dissipation Operating temperature range Storage temperature range Parameter Conditions Output transistors in cut-off state Ta = 25 °C Ratings −0.3 to 6.5 −0.3 to VDD+0.3 −0.3 to VDD+0.3 −0.3 to VDD+0.3 Unit V V V V mW °C °C 300 −20 to 85 −40 to 125 Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 119 of 124 4571 Group Recommended operating conditions Table 26 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (with a ceramic resonator) f(STCK) ≤ 6MHz f(STCK) ≤ 4.4MHz f(STCK) ≤ 2.2MHz f(STCK) ≤ 1.1MHz f(STCK) ≤ 4.8MHz f(STCK) ≤ 3.2MHz f(STCK) ≤ 1.6MHz f(STCK) ≤ 0.8MHz (at RAM back-up) P0, P1, P2, P3, D0–D4, K XIN RESET, INT0, INT1 CNTR0 P0, P1, P2, P3, D0–D4, K XIN RESET, INT0, INT1 CNTR0 P3, D0–D3 C, CNTR1 IOH(avg) “H” level average output current P3, D0–D3 (Note 1) C, CNTR1 IOL(peak) IOL(avg) ΣIOH(avg) ΣIOL(avg) Conditions VDD Supply voltage (when an external clock is used) VRAM VSS VIH RAM back-up voltage Supply voltage “H” level input voltage Min. 4 2.7 2 1.8 4 2.7 2 1.8 1.6 0.8VDD 0.7VDD 0.85VDD 0.85VDD 0 0 0 0 VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V Limits Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.3VDD 0.3VDD 0.15VDD −20 −10 −30 −15 −10 −5 −15 −7 24 12 12 6 −30 30 30 Unit V V 0 V V V VIL “L” level input voltage mA IOH(peak) “H” level peak output current mA mA “L” level peak output current P0, P1, P2, P3, D0–D4, C, RESET, CNTR0, CNTR1, mA mA mA mA “L” level average output current P0, P1, P2, P3, D0–D4, C, (Note 1) RESET, CNTR0, CNTR1, “H” level total average current P3, D0–D3, C, CNTR1 “L” level total average current P0, P10, P11, RESET P10, P11, P2, P3, D0–D4, C, CNTR0, CNTR1 Note 1.The average output current is the average value during 100ms. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 120 of 124 4571 Group Table 27 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Through mode Conditions VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V 3/f(STCK) Min. Limits Typ. Max. 6 4.4 2.2 1.1 6 4.4 2.2 6 4.4 Unit MHz Internal frequency divided by 2 Internal frequency divided by 4, 8 f(XIN) Oscillation frequency (with an external clock input) Through mode Internal frequency divided by 2 Internal frequency divided by 4, 8 f(CNTR) tw(CNTR) TPON Timer external input frequency CNTR0, CNTR1 Timer external input period CNTR0, CNTR1 (“H” and “L” pulse width) Power-on reset circuit valid VDD = 0 → 1.8V supply voltage rising time (Note 1) 4.8 MHz 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 f(STCK)/6 Hz s 100 µs Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. with a ceramic resonator f(STCK) [MHz] 6 at external clock oscillation f(STCK) [MHz] 4.8 4.4 3.2 2.2 1.6 1.1 Recommended operating conditions 1.8 2 2.7 4 5.5 VDD [V] 0.8 1.8 2 Recommended operating conditions 2.7 4 5.5 VDD [V] Fig 71. System clock (STCK) operating condition map Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 121 of 124 4571 Group Electrical characteristics Table 28 Electrical characteristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VOH Parameter “H” level output voltage P3, D0–D4 CNTR0 VDD = 5V VDD = 3V VOH “H” level output voltage C CNTR1 VDD = 5V VDD = 3V VOL “L” level output voltage P0, P1, P2, P3, D0–D4 RESET, C, CNTR0, CNTR1 VDD = 5V VDD = 3V IIH “H” level input current P0, P1, P2, P3, D0–D4, K RESET, INT0, INT1 CNTR0 P0, P1, P2, P3, D0–D4, K RESET, INT0, INT1 CNTR0 P0, P1, P2 RESET RESET, INT0, INT1 CNTR0 at active mode (with a ceramic resonator) (Note 1) VI = VDD Test conditions IOH = −10mA IOH = −3mA IOH = −5mA IOH = −1mA IOL = −20mA IOL = −6mA IOL =−10mA IOL = −3mA IOL = 15mA IOL = 5mA IOL = 9mA IOL = 3mA Min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 Limits Typ. Max. Unit V V 2 0.9 1.4 0.9 2 V µA µA IIL “L” level input current RPU VT+ −VT− VT+ −VT− IDD Pull-up resistor value Hysteresis Hysteresis Supply current VI = 0V P0, P1, P2 No pull-up VI = 0V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V f(XIN) = 6MHz f(RING) = stop −2 VDD = 5V VDD = 3V 30 50 VDD = 3V f(XIN) = 4MHz f(RING) = stop Ta = 25°C VDD = 5V VDD = 3V f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) at RAM back-up mode (POF instruction execution) 60 120 1 0.4 0.2 0.2 1.2 1.3 1.6 2.2 0.3 0.4 0.6 0.8 0.1 125 250 kΩ V V 2.4 2.6 3.2 4.4 0.6 0.8 1.2 1.6 3 10 6 mA mA µA Note 1.The voltage drop detection circuit operation current (IRST) is added. Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 122 of 124 4571 Group Voltage drop detection circuit characteristics Table 29 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VRSTParameter Detection voltage (reset occurs) (Note 1) Test conditions Ta = 25°C −20°C≤ Ta < 0°C 0°C≤ Ta < 50°C 50°C≤ Ta ≤ 85°C Ta = 25°C −20°C≤ Ta < 0°C 0°C≤ Ta < 50°C 50°C≤ Ta ≤ 85°C Ta = 25°C −20°C≤ Ta < 0°C 0°C≤ Ta < 50°C 50°C≤ Ta ≤ 85°C Min. 1.6 1.3 1.1 1.75 1.7 1.4 1.2 1.85 1.8 1.5 1.3 2.4 2.3 2.2 2.3 2.2 1.9 V Limits Typ. 1.65 Max. 2.2 2.1 1.8 V Unit V VRST+ Detection voltage (reset release) (Note 2) VINT Detection voltage (Interrupt occurs) (Note 3) 0.1 V VDD = 5V 40 80 µA VDD = 3V 20 40 VDD = 1.65V 7 15 TRST Detection time (Note 5) VDD → (VRST- −0.1V) 0.2 1.2 ms Note 1.The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. Note 2.The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. Note 3.When the supply voltage goes lower than the detection voltage (VINT), the voltage drop detection circuit interrupt request flag (VDF) is set to “1“. Note 4.IRST is added to IDD (power current). Note 5.The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V]. VRST+ −VRSTIRST Detection voltage hysteresis Voltage drop detection circuit operation current (Note 4) Basic timing diagram Machine cycle Parameter System clock Pin name STCK Mi Mi + 1 Port output D0 to D4 P00 to P03 P10 to P13 P20, P21 P30, P31, C D0 to D4 P00 to P03 P10 to P13 P20, P21 P30, P31, K INT0, INT1 Port input Interrupt input Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 123 of 124 4571 Group PACKAGE OUTLINE JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g 24 13 HE *1 E F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 Index mark *2 12 c D A2 A1 Reference Symbol Dimension in Millimeters e *3 y bp D E A2 A A1 bp c HE e y L Detail F Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 2.1 0.1 0.2 0 0.3 0.35 0.45 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 0.65 0.8 0.95 0.10 0.4 0.6 0.8 A Rev.1.02 May 25, 2007 REJ03B0179-0102 Page 124 of 124 L REVISION HISTORY 4571 Group Datasheet Rev. 1.00 1.01 Date Page Feb. 20, 2006 Apr. 18, 2007 − 1 4 6 30 31 First edition issued Description Summary FEATURES: Description revised Table 2: Subroutine nesting added Table 5: Port P2; P20 → P20/INT0, P21 → P21/INT1 Table 17: Timer control register W1; CNTR1 input → CNTR0 input • Timer control register PA: Description revised • Timer control register W3: Description revised (2) Prescaler: PRS → RPS (5) Timer 3: Description revised WATCHDOG TIMER: Description revised Table 21: Title revised Table 22: Title revised Fig 50: Ceramic resonator circuit → Ceramic oscillation circuit QzROM Writing Mode added NOTES ON NOISE added Timer control register W1: CNTR1 input → CNTR0 input SNZ1: V10 → V11 SUPT: Description revised T3HAB: Description revised Table 28: IDD; (with a ceramic oscillator) → (with a ceramic resonator) 32 37 47 48 49 51 59 64 69 86 112 122 1.02 May. 25, 2007 All pages “PRELIMINARY” deleted (1/1) Sales Strategic Planning Div. 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