553S
Datasheet
Low Skew 1 to 4 Clock Buffer
Description
Features
The 553S is a low skew, single input to four output, clock
buffer. The 553S has best in class additive phase Jitter of
sub 50 fsec.
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IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize
clocks. Contact us for all of your clocking needs.
Low additive phase jitter RMS: 50fs
Extremely low skew outputs (50ps)
Low cost clock buffer
Packaged in 8-SOIC and small 8-DFN package, Pb-free
Input/Output clock frequency up to 200MHz
Ideal for networking clocks
Operating voltages: 1.8V to 3.3V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Extended temperature range (-40°C to +105°C)
3.3V tolerant input clock
Block Diagram
Q0
Q1
ICLK
Q2
Q3
Output Enable
©2020 Renesas Electronics Corporation
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January 6, 2020
553S Datasheet
Pin Assignments
VDD
1
8
OE
VDD
1
8
OE
Q0
2
7
Q3
Q0
2
7
Q3
Q1
3
6
Q2
Q1
3
6
Q2
GN D
4
5
I CLK
GND
4
5
ICLK
8- pi n SOI C
8-pin DFN
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
VDD
Power
Connect to +1.8V, +2.5V, or +3.3V.
2
Q0
Output
Clock output 0.
3
Q1
Output
Clock output 1.
4
GND
Power
Connect to ground.
5
ICLK
Input
6
Q2
Output
Clock output 2.
7
Q3
Output
Clock output 3.
8
OE
Input
Clock input.
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be
connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor
may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 553S is capable of, careful attention must be paid to board layout. Essentially, all
four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew
will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least
15ps of skew.
©2020 Renesas Electronics Corporation
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553S Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 553S. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
3.8V
Output Enable and All Outputs
-0.5 V to VDD + 0.5 V
ICLK
3.465V
Ambient Operating Temperature (extended)
-40 to +105C
Storage Temperature
-65 to +150C
Junction Temperature
125C
Soldering Temperature
260C
Input ESD Protection (Human Body Model)
2500V
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (extended)
Power Supply Voltage (measured in respect to GND)
©2020 Renesas Electronics Corporation
Min.
Max.
Units
-40
+105
C
+1.71
+3.465
V
3
Typ.
January 6, 2020
553S Datasheet
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Operating Voltage
Conditions
VDD
Input High Voltage, ICLK
VIH
Note 1
Input Low Voltage, ICLK
VIL
Note 1
Input High Voltage, OE
VIH
VOH
IOH = -10mA
Output Low Voltage
VOL
IOL = 10mA
Operating Supply Current
IDD
No load, 135MHz
ZO
CIN
Max.
Units
1.71
1.89
V
0.7xVDD
3.45
V
0.3xVDD
V
VDD
V
0.3xVDD
VIL
Output High Voltage
Input Capacitance
Typ.
0.7xVDD
Input Low Voltage, OE
Nominal Output Impedance
Min.
1.3
0.35
15
ICLK, OE pin
V
V
V
mA
17
5
pF
Notes: 1. Nominal switching threshold is VDD/2.
VDD = 2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Operating Voltage
Conditions
VDD
Input High Voltage, ICLK
VIH
Note 1
Input Low Voltage, ICLK
VIL
Note 1
Input High Voltage, OE
VIH
VOH
IOH = -16mA
Output Low Voltage
VOL
IOL = 16mA
Operating Supply Current
IDD
No load, 135MHz
ZO
CIN
Max.
Units
2.375
2.625
V
0.7xVDD
3.45
V
0.3xVDD
V
VDD
V
0.3xVDD
VIL
Output High Voltage
Input Capacitance
Typ.
0.7xVDD
Input Low Voltage, OE
Nominal Output Impedance
Min.
1.8
0.5
18
ICLK, OE pin
V
V
V
mA
17
5
pF
Notes: 1. Nominal switching threshold is VDD/2.
VDD = 3.3 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Operating Voltage
Conditions
VDD
Input High Voltage, ICLK
VIH
Note 1
Input Low Voltage, ICLK
VIL
Note 1
Input High Voltage, OE
VIH
VOH
IOH = -25mA
Output Low Voltage
VOL
IOL = 25mA
Operating Supply Current
IDD
No load, 135MHz
ZO
CIN
Max.
Units
3.135
3.465
V
0.7xVDD
VDD
V
0.3xVDD
V
VDD
V
0.3xVDD
VIL
Output High Voltage
Input Capacitance
Typ.
0.7xVDD
Input Low Voltage, OE
Nominal Output Impedance
Min.
2.2
0.7
ICLK, OE pin
V
V
22
V
mA
17
5
pF
Notes: 1. Nominal switching threshold is VDD/2.
©2020 Renesas Electronics Corporation
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553S Datasheet
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Typ.
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
0.36 to 1.44V, CL = 5pF
tOF
1.44 to 0.36V, CL = 5pF
Note 1
Buffer Additive Phase Jitter, RMS
0.6
2.5
Note 2
Device to Device Skew
Rising edges at VDD/2
Units
200
MHz
1.0
ns
1.0
ns
3
3.5
ns
0.05
ps
65
ps
50
Rising edges at VDD/2
tSTART-UP
Max.
0.6
125MHz, Integration Range: 12kHz–20MHz
Output to Output Skew
Start-up Time
Min.
200
ps
Part start-up time for valid outputs after VDD
ramp-up
2
ms
Output Enable Time
tEN
CL < 5pF
3
cycles
Output Disable Time
tDIS
CL < 5pF
3
cycles
Max.
Units
200
MHz
0.6
1.0
ns
0.6
1.0
ns
3.5
4
ns
0.05
ps
65
ps
VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Typ.
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
0.5 to 2.0 V, CL = 5pF
tOF
2.0 to 0.5 V, CL = 5pF
Note 1
Buffer Additive Phase Jitter, RMS
3
125MHz, Integration Range: 12kHz–20MHz
Output to Output Skew
Note 2
Device to Device Skew
Start-up Time
Min.
Rising edges at VDD/2
40
Rising edges at VDD/2
tSTART-UP
200
ps
Part start-up time for valid outputs after VDD
ramp-up
2
ms
Output Enable Time
tEN
CL < 5pF
3
cycles
Output Disable Time
tDIS
CL < 5pF
3
cycles
Max.
Units
200
MHz
1.0
ns
VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Typ.
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
0.66 to 2.64 V, CL = 5pF
tOF
2.64 to 0.66 V, CL = 5pF
Note 1
Buffer Additive Phase Jitter, RMS
0.6
2.5
0.6
1.0
ns
3
3.5
ns
0.05
ps
65
ps
125MHz, Integration Range: 12kHz–20MHz
Output to Output Skew
Note 2
Device to Device Skew
Start-up Time
Min.
Rising edges at VDD/2
Rising edges at VDD/2
tSTART-UP
25
200
ps
Part start-up time for valid outputs after VDD
ramp-up
2
ms
Output Enable Time
tEN
CL < 5pF
3
cycles
Output Disable Time
tDIS
CL < 5pF
3
cycles
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
©2020 Renesas Electronics Corporation
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553S Datasheet
Phase Noise Plots
Figure 2. 553S Output Phase Noise 76fs
(12kHz to 20MHz)
Figure 1. 553S Reference Phase Noise 66fs
(12kHz to 20MHz)
The phase noise plots above show the low Additive Jitter of the 553S high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 66fs of RMS phase jitter while the output of 553S has about 76fs of RMS
phase jitter. This results in a low Additive Phase Jitter of only 37fs.
Test Load and Circuit
50ohms
Rs=33ohm
©2020 Renesas Electronics Corporation
5 inches
CL = 5pF
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January 6, 2020
553S Datasheet
Thermal Characteristics (8SOIC)
Parameter
Symbol
Thermal Resistance Junction to Ambient
JA
Still air
150
C/W
JA
1 m/s air flow
140
C/W
JA
3 m/s air flow
120
C/W
40
C/W
Thermal Resistance Junction to Case
Conditions
JC
Min.
Typ.
Max.
Units
Marking Diagrams
IDT
553S
DCGI
YYWW$
553S
YW**
8-pin DFN
8-pin SOIC
Notes:
1. “**” is the lot number.
2. “YYWW” or “YW” are the last digits of the year and week that the part was assembled.
3 “G” denotes RoHS compliant package.
4. “$” denotes mark code.
5. “I” denotes extended temperature range device.
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The
package information is the most current data available.
www.idt.com/document/psc/cmg8-package-outline-drawing-20-x-20-x-05-mm-body-05mm-pitch-dfn
www.idt.com/document/psc/8-soic-package-outline-drawing-0150-body-width-0050-pitch-dcg8d1
Ordering Information
Part / Order Number
553SDCGI
553SDCGI8
553SCMGI
553SCMGI8
Shipping Packaging
Package
Temperature
Tubes
8-pin SOIC
-40°C to +105°C
Tape and Reel
8-pin SOIC
-40°C to +105°C
Cut Tape
8-pin DFN
-40°C to +105°C
Tape and Reel
8-pin DFN
-40°C to +105°C
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
©2020 Renesas Electronics Corporation
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January 6, 2020
553S Datasheet
Revision History
Date
Description of Change
January 6, 2020
▪ Added “Input ESD Protection” information in Absolute Maximum Ratings table.
October 5, 2018
▪ Added “3.3V tolerant input clock” bullet to Features section.
▪ Updated voltage ratings in DC Electrical Characteristics tables.
▪ Updated Package Outline Drawings section.
▪ Updated legal disclaimer.
March 18, 2015
Initial release.
©2020 Renesas Electronics Corporation
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January 6, 2020
8-SOIC Package Outline Drawing
0.150" Body Width, 0.050" Pitch
DCG8D1, PSC-4068-01, Rev 01, Page 1
© Integrated Device Technology, Inc.
8-SOIC Package Outline Drawing
0.150" Body Width, 0.050" Pitch
DCG8D1, PSC-4068-01, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
July 27, 2018
Rev 01
Dedicate to Package DCG8 Only
Feb 24, 2016
Rev 00
Initial Release
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