DATASHEET
ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
Description
Features
The ICS557-05A is a spread-spectrum clock generator that
supports PCI-Express requirements. It is used in PC or
embedded systems to substantially reduce
electro-magnetic interference (EMI). The device provides
four differential HCSL or LVDS high-frequency outputs with
spread spectrum capability. The output frequency and
spread type are selectable using external pins.
• Packaged in 20-pin TSSOP
• RoHS 5 (green) or RoHS 6 (green and lead free)
complaint package
•
•
•
•
•
•
•
•
•
•
•
Supports PCI-Express applications
Four differential spread spectrum clock outputs
Spread spectrum for EMI reduction
Uses external 25 MHz clock or crystal input
Power down pin turns off chip
OE control tri-states outputs
Spread and frequency selection via external pins
Spread Bypass option available
Industrial temperature range available
For PCIe Gen2 applications, see the 5V41066
For PCIe Gen3 applications, see the 5V41236
Block Diagram
VDD
2
SEL[2:0]
3
Spread
Spectrum/
Output
clock
selection
PD
OE
Spread
Spectrum
Circuitry
CLKOUTA
25 MHz
crystal or
clock
X1
Clock
Oscillator
X2
CLKOUTA
CLKOUTB
PLL Clock
Synthesis
CLKOUTB
CLKOUTC
CLKOUTC
CLKOUTD
CLKOUTD
Optional tuning crystal
capacitors
2
Rr(IREF)
GND
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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ICS557-05A
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ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Pin Assignment
VDDXD
1
20
CLKA
S0
2
19
CLKA
S1
3
18
CLKB
S2
4
17
CLKB
X1
5
16
GNDODA
X2
6
15
VDDODA
PD
7
14
CLKC
OE
8
13
CLKC
GNDXD
9
12
CLKD
10
11
CLKD
IREF
20-pin (173 mil) TSSOP
Spread Spectrum Selection Table
S2 S1 S0 Spread% Spread Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5
Down
-1.0
Down
-1.5
Down
No Spread Not Applicable
-0.5
Down
-1.0
Down
-1.5
Down
No Spread Not Applicable
Output
Frequency
100
100
100
100
200
200
200
200
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Pin Descriptions
Pin
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
8
VDDXD
S0
S1
S2
X1
X2
PD
OE
Power
Input
Input
Input
Input
Output
Input
Input
Connect to +3.3 V digital supply.
Spread spectrum select pin #0. See table above. Internal pull-up resistor.
Spread spectrum select pin #1. See table above Internal pull-up resistor.
Spread spectrum select pin #2. See table above. Internal pull-up resistor.
Crystal connection. Connect to a fundamental mode crystal or clock input.
Crystal connection. Connect to a fundamental mode crystal or leave open.
Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor.
Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
9
10
11
12
13
14
15
16
GND
IREF
CLKD
CLKD
CLKC
CLKC
VDDODA
GND
Power
Output
Output
Output
Output
Output
Power
Power
Connect to digital ground.
Precision resistor attached to this pin is connected to the internal current reference.
Selectable 100/200 MHz spread spectrum differential Compliment output clock D.
Selectable 100/200 MHz spread spectrum differential True output clock D.
Selectable 100/200 MHz spread spectrum differential Compliment output clock C.
Selectable 100/200 MHz spread spectrum differential True output clock C.
Connect to +3.3 V analog supply.
Connect to analog ground.
17
CLKB
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B.
18
CLKB
Output Selectable 100/200 MHz spread spectrum differential True output clock B.
19
CLKA
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A.
20
CLKA
Output Selectable 100/200 MHz spread spectrum differential True output clock A.
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Application Information
Decoupling Capacitors
Load Resistors RL
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power supply
noise to perform optimally.
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-05A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pairs (1,9 and 15,16)
as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (CL-12)*2 in this equation, CL=crystal
load capacitance in pf. For example, for a crystal with a 16
pF load cap, each external crystal cap would be 8 pF.
[(16-12)x2]=8.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Output Structures
IREF
=2.3 mA
R R 475Ω
6*IREF
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-05A.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Differential Routing on a Single PCB
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI-Express Device Routing
L1
L2
L4
RS
L1’
L4’
L2’
RS
ICS557-05A
Output
Clock
RT
L3’
RT
L3
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
tOR
0.52 V
0.175 V
500 ps
500 ps
tOF
0.52 V
0.175 V
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
LVDS Compatible Layout Guidelines
Vdiff
Vp-p
0.45v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
R2a = R2b = R2
Alternative T ermination for LVDS and other Common Differential Signals
Vcm
R1
R2
R3
R4
Note
1.08
33
150
100
100
0.6
33
78.7
137
100
0.6
33
78.7
none
100
ICS874003i-02 input compatible
1.2
33
174
140
100
Standard LVDS
LVDS Device Routing
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
HCSL Output Buffer
R2a
R2b
L3'
Down Device
REF_CLK Input
L3
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
1250 mV
1150 mV
500 ps
tOF
1250 mV
1150 mV
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70° C
Ambient Operating Temperature (industrial)
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
1
1
Symbo
l
Conditions
Min.
Typ.
Max.
Units
V
3.135
3.465
VIH
2.0
VDD +0.3
VSS-0.3
0.8
V
-5
5
μA
VIL
V
Input Leakage Current2
IIL
0 < Vin < VDD
Operating Supply Current
IDD
50Ω, 2 pF load @100 MHz
105
mA
IDDOE
OE =Low
40
mA
IDDPD
No load, PD =Low
500
Input Capacitance
CIN
Output Capacitance
COUT
Pin Inductance
LPIN
μA
Input pin capacitance
7
pF
Output pin capacitance
6
pF
5
nH
Output Resistance
Rout
CLK outputs
Pull-up Resistance
RPUP
OE, SEL, PD pins
3.0
kΩ
110
kΩ
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
AC Electrical Characteristics - CLKOUT, HCSL
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Input Frequency
Typ.
Max.
Units
25
Output Frequency
200
MHz
Output High Voltage1,2
VOH
660
700
850
mV
Voltage1,2
VOL
-150
0
27
mV
250
350
550
mV
140
mV
80
ps
Output Low
HCSL termination
MHz
Crossing Point
Voltage1,2
Absolute
Crossing Point
Voltage1,2,4
Variation over all edges
Jitter, Cycle-to-Cycle1,3
Modulation Frequency
Rise
Fall
Time1,2
tOR
Time1,2
tOF
Skew between outputs
Duty
Spread spectrum
30
31.5
33
kHz
From 0.175 V to 0.525 V
175
332
700
ps
From 0.525 V to 0.175 V
175
344
700
ps
50
ps
55
%
10
us
At crossing point Voltage
Cycle1,3
45
Output Enable
Time5
Output Disable
Time5
All outputs
All outputs
10
us
Power-up Time
tSTABLE
From power-up VDD=3.3 V
3.0
ms
Spread Change Time
tSPREAD
Settling period after spread change
3.0
ms
1 Test
setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).
taken from a single-ended waveform.
3 Measurement taken from a differential waveform.
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.
2 Measurement
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
AC Electrical Characteristics - CLKOUT, LVDS
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Input Frequency
Max.
25
Output Frequency
LVDS termination
Units
MHz
100
MHz
Differential Output Voltage
VOD
247
454
mV
Offset Voltage
VOS
1.125
1.375
V
50
mV
50
mV
80
ps
∆VOD
∆VOS
|Change to VOD|
|Change to VOS|
Jitter, Cycle-to-Cycle1,3
Modulation Frequency
Spread spectrum
30
33
kHz
Slew Rate, Rise1,3
tSLR
Measured from ±150 mV from
crossing point voltage
1
4
V/ns
Slew Rate, Fall1,3
tSLF
Measured from ±150 mV from
crossing point voltage
1
4
V/ns
50
ps
Skew between outputs
Duty
31.5
At crossing point Voltage
Cycle1,3
55
%
Output Enable Time5
All outputs
45
10
µs
Output Disable Time5
All outputs
10
µs
Power-up Time
tSTABLE
From power-up VDD=3.3 V
3
ms
Spread Change Time
tSPREAD
Settling period after spread change
3
ms
1 Test
setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).
taken from a single-ended waveform.
3 Measurement taken from a differential waveform.
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.
2 Measurement
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θ JA
Still air
93
° C/W
θ JA
1 m/s air flow
78
° C/W
θ JA
3 m/s air flow
65
° C/W
20
° C/W
θ JC
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Inches*
20
Symbol
E1
A
A1
A2
b
c
D
E
E1
e
L
a
aaa
E
INDEX
AREA
1 2
D
Min
Max
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.252
0.260
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
557G-05ALF
557G-05ALF
Tubes
20-pin TSSOP
0 to +70° C
557G-05ALFT
557G-05ALF
Tape and Reel
20-pin TSSOP
0 to +70° C
557GI-05ALF
557GI-05AL
Tubes
20-pin TSSOP
-40 to +85° C
557GI-05ALFT
557GI-05AL
Tape and Reel
20-pin TSSOP
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
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PCIE SSCG
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