DATASHEET
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
Description
Features
The ICS557-08 is a 2:1 multiplexer chip that allows the user
to select one of the two HCSL (Host Clock Signal Level)
input pairs and fans out to one pair of differential HCSL or
LVDS outputs. This chip is suited especially for
PCI-Express applications, where there is a need to select
the PCI-Express clock either locally from the PCI-E card or
from the motherboard.
•
•
•
•
•
•
Packaged in 16-pin TSSOP
Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input clock frequency of up to 200 MHz
For PCIe Gen2/3 applications, see the 5V41068A
Block Diagram
OE
VDD
3
IN1
CLK
IN1
IN2
MUX
2 to 1
CLK
IN2
3
SEL
IDT® 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
GND
Rr (IREF)
PD
1
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2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Pin Assignment
Select Table
VDD
1
16
SEL
SEL
Input Pair Selected
IN1
2
15
CLK
IN1
3
14
0
1
IN2/ IN2
IN1/ IN1
CLK
PD
4
13
GND
IN2
5
12
GND
IN2
6
11
VDD
OE
7
10
VDD
GND
8
9
IREF
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Pin Name
Pin Type
Pin Description
1
2
3
4
5
6
7
VDD
IN1
IN1
PD
IN2
IN2
OE
Power
Input
Input
Input
Input
Input
Input
Connect to +3.3 V. Supply voltage for Input clocks.
HCSL true input signal 1.
HCSL complimentary input signal 1.
Powers down the chip and tri-states outputs when low. Internal pull-up
HCSL true input signal 2.
HCSL complimentary input signal 2.
Provides output or, tri-states output (High = enable outputs; Low = disable).
Internal pull-up resistor.
8
GND
Power
Connect to ground.
9
10
11
12
13
14
15
16
IREF
VDD
VDD
GND
GND
CLK
CLK
SEL
Output
Power
Power
Power
Power
Output
Output
Input
Precision resistor attached to this pin is connected to the internal current
Connect to +3.3 V. Supply Voltage for Output Clocks.
Connect to +3.3 V. Supply Voltage for Output Clocks.
Connect to ground.
Connect to ground.
HCSL/LVDS Complimentary output clock .
HCSL/LVDS True output clock.
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
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Application Information
Decoupling Capacitors
External Components
As with any high-performance mixed-signal IC, the
ICS557-08 must be isolated from system power supply
noise to perform optimally.
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pins as close to the
device as possible.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Load Resistors RL
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
Since the clock outputs are open source outputs, 50Ω
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-08
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-08.
The ICS557-08 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
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Output Structures
IREF
=2.3 mA
R R 475Ω
6*IREF
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-08.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
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PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Differential Routing on a Single PCB
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI-Express Device Routing
L1
L2
L4
RS
L1’
L4’
L2’
RS
ICS557-08
Output
Clock
RT
L3’
RT
L3
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
tOR
500 ps
0.525 V
0.175 V
500 ps
tOF
0.525 V
0.175 V
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LVDS Compatible Layout Guidelines
Vdiff
Vp-p
0.45v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
R2a = R2b = R2
Alternative T ermination for LVDS and other Common Differential Signals
Vcm
R1
R2
R3
R4
Note
1.08
33
150
100
100
0.6
33
78.7
137
100
0.6
33
78.7
none
100
ICS874003i-02 input compatible
1.2
33
174
140
100
Standard LVDS
LVDS Device Routing
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
R2a
HCSL Output Buffer
R2b
L3'
Down Device
REF_CLK Input
L3
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
1250 mV
1150 mV
500 ps
tOF
1250 mV
1150 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-08. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Supply Voltage
Symbol
Conditions
V
Max.
Units
3.135
Min.
Typ.
3.465
V
Input High
Voltage1
VIH
OE, SEL, PD
2.0
VDD +0.3
V
Input Low
Voltage1
VIL
OE, SEL, PD
VSS-0.3
0.8
V
-5
Input Leakage
Current2
Operating Supply Current
Input Capacitance
IIL
0 < Vin < VDD
5
μA
IDD
50Ω, 2 pF
40
mA
IDDOE
OE =Low
20
mA
IDDPD
No load, PD =Low
400
μA
Input pin capacitance
7
pF
Output pin capacitance
6
pF
5
nH
CIN
Output Capacitance
COUT
Pin Inductance
LPIN
Output Resistance
ROUT
CLK outputs
Pull-up Resistor
RPUP
OE, SEL, PD
3.0
kΩ
110
kΩ
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Operating Frequency
Conditions
Min.
Typ.
HCSL termination
LVDS termination
Max.
Units
200
MHz
100
MHz
850
mV
Input High Voltage1,2
VIH
HCSL
660
700
Voltage1,2
VIL
HCSL
-150
0
Differential Input
Voltages
| VID |
LVDS
250
350
450
Input Offset Voltage
(VIS)
LVDS
1.125
1.25
1.375
V
Output High Voltage1,2
VOH
HCSL
660
700
850
mV
Output Low Voltage1,2
VOL
HCSL
-150
0
27
mV
Crossing Point
Voltage1,2
Absolute
250
350
550
mV
Crossing Point
Voltage1,2,4
Variation over all edges
140
mV
Input Low
Rise Time1,2
Fall
Time1,2
mV
mV
tOR
From 0.175 V to 0.525 V
175
332
700
ps
tOF
From 0.525 V to 0.175 V
175
344
700
ps
125
ps
Rise/Fall Time
Variation1,2
Duty Cycle1,3
45
55
%
Output Enable Time5
All outputs
10
μs
Output Disable Time5
All outputs
10
μs
From power-up VDD=3.3 V
3.0
ms
Stabilization Time
Input to Output Delay
tSTABLE
Input differential clock to output
differential clock delay measured at
crossing point of input levels to
crossing point of output levels
2
4
6
1
Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).
2
Measurement taken from a single-ended waveform.
3
Measurement taken from a differential waveform.
4
Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
ns
5
CLK and CLK pins are tri-stated when OE is Low asserted. CLK and CLK are driven differential when OE is High
unless its PD = low.
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Thermal Characteristics
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Max. Units
Still air
93
° C/W
θ JA
1 m/s air flow
78
° C/W
θ JA
3 m/s air flow
65
° C/W
20
° C/W
θ JC
Marking Diagram (ICS557GI-08LF)
16
9
9
557GI08L
######
YYWW
557G08LF
######
YYWW
1
Typ.
θ JA
Marking Diagram (ICS557G-08LF)
16
Min.
1
8
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb free package.
4. “I” denotes industrial temperature device
5. Bottom marking: (origin). Origin = country of origin if not USA.
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Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
a
aaa
E
INDEX
AREA
1 2
D
A
A2
Min
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Inches*
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
*For reference only. Controlling dimensions in mm.
A1
c
-Ce
b
SEATING
PLANE
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
557G-08LF
see page 9
Tubes
16-pin TSSOP
0 to +70° C
Tape and Reel
16-pin TSSOP
0 to +70° C
557GI-08LF
Tubes
16-pin TSSOP
-40 to +85° C
557GI-08LFT
Tape and Reel
16-pin TSSOP
-40 to +85° C
557G-08LFT
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History
Rev.
Originator
Date
Description of Change
C
D.Chan
02/16/06
Added industrial temp range; updated PCI-Express Waveform diagram to include
0.525 V; changed “Supply Voltage, VDD” spec in Absolute Max. Ratings from 5.5
V to 7 V; changed CLKOUT to CLK and CLK ; added marking diagrams for
I-temp device.
D
Arvind
05/17/07
Removed Cycle-to-cycle jitter spec.
E
06/26/07
Added 27mV to VOL max. spec
F
09/24/09
Added EOL note for non-green parts.
G
10/05/09
Updated “Input to Output Delay” parameter.
H
05/13/10
Removed EOL note for non-green parts.
J
A.T.
12/15/10
Updated LVDS termination table and diagram
K
LPL
08/02/11
Updates to product description and Features bullets on pg.1
L
K.B.
11/21/11
1. Added “Gen1” to title
2. Added note in Features section, “For PCIe Gen2/3 applications, see the
5V41068A”
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