DATASHEET
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
Description
Features
The ICS571 is a high speed, high output drive, low phase
noise Zero Delay Buffer (ZDB) which integrates IDT’s
proprietary analog/digital Phase Locked Loop (PLL)
techniques. IDT introduced the world standard for these
devices in 1992 with the debut of the AV9170, and updated
that with the ICS570. The ICS571, part of IDT’s
ClockBlocks™ family, was designed to operate at higher
frequencies, with faster rise and fall times, and with lower
phase noise. The zero delay feature means that the rising
edge of the input clock aligns with the rising edges of both
outputs, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other.
•
•
•
•
•
Packaged in 8-pin SOIC (Pb free)
•
•
•
•
Can recover poor input clock duty cycle
The chip is ideal for synchronizing outputs in a large variety
of systems, from personal computers to data
communications to video. By allowing offchip feedback
paths, the ICS571 can eliminate the delay through other
devices. The use of dividers in the feedback path will enable
the part to multiply by more than two.
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V
Can function as low phase noise x2 multiplier
Low skew outputs. One is ÷2 of other
Input clock frequency up to 160 MHz at 3.3 V
Phase noise of better than -100 dBc/Hz from 1 kHz to 1
MHz offset from carrier
Output clock duty cycle of 45/55 at 3.3 V
High drive strength for >100 MHz outputs
Full CMOS clock swings with 25 mA drive capability at
TTL levels
Block Diagram
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
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ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
Feedback Configuration Table and Frequency Ranges (at 3.3 V)
Feedback From
CLK
CLK/2
Input Range
CLK
Input clock frequency
Input clock frequency/2
20 to 160 MHz
CLK/2
2x Input clock frequency
Input clock frequency
10 to 80 MHz
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
CI
Reference clock input.
2
VDD
P
Connect to +3.3 V or +5 V. Must be same as other VDD.
3
GND
P
Connect to ground.
4
CLK/2
O
Clock output per table above. Low skew divide by two of pin 7 clock.
5
GND
P
Connect to ground.
6
VDD
P
Connect to +3.3 V or +5 V. Must be same as other VDD.
7
CLK
O
Clock output per table above.
8
FBIN
CI
Feedback clock input. Connect to CLK or CLK/2 per table above.
Key: CI = clock input; I = input; O = output; P = power supply connection.
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
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LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
External Components
pins 2 and 3, and between pins 6 and 5). They must be
connected close to the ICS571 to minimize lead inductance.
No external power supply filtering is required for this device.
A 33Ω terminating resistor can be used next to each output
pin.
The ICS571 requires a minimum number of external
components for proper operation.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on each side of the chip (between
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS571. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, referenced to GND
7V
Inputs, referenced to GND
-0.5 V to VDD+0.5 V
Clock Output, referenced to GND
-0.5 V to VDD+0.5 V
Storage Temperature
-65 to +150° C
Soldering Temperature, max of 10 seconds
260° C
Ambient Operating Temperature
0 to +70° C
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
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DC Electrical Characteristics
Unless stated otherwise, VDD = 5.0 V or 3.3 V, Ambient Temperature 0 to +70° C
Parameter
Symbol
Operating Supply Voltage
VDD
Conditions
Min.
Typ.
3
Max.
Units
5.5
V
Input High Voltage
VIH
ICLK, FBIN (pins 1 and 8)
Input Low Voltage
VIL
ICLK, FBIN (pins 1 and 8)
Output High Voltage,
CMOS level
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -25 mA
2.4
V
Output Low Voltage
VOL
IOL = 25 mA
VDD/2+1
VDD/2
VDD/2
V
VDD/2-1
0.4
V
V
IDD Operating Supply
Current, 133 in, 133 out
No load, 3.3 V
34
mA
IDD Operating Supply
Current, 50 in, 100 out
No load, 3.3 V
26
mA
Short Circuit Current
IOS
Each output
±100
mA
Input Capacitance
CIN
ICLK, FBIN
5
pF
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
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AC Electrical Characteristics
Unless stated otherwise, VDD = 5.0 V or 3.3 V, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency, clock input
fIN
FB from CLK
20
160
MHz
Input Frequency, clock input
fIN
FB from CLK/2
10
80
MHz
Skew CLK/2 with respect to CLK
Note 2
150
850
ps
Input clock to output connected to FBIN
Note 2
-500
500
ps
Output Clock Rise Time, 5 V
0.8 to 2.0 V, 15 pF load
0.3
ns
Output Clock Fall Time, 5 V
2.0 to 0.8 V, 15 pF load
0.4
ns
Output Clock Rise Time, 3.3 V
0.8 to 2.0 V, 15 pF load
0.45
ns
Output Clock Fall Time, 3.3 V
2.0 to 0.8 V, 15 pF load
0.55
ns
Input Clock Duty Cycle, 3.3 V
fin = 150 MHz
20
Output Clock Duty Cycle, 3.3 V
At VDD/2
45
Absolute Clock Period Jitter, CLK,
Note 3
Deviation from Mean
One-Sigma Clock Period Jitter, CLK,
Note 3
500
49 to 51
80
%
55
%
±80
ps
50
ps
Phase Noise, Relative to carrier
1 kHz offset
-105
dBc/Hz
Phase Noise, Relative to carrier
100 kHz offset
-115
dBc/Hz
Notes:
1. Sresses beyond these can permanently damage the device.
2. Assumes clocks with the same rise time, measured from rising edges at VDD/2. Measured with 33Ω termination
resistors and 15 pF loads. Applies to both 3.3 V and 5 V operation.
3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
° C/W
θJA
1 m/s air flow
° C/W
θJA
3 m/s air flow
° C/W
θJC
° C/W
5
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
571MLF
571MLFT
571MLF
Tubes
Tape and Reel
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
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ZDB AND MULTIPLIER/DIVIDER
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