5L35021B-104NDGI

VersaClock® 3S Programmable Clock Generator 5L35021 Datasheet Description Features The 5L35021 is a member of the VersaClock 3S programmable clock generator family with 1.8V operation voltage, and is designed for industrial, consumer, and PCI Express applications. The device features a 3 PLL architecture design; each PLL is individually programmable and allowing up to 6 unique frequency outputs. The device has programmable VCO and PLL source selection, allowing power-performance optimization based on the application requirements. ▪ Configurable OE pin function as OE, PD#, PPS or DFC control function ▪ Configurable PLL bandwidth; minimizes jitter peaking ▪ PPS: Proactive Power Saving features save power during the end device power down mode ▪ PPB: Performance Power Balancing feature allows minimum power consumption based on required performance ▪ DFC: Dynamic Frequency Control feature allows user to dynamically switch between and up to 4 different frequencies smoothly ▪ Spread spectrum clock to lower system EMI ▪ I2C interface ▪ Suspend Mode, featuring RTC clock only when system goes into low-power operation modes Typical Applications Output Features The 5L35021 has built-in features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshoot Reduction Technology (ORT) and extreme low power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5L35021 again through the I2C interface. ▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output pairs: 1MHz–250MHz (125MHz with LVCMOS mode) ▪ 1 LVCMOS output: 1MHz–125MHz ▪ LVPECL, LVDS, CML and SSTL logic can be easily supported with the LP-HCSL outputs. See application note AN-891 for alternate terminations ▪ Maximum of 5 LVCMOS outputs as REF + 3 × SE + 2 × DIFF_T/C as LVCMOS ▪ Low-power 32.768kHz clock supported for SE1 output ▪ Embedded computing devices ▪ Consumer application crystal replacements ▪ SmartDevice, Handheld, and Consumer applications Key Specifications ▪ ▪ ▪ ▪ PCIe Gen1/2/3 compliant Typical 1.5ps rms jitter integer range: 12kHz–20MHz Typical ultra-power-down current 50μA < 2μA RTC clock in Suspend Mode operation Block Diagram CLKIN/X1 OSC X2 VDDDIFF 1 Programmable Load Capacitor DIFF1 DIFF1B PLL1 VDDDIFF 2 SEL_DFC/ SCL_DFC1 SDA_DFC0 Mux & Divider PLL2 DIFF2 DIFF2B Calibration VDDSE1 VDD18 SE1 PLL3 VDDA VBAT OE1 32.768K DCO ©2019 Integrated Device Technology, Inc. 1 October 4, 2019 5L35021 Datasheet Pin Assignments VSSDIFF2 DIFF2 DIFF2B VDDDIFF2 VSSDIFF1 Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View 20 19 18 17 16 VDDA 1 15 DIFF1 SDA_DFCO 2 14 DIFF1B SEL_DFC/SCL_DFC1 3 13 VDDDIFF1 CLKIN/X2 4 12 OE1 CLKINB/X1 5 11 SE1 9 10 VDDSE1 VSS 8 VSSSE1 7 VDD18 6 VBAT 5L35021 3 x 3 mm 20-QFN Pin Descriptions Table 1. Pin Descriptions Number Name Type 1 VDDA Power 2 SDA_DFC0 I/O Description VDD 1.8V I2C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status. I2C CLK pin. SEL_DFC is a latch input pin during the power-up. High on power-on: I2C mode as SCLK function. Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins. 3 SEL_DFC/ SCL_DFC1 Input 4 CLKIN/X2 I/O Crystal oscillator interface output or differential clock input pin (CLKIN). 5 CLKINB/X1 Input Crystal oscillator interface input or differential clock input pin (CLKINB). 6 VBAT Power Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 1.8V. 7 VSS Power Connect to ground. 8 VDD18 Power VDD 1.8V. 9 VSSSE1 Power Connect to ground. 10 VDDSE1 Power Output power supply. Connect to 1.8V. Sets output voltage levels for SE1. 11 SE1 Output Output clock SE1. 12 OE1 Input OE1’s function selected from OTP pre-programmed register bits. OE1 pull to 6.5V when burn OTP registers. Refer to OE Pin Functions table for details. 13 VDDDIFF1 Power Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1. ©2019 Integrated Device Technology, Inc. 2 October 4, 2019 5L35021 Datasheet Table 1. Pin Descriptions (Cont.) Number Name Type Description 14 DIFF1B Output Differential clock output 1_Complement; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 15 DIFF1 Output Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 16 VSSDIFF1 Power Connect to ground. 17 VDDDIFF2 Power Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2. 18 DIFF2B Output Differential clock output 2_Complement; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 19 DIFF2 Output Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 20 VSSDIFF2 Power Connect to ground. EPAD Power Connect to ground pad. Detailed Block Diagram DIV1/REF OSC MUX CLKINB/X1 PLL1 CLKIN/X2 VBAT DIV 2 Power Monitor MUX PLL2 MUX DIV 3 MUX DIV 4 VDD18 POR VDDA VSS DIV 1 Calibration MUX DIV 5 PLL3 DIV3 MUX VDDDIFF1 DIV1/REF DIV3 MUX DIFF1 DIFF1B DIV4/REF DIV5 32K MUX OE1 SE1 VDDSE1 32.768K DCO SCL_DFC1 SDA_DFC0 I 2C Engine OTP memory (1 configuration) ©2019 Integrated Device Technology, Inc. Overshot Reduction (ORT) VDDDIFF2 DIFF2 DIFF2B Dynamic Frequency Control Logic (DFC) Proactive Power Saving Logic (PPS) 3 Timer October 4, 2019 5L35021 Datasheet Power Group Table 2. Power Group Power Supply SE DIFF DIV MUX PLL VDDSE1 SE1 1 VDDDIFF1 DIFF1 DIV3/4 MUXPLL2 PLL2 VDDDIFF2 DIFF2 DIV1 MUXPLL1 VDD18 DIV5 PLL3 VBAT REF Xtal DCO REF Xtal DCO VDDA 1 DCO DIV2 Xtal PLL1 VDDSE1 for non-32kHz outputs should be OFF when VDDA/VDD18 turns OFF; VBAT mode only supports 32.768kHz outputs from SE1. Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 5L35021 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3. Absolute Maximum Ratings Item Rating Supply Voltage, VDDA, VDD18, VDDSE,VDDDIFF VDD + 5% Supply Voltage, VBAT VDD + 5% Inputs XIN/CLKIN 0V to 1.8V voltage swing for both LVCMOS or DIFF CLK Other Inputs -0.5V to VDD18 or VDDSEx Outputs, VDDSEx (LVCMOS) -0.5V to VDDSEx or VDDDIFF + 0.5V Outputs, IO (SDA) 10mA Package Thermal Impedance, ΘJA 42°C/W (0mps) Package Thermal Impedance, ΘJC 41.8°C/W (0mps) Storage Temperature, TSTG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C ©2019 Integrated Device Technology, Inc. 4 October 4, 2019 5L35021 Datasheet Recommended Operating Conditions Table 4. Recommended Operating Conditions Symbol Parameter Minimum Typical Maximum Units VDDSEx Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V VDD18 Power supply voltage for core logic functions. 1.71 1.8 1.89 V VDDA Analog power supply voltage. Use filtered analog power supply if available. 1.71 1.8 1.89 V VBAT Battery power supply voltage. 1.71 1.8 1.89 V Operating temperature, ambient. -40 85 °C TA CLOAD_OUT FIN tPU Maximum load capacitance (LVCMOS only). 5 pF External reference crystal. 8 40 External reference clock CLKIN, CLKINB. 1 125 0.05 3 Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). MHz ms Crystal Characteristics Table 5. Crystal Characteristics Parameter Conditions Minimum Mode of Oscillation — Frequency — 8 Frequency when 32.768kHz DCO is used — 8 Equivalent Series Resistance (ESR) Typical Maximum Units Fundamental 40 MHz 25 39 MHz — 10 100 Ω Shunt Capacitance — 2 7 pF Load Capacitance (CL) — 8 10 pF Maximum Crystal Drive Level — 30 100 μW ©2019 Integrated Device Technology, Inc. 6 5 October 4, 2019 5L35021 Datasheet Electrical Characteristics Supply voltage: all VDD ±5%, unless otherwise stated Table 6. Electrical Characteristics – Current Consumption Symbol Parameter IDDCORE Core Supply Current IDD_PLL1 3 Typical Maximum Units VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz, PLL2/3 off, no output, PLLs disabled. 3.4 4.8 mA PLL1 Supply Current VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz, PLL2/3 off, no output, PLL1 = 600MHz. 12.1 15.3 mA IDD_PLL2 3 PLL2 Supply Current VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz, PLL1/3 off, no output, PLL2 = 60MHz. 0.5 0.8 mA IDD_PLL3 3 PLL3 Supply Current VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz, PLL1/2 off, no output, PLL3 = 480MHz. 2.5 3.2 mA LPHCSL, 125MHz, 1.8V VDDDIFF, no load (DIFF1,2). 3.4 4.1 mA LPHCSL, 100MHz, 1.8V VDDDIFF, no load (DIFF1,2). 2.9 3.5 mA LVCMOS, 8MHz, 1.8V, VDDSE 1,2 (SE1). 0.5 0.6 mA LVCMOS, 160MHz, 1.8V VDDSEx 1,2 (SE1). 2.7 3.4 mA Output Buffer Supply Current IDDOx Conditions Minimum IDDPD 3 Power Down Current – LPHCSL I2C functional during power-down, just 32kHz running (if any); DIFF outputs in LPHCSL mode are high/low. 2.6 3.4 mA IDDPD 3 Power Down Current – LVCMOS I2C functional during power-down, just 32kHz running (if any); DIFF outputs in LVCMOS mode are high/low or low/low. 0.5 1 mA IDDUPD 4 Ultra Power Down Current – LPHCSL I2C functional during power-down, just 32kHz running (if any); DIFF outputs in LPHCSL mode are low/low. 33 65 μA IDDUPD 4 Ultra Power Down Current – LVCMOS I2C functional during power-down, just 32kHz running (if any) – DIFF outputs in LVCMOS mode are low/low. 33 65 μA Suspend Mode Current – 32kHz x 1 I2C off in Suspend Mode. One 32kHz output running. 1.4 2.1 μA IDDSUSPEND 5 1 All output currents measured with 0.5 inch transmission line and 0pF load. 2 Single CMOS driver active. 3 Power-down can be controlled by PD (OE1 input pin) and/or I2C bit. 4 Ultra Power-down must be controlled by PD (OE1 input pin). 5 Suspend mode requires all VDD to GND except VDDSEn (as desired) and VDD18. 6 1,2 DIFF outputs in LVCMOS mode can power-down to be high/low or low/low, depending on register 0x22. ©2019 Integrated Device Technology, Inc. 6 October 4, 2019 5L35021 Datasheet Table 7. Electrical Characteristics–Input Parameters Symbol Parameter Conditions Minimum Typical Maximum Units VIH Input High Voltage Single-ended inputs – OE pins. 0.65 x VDDSE VDDSE + 0.3 V VIL Input Low Voltage Single-ended inputs – OE pins. GND - 0.3 0.35 x VDDSE V VIH Input High Voltage – OE Single-ended input. 0.65 x VDDSE VDDSE + 0.3 V VIL Input Low Voltage – OE Single-ended input. GND - 0.3 0.35 x VDDSE V VSWING Input Amplitude – CLKIN Single-ended input swing. 600 VDD mV IIL Input Leakage Low Current VIN = GND -20 20 μA IIH Input Leakage High Current VIN = 1.89V. -20 20 μA dTIN Input Duty Cycle Measurement from differential waveform. 45 55 % CIN Input capacitance (CLKIN, CLKINB, OE, SDA, SCL, DFC1:0). 7 pF 3 RPDR Pull-down Resistor – OE pin 550 kΩ ROUT LVCMOS output driver impedance (VDDSE = 1.8V) 17 Ω Table 8. DC Electrical Characteristics – LVCMOS Symbol Parameter Conditions Minimum VOH Output High Voltage IOH = -8mA. VOL Output Low Voltage IOL = 8mA. Output Leakage Current Tri-state outputs, VDDSE = 1.89V. Output Rise/Fall Time Single-ended LVCMOS output clock rise and fall time, 20% to 80% of VDDSE 1.8V. IOZDD tR/F Typical 0.7 x VDDSE Maximum Units VDDSE V 0.25 x VDDSE V 3 μA 1.0 ns Table 9. Electrical Characteristics – LPHCSL Differential Outputs Symbol Parameter Minimum Typical Maximum Units Notes 1 2.5 4 V/ns 1,2,3,8 20 % 1,2,3,8,9 1150 mV 1,6 dV/dt Slew Rate ΔdV/dt Slew Rate Mismatch VMAX Maximum Voltage VMIN Minimum Voltage -300 mV 1,6 VSWING Voltage Swing 300 mV 1,2,6 VCROSS Crossing Voltage Value 250 mV 1,4,6 ©2019 Integrated Device Technology, Inc. 7 400 550 October 4, 2019 5L35021 Datasheet Table 9. Electrical Characteristics – LPHCSL Differential Outputs (Cont.) Symbol ΔVCROSS Jitter-Cy/Cy Jitter-STJ TDC Parameter Minimum Maximum Units Notes Crossing Voltage Variation 140 mV 1,5,9 Cycle to Cycle Jitter 160 ps 1,2 Short Term Period Jitter 300 ps 1,2 55 % 1,2 Duty Cycle 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform. 3 Typical Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a ±150mV window around differential 0V. 4 VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 5 The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute) allowed. The intent is to limit VCROSS induced modulation by setting ΔVCROSS to be smaller than VCROSS absolute. 6 Measured from single-ended waveform. 7 Measured with scope averaging off, using statistics function. Variation is the difference between minimum and maximum. 8 Scope average on. 9 100MHz, spread off and 0.5% spread. ©2019 Integrated Device Technology, Inc. 8 October 4, 2019 5L35021 Datasheet General AC Electrical Characteristics VDD = 1.8V ±5%, TA = -40°C to +85°C; spread spectrum = off Table 10. AC Timing Electrical Characteristics Symbol Parameter Conditions Minimum Typical Maximum Units Input frequency limit (XIN). 8 40 MHz Input frequency limit (LVCMOS to X1). 1 125 MHz Single-ended clock output limit (LVCMOS). 1 125 MHz Differential clock output frequency (LPHCSL). 1 125 MHz VCO Frequency Range of PLL1 VCO operating frequency range. 300 600 MHz fVCO2 VCO Frequency Range of PLL2 VCO operating frequency range. 30 130 MHz fVCO3 VCO Frequency Range of PLL3 VCO operating frequency range. 300 800 MHz Output Duty Cycle LVCMOS (measured at VDDO/2). 45 55 % Output Duty Cycle – REF Reference clock output or SE1–3 fan out clock measured at VDDO/2. 40 60 % fIN 1 Input Frequency fOUT Output Frequency fVCO1 tODC Cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs (1.8V nominal output voltage). SE1 = 25MHz. 50 ps 1.5 ps 75 ps DIFF1/2 = 100MHz. tJ Clock Jitter RMS phase jitter (12kHz to 20MHz integration range) differential output, 1.8V nominal output voltage. 25MHz crystal. SE1 = 12.5MHz – REF/2. DIFF1/2 = 100MHz – PLL1. REF = 25M. tSKEW Output Skew Skew between the same frequencies, with outputs using the same driver format. tLOCK 2 Lock Time PLL/DCO lock time. 1 10 ms Practical lower frequency is determined by loop filter settings. 2 Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time. 3 Actual PLL lock time depends on the loop configuration. ©2019 Integrated Device Technology, Inc. 9 October 4, 2019 5L35021 Datasheet PCI Express Jitter Specifications VDDDIFF = 1.8V ±5% TA = -40°C to +85°C Table 11. PCI Express Jitter Specifications Symbol tJ (PCIe Gen1) Parameter Conditions Phase Jitter Peak-to-Peak ƒ = 100MHz/125MHz, 25MHz crystal input. Evaluation band: 0Hz – Nyquist (clock frequency/2). tREFCLK_HF_RMS (PCIe Gen2) Phase Jitter RMS tREFCLK_LF_RMS (PCIe Gen2) Phase Jitter RMS tREFCLK_RMS (PCIe Gen3) Phase Jitter RMS Minimum ƒ = 100MHz/125MHz, 25MHz crystal input. High band: 1.5MHz – Nyquist (clock frequency/2). ƒ = 100MHz/125MHz, 25MHz crystal input. Typical Maximum Industry Specification Units Notes 27 86 ps 1,4 1.9 3.10 ps 2,4 0.9 3.0 ps 2,4 0.5 1.0 ps 3,4 Low band: 10kHz – 1.5MHz. ƒ = 100MHz/125MHz, 25MHz crystal input. Evaluation band: 0Hz – Nyquist (clock frequency/2). Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 1 Peak-to-peak 2 jitter after applying system transfer function for the common clock architecture. Maximum limit for PCI Express Gen1. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Gen2 is 3.1ps RMS for t REFCLK_HF_RMS (high band) and 3.0ps RMS for tREFCLK_LF_RMS (low band). 3 RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov. 2010 specification, and is subject to change pending the final release version of the specification. 4 This parameter is guaranteed by characterization. Not tested in production. I2C Bus Characteristics Table 12. I2C Bus DC Characteristics Symbol Parameter VIH Input High Level VIL Input Low Level VHYS Conditions Input Leakage Current VOL Output Low Voltage ©2019 Integrated Device Technology, Inc. Typical Maximum 0.7 × VDD18 0.05 × VDD18 IOL = 3mA. 10 Units V 0.3 × VDD18 Hysteresis of Inputs IIN Minimum V V ±1 μA 0.4 V October 4, 2019 5L35021 Datasheet Table 13. I2C Bus AC Characteristics Symbol FSCLK tBUF Parameter Conditions Minimum Serial Clock Frequency (SCL) Typical Maximum Units 100 400 kHz Bus Free Time between STOP and START 1.3 μs tSU:START Setup Time, START 0.6 μs tHD:START Hold Time, START 0.6 μs tSU:DATA Setup Time, data input (SDA) 100 ns tHD:DATA Hold Time, data input (SDA) 1 0 μs tOVD Output Data Valid from Clock 0.9 μs CB Capacitive Load for Each Bus Line 400 pF tR Rise Time, data and clock (SDA, SCL) 20 + 0.1 × CB 300 ns tF Fall Time, data and clock (SDA, SCL) 20 + 0.1 × CB 300 ns tHIGH High Time, clock (SCL) 0.6 μs tLOW Low Time, clock (SCL) 1.3 μs Setup Time, STOP 0.6 μs tSU:STOP 1 A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Glossary of Features Table 14. Glossary of Features Term Function Description Apply to DFC Dynamic Frequency Control; from selected PLL to support four VCO frequencies; means two different output frequencies by assigned H/W pin state changes (H-L or L-H) needs to have frequency change Glitch-Free function in order to not crash application system. PLL2 ORT Overshot Reduction; when the DFC dynamic frequency change is functional, the VCO changes frequencies smoothly to target frequency without overshoot or undershoot. PLL2 OE Output enable function; each output can be controlled by assigned OE pin and the dedicated OE pin can be OTP programmable as global Power Down function (PD#) or Output Enable (OE) or Proactive Power Saving function (PPS) or RESET pin function. OE1 SS Spread spectrum clock. Slew Rate PPS PLL1/PLL2 LVCMOS outputs with slew rate control – slow and fast. Proactive Power Saving; utilize OE pin as monitor pin for end device X2 clock status. See PPS Function description for details. ©2019 Integrated Device Technology, Inc. 11 LVCMOS SE1 October 4, 2019 5L35021 Datasheet Device Features and Functions Performance Power Balancing VersaClock 3S features Performance Power Balancing with three individual programmable PLL designs and provides a balance between performance and power consumption. The device can operate within single-digit mA low-power operation or support high-performance requirements such as PCIe Gen 3 with additional power. In order to satisfy system trade-off, outputs have the option to route from different PLL/input sources. Table 15. Power Saving Modes Summary Power Mode External Condition Internal Operating Condition Core Current Consumption Power-down Mode VDD all connected. All off, I2C still active. 2mA Ultra-power-down VDD all connected. All off. 50μA Suspend Mode Only VBAT connected. All off, only DCO on with RTC (32.768kHz) output only. 2μA Table 16. Output Source Outputs Source SE1 DIFF1 DIFF2 Xtal REF Xtal REF Xtal REF Xtal REF 32.768kHz 32.768kHz PLL1 PLL1 PLL1 PLL2 PLL2 PLL2 PLL2 PLL3 PLL3 PLL3 PLL3 Table 17. SE1 Output SE1 B36 B36 B31 B29 From 32kHz 0 1 0 0 From PLL3 + Divider 5 1 0 0 0 From PLL2 + Divider 4 1 1 1 0 From REF + Divider 4 1 1 0 1 B34 B0 From PLL1 + Divider 1 0 0 From PLL2 + Divider 3 1 0 From REF + Divider 1 0 1 Table 18. DIFF1 Output DIFF1 ©2019 Integrated Device Technology, Inc. 12 October 4, 2019 5L35021 Datasheet Table 19. DIFF2 Output DIFF2 B35 B0 From PLL1 + Divider 1 0 0 From PLL2 + Divider 3 1 0 From REF + Divider 1 0 1 DFC – Dynamic Frequency Control ▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2. ▪ ORT (over shoot reduction) function will be applied automatically during the VCO frequency change. ▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection. Figure 2. DFC Function Block Diagram M divider PLL2 OUT DIV Selector 00 N divider 01 N divider 10 N divider 11 N divider DFC1:0 OTP/I2C Table 20. DFC Function Priority DFC_EN bit (W32[4]) OE1_fun_sel (W30[6:5]) *OE3_fun_sel (W30[3:2]) SCL_DFC1 DFC[1:0] Notes 0 x x x 0 DFC disable 1 11 (DFC) 00–10 (DFC) x [0,OE1] One pin DFC–OE1 1 11 (DFC) 11 (DFC) x [OE3,OE1] Two pin DFC–OE3, OE1 1 00–10 11 x Not permitted Not supported 1 00–10 00–10 0 [SCL_DFC1, SDA_DFC0] I2C pin as DFC control pins mode 1 00–10 00–10 1 W30[1:0] I2C control DFC mode * The 5L35021 has only OE1 pin for DFC function hardware pin selection. For OE1/OE3 two pins DFC control, use 5L35023 24-QFN package device. ©2019 Integrated Device Technology, Inc. 13 October 4, 2019 5L35021 Datasheet DFC Function Programming ▪ Register B63b3:2 selects DFC00–DFC11 configuration. ▪ Byte16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored in selected configuration OTP memory. ▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function. ▪ Note the DFC function can also be controlled by I2C access. PPS – Proactive Power Saving Function PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes