VersaClock® 3S Programmable
Clock Generator
5L35023
Datasheet
Description
Features
The 5L35023 is a member of the VersaClock® 3S programmable
clock generator family with 1.8V operation voltage, and is
designed for industrial, consumer, and PCI Express applications.
The device features a 3 PLL architecture design; each PLL is
individually programmable and allowing up to 6 unique frequency
outputs.
The device has programmable VCO and PLL source selection,
allowing power-performance optimization based on the application
requirements.
▪ Configurable OE pin function as OE, PD#, PPS or DFC control
function
▪ Configurable PLL bandwidth; minimizes jitter peaking
▪ PPS: Proactive Power Saving features save power during the
end device power down mode
▪ PPB: Performance Power Balancing feature allows minimum
power consumption based on required performance
▪ DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 different frequencies
smoothly
▪ Spread spectrum clock to lower system EMI
▪ I2C interface
▪ Suspend Mode, featuring RTC clock only when system goes
into low-power operation modes
Typical Applications
Output Features
The 5L35023 has built-in features such as Proactive Power
Saving (PPS), Performance-Power Balancing (PPB), Overshoot
Reduction Technology (ORT) and extreme low power DCO. An
internal OTP memory allows the user to store the configuration in
the device without programming after power-up, then program the
5L35023 again through the I2C interface.
▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output
pairs: 1MHz–125MHz
▪ 3 LVCMOS outputs: 1MHz–125MHz
▪ LVPECL, LVDS, CML and SSTL logic can be easily supported
with the LP-HCSL outputs. See application note AN-891 for
alternate terminations
▪ Maximum of 8 LVCMOS outputs
▪ Low-power 32.768kHz clock supported for all SE1–SE3
▪ Embedded computing devices
▪ Consumer application crystal oscillator replacements
▪ SmartDevice, Handheld, and Consumer applications
Key Specifications
▪
▪
▪
▪
PCIe Gen1/2/3 compliant
Typical 1.5ps rms jitter integer range: 12kHz–20MHz
Typical ultra-power-down current 50μA
< 2μA RTC clock in Suspend Mode operation
Block Diagram
CLKIN/X1
X2
REF
OSC
VDDDIFF1
DIFF1
DIFF1B
Programmable
Load Capacitor
PLL1
SEL_DFC/ SCL_DFC1
SDA_DFC0
VDDDIFF2
DIFF2
DIFF2B
Mux
&
Divider
PLL2
Calibration
VDDA
OE2
32.768K
DCO
VDDSE3
SE3
VBAT
©2019 Integrated Device Technology, Inc.
OE1
VDDSE2
SE2
PLL3
VDD18
VDDSE1
SE1
OE3
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October 4, 2019
5L35023 Datasheet
Pin Assignments
DIFF2
DIFF2B
VDDDIFF2
OE3
VDDSE3
SE3
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
24
23
22
21
20
19
VDDA
1
18
DIFF1
SDA_DFCO
2
17
DIFF1B
SEL_DFC/SCL_DFC1
3
16
VDDDIFF1
X2
4
15
OE1
CLKIN/X1
5
14
SE1
VBAT
6
13
VDDSE1
10
11
12
VDDSE2
SE2
REF
9
OE2
8
VDD18
7
NC
5L35023
4 x 4 mm 24-VFQFPN
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
1
VDDA
Power
2
SDA_DFC0
I/O
3
SEL_DFC/
SCL_DFC1
Input
4
X2
I/O
5
CLKIN/X1
Input
Crystal oscillator interface input or single-ended clock input pin (CLKIN).
6
VBAT
Power
Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 1.8V.
7
NC
—
8
REF
Output
1.8V reference clock output.
9
VDD18
Power
VDD 1.8V.
10
OE2
Input
Output enable control 2, multi-function pin. Refer to OE function table.
11
VDDSE2
Power
Output power supply. Connect to 1.8V. Sets output voltage levels for SE2.
12
SE2
Output
Output clock SE2.
13
VDDSE1
Power
Output power supply. Connect to 1.8V. Sets output voltage levels for SE1.
©2019 Integrated Device Technology, Inc.
Description
VDD 1.8V.
I2C DATA pin, the pin can be DFC0 function by pin 3 SEL_DFC power on latch status.
I2C CLK pin, SEL_DFC is a latch input pin during the power-up.
High on power-on: I2C mode as SCLK function.
Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins.
Crystal oscillator interface output.
No connection.
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5L35023 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Description
14
SE1
Output
15
OE1
Input
OE1 function selected from OTP pre-program register bits.
OE1 pull to 6.5V when burn OTP registers.
Refer to OE function table for details.
16
VDDDIFF1
Power
Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1.
17
DIFF1B
Output
Differential clock output 1_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
18
DIFF1
Output
Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
19
SE3
Output
Output clock SE3.
20
VDDSE3
Power
Output power supply. Connect to 1.8V. Sets output voltage levels for SE3.
21
OE3
Input
Output enable control 3, multi-function pin. Refer to OE Pin Function table.
22
VDDDIFF2
Power
Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2.
23
DIFF2B
Output
Differential clock output 2_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
24
DIFF2
Output
Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
EPAD
Power
Connect to ground pad.
Output clock SE1.
Detailed Block Diagram
DIV1/REF
OSC
MUX
CLKINB/X1
PLL1
CLKIN/X2
VBAT
DIV
2
Power
Monitor
MUX
PLL2
MUX
DIV
3
MUX
DIV
4
VDD18
POR
VDDA
VSS
DIV
1
Calibration
MUX
DIV
5
PLL3
DIV3
MUX
VDDDIFF1
DIV1/REF
DIV3
MUX
DIFF1
DIFF1B
MUX
OE3
SE3
VDDSE3
MUX
OE2
SE2
VDDSE2
MUX
OE1
SE1
VDDSE1
DIV2
DIV4/REF
32K
DIV4/REF
DIV5
32K
DIV4/REF
DIV5
32K
32.768K
DCO
SCL_DFC1
SDA_DFC0
I 2C Engine
OTP memory (1 configuration)
©2019 Integrated Device Technology, Inc.
VDDDIFF2
DIFF2
DIFF2B
REF
Overshot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
Proactive Power Saving Logic (PPS)
3
Timer
October 4, 2019
5L35023 Datasheet
Power Group
Table 2. Power Group
Power Supply
SE
DIFF
DIV
MUX
PLL
VDDSE1
SE1 1
VDDSE2
SE2 1
VDDSE3
SE3 1
VDDDIFF1
DIFF1
DIV3/4
MUXPLL2
PLL2
VDDDIFF2
DIFF2
DIV1
MUXPLL1
VDD18
DIV5
PLL3
VBAT
REF
Xtal
DCO
REF
Xtal
DCO
VDDA
1
DCO
DIV2
Xtal
PLL1
VDDSEx for non-32kHz outputs should be OFF when VDDA/VDD18 turns OFF; VBAT mode only supports 32.768kHz outputs from SE1–3.
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 5L35023 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 3. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDDA, VDD18, VDDSE,VDDDIFF
VDD + 5% maximum
Supply Voltage, VBAT
VDD + 5% maximum
Inputs
XIN/CLKIN
0V to 1.8V voltage swing for both LVCMOS or DIFF CLK
Other Inputs
-0.5V to VDD18 or VDDSEx
Outputs, VDDSEx (LVCMOS)
-0.5V to VDDSEx or VDDDIFF + 0.5V
Outputs, IO (SDA)
10mA
Package Thermal Impedance, ΘJA
42°C/W (0mps)
Package Thermal Impedance, ΘJC
41.8°C/W (0mps)
Storage Temperature, TSTG
-65°C to 150°C
ESD Human Body Model
2000V
Junction Temperature
125°C
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5L35023 Datasheet
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol
Parameter
Minimum
Typical
Maximum Units
VDDSEx
Power supply voltage for supporting 1.8V outputs.
1.71
1.8
1.89
V
VDD18
Power supply voltage for core logic functions.
1.71
1.8
1.89
V
VDDA
Analog power supply voltage. Use filtered analog power supply if
available.
1.71
1.8
1.89
V
VBAT
Battery power supply voltage.
1.71
1.8
1.89
V
Operating temperature, ambient.
-40
85
°C
TA
CLOAD_OUT
FIN
tPU
Maximum load capacitance (LVCMOS only).
5
pF
External reference crystal.
8
40
External reference clock CLKIN, CLKINB.
1
125
0.05
3
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic).
MHz
ms
Crystal Characteristics
Table 5. Crystal Characteristics
Parameter
Minimum
Typical
Mode of Oscillation
Maximum
Units
Fundamental
Frequency
8
40
MHz
Frequency when 32.768kHz DCO is used
8
25
39
MHz
Equivalent Series Resistance (ESR)
10
100
Ω
Shunt Capacitance
2
7
pF
8
10
pF
30
100
μW
Load Capacitance (CL)
6
Maximum Crystal Drive Level
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October 4, 2019
5L35023 Datasheet
Electrical Characteristics
Supply voltage: all VDD ±5%, unless stated otherwise
Table 6. Electrical Characteristics – Current Consumption
Symbol
Parameter
IDDCORE
Core Supply Current
IDD_PLL1 3
1,2
Typical
Maximum
Units
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL2/3 off, no output, PLLs disabled.
3.4
4.8
mA
PLL1 Supply
Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL2/3 off, no output, PLL1 = 600MHz.
12.1
15.3
mA
IDD_PLL2 3
PLL2 Supply
Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL1/3 off, no output, PLL2 = 60MHz.
0.5
0.8
mA
IDD_PLL3 3
PLL3 Supply
Current
VDD = VDDSE = VDD18 = 1.8V; XTAL = 25MHz,
PLL1/2 off, no output, PLL3 = 480MHz.
2.5
3.2
mA
LPHCSL, 125MHz, 1.8V VDDDIFF, no load
(DIFF1,2).
3.4
4.1
mA
LPHCSL, 100MHz, 1.8V VDDDIFF, no load
(DIFF1,2).
2.9
3.5
mA
LVCMOS, 8MHz, 1.8V, VDDSE 1,2 (SE1).
0.5
0.6
mA
LVCMOS, 160MHz, 1.8V VDDSEx 1,2 (SE1).
2.7
3.4
mA
C functional during power-down, just 32kHz
running (if any); DIFF outputs in LPHCSL mode
are high/low.
2.6
3.4
mA
Output Buffer
Supply Current
IDDOx
IDDPD 3
Power Down
Current–LPHCSL
Conditions
Minimum
I2
3,6
Power Down
Current–LVCMOS
I2C functional during power-down, just 32kHz
running (if any); DIFF outputs in LVCMOS mode
are high/low or low/low.
0.5
1
mA
IDDUPD
4
Ultra Power Down
Current–LPHCSL
I2C functional during power-down, just 32kHz
running (if any); DIFF outputs in LPHCSL mode
are low/low.
33
65
μA
IDDUPD
4
Ultra Power Down
Current–LVCMOS
I2C functional during power-down, just 32kHz
running (if any) – DIFF outputs in LVCMOS mode
are low/low.
33
65
μA
IDDSUSPEND 5
Suspend Mode
Current–32kHz x 1
I2C off in Suspend Mode. One 32kHz output
running.
1.4
2.1
μA
IDDSUSPEND 5
Suspend Mode
Current–32kHz x 2
I2C off in Suspend Mode. Two 32kHz outputs
running.
3.2
7.9
μA
IDDSUSPEND 5
Suspend Mode
Current–32kHz x 3
I2C off in Suspend Mode. Three 32kHz outputs
running.
3.7
8.6
μA
IDDPD
1
All output currents measured with 0.5 inch transmission line and 0pF load.
2
Single CMOS driver active.
3
Power-down can be controlled by PD (OE1 input pin) and/or I2C bit.
4
Ultra power-down must be controlled by PD (OE1 input pin).
5
Suspend Mode requires all VDD to GND except VDDSEn (as desired) and VDD18.
6
DIFF outputs in LVCMOS mode can power-down to be high/low or low/low, depending on register 0x22[1:0].
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
Table 7. Electrical Characteristics – Input Parameters
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
Single-ended inputs–OE pins.
0.65 x VDDSE
VDDSE + 0.3
V
VIL
Input Low Voltage
Single-ended inputs–OE pins.
GND - 0.3
0.35 x VDDSE
V
VIH
Input High Voltage–SEL_DFC
Single-ended latched input.
0.65 x VDDSE
VDDSE + 0.3
V
VIL
Input Low Voltage–SEL_DFC
Single-ended latched input.
GND - 0.3
0.35 x VDDSE
V
Input Amplitude–CLKIN
Single-ended input swing.
600
VDD
mV
IIL
Input Leakage Low Current
VIN = GND.
-20
20
μA
IIH
Input Leakage High Current
VIN = 1.89V.
-20
20
μA
dTIN
Input Duty Cycle
Measurement from differential
waveform.
45
55
%
CIN
Input Capacitance (CLKIN,
CLKINB, OE, SDA, SCL, DFC1:0).
7
pF
VSWING
3
RPDR
Pull-down Resistor–OE pin
550
kΩ
ROUT
LVCMOS Output Driver
Impedance (VDDSE = 1.8V)
17
Ω
Table 8. Electrical Characteristics – LVCMOS
Symbol
Parameter
Conditions
Minimum
Typical
Units
VDDSE
V
0.25 x VDDSE
V
3
μA
VOH
Output High Voltage
IOH = -8mA.
VOL
Output Low Voltage
IOL = 8mA.
Output Leakage Current
Tri-state outputs, VDDSE = 1.89V.
Output Rise/Fall Time
Single-ended LVCMOS output clock
rise and fall time, 20% to 80% of
VDDSE 1.8V.
Output Duty Cycle
LVCMOS (measured at VDDO/2).
45
55
%
Output Duty Cycle–REF
Reference clock output or SE1–3 fan
out clock measured at VDDO/2.
40
60
%
IOZDD
tR/F
tODC
0.7 x VDDSE
Maximum
1.0
ns
Table 9. Electrical Characteristics – LPHCSL Differential Outputs
Symbol
Parameter
Minimum
Typical
Maximum
Units
Notes
1
2.5
4
V/ns
1,2,3,8
20
%
1,2,3,8,9
1150
mV
1,6
dV/dt
Slew Rate
ΔdV/dt
Slew Rate Mismatch
VMAX
Maximum Voltage
VMIN
Minimum Voltage
-300
mV
1,6
Voltage Swing
300
mV
1,2,6
VSWING
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October 4, 2019
5L35023 Datasheet
Table 9. Electrical Characteristics – LPHCSL Differential Outputs (Cont.)
Symbol
Parameter
VCROSS
Crossing Voltage Value
ΔVCROSS
Jitter-Cy/Cy
Jitter-STJ
tDC
Minimum
Typical
Maximum
Units
Notes
250
400
550
mV
1,4,6
Crossing Voltage Variation
140
mV
1,5,9
Cycle to Cycle Jitter
160
ps
1,2
Short Term Period Jitter
300
ps
1,2
55
%
1,2
Duty Cycle
45
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform.
3
Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a ±150mV window around differential 0V.
4
VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock
rising and Clock# falling).
5
The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute) allowed.
The intent is to limit VCROSS induced modulation by setting ΔVCROSS to be smaller than VCROSS absolute.
6
Measured from single-ended waveform.
7
Measured with scope averaging off, using statistics function. Variation is the difference between minimum and maximum.
8
Scope average on.
9
100MHz, spread off and 0.5% spread.
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October 4, 2019
5L35023 Datasheet
General AC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C; spread spectrum = off
Table 10. AC Electrical Characteristics
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
Input frequency limit (XIN).
8
40
MHz
Input frequency limit (LVCMOS to X1).
1
125
MHz
Single-ended clock output limit (LVCMOS).
1
125
MHz
Differential clock output frequency (LPHCSL).
1
125
MHz
VCO Frequency Range of PLL1 VCO operating frequency range.
300
600
MHz
fVCO2
VCO Frequency Range of PLL2 VCO operating frequency range.
30
130
MHz
fVCO3
VCO Frequency Range of PLL3 VCO operating frequency range.
300
800
MHz
fIN 1
Input Frequency
fOUT
Output Frequency
fVCO1
Cycle-to-cycle jitter (peak-to-peak), multiple
output frequencies switching, differential
outputs (1.8V nominal output voltage).
SE1 = 25MHz.
SE2 = 100MHz.
50
ps
1.5
ps
75
ps
SE3 = 125MHz.
DIFF1/2 = 100MHz.
tJ
Clock Jitter
RMS phase jitter (12kHz to 20MHz integration
range) differential output, 1.8V nominal output
voltage.
25MHz crystal.
SE1=12.5MHz–REF/2.
SE2=133.333MHz–PLL3.
SE3=120MHz–PLL1.
DIFF1/2=100MHz–PLL1.
REF=25M.
tSKEW
Output Skew
Skew between the same frequencies, with
outputs using the same driver format.
tLOCK 2
Lock Time
PLL/DCO lock time.
10
1
Practical lower frequency is determined by loop filter settings.
2
Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time.
3
Actual PLL lock time depends on the loop configuration.
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
PCI Express Jitter Specifications
VDDDIFF = 1.8V ±5%, TA = -40°C to +85°C
Table 11. PCI Express Jitter Specifications
Symbol
tJ (PCIe Gen1)
Parameter
Conditions
Phase Jitter
Peak-to-Peak
ƒ = 100MHz/125MHz,
25MHz crystal input.
Evaluation band: 0Hz –
Nyquist (clock frequency/2).
tREFCLK_HF_RMS
(PCIe Gen2)
Phase Jitter
RMS
tREFCLK_LF_RMS
(PCIe Gen2)
Phase Jitter
RMS
tREFCLK_RMS
(PCIe Gen3)
Phase Jitter
RMS
Minimum
ƒ = 100MHz/125MHz,
25MHz crystal input.
High band: 1.5MHz –
Nyquist (clock frequency/2).
ƒ = 100MHz/125MHz,
25MHz crystal input.
Typical
Maximum
Industry
Specification
Units Notes
27
86
ps
1,4
1.9
3.10
ps
2,4
0.9
3.0
ps
2,4
0.5
1.0
ps
3,4
Low band: 10kHz – 1.5MHz.
ƒ = 100MHz/125MHz,
25MHz crystal input.
Evaluation band: 0Hz –
Nyquist (clock frequency/2).
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
1 Peak-to-peak
2
3
4
jitter after applying system transfer function for the common clock architecture. Maximum limit for PCI Express Gen1.
RMS jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst
case results for each evaluation band. Maximum limit for PCI Express Gen2 is 3.1ps RMS for tREFCLK_HF_RMS (high band) and 3.0ps RMS for
tREFCLK_LF_RMS (low band).
RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10
Nov. 2010 specification, and is subject to change pending the final release version of the specification.
This parameter is guaranteed by characterization. Not tested in production.
I2C Bus Characteristics
Table 12. I2C Bus DC Characteristics
Symbol
Parameter
VIH
Input High Level
VIL
Input Low Level
VHYS
Conditions
Input Leakage Current
VOL
Output Low Voltage
©2019 Integrated Device Technology, Inc.
Typical
Maximum
0.7 × VDD18
0.05 × VDD18
IOL = 3mA.
10
Units
V
0.3 × VDD18
Hysteresis of Inputs
IIN
Minimum
V
V
±1
μA
0.4
V
October 4, 2019
5L35023 Datasheet
Table 13. I2C Bus AC Characteristics
Symbol
FSCLK
tBUF
Parameter
Conditions
Minimum
Serial Clock Frequency (SCL)
Typical
Maximum
Units
100
400
kHz
Bus Free Time between STOP and START
1.3
μs
tSU:START
Setup Time, START
0.6
μs
tHD:START
Hold Time, START
0.6
μs
tSU:DATA
Setup Time, Data Input (SDA)
100
ns
tHD:DATA
Hold Time, Data Input (SDA) 1
0
μs
tOVD
Output Data Valid from Clock
0.9
μs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, Data and Clock (SDA, SCL)
20 + 0.1 × CB
300
ns
tF
Fall Time, Data and Clock (SDA, SCL)
20 + 0.1 × CB
300
ns
tHIGH
High Time, Clock (SCL)
0.6
μs
tLOW
Low Time, Clock (SCL)
1.3
μs
Setup Time, STOP
0.6
μs
tSU:STOP
1
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
Glossary of Features
Table 14. Glossary of Features
Term
Function Description
Apply to
DFC
Dynamic Frequency Control; from selected PLL to support four VCO frequencies; means two different
output frequencies by assigned H/W pin state changes.
PLL2
ORT
Overshot Reduction; when the DFC dynamic frequency change is functional, the VCO changes
frequencies smoothly to target frequency without overshoot or undershoot.
PLL2
OE
Output enable function; each output can be controlled by assigned OE pin and the dedicated OE pin can
be OTP programmable as global Power Down function (PD#) or Output Enable (OE) or Proactive Power
Saving function (PPS) or RESET pin function.
SS
Spread spectrum clock.
Slew Rate
PPS
PLL1/PLL2
LVCMOS outputs with slew rate control – slow and fast.
Proactive Power Saving; utilize OE pin as monitor pin for end device X2 clock status. See PPS Function
description for details.
©2019 Integrated Device Technology, Inc.
OE1–3
11
LVCMOS
SE1–3
October 4, 2019
5L35023 Datasheet
Device Features and Functions
Performance Power Balancing
VersaClock 3S features Performance Power Balancing with three individual programmable PLL designs and provides a balance between
performance and power consumption.
The device can operate within single-digit mA low-power operation or support high-performance requirements such as PCIe Gen 3 with
additional power.
In order to satisfy system trade-off, outputs have the option to route from different PLL/input sources.
Table 15. Power Saving Modes Summary
Power Mode
External Condition
Internal Operating Condition
Core Current Consumption
Power-down Mode
VDD all connected.
All off, I2C still active.
2mA
Ultra-power-down
VDD all connected.
All off.
50μA
Suspend Mode
Only VBAT connected.
All off, only DCO on with RTC
(32.768kHz) output only.
2μA
Table 16. Output Source
Source
Xtal REF
Outputs
REF
SE1
SE2
SE3
Xtal REF
Xtal REF
Xtal REF
Xtal REF
32.768kHz
32.768kHz
32.768kHz
32.768kHz
PLL1
PLL2
PLL2
PLL2
PLL3
PLL3
PLL3
DIFF1
DIFF2
PLL1
PLL1
PLL1
PLL2
PLL2
PLL2
PLL3
PLL3
Table 17. SE1 Output
SE1
B36
B36
B31
B29
From 32kHz
0
1
0
0
From PLL3 + Divider 5
1
0
0
0
From PLL2 + Divider 4
1
1
1
0
From REF + Divider 4
1
1
0
1
B31
B31
B36
B31
B29
From 32kHz
0
0
0
0
0
From PLL3 + Divider 5
1
0
0
0
0
From PLL2 + Divider 4
1
1
1
1
0
From REF + Divider 4
1
1
1
0
1
Table 18. SE2 Output
SE2
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5L35023 Datasheet
Table 19. SE3 Output
SE3
B33
B33
B7
B29
B36
B31
From 32kHz
0
0
0
0
0
0
From PLL1 + Divider 2
1
0
1
0
0
0
From PLL2 + Divider 4
1
1
0
0
1
1
From REF + Divider 4
1
1
0
1
1
0
B34
B0
From PLL1 + Divider 1
0
0
From PLL2/3 + Divider 3
1
0
From REF + Divider 1
0
1
B35
B0
From PLL1 + Divider 1
0
0
From PLL2/3 + Divider 3
1
0
From REF + Divider 1
0
1
Table 20. DIFF1 Output
DIFF1
Table 21. DIFF2 Output
DIFF2
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5L35023 Datasheet
DFC – Dynamic Frequency Control
▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.
▪ ORT (over shoot reduction) function will be applied automatically during the VCO frequency change.
▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
Figure 2. DFC Function Block Diagram
M divider
PLL2
OUT DIV
Selector
00
01
10
N divider
N divider
N divider
11
N divider
DFC1:0
OTP/I2C
Table 22. DFC Function Priority
DFC_EN bit (W32[4])
OE1_fun_sel
(W30[6:5])
OE3_fun_sel
(W30[3:2])
SCL_DFC1
DFC[1:0]
Notes
0
x
x
x
0
DFC disable
1
11 (DFC)
00–10 (DFC)
x
[0,OE1]
One pin DFC–OE1
1
11 (DFC)
11 (DFC)
x
[OE3,OE1]
Two pin DFC–OE3,
OE1
1
00–10
11
x
Not permitted
Not supported
1
00–10
00–10
0
[SCL_DFC1,
SDA_DFC0]
I2C pin as DFC
control pins mode
1
00–10
00–10
1
W30[1:0]
I2C control DFC
mode
DFC Function Programming
▪ Register B63b3:2 selects DFC00–DFC11 configuration.
▪ Bytes 16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored
in selected configuration OTP memory.
▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function.
▪ Note the DFC function can also be controlled by I2C access.
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5L35023 Datasheet
PPS – Proactive Power Saving Function
PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down
state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes
< 2μA current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown
as below.
Figure 3. PPS Function Block Diagram
I2C
&
Logic
Xtal
Oscillator
PPS
Control
Logic
Power
Down
Control
Low
Power
DCO
XOUT
XIN
PLL
Xtal
Oscillator
Logic
MHz / kHz
Switching
Figure 4. PPS Assertion/Deassertion Timing Chart
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5L35023 Datasheet
PPS Function Programming
1. Refer to the OE Pin Functions table to have the proper PPS function selected for OE pin(s). Note that the register default is set to
Output enable (OE) function for OE pins.
2. Have proper setup to Byte 30 and 32 for OE1–OE3 function selection; for PPS function, select 10 to control register bits.
Timer Function Description
1. The timer function can be used together with the DFC (Dynamic Frequency Control) function or with another PLL frequency
programming.
2. The timer provides 4 different delay times by two bits selection: 0.5 seconds, 1 seconds, 2 seconds, 4 seconds.
3. The timeout flag will be set when timer times out and the flag can be cleared by writing 0 to timer enable bit.
4. When timer times out, RESET pin can generate a 250ms pulse signal if RESET control bit is enabled.
5. When timer times out, DFC stage will switch back to DFC00 setting if DFC function is enabled and DFC function will be disabled after
RESET.
Figure 5. Timer Functions
Select delay time 0.5 - 4.0 seconds and enable timer
Program New VCO frequency or enable DFC
System functional check
Disable Timer
Timer continue if system is not able to stop timer
Timeout Flag set and generate RESET pulse
OE Pin Function
OE pins in the 5L35023 have multiple functions. The OE pins can be configured as output enable control (OE) or chip power-down control
(PD#) or Proactive Power Saving function (PPS). Furthermore, the OE pins can be configured as single or two-pin Dynamic Frequency
Control (DFC), or the RESET out function that is associated with the Timer function.
Table 23. OE Pin Functions
Function
Pin
OE1
OE2
OE3
SE Output Enable/Disable
SE1 (default)
SE2 (default)
SE3(default)
DIFF Output Enable/Disable
—
DIFF1/DIFF2
—
Global Power Down (PD#)
PD#
—
—
Proactive Power Saving Input
SE1_PPS
SE2_PPS
SE3_PPS
DOC Control (Only PLL2)
DFC0
—
DFC1
RESET OUT
—
RESET OUT
—
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5L35023 Datasheet
Table 24. OE Pin Function Summary
OE Pin
Description
OE1: SE1
OE1 only control SE1 enable/disable; other outputs are not affected by this pin status.
OE2: SE2
OE2 only control SE2 enable/disable; other outputs are not affected by this pin status.
OE2: SE3
OE3 only control SE3 enable/disable; other outputs are not affected by this pin status.
OE2: DIFF1/DIFF2
OE1: PD#
OE2 control differential outputs 1 and 2 only; other SE outputs are not affected by this pin status.
OE1 control chip global power down (PD#) except 32.768kHz on OE1 (when 32kHz is enabled). When the
PD# pin is active low, the chip goes to lowest power down mode and all outputs are disabled except 32kHz
output and only keep 32kHz/Xtal calibration.
OE1: SE1_PPS
Configure OE1 as SE1_PPS (Proactive Power Saving) function pin.
OE2: SE2_PPS
Configure OE2 as SE2_PPS (Proactive Power Saving) function pin.
OE3: SE3_PPS
Configure OE3 as SE3_PPS (Proactive Power Saving) function pin.
OE1: DFC0
Configure OE1 as DFC0 control pin 0.
OE3/DFC1
Configure OE3 as DFC1 control pin 1.
Table 25. PD# Priority
PD#
I2C_OE_EN_bit
SE1/2/3, DIFF1/DIFF2
Output
Notes
0
x
x
stop
32kHz free run
1
0
x
stop
1
1
0
stop
1
1
1
running
Crystal Input (X1/X2)
The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should be
specified for parallel resonance with 40MHz maximum.
A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. When the oscillator load
capacitance matches the crystal load capacitance, the oscillation frequency will be accurate as 0 PPM. When the oscillator load
capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal. In order to get an accurate
oscillation frequency, the matching the oscillator load capacitance with the crystal load capacitance is required.
To set the oscillator load capacitance, 5L35023 has built-in two programmable tuning capacitors inside the chip, one at XIN and one at
XOUT. They can be adjusted independently. The value of each capacitor is composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[7:0] register. Adjustment of the crystal tuning capacitors allows for maximum flexibility to
accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance with the following
table.
Table 26. Programmable Tuning Caps
Parameter
Bits
Range
Minimum (pF)
Maximum (pF)
Xtal [7:0]
4×2
+1 / +2 / +4 / +8pF
0
15pF
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5L35023 Datasheet
XTAL[4:0] = (XTAL CL - 7pF) *2 (Eq.1)
Equation 1 and the table of XTAL[7:0] tuning capacitor characteristics show that the parallel tuning capacitance can be set between 4.5pF
to 12.5pF with a resolution of 0.25pF.
For a crystal CL = 8pF, where CL is the parallel capacity specified by the crystal vendor that sets the crystal frequency to the nominal
value. Under the assumptions that the stray capacity between the crystal leads on the circuit board is zero and that no external tuning
caps are placed on the crystal leads, then the internal parallel tuning capacity is equal to the load capacity presented to the crystal by the
device.
The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes.
External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency requirements.
The 5L35023 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with analog spread spectrum and PLL2 has digital
spread spectrum.
Spread Spectrum
The 5L35023 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with analog spread spectrum and PLL2 has digital
spread spectrum.
Table 27. Spread Spectrum Generation Specifications
Symbol
Parameter
Description
fOUT
Output Frequency
Output frequency range.
fMOD
Mod Frequency
Modulation frequency.
Spread Value
Amount of spread value
(programmable)–down spread.
Spread% Value
Variation of spread range.
fSPREAD
%tolerance
©2019 Integrated Device Technology, Inc.
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Minimum
Typical
1
Maximum
Units
125
MHz
30 to 63
kHz
-0.5% to -2%
% fOUT
15
%
October 4, 2019
5L35023 Datasheet
Figure 6. Digital Spread Spectrum
N
Fvco
2 * Fout
period
step
Fpfd
2 * Fss
N * SSamount
period
Down spread or Spread off
N = Fvco/Fpfd
Center Spread
N = Nssoff + N × SSamount/2
N: include integer and fraction
Fvco: VCOs frequency
Fpfd: PLLs pfd frequency
Fss: spread modulation rate
SSamount: spread percentage
The black line is for the down spread; N will decrease to make the center frequency is lower than spread off.
The blue line is for the center spread; there is an offset put on divider ratio to make the center frequency keep same as spread off.
Example: 0.5% down spread at 32kHz modulation rate.
Suspend Mode with RTC Clock Only
VersaClock 3S can operate on the following two modes:
▪ Full-power mode:
— Full chip active with the most functionality and all VDDs are connected to power supply.
▪ Low-power Suspend Mode:
— Device power-up with below sequence:
1. VBAT and all other VDDs are powered up. VBAT ramp must be earlier or same time as other VDDs.
2. After full power up is completed, the device can go into Suspend Mode triggered by VBAT is powered and rest of the VDDs ramped down
(ramp down time slower than 3ms).
In Suspend Mode, device will operate with a 2uA core power with only VBAT powered up. Producing 32kHz outputs on SEx outputs (it can
be multiple copies). Operating at this state helps system in power-down, or sleep mode without losing date-time information at a very low
power budget. When system waking up, device will go back to full power mode automatically and produce outputs upon user
configuration.
When there is core power present (VDD18 and VDDA), the device will switch DCO supply to core power to save battery.
©2019 Integrated Device Technology, Inc.
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5L35023 Datasheet
ORT–VCO Overshoot Reduction Technology
The 5L35023 supports the VCO overshoot reduction technology (ORT) to prevent an output clock frequency spike when the device is
changing frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency changes are under control
instead of free-run to targeted frequency.
PLL Features and Descriptions
Table 28. Output 1 Divider
Output Divider bits
Output Divider bits
00
01
10
11
00
1
2
4
8
01
4
8
16
32
10
5
10
20
40
11
6
12
24
48
Table 29. Output 2, 4, and 5 Divider
Output Divider bits
Output Divider bits
00
01
10
11
00
1
2
4
5
01
3
6
12
15
10
5
10
20
25
11
10
20
40
50
Table 30. Output 3 Divider
Output Divider bits
Output Divider bits
00
01
10
11
00
1
2
4
8
01
3
6
12
24
10
5
10
20
40
11
10
20
40
80
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5L35023 Datasheet
Output Clock Test Conditions
Figure 7. LVCMOS Output Test Conditions
33 ohm
2 inches
2pF
LVCMOS
Figure 8. LP-HCSL Output Test Conditions
33 ohm
33 ohm
5 inches
2pF
LPHCSL
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2pF
October 4, 2019
5L35023 Datasheet
General I2C Mode Operations
The device acts as a slave device on the I2C bus using one of the four I2C addresses (0xD0, 0xD2, 0xD4, or 0xD6) to allow multiple
devices to be used in the system. The interface accepts byte-oriented block write and block read operations. Two address bytes specify
the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from
the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer.
During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the
block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-down
resistors have a size of 100kΩ typical.
Figure 9. I2C Slave Read and Write Cycle Sequencing
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
Abar
P
Sequential Read
S
Dev Addr + W
A
Reg start Addr
A
A
Reg start Addr
A
Sr
Dev Addr + R
A
Data 0
Data 1
A
A
Data 1
A
A
Data n
Abar
P
Sequential Write
S
Dev Addr + W
from master to slave
from slave to master
Data 0
A
A
Data n
A
P
S = start
Sr = repeated start
A = acknowledge
Abar = none acknowledge
P = stop
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5L35023 Datasheet
Byte 0: General Control
Byte 00h
Name
Control Function
Type
0
1
PWD
Bit 7
OTP_Burned
OTP memory programming
indication
R/W
OTP memory
non-programmed
OTP memory
programmed
0
Bit 6
I2C_addr[1]
I2C address select bit 1
R/W
Bit 5
I2C_addr[0]
I2C address select bit 0
R/W
Bit 4
PLL1_SSEN
PLL1 Spread Spectrum enable
R/W
disable
enable
0
Bit 3
DIV1_src_sel
Divider 1 source clock select
R/W
PLL1
Xtal
0
Bit 2
PLL3_refin_sel
PLL3 source selection
R/W
Xtal
Seed (DIV2)
0
Bit 1
Bit 0
0
00: D0 / 01: D2
10: D4 / 11: D6
0
Reserved
OTP_protect
0
OTP memory protection
R/W
read/write
write locked
0
Byte 1: Dash Code ID (optional)
Byte 01h
Name
Control Function
Type
0
1
PWD
Bit 7
DashCode ID[7]
Dash code ID
R/W
—
—
0
Bit 6
DashCode ID[6]
Dash code ID
R/W
—
—
0
Bit 5
DashCode ID[5]
Dash code ID
R/W
—
—
0
Bit 4
DashCode ID[4]
Dash code ID
R/W
—
—
0
Bit 3
DashCode ID[3]
Dash code ID
R/W
—
—
0
Bit 2
DashCode ID[2]
Dash code ID
R/W
—
—
0
Bit 1
DashCode ID[1]
Dash code ID
R/W
—
—
0
Bit 0
DashCode ID[0]
Dash code ID
R/W
—
—
0
0
1
PWD
Byte 2: Crystal Cap Setting
Byte 02h
Name
Control Function
Type
Bit 7
Xtal_Cap[7]
Xtal cap load trimming bits
R/W
0
Bit 6
Xtal_Cap[6]
Xtal cap load trimming bits
R/W
0
Bit 5
Xtal_Cap[5]
Xtal cap load trimming bits
R/W
0
Bit 4
Xtal_Cap[4]
Xtal cap load trimming bits
R/W
Bit 3
Xtal_Cap[3]
Xtal cap load trimming bits
R/W
Bit 2
Xtal_Cap[2]
Xtal cap load trimming bits
R/W
0
Bit 1
Xtal_Cap[1]
Xtal cap load trimming bits
R/W
0
Bit 0
Xtal_Cap[0]
Xtal cap load trimming bits
R/W
1
©2019 Integrated Device Technology, Inc.
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x1 x2
x4 x8
total 15pf
1
0
October 4, 2019
5L35023 Datasheet
Byte 3: PLL3 M Divider
Byte 03h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL3_MDIV1
PLL3 source clock divider
R/W
disable M DIV1
bypadd divider (/1)
0
Bit 6
PLL3_MDIV2
PLL3 source clock divider
R/W
disable M DIV2
bypadd divider (/2)
0
Bit 5
PLL3 M_DIV[5]
PLL3 reference integer divider
R/W
3–64
default 25
0
Bit 4
PLL3 M_DIV[4]
PLL3 reference integer divider
R/W
—
—
1
Bit 3
PLL3 M_DIV[3]
PLL3 reference integer divider
R/W
—
—
1
Bit 2
PLL3 M_DIV[2]
PLL3 reference integer divider
R/W
—
—
0
Bit 1
PLL3 M_DIV[1]
PLL3 reference integer divider
R/W
—
—
0
Bit 0
PLL3 M_DIV[0]
PLL3 reference integer divider
R/W
—
—
1
Byte 4: PLL3 N Divider
Byte 04h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL3 N_DIV[7]
PLL3 VCO feedback integer divider bit7
R/W
1
Bit 6
PLL3 N_DIV[6]
PLL3 VCO feedback integer divider bit6
R/W
1
Bit 5
PLL3 N_DIV[5]
PLL3 VCO feedback integer divider bit5
R/W
1
Bit 4
PLL3 N_DIV[4]
PLL3 VCO feedback integer divider bit4
R/W
Bit 3
PLL3 N_DIV[3]
PLL3 VCO feedback integer divider bit3
R/W
Bit 2
PLL3 N_DIV[2]
PLL3 VCO feedback integer divider bit2
R/W
0
Bit 1
PLL3 N_DIV[1]
PLL3 VCO feedback integer divider bit1
R/W
0
Bit 0
PLL3 N_DIV[0]
PLL3 VCO feedback integer divider bit0
R/W
0
12–2048, default VCO setting is
480MHz
0
0
Byte 5: PLL3 Loop Filter Setting and N Divider 10:8
Byte 05h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL3_R100K
PLL3 Loop filter resister 100kohm
R/W
bypass
plus 100kohm
0
Bit 6
PLL3_R50K
PLL3 Loop filter resister 50kohm
R/W
bypass
plus 50kohm
0
Bit 5
PLL3_R25K
PLL3 Loop filter resister 25kohm
R/W
bypass
plus 25kohm
0
Bit 4
PLL3_R12.5K
PLL3 Loop filter resister 12.5kohm
R/W
bypass
plus 12.5kohm
1
Bit 3
PLL3_R6K
PLL3 Loop filter resister 6kohm
R/W
bypass
only 6kohm
applied
0
Bit 2
PLL3 N_DIV[10]
PLL3 VCO feedback integer divider bit10
R/W
Bit 1
PLL3 N_DIV[9]
PLL3 VCO feedback integer divider bit9
R/W
Bit 0
PLL3 N_DIV[8]
PLL3 VCO feedback integer divider bit8
R/W
©2019 Integrated Device Technology, Inc.
24
0
12–2048, default VCO setting is
480MHz
0
1
October 4, 2019
5L35023 Datasheet
Byte 6: PLL3 Charge Pump Control
Byte 06h
Name
Control Function
Type
0
1
PWD
Bit 7
OUTDIV 3 Source
Output divider 3 source clock selection
R/W
PLL2
PLL3
0
Bit 6
PLL3_CP_8X
PLL3 charge pump control
R/W
—
x8
1
Bit 5
PLL3_CP_4X
PLL3 charge pump control
R/W
—
x4
1
Bit 4
PLL3_CP_2X
PLL3 charge pump control
R/W
—
x2
0
Bit 3
PLL3_CP_1X
PLL3 charge pump control
R/W
—
x1
1
Bit 2
PLL3_CP_/24
PLL3 charge pump control
R/W
—
/24
1
Bit 1
PLL3_CP_/3
PLL3 charge pump control
R/W
—
/3
0
Bit 0
PLL3_SIREF
PLL3 SiRef current selection
R/W
10μA
20μA
0
Formula: (iRef (10μA) × (1 + SIREF) × (1 × 1X + 2 × 2X + 4 × 4X + 8 × 8X + 16 × 16X))/((24 × /24) + (3 × /3))
Byte 7: PLL1 Control and OUTDIV5 Divider
Byte 07h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_MDIV_Doubler
PLL1 reference clock doubler
R/W
disable
enable
0
Bit 6
PLL1_SIREF
PLL1 SiRef current selection
R/W
10.8μA
21.6μA
0
Bit 5
PLL1_EN_CH2
PLL1 output Channel 2 control
R/W
disable
enable
1
Bit 4
PLL1_EN_3rdpole
PLL1 3rd Pole control
R/W
disable
enable
0
Bit 3
OUTDIV5[3]
Output divider5 control bit 3
R/W
—
—
0
Bit 2
OUTDIV5[2]
Output divider5 control bit 2
R/W
—
—
0
Bit 1
OUTDIV5[1]
Output divider5 control bit 1
R/W
—
—
1
Bit 0
OUTDIV5[0]
Output divider5 control bit 0
R/W
—
—
1
Byte 8: PLL1 M Divider
Byte 08h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_MDIV1
PLL3 VCO reference clock divider 1
R/W
disable M DIV1
bypass divider (/1)
0
Bit 6
PLL1_MDIV2
PLL3 VCO reference clock divider 2
R/W
disable M DIV2
bypass divider (/2)
0
Bit 5
PLL1 M_DIV[5]
PLL1 reference clock divider control bit 5
R/W
0
Bit 4
PLL1 M_DIV[4]
PLL1 reference clock divider control bit 4
R/W
1
Bit 3
PLL1 M_DIV[3]
PLL1 reference clock divider control bit 3
R/W
Bit 2
PLL1 M_DIV[2]
PLL1 reference clock divider control bit 2
R/W
Bit 1
PLL1 M_DIV[1]
PLL1 reference clock divider control bit 1
R/W
0
Bit 0
PLL1 M_DIV[0]
PLL1 reference clock divider control bit 0
R/W
1
©2019 Integrated Device Technology, Inc.
25
3–64, default is 25
1
0
October 4, 2019
5L35023 Datasheet
Byte 9: PLL1 VCO N Divider
Byte 09h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1 N_DIV[7]
PLL1 VCO feedback divider control bit 7
R/W
0
Bit 6
PLL1 N_DIV[6]
PLL1 VCO feedback divider control bit 6
R/W
1
Bit 5
PLL1 N_DIV[5]
PLL1 VCO feedback divider control bit 5
R/W
0
Bit 4
PLL1 N_DIV[4]
PLL1 VCO feedback divider control bit 4
R/W
Bit 3
PLL1 N_DIV[3]
PLL1 VCO feedback divider control bit 3
R/W
Bit 2
PLL1 N_DIV[2]
PLL1 VCO feedback divider control bit 2
R/W
0
Bit 1
PLL1 N_DIV[1]
PLL1 VCO feedback divider control bit 1
R/W
0
Bit 0
PLL1 N_DIV[0]
PLL1 VCO feedback divider control bit 0
R/W
0
1
12–2048, default is 600
1
Byte 10: PLL Loop Filter and N Divider
Byte 0Ah
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_R100K
PLL1 Loop filter resister 100kohm
R/W
bypass
plus 100kohm
1
Bit 6
PLL1_R50K
PLL1 Loop filter resister 50kohm
R/W
bypass
plus 50kohm
0
Bit 5
PLL1_R25K
PLL1 Loop filter resister 25kohm
R/W
bypass
plus 25kohm
1
Bit 4
PLL1_R12.5K
PLL1 Loop filter resister 12.5kohm
R/W
bypass
plus 12.5kohm
1
Bit 3
PLL1_R1.0K
PLL1 Loop filter resister 1kohm
R/W
bypass
only 1.0kohm applied
0
Bit 2
PLL1 N_DIV[10]
PLL1 VCO feedback integer divider bit10
R/W
Bit 1
PLL1 N_DIV[9]
PLL1 VCO feedback integer divider bit9
R/W
Bit 0
PLL1 N_DIV[8]
PLL1 VCO feedback integer divider bit8
R/W
0
12–2048, default is 600
1
0
Byte 11: PLL1 Charge Pump
Byte 0Bh
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_CP_32X
PLL1 charge pump control
R/W
—
x32
0
Bit 6
PLL1_CP_16X
PLL1 charge pump control
R/W
—
x16
0
Bit 5
PLL1_CP_8X
PLL1 charge pump control
R/W
—
x8
0
Bit 4
PLL1_CP_4X
PLL1 charge pump control
R/W
—
x4
0
Bit 3
PLL1_CP_2X
PLL1 charge pump control
R/W
—
x2
0
Bit 2
PLL1_CP_1X
PLL1 charge pump control
R/W
—
x1
1
Bit 1
PLL1_CP_/24
PLL1 charge pump control
R/W
—
/24
1
Bit 0
PLL1_CP_/3
PLL1 charge pump control
R/W
—
/3
0
©2019 Integrated Device Technology, Inc.
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5L35023 Datasheet
Byte 12: PLL1 Spread Spectrum Control
Byte 0Ch
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_SS_REFDIV23
PLL1 Spread Spectrum control - Ref divider 23
R/W
—
—
0
Bit 6
PLL1_SS_REFDIV[6]
PLL1 Spread Spectrum control - Ref divider 6
R/W
—
—
0
Bit 5
PLL1_SS_REFDIV[5]
PLL1 Spread Spectrum control - Ref divider 5
R/W
—
—
0
Bit 4
PLL1_SS_REFDIV[4]
PLL1 Spread Spectrum control - Ref divider 4
R/W
—
—
0
Bit 3
PLL1_SS_REFDIV[3]
PLL1 Spread Spectrum control - Ref divider 3
R/W
—
—
0
Bit 2
PLL1_SS_REFDIV[2]
PLL1 Spread Spectrum control - Ref divider 2
R/W
—
—
0
Bit 1
PLL1_SS_REFDIV[1]
PLL1 Spread Spectrum control - Ref divider 1
R/W
—
—
0
Bit 0
PLL1_SS_REFDIV[0]
PLL1 Spread Spectrum control - Ref divider 0
R/W
—
—
0
Byte 13: PLL1 Spread Spectrum Control
Byte 0Dh
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_SS_FBDIV[15]
PLL1 Spread Spectrum - feedback divider 15
R/W
—
—
0
Bit 6
PLL1_SS_FBDIV[14]
PLL1 Spread Spectrum - feedback divider 14
R/W
—
—
0
Bit 5
PLL1_SS_FBDIV[13]
PLL1 Spread Spectrum - feedback divider 13
R/W
—
—
0
Bit 4
PLL1_SS_FBDIV[12]
PLL1 Spread Spectrum - feedback divider 12
R/W
—
—
0
Bit 3
PLL1_SS_FBDIV[11]
PLL1 Spread Spectrum - feedback divider 11
R/W
—
—
0
Bit 2
PLL1_SS_FBDIV[10]
PLL1 Spread Spectrum - feedback divider 10
R/W
—
—
0
Bit 1
PLL1_SS_FBDIV[9]
PLL1 Spread Spectrum - feedback divider 9
R/W
—
—
0
Bit 0
PLL1_SS_FBDIV[8]
PLL1 Spread Spectrum - feedback divider 8
R/W
—
—
0
Byte 14: PLL1 Spread Spectrum Control
Byte 0Eh
Name
Control Function
Type
0
1
PWD
Bit 7
PLL1_SS_FBDIV[7]
PLL1 Spread Spectrum - feedback divider 7
R/W
—
—
0
Bit 6
PLL1_SS_FBDIV[6]
PLL1 Spread Spectrum - feedback divider 6
R/W
—
—
0
Bit 5
PLL1_SS_FBDIV[5]
PLL1 Spread Spectrum - feedback divider 5
R/W
—
—
0
Bit 4
PLL1_SS_FBDIV[4]
PLL1 Spread Spectrum - feedback divider 4
R/W
—
—
0
Bit 3
PLL1_SS_FBDIV[3]
PLL1 Spread Spectrum - feedback divider 3
R/W
—
—
0
Bit 2
PLL1_SS_FBDIV[2]
PLL1 Spread Spectrum - feedback divider 2
R/W
—
—
0
Bit 1
PLL1_SS_FBDIV[1]
PLL1 Spread Spectrum - feedback divider 1
R/W
—
—
0
Bit 0
PLL1_SS_FBDIV[0]
PLL1 Spread Spectrum - feedback divider 0
R/W
—
—
0
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
Byte 15: Output Divider1 Control
Byte 0Fh
Name
Control Function
Type
0
1
PWD
Bit 7
OUTDIV1[3]
Output divider1 control bit 3
R/W
—
—
0
Bit 6
OUTDIV1[2]
Output divider1 control bit 2
R/W
—
—
0
Bit 5
OUTDIV1[1]
Output divider1 control bit 1
R/W
—
—
1
Bit 4
OUTDIV1[0]
Output divider1 control bit 0
R/W
—
—
1
Bit 3
OUTDIV2[3]
Output divider2 control bit 3
R/W
—
—
0
Bit 2
OUTDIV2[2]
Output divider2 control bit 2
R/W
—
—
0
Bit 1
OUTDIV2[1]
Output divider2 control bit 1
R/W
—
—
1
Bit 0
OUTDIV2[0]
Output divider2 control bit 0
R/W
—
—
1
Control Function
Type
0
1
PWD
Byte 16: PLL2 Integer Feedback Divide
Byte 10h
Name
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
PLL2_FB_INT[10]
PLL2 feedback integer divider 10
R/W
—
—
0
Bit 1
PLL2_FB_INT[9]
PLL2 feedback integer divider 9
R/W
—
—
0
Bit 0
PLL2_FB_INT[8]
PLL2 feedback integer divider 8
R/W
—
—
0
Byte 17: PLL2 Integer Feedback Divider
Byte 11h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_FB_INT_DIV[7]
PLL2 feedback integer divider 7
R/W
—
—
0
Bit 6
PLL2_FB_INT_DIV[6]
PLL2 feedback integer divider 6
R/W
—
—
0
Bit 5
PLL2_FB_INT_DIV[5]
PLL2 feedback integer divider 5
R/W
—
—
1
Bit 4
PLL2_FB_INT_DIV[4]
PLL2 feedback integer divider 4
R/W
—
—
1
Bit 3
PLL2_FB_INT_DIV[3]
PLL2 feedback integer divider 3
R/W
—
—
1
Bit 2
PLL2_FB_INT_DIV[2]
PLL2 feedback integer divider 2
R/W
—
—
1
Bit 1
PLL2_FB_INT_DIV[1]
PLL2 feedback integer divider 1
R/W
—
—
0
Bit 0
PLL2_FB_INT_DIV[0]
PLL2 feedback integer divider 0
R/W
—
—
0
©2019 Integrated Device Technology, Inc.
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5L35023 Datasheet
Byte 18: PLL2 Fractional Feedback Divider
Byte 12h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_FB_FRC_DIV[15]
PLL2 feedback fractional divider 15
R/W
—
—
0
Bit 6
PLL2_FB_FRC_DIV[14]
PLL2 feedback fractional divider 14
R/W
—
—
0
Bit 5
PLL2_FB_FRC_DIV[13]
PLL2 feedback fractional divider 13
R/W
—
—
0
Bit 4
PLL2_FB_FRC_DIV[12]
PLL2 feedback fractional divider 12
R/W
—
—
0
Bit 3
PLL2_FB_FRC_DIV[11]
PLL2 feedback fractional divider 11
R/W
—
—
0
Bit 2
PLL2_FB_FRC_DIV[10]
PLL2 feedback fractional divider 10
R/W
—
—
0
Bit 1
PLL2_FB_FRC_DIV[9]
PLL2 feedback fractional divider 9
R/W
—
—
0
Bit 0
PLL2_FB_FRC_DIV[8]
PLL2 feedback fractional divider 8
R/W
—
—
0
Byte 19: PLL2 Fractional Feedback Divider
Byte 13h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_FB_FRC_DIV[7]
PLL2 feedback fractional divider 7
R/W
—
—
0
Bit 6
PLL2_FB_FRC_DIV[6]
PLL2 feedback fractional divider 6
R/W
—
—
0
Bit 5
PLL2_FB_FRC_DIV[5]
PLL2 feedback fractional divider 5
R/W
—
—
0
Bit 4
PLL2_FB_FRC_DIV[4]
PLL2 feedback fractional divider 4
R/W
—
—
0
Bit 3
PLL2_FB_FRC_DIV[3]
PLL2 feedback fractional divider 3
R/W
—
—
0
Bit 2
PLL2_FB_FRC_DIV[2]
PLL2 feedback fractional divider 2
R/W
—
—
0
Bit 1
PLL2_FB_FRC_DIV[1]
PLL2 feedback fractional divider 1
R/W
—
—
0
Bit 0
PLL2_FB_FRC_DIV[0]
PLL2 feedback fractional divider 0
R/W
—
—
0
Byte 20: PLL2 Spread Spectrum Control
Byte 14h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_STEP[7]
PLL2 spread step size control bit 7
R/W
—
—
0
Bit 6
PLL2_STEP[6]
PLL2 spread step size control bit 6
R/W
—
—
0
Bit 5
PLL2_STEP[5]
PLL2 spread step size control bit 5
R/W
—
—
0
Bit 4
PLL2_STEP[4]
PLL2 spread step size control bit 4
R/W
—
—
0
Bit 3
PLL2_STEP[3]
PLL2 spread step size control bit 3
R/W
—
—
0
Bit 2
PLL2_STEP[2]
PLL2 spread step size control bit 2
R/W
—
—
0
Bit 1
PLL2_STEP[1]
PLL2 spread step size control bit 1
R/W
—
—
0
Bit 0
PLL2_STEP[0]
PLL2 spread step size control bit 0
R/W
—
—
0
©2019 Integrated Device Technology, Inc.
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5L35023 Datasheet
Byte 21: PLL2 Spread Spectrum Control
Byte 15h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_STEP_DELTA[7]
PLL2 spread step size control delta bit 7
R/W
—
—
0
Bit 6
PLL2_STEP_DELTA[6]
PLL2 spread step size control delta bit 6
R/W
—
—
0
Bit 5
PLL2_STEP_DELTA[5]
PLL2 spread step size control delta bit 5
R/W
—
—
0
Bit 4
PLL2_STEP_DELTA[4]
PLL2 spread step size control delta bit 4
R/W
—
—
0
Bit 3
PLL2_STEP_DELTA[3]
PLL2 spread step size control delta bit 3
R/W
—
—
0
Bit 2
PLL2_STEP_DELTA[2]
PLL2 spread step size control delta bit 2
R/W
—
—
0
Bit 1
PLL2_STEP_DELTA[1]
PLL2 spread step size control delta bit 1
R/W
—
—
0
Bit 0
PLL2_STEP_DELTA[0]
PLL2 spread step size control delta bit 0
R/W
—
—
0
Byte 22: PLL2 Spread Spectrum Control
Byte 16h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_STEP[15]
PLL2 spread step size control bit 15
R/W
—
—
0
Bit 6
PLL2_STEP[14]
PLL2 spread step size control bit 14
R/W
—
—
0
Bit 5
PLL2_STEP[13]
PLL2 spread step size control bit 13
R/W
—
—
0
Bit 4
PLL2_STEP[12]
PLL2 spread step size control bit 12
R/W
—
—
0
Bit 3
PLL2_STEP[11]
PLL2 spread step size control bit 11
R/W
—
—
0
Bit 2
PLL2_STEP[10]
PLL2 spread step size control bit 10
R/W
—
—
0
Bit 1
PLL2_STEP[9]
PLL2 spread step size control bit 9
R/W
—
—
0
Bit 0
PLL2_STEP[8]
PLL2 spread step size control bit 8
R/W
—
—
0
Byte 23: PLL2 Period Control
Byte 17h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_PERIOD[7]
PLL2 period control bit 7
R/W
—
—
0
Bit 6
PLL2_PERIOD[6]
PLL2 period control bit 6
R/W
—
—
0
Bit 5
PLL2_PERIOD[5]
PLL2 period control bit 5
R/W
—
—
0
Bit 4
PLL2_PERIOD[4]
PLL2 period control bit 4
R/W
—
—
0
Bit 3
PLL2_PERIOD[3]
PLL2 period control bit 3
R/W
—
—
0
Bit 2
PLL2_PERIOD[2]
PLL2 period control bit 2
R/W
—
—
0
Bit 1
PLL2_PERIOD[1]
PLL2 period control bit 1
R/W
—
—
0
Bit 0
PLL2_PERIOD[0]
PLL2 period control bit 0
R/W
—
—
0
©2019 Integrated Device Technology, Inc.
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5L35023 Datasheet
Byte 24: PLL2 Control Register
Byte 18h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_PERIOD[9]
PLL2 period control bit 9
R/W
—
—
0
Bit 6
PLL2_PERIOD[8]
PLL2 period control bit 8
R/W
—
—
0
Bit 5
PLL2_SSEN
PLL2 spread spectrum enable
R/W
disable
enable
0
Bit 4
PLL2_R100K
PLL2 Loop filter resister 100kohm
—
bypass
plus 100kohm
0
Bit 3
PLL2_R50K
PLL2 Loop filter resister 50kohm
—
bypass
plus 50kohm
1
Bit 2
PLL2_R25K
PLL2 Loop filter resister 25kohm
—
bypass
plus 25kohm
1
Bit 1
PLL2_R12.5K
PLL2 Loop filter resister 12.5kohm
—
bypass
plus 12.5kohm
1
Bit 0
PLL2_R6K
PLL2 Loop filter resister 6kohm
—
bypass
only 6kohm applied
0
Byte 25: PLL2 Charge Pump Control
Byte 19h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_CP_16X
PLL2 charge pump control
R/W
—
x16
0
Bit 6
PLL2_CP_8X
PLL2 charge pump control
R/W
—
x8
0
Bit 5
PLL2_CP_4X
PLL2 charge pump control
R/W
—
x4
0
Bit 4
PLL2_CP_2X
PLL2 charge pump control
R/W
—
x2
1
Bit 3
PLL2_CP_1X
PLL2 charge pump control
R/W
—
x1
0
Bit 2
PLL2_CP_/24
PLL2 charge pump control
R/W
—
/24
1
Bit 1
PLL2_CP_/3
PLL2 charge pump control
R/W
—
/3
0
Bit 0
PLL2_SIREF
PLL2 SiRef current selection
R/W
10μA
20μA
0
Byte 26: PLL2 M Divider Setting
Byte 1Ah
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_MDIV_Doubler
PLL2 reference divider - doubler
R/W
disable
enable
0
Bit 6
PLL2_MDIV1
PLL2 reference divider 1
R/W
disable M DIV1
bypadd divider (/1)
0
Bit 5
PLL2_MDIV2
PLL2 reference divider 2
R/W
disable M DIV2
bypadd divider (/2)
0
Bit 4
PLL2_MDIV[4]
PLL2 reference divider control bit 4
R/W
1
Bit 3
PLL2_MDIV[3]
PLL2 reference divider control bit 3
R/W
1
Bit 2
PLL2_MDIV[2]
PLL2 reference divider control bit 2
R/W
Bit 1
PLL2_MDIV[1]
PLL2 reference divider control bit 1
R/W
0
Bit 0
PLL2_MDIV[0]
PLL2 reference divider control bit 0
R/W
1
©2019 Integrated Device Technology, Inc.
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3–64, default is 25
0
October 4, 2019
5L35023 Datasheet
Byte 27: Output Divider 4
Byte 1Bh
Name
Control Function
Type
0
1
PWD
Bit 7
OUTDIV3[3]
Out divider 4 control bit 7
R/W
—
—
0
Bit 6
OUTDIV3[2]
Out divider 4 control bit 6
R/W
—
—
1
Bit 5
OUTDIV3[1]
Out divider 4 control bit 5
R/W
—
—
0
Bit 4
OUTDIV3[0]
Out divider 4 control bit 4
R/W
—
—
0
Bit 3
OUTDIV4[3]
Out divider 4 control bit 3
R/W
—
—
0
Bit 2
OUTDIV4[2]
Out divider 4 control bit 2
R/W
—
—
0
Bit 1
OUTDIV4[1]
Out divider 4 control bit 1
R/W
—
—
1
Bit 0
OUTDIV4[0]
Out divider 4 control bit 0
R/W
—
—
1
Byte 28: PLL Operation Control Register
Byte 1Ch
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_HRS_EN
PLL2 spread high resolution selection enable
R/W
normal
enable (shift 4 bits)
0
Bit 6
PLL2_refin_sel
PLL2 reference clock source select
R/W
Xtal
DIV2
0
Bit 5
PLL3_PDB
PLL3 Power Down
R/W
Power Down
running
1
Bit 4
PLL3_LCKBYPSSB
PLL3 lock bypass
R/W
bypass lock
lock
1
Bit 3
PLL2_PDB
PLL2 Power Down
R/W
Power Down
running
1
Bit 2
PLL2_LCKBYPSSB
PLL2 lock bypass
R/W
bypass lock
lock
1
Bit 1
PLL1_PDB
PLL1 Power Down
R/W
Power Down
running
1
Bit 0
PLL1_LCKBYPSSB
PLL1 lock bypass
R/W
bypass lock
lock
1
0
1
PWD
Byte 29: Output Control
Byte 1Dh
Name
Control Function
Bit 7
DIFF1_SEL
Differential clock 1 output OE2 control
not controlled
controlled
0
Bit 6
DIFF2_SEL
Differential clock 2 output OE2 control
not controlled
controlled
0
Bit 5
DIFF1_EN
Differential clock 1 output enable
R/W
disable
enable
1
Bit 4
DIFF2_EN
Differential clock 2 output enable
R/W
disable
enable
1
Bit 3
OUTDIV4_Source
Output divider 4 source clock selection
R/W
PLL2
Xtal
0
Bit 2
SE1_SLEW
SE 1 slew rate control
R/W
normal
strong
0
Bit 1
VDD1_SEL[1]
VDD1 level control bit 1
R/W
Bit 0
VDD1_SEL[0]
VDD1 level control bit 0
R/W
©2019 Integrated Device Technology, Inc.
32
Type
11: 1.8
0
0
October 4, 2019
5L35023 Datasheet
Byte 30: OE and DFC Control
Byte 1Eh
Name
Control Function
Type
0
1
PWD
Bit 7
SE1_EN
SE1 output enable control
R/W
disable
enable
1
Bit 6
OE1_fun_sel[1]
OE1 pin function selection bit 1
R/W
OE1_fun_sel[0]
OE1 pin function selection bit 0
R/W
10: SE1_PPS
00: SE1 OE
0
Bit 5
11:DFC0
01: PD#
0
Bit 4
* SE3_EN
SE3 output enable
R/W
disable
enable
1
Bit 3
* OE3_fun_sel[1]
OE3 pin function selection bit 1
R/W
Bit 2
* OE3_fun_sel[0]
OE3 pin function selection bit 0
R/W
Bit 1
* DFC_SW_Sel[1]
DFC frequency select bit 1
R/W
Bit 0
* DFC_SW_Sel[0]
DFC frequency select bit 0
R/W
Type
11: DFC1 10: SE3_PPS
01:xx
00:SE3_OE
00: N0 01: N1 10:N2 11:N3
0
0
0
0
Byte 31: Control Register
Byte 1Fh
Name
Control Function
Bit 7
* SE2_CLKSEL1
SE2 source clock selection
Bit 6
* VDD2_SEL[1]
VDD2 level control bit 1
R/W
Bit 5
* VDD2_SEL[0]
VDD2 level control bit 0
R/W
Bit 4
* SE2_SLEW
SE 2 slew rate control
R/W
Bit 3
PLL2_3rd_EN_CFG
PLL2 3rd order control
Bit 2
PLL2_EN_CH2
PLL2 channel 2 enable control
Bit 1
PLL2_EN_3rdpole
PLL2 3rd Pole control
Bit 0
* SE2_CLKSEL1
SE2 source clock selection
0
1
PWD
DIV5
DIV4
1
0
11: 1.8
0
normal
strong
0
1st order
3rd order
0
R/W
disable
enable
1
R/W
disable
enable
0
DIV5
DIV4
0
Byte 32: Control Register
Byte 20h
Name
Control Function
Type
0
1
PWD
Bit 7
* SE2_EN
SE2 output enable
R/W
disable
enable
1
Bit 6
* OE2_fun_sel[1]
OE2 pin function selection bit 1
R/W
Bit 5
* OE2_fun_sel[0]
OE2 pin function selection bit 0
R/W
Bit 4
DFC_EN
DFC function control
R/W
disable
enable
0
Bit 3
WD_EN
WatchDog timer control
R/W
disable
enable
0
Bit 2
Timer_sel
Watchdog timer select bit 1
R/W
Bit 1
Timer_sel
Watchdog timer select bit 0
R/W
Bit 0
Alarm_Flag
Alarm Status (Read Only)
R
©2019 Integrated Device Technology, Inc.
33
11: RESET 10: SE2_PPS
01: DIFF1/2 OE 00: SE2 OE
00: 250ms 01: 500ms
10: 2s 11: 4s
No alarm
Alarmed
0
0
0
0
0
October 4, 2019
5L35023 Datasheet
Byte 33: SE3 and DIFF1 Control Register
Byte 21h
Name
Control Function
Type
0
1
PWD
Bit 7
* SE3_Freerun_32K
SE3 32K free run
R/W
freerun 32K
DIV2 or DIV4
selected by
B33bit6
1
Bit 6
* SE3_CLKSEL1
SE3 source clock selection
R/W
DIV2
DIV4
0
Bit 5
* VDD3_SEL[1]
VDD3 level control bit 1
R/W
Bit 4
* VDD3_SEL[0]
VDD3 level control bit 0
R/W
Bit 3
* SE3_SLEW
SE 3 slew rate control
R/W
normal
strong
0
Bit 2
DIFF_PDBHiZEN
Differential output high-Z at power down
R/W
TBD
output tri-state,
bias off
0
Bit 1
DIFF1_CMOS2_FLIP
Differential 1/2 LVCMOS output control
R/W
DIFF1_B inverted
DIFF1_B
non-inverted
0
Bit 0
DIFF2_CMOS2_FLIP
Differential 1/2 LVCMOS output control
R/W
DIFF2_B inverted
DIFF2_B
non-inverted
0
0
11: 1.8V
0
Byte 34: DIFF1 Control Register
Byte 22h
Name
Control Function
Type
0
1
PWD
Bit 7
DIFF1_CLK_SEL
Differential clock 1 source selection
R/W
DIV1
DIV3
1
Reserved
Bit 6
1
Bit 5
DIFF1_OUTPUT_TYPE[1]
Differential clock 1 type select bit 1
R/W
Bit 4
DIFF1_OUTPUT_TYPE[0]
Differential clock 1 type select bit 0
R/W
00: LVMOS 01: Reserved
10: Reserved 11: LPHCSL
1
1
Bit 3
Reserved
0
Bit 2
Reserved
1
Bit 1
DIFF1_CMOS_SLEW
Differential clock 1 LVCMOS slew
rate control
R/W
normal
strong
0
Bit 0
D1FF1_CMOS2_EN
Differential clock 1 LVCMOS
output_B control
R/W
disable
enable
0
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
Byte 35: DIFF2 Control Register
Byte 23h
Name
Control Function
Type
0
1
PWD
Bit 7
DIFF2_CLK_SEL
Differential clock 2 source selection
R/W
DIV1
DIV3
0
Reserved
Bit 6
1
Bit 5
DIFF2_OUTPUT_TYPE[1]
Differential clock 2 type select bit 1
R/W
Bit 4
DIFF2_OUTPUT_TYPE[0]
Differential clock 2 type select bit 0
R/W
00: LVMOS 01: Reserved
10: Reserved 11: LPHCSL
1
1
Bit 3
Reserved
0
Bit 2
Reserved
0
Bit 1
DIFF2_CMOS_SLEW
Differential clock 2 LVCMOS slew
rate control
R/W
normal
strong
0
Bit 0
DIFF2_CMOS2_EN
Differential clock 2 LVCMOS
output_B control
R/W
disable
enable
0
Byte 36: SE1 and DIV4 control
Byte 24h
Name
Control Function
Type
0
1
PWD
Bit 7
I2C_PDB
chip power down control bit
R/W
power down
normal
1
Bit 6
Ref_free_run
Reference clock output (SE2/SE3)
R/W
stop
freerun
0
Bit 5
free_run_output_config
SE clocks free run control
R/W
SE2 free run
SE2/3 free run
0
Bit 4
SE1_Freerun_32K
SE1 clock output default
R/W
32k freerun
B36bit3 control
0
Bit 3
SE1_CLKSEL1
SEL1 output select
R/W
DIV5
DIV4
1
Bit 2
REF_EN
REF output enable
R/W
disable
enable
1
Bit 1
DIV4_CH3_EN
DIV4 channel 3 output control
R/W
disable
enable
0
Bit 0
DIV4_CH2_EN
DIV4 channel 3 output control
R/W
disable
enable
0
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-090-mm-body050mm-pitchepad-245-x-245-mm-nlg24p1
Marking Diagrams
L5023
-000
YWW**$
L023B
-000
YWW**$
L5023
-ddd
YWW**$
L023B
-ddd
YWW**$
▪ Line 1 is the truncated part number.
▪ “-000” denotes un-programmed part. Configuration left blank for user
customization.
▪ “-ddd” denotes the dash code.
▪ “YWW” is the last digit of the year and week that the part was assembled.
▪ “**” denotes sequential lot number.
▪ “$” denotes mark code.
Ordering Information
Orderable Part Number
Package
Carrier Type
Temperature
5L35023-000NLGI
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Trays
-40° to +85°C
5L35023-000NLGI8
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Tape and Reel
-40° to +85°C
5L35023-dddNLGI
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Trays
-40° to +85°C
5L35023-dddNLGI8
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Tape and Reel
-40° to +85°C
5L35023B-000NLGI
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Trays
-40° to +85°C
5L35023B-000NLGI8
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Tape and Reel
-40° to +85°C
5L35023B-dddNLGI
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Trays
-40° to +85°C
5L35023B-dddNLGI8
4 x 4 mm, 0.5mm pitch 24-VFQFPN
Tape and Reel
-40° to +85°C
©2019 Integrated Device Technology, Inc.
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October 4, 2019
5L35023 Datasheet
Revision History
Revision Date
October 4, 2019
Description of Change
Removed comment “VBAT power ramp-up should be same or earlier time than other VDD power rail.” from
Power Group table.
September 26, 2019
▪
▪
▪
▪
▪
▪
November 29, 2017
Updated I2C section.
Updated Supply Voltage values in Absolute Maximum Ratings table.
Added FIN parameter/values to Recommended Operating Conditions table.
Updated fVCO3 VCO Frequency Range of PLL3 in AC Timing Electrical Characteristics table.
Updated VMAX values in Electrical Characteristics - LPHCSL Differential Outputs table.
Updated PPS Assertion/Deassertion Timing diagram.
Added “B” revision orderable part numbers and marking diagrams.
July 13, 2017
Corrected typo in block diagram.
June 29, 2017
Initial release.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
©2019 Integrated Device Technology, Inc.
37
October 4, 2019
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 1
© Integrated Device Technology, Inc.
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
Sept 9, 2016
Rev 01
Sept 13, 2018
Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN
Add Chamfer on Epad
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