DATASHEET
VERSACLOCK® LOW POWER CLOCK GENERATOR
IDT5P49EE502
Description
Features
The IDT5P49EE502 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to five differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal.
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I2C EEPROM master interface
• FAST (400kHz) mode I2C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
The IDT5P49EE502 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
• Output Frequency Ranges: kHz to 120 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
spectrum mode.
2 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
• 1.8V VDD Core Voltage
• Available in 20pin 3x3mm QFN packages
• -40 to +85 C Industrial Temp operation
There are total five 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
•
•
•
•
•
•
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Functional Block Diagram
VDD
VDDO1
VDDO2
S
R
C
0
/ DIV0
OUT0
S
R
C
1
/DIV1
OUT1
S
R
C
2
/DIV2
OUT2
/DIV3
OUT3
/DIV4
OUT4
XIN/ REF
PLLA
XOUT
PLLB(SS)
SDA
SCL
Control
Logic
SEL
S
R
C
3
PLLC
S
R
C
4
PLLD
GND
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XOUT
OUT4
GND
VDD
VDDO2
SDA
Pin Assignment
16
1
XIN/REF
SCLK
GND
GND
SEL1
OUT3
11
OUT1
OUT2
6
VDD
VDDx
VDDO1
GND
SEL0
OUT0
20- pin QFN
Pin Descriptions
Pin Name
Pin #
I/O
Pin Type
Pin Description
XOUT
1
O
LVTTL
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
XIN/ REF
2
I
LVTTL
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum clock input voltage is 1.8V.
GND
3
Power
Connect to Ground.
OUT3
4
O
OUTPUT
SEL0*
5
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
VDD
6
Power
Device power supply. Connect to 1.8V.
VDDx
7
Power
Device power supply. Connect to 1.8V.
VDDO1
8
Power
Device power supply. Connect to 1.8 to 3.3V. VDDO1 must be
the highest voltage on the device. Using register settings, select
output voltage levels for OUT0-OUT3.
GND
9
Power
Connect to Ground.
OUT2
10
O
Adjustable
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
OUT1
11
O
Adjustable
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
SEL1*
12
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
GND
13
Power
Connect to Ground.
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Buffered reference clock output. Single-ended output voltage
levels are register controlled by either VDDO1 or VDDO2.
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VERSACLOCK® LOW POWER CLOCK GENERATOR
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I2C clock. Logic levels set by VDDO1. 5V tolerant.
SCLK
14
I
LVTTL
OUT0
15
O
Adjustable
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
OUT4
16
O
Adjustable
Configurable clock output 8. Single-ended output voltage levels
controlled by VDDO2.
SDA
17
I/O
Open Drain Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
VDDO2
18
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4.
VDD
19
Power
Device power supply. Connect to 1.8V.
GND
20
Power
Connect to Ground.
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above. Always
completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
Ideal Power Up Sequence
Ideal Power Down Sequence
1) VDDO must drop first, followed by VDD and VDDx
2) VDD and VDDx must come down within 1ms after VDDO1 comes down
3) VDDO2 must be equal to, or lower than, VDDO1
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2 have approx. same ramp rate
1) VDD and VDDx must come up first, followed by VDDO
2) VDDO1 must come up within 1ms after VDD and VDDX come up
3) VDDO2 must be equal to, or lower than, VDDO1
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2 have approx. same ramp rate
V
V
VDDO1
VDDO1
VDD, VDDx
VDDO2, VDDO3
VDDO2, VDDO3
VDD, VDDx
1 ms
1 ms
t
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
PLL Features and Descriptions
VCO
D
M
XDIV
PLL Block Diagram
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
Feedback
(M) Values
PLLA
1 - 255
1 or 4
6 - 2047
Yes
No
PLLB
1 - 255
4
6 - 2047
Yes
Yes
PLLC
1 - 255
1 or 8 bit divide
6 - 2047
Yes
No
PLLD
1 - 255
1 or 4
6 - 2047
Yes
No
Crystal Input (XIN/REF)
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50 maximum equivalent series resonance. 0
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
ONXTALB=0 bit needs to be set for XIN/REF.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
XDIV*M
FOUT = FIN * (
)
D (Eq. 2)
ODIV
Where FIN is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and FOUT is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
The crystal cpacitors are internal to the device and have an
effective value of 4pF.
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SPREAD SPECTRUM GENERATION
(PLLB)
Modulation frequency:
PLLB has spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The programmable spread
spectrum generation parameters are NC[10:0], MOD[12:0],
and NSS[10:0] bits. To enable spread spectrum, set
SSENB_B=0.
Video Example
FMOD = FMID / NC (Eq. 11)
FREF = 27 MHz, FOUT = 27 MHz, 640 pixels per line, center
spread of ±1%. Using FVCO=432MHz, find the necessary
spread spectrum register settings.
FMID = FVCO/8
NC = 640 (integer number of spread periods/screen)
The spread spectrum circuitry was specifically developed to
accommodate video display applications. The spread
modulation frequency can be defined to exactly equal the
horizontal line frequency (HSYNC)
MOD = (25MHz * 640)/(2 * 54MHz) = 160
NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz =
321.
NC[10:0]
These bits are used to determine the number of pulses per
spread spectrum cycle. For video applications, NC is the
number of pixels on the horizontal display row (or integer
multiple of displayed pixels in a row). By matching the
spread period to the screen, no tearing or “shimmer” will be
apparent.
FMOD = 27MHz/640 = 11.8kHz.
Non-Video Example
FREF = 25MHz, FOUT = 27 MHz, 31.25kHz modulation rate,
center spread of ±1%. Find the necessary spread spectrum
register settings.
NC must be an even number to insure that the upward
spread transition has the same number of steps as the
downward spread transition.
FMID = FVCO/ 8
FMOD = 31.25kHz = 50.625MHz/NC.
For non-video applications, this can also be seen as the
number of clock cycles for a complete spread spectrum
period.
NC = 1620
MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400
MOD[12:0]
NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz =
814.
These bits relate the VCO frequency to the target average
spread output frequency (FMID).
FMID = (FVCO) / 8
FMAX = FMID + (SS% * FMID)
FMIN = FMID - (SS% * FMID)
MOD = (FREF* NC) / (2 * FMID)
NSS[10:0]
These bits control the amplitude of the spread modulation.
NSS = (NC / 2) + (NC / 8) * (FMAX - FMIN) / FMID
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VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship
VSYNC
HSYNC
Integer multiple of HSYNC periods
DOT_CLK
Modulation
Rate
X/2
X/2
X
X
X = Number of cycles of DOT_CLK per HSYNC period.
X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls.
LOOP FILTER
The following equations govern how the loop filter is set:
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low jitter
generation. The specific loop filter components that can be
programmed are the resistor via the RZ[4:0] bits, zero
capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0]
bits, and the charge pump current via the IP#[2:0] bits.
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Zero capacitor (Cz) = 280pF
Pole capacitor (Cp) = 30pF
Charge pump (Ip) = IP#[2:0] uA
VCO gain (KVCO) = 350MHz/V * 2
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Damping Factor:
= Rz/2 *(KVCO * Ip * Cz)1/2/M
Example
Fc = 150KHz is the desired loop bandwidth. The total A*M
value is 160. The (damping factor) target should be 0.7,
meaning the loop is critically damped. Given Fc and A*M, an
optimal loop filter setting needs to be solved for that will
meet both the PLL loop bandwidth and maintain loop
stability.
Choose a mid-range charge pump from register table
Icp= 11.9uA.
PLL Loop Bandwidth:
K* KVCO = 350MHz/V * 40uA = 12000A/Vs
Charge pump gain (K) = Ip / 2
c = 2* Fc = 9.42x105 s-1
VCO gain (KVCO) = 350MHz/V * 2
p = (Cz + Cp)/(Rz * Cz * Cp) = z (1 + Cz / Cp)
M = Total multiplier value (See the PRE-SCALERS,
FEEDBACK-DIVIDERS, POST-DIVIDERS section for more
detail)
Solving for Rz, the best possible value Rz=30kOhms
(RZ[1:0]=10) gives
c = (Rz * K* KVCO * Cz)/(M * (Cz + Cp))
= 1.4 (Ideal range for is 0.7 to 1.4)
Fc = c / 2
Solving back for the PLL loop bandwidth, Fc=149kHz.
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce your phase margin thus
compromising loop stability.
The phase margin must be checked for loop stability.
To determine if the loop is stable, the phase margin (m)
would need to be calculated as follows.
The phase margin would be acceptable with a fairly stable
loop.
m = (360 / 2) * [tan-1 (9.42x105 s-1 / 1.19x105s-1)
- tan-1(9.42x105 s-1/ 1.23x106 s-1)] = 45°
Phase Margin:
z = 1 / (Rz * Cz)
p = (Cz + Cp)/(Rz * Cz * Cp)
m = (360 / 2) * [tan-1(c/ z) - tan-1(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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SEL[1:0] Function
Always power with SEL1=1 and/or SEL0=1.
The IDT5P49EE502 can support up to three unique
configurations. Users may pre-program all configurations,
selected using SEL[1:0] pins. Alternatively, users may use
I2C interface to configure these registers on- the-fly.
SEL1
SEL0
0
0
Power Down/Sleep Mode
0
1
Select CONFIG0
1
0
Select CONFIG1
1
1
Select CONFIG2
.
Configuration Selections
Configuration OUTx IO Standard
2.5V or 3.3V LVCMOS. VDDO1 must have the highest
voltage of any pin on the device. VDDO2 may have any
value between 1.8V and VDDO1.
Users can configure the individual output IO standard from
a single 1.8V power supply. Each output can support 1.8V/
Programming the Device
I2C may be used to program the IDT5P49EE502.
The frame formats are shown in the following illustration.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5P49EE502 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
Framing
First Byte Transmitted on I2C Bus
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External I2C Interface Condition
EEPROM Interface
after the STOP condition is issued by the Master, during
which time the IDT5P49EE502 will not generate
Acknowledge bits. The IDT5P49EE502 will acknowledge
the instructions after it has completed execution of them.
During that time, the I2C bus should be interpreted as busy
by all other users of the bus.
The IDT5P49EE502 can store its configuration in an internal
EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
On power-up of the IDT5P49EE502, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5P49EE502 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
2
To initiate a save or restore using I C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
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Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S
Address
R/W
ACK
ID Byte
ACK
Data_1
ACK
Data_2
ACK
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
Data_last NACK
8-bits
P
1-bit
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5P49EE502 registers.
PROGREAD is for reading the IDT5P49EE502 registers.
PROGSAVE is for saving all the contents of the
IDT5P49EE502 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM
contents to the IDT5P49EE502 registers.
Progrestore
During PROGRESTORE, outputs will be turned off to
ensure that no improper voltage levels are experienced
before initialization.
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I2C Bus DC Characteristics
Symbol
Parameter
VIH
Input HIGH Level
VIL
Input LOW Level
VHYS
IIN
VOL
Conditions
Min
Typ
0.7xVDDO1
Hysteresis of Inputs
Max
Unit
5.5
V
0.3xVDDO1
V
0.05xVDDO1
V
Input Leakage Current
VDD = 0V
±1.0
µA
Output LOW Voltage
IOL = 3 mA
0.4
V
I2C Bus AC Characteristics for Standard Mode1
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
100
kHz
Bus free time between STOP and START
4.7
µs
tSU:START
Setup Time, START
4.7
µs
tHD:START
Hold Time, START
4
µs
tSU:DATA
Setup Time, data input (SDA)
250
ns
tHD:DATA
Hold Time, data input (SDA)2
0
µs
tOVD
Output data valid from clock
3.45
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCLK)
1000
ns
tF
Fall Time, data and clock (SDA, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
µs
tLOW
LOW Time, clock (SCLK)
4.7
µs
4
µs
tSU:STOP
Setup Time, STOP
1) No activity is allowed on I2C lines until VDD>1.62V.
2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCLK signal)
to bridge the undefined region of the falling edge of SCLK.
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I2C Bus AC Characteristics for Fast Mode1
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
400
kHz
Bus free time between STOP and START
1.3
µs
tSU:START
Setup Time, START
0.6
µs
tHD:START
Hold Time, START
0.6
µs
100
ns
0
µs
tSU:DATA
Setup Time, data input (SDA)
tHD:DATA
Hold Time, data input (SDA)
1
tOVD
Output data valid from clock
0.9
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tF
Fall Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tHIGH
HIGH Time, clock (SCL)
0.6
µs
tLOW
LOW Time, clock (SCL)
1.3
µs
Setup Time, STOP
0.6
µs
tSU:STOP
1) No activity is allowed on I2C lines until VDD>1.62V.
2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P49EE502. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
Max
Unit
Internal Power Supply Voltage
-0.5 to +4.6
V
VI
Input Voltage
-0.5 to +4.6
V
VO
Output Voltage (not to exceed 4.6 V)
-0.5 to VDD+0.5
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-65 to +150
°C
VDD
Description
Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
1.71
1.8
1.89
V
1.71
1.8
1.89
V
2.375
2.5
2.625
V
3.135
3.3
3.465
V
+85
°C
CLOAD_OUT Maximum load capacitance (3.3V LVTTL only)
15
pF
CLOAD_OUT Maximum load capacitance (1.8V or 2.5V LVTTL only)
8
pF
MHz
VDD , VDDx Power supply voltage for VDD
VDDOX
TA
FIN
XIN/REF
tPU
Power supply voltage for outputs VDDO1/2/3
Operating temperature, ambient
-40
External reference crystal
8
30
External reference clock CLKIN
1
40
Voltage swing for clock input
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
VDD
V
5
ms
0.05
Capacitance (TA = +25 °C, f = 1 MHz)
Symbol
CIN
Parameter
Min
Input Capacitance
Typ
Max
3
Unit
pF
Crystal Specifications
XTAL_FREQ
Crystal frequency
8
30
MHz
XTAL_MIN
Minimum crystal load capacitance
7
pF
XTAL_MAX
Maximum crystal load capacitance
20
pF
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
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IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
DC Electrical Characteristics for 3.3 Volt LVTTL 1
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = 33mA
VOL
Output LOW Voltage
IOH = 33mA
IOZDD
Min
Typ
Max
Unit
VDDO
V
0.4
V
5
µA
Max
Unit
VDDO
V
0.4
V
5
µA
Max
Unit
VDDO
V
0.35*VDDO
V
2.4
Output Leakage Current 3-state outputs
DC Electrical Characteristics for 2.5Volt LVTTL 1
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = 25mA
VOL
Output LOW Voltage
IOH = 25mA
IOZDD
Min
Typ
2.1
Output Leakage Current 3-state outputs
DC Electrical Characteristics for 1.8Volt LVTTL 1
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
SEL[1:0], 3.3V tolerant
VIL
Input LOW Voltage
SEL[1:0], 3.3V tolerant
IOZDD
Min
VDD = 1.71V to 1.89V
Typ
0.65*VDDO
0.75VDD
V
0.25VDD
V
5
µA
Output Leakage Current 3-state outputs
Power Supply Characteristics for LVTTL Outputs
Total Supply Current Vs VCO Frequency
Supply current Vs Output Frequency
14
12
10
8
6
4
2
0
Supply Current(mA)
Total Supply
Current(mA)
30
0
100
200
300
25
20
15
10
5
0
400
0
VCO Frequency(MHz)
20
40
60
80
1 PLL ON IDD (mA)
2 PLLs On IDD (mA)
Output Frequency(MHz)
1 output on
2 outputs on
3 PLLs on IDD (mA)
All PLLs ON IDD (mA)
4 outputs on
100
120
3 outputs on
5 outputs on
1: See “Recommended Operating Conditions” table. Alway completely power up VDD and VDDx prior to applying VDDO
power.
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
15
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IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
fIN
1 / t1
fVCO
Parameter
Test Conditions
Max.
Units
11
40
MHz
0.001
120
MHz
Single Ended Clock output limit (LVTTL) 2.5V
110
MHz
Single Ended Clock output limit (LVTTL) 1.8V
100
MHz
475
MHz
20
MHz
Input Frequency
Input Frequency Limit (CLKIN)
Output Frequency
Single Ended Clock output limit (LVTTL) 3.3V
VCO Frequency
Min.
VCO operating Frequency Range
100
1
fPFD
PFD Frequency
PFD operating Frequency Range
t2
Input Duty Cycle
Duty Cycle for Input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2
45
55
%
t4
Slew Rate, SLEWx(bits) = 00
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
5.1
Slew Rate, SLEWx(bits) = 01
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
4.4
Slew Rate, SLEWx(bits) = 10
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
2.8
Slew Rate, SLEWx(bits) = 11
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
1.8
Clock Jitter
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Single output frequency only.
100
ps
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Multiple output frequencies switching.
200
ps
200
ps
t5
0.5
Typ.
V/ns
t6
Output Skew
Skew between any output (Same freq and IO
type, FOUT >10MHz)
t7
Lock Time
PLL Lock Time from Power-up (using MHz
reference clock)2
5
20
ms
PLL Lock time from shutdown mode
5
10
ms
1.Input clock (square wave) may be used at 1 MHz.
2.Time from supply voltage crosses VDD=1.62V to PLLs are locked.
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Spread Spectrum Generation Specifications
Symbol
fIN
fMOD
fSPREAD
Parameter
Description
Min
Typ
Max
Unit
Input Frequency Input Frequency Limit
11
40
MHz
Mod Frequency
Modulation Frequency
32
120
kHz
Spread Value
Amount of Spread Value (programmable) - Down Spread
Programmable
Amount of Spread Value (programmable) - Center Spread
Programmable
Total Spread Value
0.5
%fOUT
4.0
1) Practical lower frequency is determined by loop filter settings.
Test Circuits and Conditions 1
Test Circuits for DC Outputs
Termination Scheme (Block Diagram)
RS
OUTPUTS
CLKOUT
CLOAD
GND
LVTTL Output Load: ~7pF for each output
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Programming Registers Table
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
0x00
04
ONXTALB
0x01
00
INV[0]
0x02
00
0x03
00
0x04
00
INV[1]
SLEW1[1:0]
0x05
00
INV[2]
0x06
00
INV[3]
0x07
00
0x08
00
0x09
00
0x0A
00
Reserved
Reserved
Reserved
PS1[2:1]
Reserved
SLEW2[1:0]
Reserved
PS2[2:1]
Reserved
SLEW3[1:0]
Reserved
PS3[2:1]
Reserved
Reserved
Reserved
Reserved
Reserved
INV[4]
SLEW4[1:0]
Reserved
Reserved
Reserved
0x0D
00
Reserved
0x0E
00
REFA[7:0]
0x11
00
INV[#] - Invert output#
SLEW#[0:1] - output# slew setting
0 0 - 5.1V/ns
0 1 - 4.4V/ns
1 0 - 2.8V/ns
1 1 - 1.8V/ns
PS#[2:1] -Power Select
00 - Reserved
01 - OUT# connects to VDDO1
10 - OUT# connects to VDDO2
11 - Reserved
CLK4 is tied to VDD02
Reserved
00
00
ONXTALB - MHz Crystal active low
Reserved
00
00
Description
0
PS0[2:1]
0x0B
0x10
1
Reserved
SLEW0[1:0]
0x0C
0x0F
2
Configuration0
REFA[7:0] - Reference Divide PLLA
FBA[10:3)
FBA[10:0] - Feedback Divide PLLA
Reserved
Reserved
XDIVA
FBA[2:0)
RZA[1:0]
IPA[2:0]
Reserved
XDIVA - FB predivide PLLA;
0 - /1; 1 - /4
RZA[1:0] - Zero Resistor PLLA
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPA[2:0] - charge Pump Current PLLA
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
0x12
00
REFB[7:0]
REFB[7:0] - Reference Divide PLLB
0x13
00
FBB[10:3]
FBB[10:0] - Feedback Divide PLLB
0x14
00
0x15
00
0x16
00
0x17
00
0x18
00
0x19
20
0x1A
00
MOD[4:0]
FBB[2:0]
PLLB Spread Parameters MOD[12:0]
NC[10:0]
NSS[12:0]
MOD[12:5]
NC[10:3]
NSS[4:0]
NC[2:0]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
Reserved
SSENB_B
RZB[1:0] - Zero Resistor PLLB
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPB[2:0] - charge Pump Current PLLB
000 - 0.37uA, 100 - 6.3uA
001 - 1.1uA, 101 - 11.9uA
010 - 1.8 uA, 110 - 17.7uA
011 - 3.4uA, 111 - 22.7uA
0x1B
00
REFC[7:0]
REFC[7:0] - Reference Divide PLLC
0x1C
00
FBC[10:3]
FBC[10:0] - Feedback Divide PLLC
0x1D
00
0x1E
00
Reserved
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
FBC[2:0]
FBC2[7:0]
FBC2 - Feedback Predivide PLLC
Turn on using XDIVC=1
18
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REV L 111714
IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
0x1F
EEPROM CLOCK GENERATOR
Bit #
7
6
00
5
4
3
IPC[2:0]
RZC[1:0]
Description
2
1
0
Reserved
XDIVC
Reserved
RZC[1:0] - Zero Resistor PLLC
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPC[2:0] - charge Pump Current PLLC
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
0x20
00
REFD[7:0]
REFD[7:0] - Reference Divide PLLD
0x21
00
FBD[10:3]
FBD[10:0] - Feedback Divide PLLD
0x22
00
0x23
00
0x24
00
OD0[7:0]
0x25
00
Reserved
0x26
00
Reserved
0x27
00
OD1[7:0]
0x28
00
OD2[7:0]
0x29
00
OD3[7:0]
0x2A
00
Reserved
Reserved
Reserved
XDIVD
0x2B
00
0x2C
00
0x2D
00
SCR4[1:0]
0x2E
00
SCR2[1:0]
0x2F
01
SCR0[1:0]
0x30
FF
FBD[2:0]
RZD[1:0]
IPD[2:0]
Reserved
XDIVD - FB predivide PLLD;
0 - /1; 1 - /4
RZD[1:0] - Zero Resistor PLLD
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPD[2:0] - charge Pump Current PLLD
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
SCR3[1:0]
SRC3[1:0] - OD4 source
00 - off; 10 - PLLA
01 - Reference; 11 - PLLD
SRC4[1:0] - OD4 source
00 - off; 10 - PLLC
01 - PLLA; 11 - Reference
OD4[7:0]
Reserved
SCR1[1:0]
Reserved
SRC1[1:0] - OD1 source
00 - off; 10 - PLLB
01 - PLLA; 11 - PLLD
SRC2[1:0] - OD2 source
00 - off; 10 - PLLC
01 - PLLA; 11 - PLLD
Reserved
SRC0[1:0] - OD0 source
00 - off; 10 - PLLC
01 - PLLB; 11 - PLLD
Reserved
0x31
00
0x32
00
PDB[4]
Reserved
Reserved
OE[3]
OE[2]
OE[4]
OE[1]
Reserved
OE[0]
0x33
00
Reserved
PDB[3]
PDB[2]
PDB[1]
Reserved
PDB[0]
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Reserved
19
PDB[4:0] - Powerdown OUT#.
PDB#=0, OUT# driven low
OE[4:0] - Output enable OUT#.
OE#=0, OUT# tri-stated.
If PDB#=OE#=0, OUT# driven low
IDT5P49EE502
REV L 111714
IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
EEPROM CLOCK GENERATOR
Bit #
7
6
5
4
3
0x34
00
REFA[7:0]
0x35
00
FBA[10:3)
0x36
00
0x37
00
0x38
00
0x39
00
0x3A
00
0x3B
00
2
1
Configuration1
(See definitions from Configuration0
above)
Reserved
Reserved
XDIVA
Description
0
FBA[2:0)
RZA[1:0]
IPA[2:0]
Reserved
REFB[7:0]
FBB[10:3]
MOD[4:0]
FBB[2:0]
MOD[12:5]
0x3C
00
0x3D
00
NC[10:3]
0x3E
00
0x3F
40
0x40
00
0x41
00
0x42
00
0x43
00
0x44
00
0x45
00
0x46
00
0x47
00
0x48
00
0x49
00
0x4A
00
OD0[7:0]
NSS[4:0]
NC[2:0]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
Reserved
Reserved
SSENB_B
REFC[7:0]
FBC[10:3]
Reserved
FBC[2:0]
FBC2[7:0]
IPC[2:0]
RZC[1:0]
Reserved
XDIV
Reserved
REFD[7:0]
FBD[10:3]
Reserved
XDIVD
FBD[2:0]
RZD[1:0]
IPD[2:0]
Reserved
0x4B
00
Reserved
0x4C
00
Reserved
0x4D
00
OD1[7:0]
0x4E
00
OD2[7:0]
0x4F
00
OD3[7:0]
0x50
00
Reserved
0x51
00
Reserved
0x52
00
0x53
00
SCR4[1:0]
0x54
00
SCR2[1:0]
0x55
01
SCR0[1:0]
0x56
FF
0x57
00
0x58
00
Reserved
OE[3]
OE[2]
OE[1]
Reserved
OE[0]
0x59
00
Reserved
PDB[3]
PDB[2]
PDB[1]
Reserved
PDB[0]
OD4[7:0]
Reserved
SCR3[1:0]
SCR1[1:0]
Reserved
Reserved
Reserved
PDB[4]
Reserved
OE[4]
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Reserved
20
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REV L 111714
IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
EEPROM CLOCK GENERATOR
Bit #
7
6
5
4
3
0x5A
00
REFA[7:0]
0x5B
00
FBA[10:3)
0x5C
00
0x5D
00
0x5E
00
0x5F
00
0x60
00
0x61
00
0x62
00
0x63
00
0x64
00
0x65
40
0x66
00
0x67
00
0x68
00
0x69
00
0x6A
00
2
1
Configuration2
(See definitions from Configuration0
above)
Reserved
Reserved
XDIVA
Description
0
FBA[2:0)
RZA[1:0]
IPA[2:0]
Reserved
REFB[7:0]
FBB[10:3]
MOD[4:0]
FBB[2:0]
MOD[12:5]
NC[10:3]
NSS[4:0]
NC[2:0]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
Reserved
Reserved
SSENB_B
REFC[7:0]
FBC[10:3]
Reserved
FBC[2:0]
FBC2[7:0]
0x6B
00
0x6C
00
IPC[2:0]
RZC[1:0]
Reserved
0x6D
00
0x6E
00
0x6F
00
0x70
00
OD0[7:0]
0x71
00
Reserved
0x72
00
Reserved
0x73
00
OD17:0]
0x74
00
OD2[7:0]
0x75
00
OD3[7:0]
0x76
00
Reserved
0x77
00
Reserved
0x78
00
0x79
00
SCR4[1:0]
0x7A
00
SCR2[1:0]
SCR0[1:0]
XDIV
Reserved
REFD[7:0]
FBD[10:3]
Reserved
XDIVD
FBD[2:0]
RZD[1:0]
IPD[2:0]
Reserved
OD4[7:0]
Reserved
SCR3[1:0]
SCR1[1:0]
Reserved
0x7B
01
0x7C
FF
Reserved
0x7D
00
0x7E
00
Reserved
OE[3]
OE[2]
OE[1]
Reserved
OE[0]
0x7F
00
Reserved
PDB[3]
PDB[2]
PDB[1]
Reserved
PDB[0]
Reserved
PDB[4]
Reserved
OE[4]
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Reserved
21
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IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Marking Diagram (ND20)
YYWW
2DGI
Notes:
1. YYWW is the last two digits of the year and week that the part was assembled.
2. “G” indicates Pb-free, RoHS compliant package.
3. “I” at the end of part number indicates industrial temperature range.
Thermal Characteristics 20-pin VFQFPN
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
Symbol
Conditions
JA
Still air
JA
JA
Min.
Typ.
Max. Units
64
C/W
1 m/s air flow
56.6
C/W
3 m/s air flow
51.8
C/W
84.3
C/W
JC
22
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REV L 111714
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
20-pin QFN PCB Land Pattern
ZDMAX =
3.26 mm
D2 =
1.75 mm
ZEMAX =
3.26 mm
AEMAX =
1.83 mm
E2 =
1.75 mm
GEMIN =
2.15 mm
ADMAX =
1.83 mm
Y = 0.55 mm
GDMIN =
2.15 mm
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
23
X = 0.23 mm
IDT5P49EE502
REV L 111714
IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Package Outline and Package Dimensions (20-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND -1)x e
(Ref)
L
A3
e
N
1
Sawn
Singulation
E
E2
2
C0.35
E2
Top View
(Typ)
& NE
If
N
D
2
are Even
(NE -1)x e
(Ref)
2
b
A
D
(Ref)
ND & NE
Odd
C
0.08 C
Symbol
A
A1
A3
b
e
N
ND
NE
D x E BASIC
D2
E2
L
Min
e
D2
2
D2
Thermal Base
EP – Exposed thermal pad
should be externally
connected to ground.
Millimeters
Max
0.80
1.00
0
0.05
0.25 Reference
0.15
0.23
0.40 BASIC
20
5
5
3.00 x 3.00
1.55
1.75
1.55
1.75
0.30
0.50
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
5P49EE502NDGI
5P49EE502NDGI8
See page 22
See page 22
Tubes
Tape and Reel
20pin VFQFPN
20pin VFQFPN
-40 to +85 C
-40 to +85 C
“G” after the two-letter pacakage code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
24
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Revision History
Rev.
Date
Originator
Description of Change
--
10/27/09
R.Willner
Initial Preliminary Datasheet
A
11/10/09
R.Willner
Revised pinout.
B
3/25/10
R.Willner
Typographical changes. Register corrections. Correct spread spectrum calculations.
C
6/11/10
R. Willner
Default configuration. Clarification of OUT4 is tied to VDDO2.
D
07/26/10
R. Willner
Updated thermal pad and dimensions on package drawing.
E
8/30/10
R.Willner
Input Clock max voltage swing 1.8V.
F
9/08/10
R.Willner
Power ramp sequence.
G
10/18/10
R.Willner
Typographical changes. Loop filter calculations. Default register bit corrections.
H
01/19/11
R.Willner
Corrected notes for top-side marking.
J
04/13/11
R. Willner
1. Updated SCLK and SDA pin descriptions
2. Updated DC Electrical Char table for 1.8V LVTTL; added VIH and VIL.
3. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC
Timing Electrical Char table.
K
09/30/11
R. Willner
Updated Power-up/Power-down Sequence notes.
L
11/17/14
R. Willner
Aded pin 1 dot indicator on marking diagram.
Corrected typo in Register Map table; SLEWx[0:1] was changed to SLEWx[1:0]
IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR
25
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REV L 111714
IDT5P49EE502
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
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