VersaClock® 6E Programmable
Clock with Internal Crystal
Description
Features
The 5P49V6975 is a programmable clock generator intended for
high-performance consumer, networking, industrial, computing,
and data-communications applications. The device is a member of
Renesas’ sixth generation of programmable clock technology,
VersaClock 6E.
The 5P49V6975 contains an internal crystal, which eliminates the
need for external crystal and load cap tuning.
Two select pins allow up to four different configurations to be
programmed, and can be used for different operating modes (full
function, partial function, partial power-down), regional standards
(US, Japan, Europe) or system production margin testing. The
5P49V6975 can be configured to use one of two I2C addresses to
allow the use of multiple devices in a system.
Typical Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0/4.0 spread spectrum on
PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
Laser distance sensing
5P49V6975
Datasheet
Internal crystal input integrated into package
Flexible 1.8V, 2.5V, 3.3V power rails
High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
Four banks of internal OTP memory
• In-system or factory programmable
• Two select pins accessible with processor GPIOs or
bootstrapping
I2C serial programming interface
• 0xD0 or 0xD4 I2C address options allow multiple devices
configured in a same system
Reference LVCMOS output clock
Four universal output pairs individually configurable:
• Differential (LVPECL, LVDS, or HCSL)
• Two single-ended (2 LVCMOS in-phase or 180 degrees out
of phase)
• I/O VDDs can be mixed and matched, supporting 1.8V
(LVDS and LVCMOS), 2.5V, or 3.3V
• Independent spread spectrum on each output pair
Output frequency ranges:
• LVCMOS clock outputs: 1kHz to 200MHz
• LVDS, LVPECL, HCSL differential clock outputs: 1kHz to
350MHz
Programmable output enable or power-down mode
Available in 4 × 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
Block Diagram
VDDO 0
OUT0_SEL_I2CB
VDDO 1
OUT1
CLKIN
FOD1
CLKINB
VDDO 2
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
OUT1B
OTP
and
Control
Logic
FOD2
PLL
OUT2
OUT2B
VDDO 3
VDDA
FOD3
VDDD
OUT3
OUT3B
VDDO 4
FOD4
© 2021 Renesas Electronics Corporation.
1
OUT4
OUT4B
February 11, 2021
5P49V6975 Datasheet
Contents
1.
Pin Assignments ...........................................................................................................................................................................................3
2.
Pin Descriptions............................................................................................................................................................................................3
3.
Absolute Maximum Ratings ..........................................................................................................................................................................5
4.
Thermal Characteristics................................................................................................................................................................................5
5.
Recommended Operating Conditions...........................................................................................................................................................5
6.
Electrical Characteristics ..............................................................................................................................................................................6
7.
Test Loads ..................................................................................................................................................................................................13
8.
Jitter Performance Characteristics..............................................................................................................................................................14
9.
PCI Express Jitter Performance and Specification .....................................................................................................................................15
10. Features and Functional Blocks .................................................................................................................................................................17
10.1 Device Startup and Power-on-Reset................................................................................................................................................17
10.2 Reference Clock and Selection ........................................................................................................................................................18
10.3 Manual Switchover...........................................................................................................................................................................18
10.4 Programmable Loop Filter................................................................................................................................................................19
10.5 Fractional Output Dividers (FOD).....................................................................................................................................................19
10.5.1
Individual Spread Spectrum Modulation ...........................................................................................................................19
10.5.2
Bypass Mode ....................................................................................................................................................................19
10.5.3
Cascaded Mode ................................................................................................................................................................19
10.5.4
Dividers Alignment ............................................................................................................................................................19
10.5.5
Programmable Skew.........................................................................................................................................................20
10.6 Output Drivers ..................................................................................................................................................................................20
10.7 SD/OE Pin Function .........................................................................................................................................................................20
10.8 I2C Operation ...................................................................................................................................................................................21
11. Typical Application Circuit ..........................................................................................................................................................................22
11.1 Input – Driving the CLKIN ................................................................................................................................................................23
11.1.1
Wiring the CLKIN Pin to Accept Single-Ended Inputs .......................................................................................................23
11.1.2
Driving CLKIN with Differential Clock ................................................................................................................................24
11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................24
11.2.1
LVDS Termination.............................................................................................................................................................24
11.2.2
LVPECL Termination ........................................................................................................................................................25
11.2.3
HCSL Termination.............................................................................................................................................................26
11.2.4
LVCMOS Termination .......................................................................................................................................................26
12. Package Outline Drawings .........................................................................................................................................................................26
13. Marking Diagram .........................................................................................................................................................................................27
14. Ordering Information ...................................................................................................................................................................................27
15. Revision History ..........................................................................................................................................................................................28
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
Pin Assignments
24 23 22
OUT1B
OUT1
VDDO1
21 20 19
18
VDDO2
2
17
OUT2
3
16
OUT2B
15
VDDO3
14
OUT3
13
OUT3B
VDDA
5
CLKSEL
6
7
8
9
10 11 12
OUT4B
4
SEL0/SCL
NC
EPAD
SEL1/SDA
NC
SD/OE
CLKINB
OUT4
1
VDDO4
CLKIN
VDDD
Pin Assignments for 4 × 4 mm 24-LGA Package – Top View
OUT0_SEL_I2CB
Figure 1.
VDDO0
1.
4 × 4 mm 24-LGA
2.
Pin Descriptions
Table 1.
Number
Pin Descriptions
Name
Type
Description
CLKIN
Input
Internal Differential clock input. Weak 100kΩ internal pull-down.
Pull-down
2
CLKINB
Input
Internal Complementary differential clock input. Weak 100kΩ internal pull-down.
Pull-down
3
NC
No connect.
4
NC
No connect
5
VDDA
1
6
CLKSEL
Power
Input
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD should
have the same voltage applied.
Input clock select. Selects the active input reference source in manual switchover
mode.
Internal 0 = Internal crystal (default).
Pull-down
1 = CLKIN, CLKINB.
See Table 20. Input Clock Select for details.
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
Number
7
8
9
Name
Type
Description
SD/OE
Input
Internal
Enables/disables the outputs (OE) or powers down the chip (SD).
Pull-down
SEL1/SDA
Input
Internal Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak
Pull-down internal pull-down resistor.
SEL0/SCL
Input
Internal Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak
Pull-down internal pull-down resistor.
10
VDDO4
Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT4/OUT4B.
11
OUT4
Output
Output clock 4. Refer to Output Drivers section for more details.
12
OUT4B
Output
Complementary output clock 4. Refer to Output Drivers section for more details.
13
OUT3B
Output
Complementary output clock 3. Refer to Output Drivers section for more details.
14
OUT3
Output
Output clock 3. Refer to Output Drivers section for more details.
15
VDDO3
Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT3/OUT3B.
16
OUT2B
Output
Complementary output clock 2. Refer to Output Drivers section for more details.
17
OUT2
Output
Output clock 2. Refer to Output Drivers section for more details.
18
VDDO2
Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
19
OUT1B
Output
Complementary output clock 1. Refer to Output Drivers section for more details.
20
OUT1
Output
Output clock 1. Refer to Output Drivers section for more details.
21
VDDO1
Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
22
VDDD
Power
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDD should have
the same voltage applied.
23
VDDO0
Power
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT0.
24
OUT0_SEL
_I2CB
EPAD
GND
Input/
Output
Latched input/LVCMOS output. At power-up, the voltage at the pin OUT0_SEL_I2CB is
latched by the part and used to select the state of pins 8 and 9. If a weak pull-up (10kΩ)
Internal is placed on OUT0_SEL_I2CB, pins 8 and 9 are configured as hardware select pins,
Pull-down SEL1 and SEL0. If a weak pull-down (10kΩ) is placed on OUT0_SEL_I2CB or it is left
floating, pins 8 and 9 will act as the SDA and SCL pins of an I2C interface. After powerup, the pin acts as an LVCMOS reference output.
GND
© 2021 Renesas Electronics Corporation.
Connect to ground pad.
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February 11, 2021
5P49V6975 Datasheet
3.
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the device at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2.
Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDDA, VDDD, VDDO
3.6V
Internal Crystal
1.2V
CLKIN, CLKINB Input
VDDO0, 1.2V voltage swing
I2C Loading Current (SDA)
10mA
Storage Temperature, TSTG
-65°C to 150°C
Junction Temperature
125 °C
ESD Human Body Model
2000V
4.
Thermal Characteristics
Table 3.
Thermal Characteristics
Symbol
5.
Parameter
Value
Units
θJA
Theta JA. Junction to air thermal impedance (0mps)
75.98
°C/W
θJB
Theta JB. Junction to board thermal impedance (0mps)
24.3
°C/W
θJC
Theta JC. Junction to case thermal impedance (0mps)
57.32
°C/W
Recommended Operating Conditions
Table 4.
Recommended Operating Conditions
Symbol
Minimum
Typical
Maximum
Units
Power supply voltage for supporting 1.8V outputs.
1.71
1.8
1.89
V
Power supply voltage for supporting 2.5V outputs.
2.375
2.5
2.625
V
Power supply voltage for supporting 3.3V outputs.
3.135
3.3
3.465
V
VDDD
Power supply voltage for core logic functions.
1.71
3.465
V
VDDA
Analog power supply voltage. Use filtered analog power
supply.
1.71
3.465
V
TPU
Power ramp time for all VDDs to reach 90% of VDD.
0.05
50
ms
TA
Operating temperature, ambient.
-40
85
°C
CL
Maximum load capacitance (3.3V LVCMOS only).
15
pF
VDDOx
Parameter
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
6.
Electrical Characteristics
Table 5.
Current Consumption Characteristics
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
IDDCORE[a]
Core Supply Current
Output Buffer Supply
Current
IDDOX
IDDPD
Power Down Current
Conditions
Minimum
Typical
Maximum
Units
100MHz on all outputs.
33
42
mA
LVPECL, 350MHz, 3.3V VDDOx.
45
58
mA
LVPECL, 350MHz, 2.5V VDDOx.
36
47
mA
LVDS, 350MHz, 3.3V VDDOx.
26
32
mA
LVDS, 350MHz, 2.5V VDDOx.
25
30
mA
LVDS, 350MHz, 1.8V VDDOx.
22
27
mA
HCSL, 250MHz, 3.3V VDDOx [b]
39
48
mA
HCSL, 250MHz, 2.5V VDDOx [b]
37
46
mA
LVCMOS, 50MHz, 3.3V, VDDOx [b],[c]
22
27
mA
LVCMOS, 50MHz, 2.5V, VDDOx [b],[c]
20
24
mA
LVCMOS, 50MHz, 1.8V, VDDOx [b],[c]
17
21
mA
LVCMOS, 200MHz, 3.3V VDDOx [b],[c]
43
56
mA
LVCMOS, 200MHz, 2.5V VDDOx [b],[c]
33
43
mA
LVCMOS, 200MHz, 1.8V VDDOx [b],[c]
24
31
mA
SD asserted, I2C programming.
10
12
mA
[a] IDDCORE = IDDA + IDDD, no loads.
[b] Measured into a 5” 50Ω trace with a 2pF load. See Test Loads section for more details.
[c] Single CMOS driver active.
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
Table 6.
General AC Timing Characteristics
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
FIN [a]
Parameter
Input Frequency
Conditions
Output Frequency
1
350
Single-ended clock output limit (LVCMOS),
individual FOD mode.
1
200
1
350
0.001
200
0.001
350
2500
2900
MHz
Single-ended clock output limit (LVCMOS),
cascaded FOD mode, output 2–4.
Differential clock output limit
(LVPECL/LVDS/HCSL), cascaded FOD mode,
output 2–4.
fVCO
TDC [c]
TSKEW
VCO Frequency Range
Output Duty Cycle
Output Skew
TSTARTUP [d] [e] Startup Time
Typical Maximum Units
Input frequency limit (CLKIN,CLKINB)
Differential clock output (LVPECL/LVDS/HCSL),
individual FOD mode.
FOUT [b]
Minimum
Frequency Stability
45
50
55
%
Measured at VDD/2, all outputs except reference
output, VDDOX = 1.8V.
40
50
60
%
Measured at VDD/2, reference output OUT0 (5MHz–
150.1MHz) with 50% duty cycle input.
40
50
60
%
Measured at VDD/2, reference output OUT0
(150.1MHz–200MHz) with 50% duty cycle input.
30
50
70
%
Skew between the same frequencies, with outputs
using the same driver format and 0 phase delay.
75
Measured after all VDDs have raised above 90% of
their target value. [f]
PLL lock time from shutdown mode.
3
Initial frequency accuracy at 25°C.
±2
Crystal aging first year.
ps
30
ms
4
ms
ppm
±20
±3
Frequency stability over 10 years all inclusive
(temperature and aging).
[a]
[b]
[c]
[d]
[e]
[f]
MHz
Measured at VDD/2, all outputs except reference
output, VDDOX = 2.5V or 3.3V.
Frequency stability across temperature.
TCRYSTAL
MHz
ppm
ppm
±50
ppm
Practical lower frequency is determined by loop filter settings.
A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
Duty cycle is only guaranteed at maximum slew rate settings.
Actual PLL lock time depends on the loop configuration.
Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
Power-up with temperature calibration enabled, please contact Renesas if shorter lock-time is required in system.
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
Table 7.
General Input Characteristics
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Pins
Minimum
CIN
Input Capacitance
CLKIN,CLKINB,CLKSEL,SD/OE,SEL1/SDA,
SEL0/SCL
RPD
Pull-down Resistor
CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN,
CLKINB, OUT0_SEL_I2CB
VIH
Input High Voltage
VIL
Typical
Maximum
3
7
Units
pF
100
300
CLKSEL, SD/OE
0.7 x VDDD
VDDD + 0.3
V
Input Low Voltage
CLKSEL, SD/OE
GND - 0.3
0.3 x VDDD
V
VIH
Input High Voltage
OUT0_SEL_I2CB
0.65 x
VDDO0 + 0.3
V
VIL
Input Low Voltage
OUT0_SEL_I2CB
GND - 0.3
0.4
V
VIH
Input High Voltage
Internal crystal
0.8
1.2
V
VIL
Input Low Voltage
Internal crystal
GND - 0.3
0.4
V
Input Rise/Fall Time
CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL
300
ns
Maximum
Units
TR/TF
Table 8.
kΩ
CLKIN Electrical Characteristics
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Conditions
Minimum
Typical
VSWING
Input Amplitude – CLKIN, CLKINB
Peak to peak value, single-ended.
200
1200
mV
dv/dt
Input Slew Rate – CLKIN, CLKINB
Measured differentially.
0.4
8
V/ns
IIL
Input Leakage Low Current
VIN = GND.
-5
5
μA
IIH
Input Leakage High Current
VIN = 1.7V.
20
μA
Input Duty Cycle
Measurement from differential
waveform.
DCIN
© 2021 Renesas Electronics Corporation.
8
45
55
%
February 11, 2021
5P49V6975 Datasheet
Table 9.
Electrical Characteristics – CMOS Outputs
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Units
VOH
Output High Voltage
IOH = -15mA (3.3V), -12mA (2.5V).
0.7 x VDDO
VDDO
V
VOH
Output High Voltage
IOH = -8mA(1.8V)
0.5 x VDDO
VDDO
V
VOL
Output Low Voltage
IOH = 15mA (3.3V), 12mA (2.5V), 8mA (1.8V) .
0.45
V
ROUT
Output Driver Impedance
CMOS output driver.
TSR
IOZDD
17
Slew Rate, SLEW[1:0] = 00
1.0
2.2
Slew Rate, SLEW[1:0] = 01 Single-ended 3.3V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO (output load = 5pF)
Slew Rate, SLEW[1:0] = 10 VDDOX = 3.3V.
1.2
2.3
1.3
2.4
Slew Rate, SLEW[1:0] = 11
1.7
2.7
Slew Rate, SLEW[1:0] = 00
0.6
1.3
Slew Rate, SLEW[1:0] = 01 Single-ended 2.5V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO (output load = 5pF)
Slew Rate, SLEW[1:0] = 10 VDDOX = 2.5V.
0.7
1.4
0.6
1.4
Slew Rate, SLEW[1:0] = 11
1.0
1.7
Slew Rate, SLEW[1:0] = 00
0.3
0.7
Slew Rate, SLEW[1:0] = 01 Single-ended 1.8V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO (output load = 5pF)
Slew Rate, SLEW[1:0] = 10 VDD = 1.8V.
0.4
0.8
0.4
0.9
Slew Rate, SLEW[1:0] = 11
0.7
1.2
Output Leakage Current
(OUT1–4)
Tri-state outputs.
Output Leakage Current
(OUT0)
Tri-state outputs.
© 2021 Renesas Electronics Corporation.
Ω
V/ns
5
30
9
μA
μA
February 11, 2021
5P49V6975 Datasheet
Table 10. Electrical Characteristics – LVDS Outputs
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Minimum
Typical
Maximum Units
VOT (+)
Differential Output Voltage for the TRUE Binary State
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE Binary State
-454
-247
mV
ΔVOT
Change in VOT between Complimentary Output States
50
mV
VOS
ΔVOS
Output Common Mode Voltage (Offset Voltage) at 3.3V±5%, 2.5V±5%
Output Common Mode Voltage (Offset Voltage) at 1.8V±5%
1.125
1.25
1.375
V
0.8
0.875
0.96
V
50
mV
Change in VOS between Complimentary Output States
IOS
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
9
24
mA
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT-
6
12
mA
TR
LVDS Rise Time 20%-80%
300
ps
TF
LVDS Fall Time 80%-20%
300
ps
Table 11. Electrical Characteristics – LVPECL Outputs
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Minimum
Typical
Maximum Units
VOH
Output Voltage High, terminated through 50Ω tied to VDD - 2V
VDDO - 1.19
VDDO - 0.69
V
VOL
Output Voltage Low, terminated through 50Ω tied to VDD - 2V
VDDO - 1.94
VDDO - 1.4
V
1.1
2
V
VSWING
Peak-to-Peak Differential Output Voltage Swing
TR
LVPECL Rise Time 20%-80%
400
ps
TF
LVPECL Fall Time 80%-20%
400
ps
© 2021 Renesas Electronics Corporation.
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February 11, 2021
5P49V6975 Datasheet
Table 12. Electrical Characteristics – HCSL Outputs[a]
VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, TA = -40°C to +85°C, unless stated otherwise.
Symbol
Parameter
Conditions
dV/dt
Slew Rate
Scope averaging on. [b] [c]
ΔdV/dt
Slew Rate Matching
Scope averaging on. [b] [c]
V MAX
Maximum Voltage
VMIN
Minimum Voltage
Measurement on single-ended signal using
absolute value (scope averaging off).
Minimum
Typical
Maximum
Units
4
V/ns
20
%
1150
mV
1
-300
mV
mV
VSWING
Voltage Swing
Scope averaging off. [b] [f]
300
VCROSS
Crossing Voltage Value
Scope averaging off. [d] [f]
250
ΔVCROSS
Crossing Voltage Variation
Scope averaging off. [e]
550
mV
140
mV
[a] Guaranteed by design and characterization. Not 100% tested in production.
[b] Measured from differential waveform.
[c] Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a ±150mV window around differential
0V.
[d] VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.,
Clock rising and Clock# falling).
[e] The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute) allowed.
The intent is to limit VCROSS induced modulation by setting Δ VCROSS to be smaller than VCROSS absolute.
[f] Measured from single-ended waveform.
Table 13. Spread-Spectrum Generation Specifications
Symbol
fSSOUT
fMOD
fSPREAD
Parameter
Conditions
Spread Frequency Output frequency range for spread spectrum
Mod Frequency
Spread Value
Modulation frequency.
Minimum
Typical Maximum Units
5
300
30 to 63
kHz
Amount of spread value (programmable)–center spread.
±0.1% to ±2.5%
Amount of spread value (programmable)–down spread.
-0.2% to -5%
© 2021 Renesas Electronics Corporation.
11
MHz
%fOUT
February 11, 2021
5P49V6975 Datasheet
Table 14. I2C Bus (SCL/SDA) DC Characteristics
Symbol
Parameter
Conditions
VIH
Input High Level
For SEL1/SDA pin and
SEL0/SCL pin.
VIL
Input Low Level
For SEL1/SDA pin and
SEL0/SCL pin.
VHYS
Hysteresis of Inputs
IIN
Input Leakage Current
VOL
Output Low Voltage
Minimum
Typical
Maximum
0.7 x VDDD
Units
V
0.3 x VDDD
0.05 x VDDD
V
V
-1
IOL = 3mA.
36
μA
0.45
V
Maximum
Units
400
kHz
Table 15. I2C Bus (SCL/SDA) AC Characteristics
Symbol
Parameter
Minimum
Typical
FSCLK
Serial Clock Frequency (SCL)
10
tBUF
Bus Free Time between Stop and Start
1.3
μs
tSU:START
Setup Time, Start
0.6
μs
tHD:START
Hold Time, Start
0.6
μs
tSU:DATA
Setup Time, Data Input (SDA)
0.1
μs
tHD:DATA
Hold Time,
0
μs
Data Input (SDA) 1
Output Data Valid from Clock
0.9
μs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, Data and Clock (SDA, SCL)
20 + 0.1 x CB
300
ns
tF
Fall Time, Data and Clock (SDA, SCL)
20 + 0.1 x CB
300
ns
tOVD
tHIGH
High Time, Clock (SCL)
0.6
μs
tLOW
Low Time, Clock (SCL)
1.3
μs
Setup Time, Stop
0.6
μs
tSU:STOP
[a] A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
[b] I2C inputs are 3.3V tolerant.
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7.
Test Loads
Figure 2.
LVCMOS Test Load
Test
Point
33Ω
Zo = 50Ω
5pF
Device
Figure 3.
HCSL Test Load
50Ω
33Ω
2pF
Differential
Zo=100Ω
33Ω
Test
Points
50Ω
2pF
Device
Figure 4.
LVDS Test Load
2pF
Differential
Zo=100Ω
100Ω
Test
Points
2pF
Device
Figure 5.
LVPECL Test Load
Differential
Zo=100Ω
Test
Points
2pF
50Ω
Device
50Ω
2pF
R
R=50Ω for 3.3V LVPECL
R=18Ω for 2.5V LVPECL
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5P49V6975 Datasheet
8.
Jitter Performance Characteristics
Figure 6.
Typical Phase Jitter Plot at 156.25MHz
Note: Measured with OUT2=156.25MHz on, 39.625MHz input.
Table 16. Jitter Performance[a] [b]
Symbol
JCY-CY
Jpk-pk
JRMS
Parameter
Cycle to Cycle Jitter
Period Jitter
RMS Phase Jitter
(12kHz-20MHz)
Conditions
Minimum
Typical
Maximum
Units
LVCMOS 3.3V ±5%,-40°C–90°C.
5
30
ps
All differential outputs 3.3V ±5%,-40°C–90°C.
25
35
ps
LVCMOS 3.3V ±5%,-40°C–90°C.
28
40
ps
All differential outputs 3.3V ±5%,-40°C–90°C.
4
30
ps
LVCMOS 3.3V ±5%,-40°C–90°C.
0.3
ps
All differential outputs 3.3V ±5%,-40°C–90°C.
0.5
ps
[a] Measured with 25MHz crystal input.
[b] Configured with OUT0 = 25MHz–LVCMOS; OUT1 = 100MHz–HCSL; OUT2 = 125MHz–LVDS; OUT3 = 156.25MHz–LVPECL.
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5P49V6975 Datasheet
9.
PCI Express Jitter Performance and Specification
Table 17. PCI Express Jitter Performance (Spread Spectrum = OFF)
Parameter
Symbol
Conditions
tjphPCIeG1-CC
PCIe Gen1 (2.5 GT/s)
SSC = OFF
Limit
Units
Notes
4
86
ps
(p-p)
1, 2
PCIe Gen2 Lo Band (5.0 GT/s)
SSC = OFF
0.05
3
ps
(RMS)
1, 2
PCIe Gen2 Hi Band (5.0 GT/s)
SSC = OFF
0.22
3.1
ps
(RMS)
1, 2
tjphPCIeG3-CC
PCIe Gen3 (8.0 GT/s)
SSC = OFF
0.12
1
ps
(RMS)
1, 2
tjphPCIeG4-CC
PCIe Gen4 (16.0 GT/s)
SSC = OFF
0.12
0.5
ps
(RMS)
1, 2, 3,
4
tjphPCIeG5-CC
PCIe Gen5 (32.0 GT/s)
SSC = OFF
0.05
0.15
ps
(RMS)
1, 2, 3,
5
tjphPCIeG1-SRNS
PCIe Gen1 (2.5 GT/s)
SSC = OFF
0.3
n/a
ps
(p-p)
1, 2, 6
tjphPCIeG2-SRNS
PCIe Gen2 (5.0 GT/s)
SSC = OFF
0.26
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG3-SRNS
PCIe Gen3 (8.0 GT/s)
SSC = OFF
0.07
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG4-SRNS
PCIe Gen4 (16.0 GT/s)
SSC = OFF
0.07
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG5-SRNS
PCIe Gen5 (32.0 GT/s)
SSC = OFF
0.07
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG2-CC
PCIe Phase Jitter
(Common Clocked
Architectures)
PCIe Phase Jitter
(SRNS Architectures)
1
2
3
4
5
6
Minimum
Typical Maximum
The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the
data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table.
Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20GS/s
or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements.
Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to
an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the
2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA
measurements have both been done and produce different results the RTO result must be used.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content.
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification
limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a
clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by Ö2.
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5P49V6975 Datasheet
Table 18. PCI Express Jitter Performance (Spread Spectrum = ON)
Parameter
Symbol
Conditions
tjphPCIeG1-CC
PCIe Gen1 (2.5 GT/s)
SSC = < -0.5%
Limit
Units
Notes
16
86
ps
(p-p)
1, 2
PCIe Gen2 Lo Band (5.0 GT/s)
SSC = < -0.5%
0.02
3
ps
(RMS)
1, 2
PCIe Gen2 Hi Band (5.0 GT/s)
SSC = < -0.5%
0.92
3.1
ps
(RMS)
1, 2
tjphPCIeG3-CC
PCIe Gen3 (8.0 GT/s)
SSC = < -0.5%
0.37
1
ps
(RMS)
1, 2
tjphPCIeG4-CC
PCIe Gen4 (16.0 GT/s)
SSC = < -0.5%
0.37
0.5
ps
(RMS)
1, 2, 3,
4
tjphPCIeG5-CC
PCIe Gen5 (32.0 GT/s)
SSC = < -0.5%
N/A
0.15
ps
(RMS)
1, 2, 3,
5
tjphPCIeG1-SRIS
PCIe Gen1 (2.5 GT/s)
SSC = < -0.3%
14
n/a
ps
(p-p)
1, 2, 6
tjphPCIeG2-SRIS
PCIe Gen2 (5.0 GT/s)
SSC = < -0.3%
1.4
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG3-SRIS
PCIe Gen3 (8.0 GT/s)
SSC = < -0.3%
0.42
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG4-SRIS
PCIe Gen4 (16.0 GT/s)
SSC = < -0.3%
0.36
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG5-SRIS
PCIe Gen5 (32.0 GT/s)
SSC = < -0.3%
N/A
n/a
ps
(RMS)
1, 2, 6
tjphPCIeG2-CC
PCIe Phase Jitter
(Common Clocked
Architectures)
PCIe Phase Jitter
(SRIS Architectures)
1
2
3
4
5
6
Minimum
Typical Maximum
The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the
data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table.
Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20GS/s
or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements.
Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to
an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the
2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA
measurements have both been done and produce different results the RTO result must be used.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content.
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification
limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a
clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by Ö2.
© 2021 Renesas Electronics Corporation.
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5P49V6975 Datasheet
10. Features and Functional Blocks
10.1 Device Startup and Power-on-Reset
The 5P49V6975 has an internal power-up reset (POR) circuit. All VDDs must be connected to the desired supply voltage to trigger a POR.
The user can define specific default configurations through internal One-Time-Programmable (OTP) memory -- either the user or factory can
program the default configuration. Contact Renesas if a specific factory-programmed default configuration is required, or refer to the VersaClock
6E Programming Guide.
The device will identity which of the two modes to operate in by the state of the OUT0_SEL_I2CB pin at POR. Both modes’ default configurations
can be programmed as follows:
1.
Software Mode (I2C): OUT0_SEL_I2CB is low at POR.
The I2C interface will be open to users for in-system programming, overriding device default configurations at any time.
2.
Hardware Select Mode: OUT0_SEL_I2CB is high at POR.
The device has been programmed to load OTP at power-up (REG0[7] = 1). The device will load internal registers according to Table 19.
Power-Up Behavior.
Internal OTP memory can support up to four configurations, which selectable by the SEL0/SEL1 pins.
At POR, logic levels at SEL0 and SEL1 pins must be settled, which results in the selected configuration to be loaded at power up.
After the first 10ms of operation, the levels of the SELx pins can be changed, either to low or to the same level as VDDD/VDDA. The SELx
pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. After a pin level change,
the device must not be interrupted for at least 1ms so that the new values have time to load and take effect.
Table 19. Power-Up Behavior
OUT0_SEL_I2CB
at POR
SEL1
1
SEL0
I2C
Access
REG0:7
Config
0
0
No
0
0
1
0
1
No
0
1
1
1
0
No
0
2
1
1
1
No
0
3
0
X
X
Yes
1
I2C
defaults
0
X
X
Yes
0
0
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5P49V6975 Datasheet
10.2 Reference Clock and Selection
The 5P49V6975 supports up to two clock inputs:
Internal crystal input: This can be driven by a single ended clock.
Clock input (CLKIN, CLKINB): This is a fully differential input that only accepts a reference clock. A single-ended clock can also drive it on
CLKIN.
Figure 7.
Clock Input Diagram Internal Logic
Internal
Cystal
CLKIN
CLKINB
PRIMSRC
Reg 0x13[1]
CLKSEL
OTP
and
Control
Logic
10.3 Manual Switchover
The CLKSEL pin selects the input clock between either the internal crystal or (CLKIN, CLKINB). CLKSEL polarity can be changed by I2C
programming (Byte 0x13[1]) as shown in the following table.
0 = Internal crystal (default)
1 = CLKIN, CLKINB
Table 20. Input Clock Select
PRIMSRC
CLKSEL
Source
0
0
Internal crystal
0
1
CLKIN, CLKINB
1
0
CLKIN, CLKINB
1
1
Internal crystal
When SM[1:0] is “0x”, the redundant inputs are in manual switchover mode. In this mode, CLKSEL pin is used to switch between the primary
and secondary clock sources. The PRIMSRC bit determines the primary and secondary clock source setting. During the switchover, no glitches
will occur at the output of the device, although there may be frequency and phase drift depending on the exact phase and frequency relationship
between the primary and secondary clocks.
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10.4 Programmable Loop Filter
The device PLL loop bandwidth operating range depends on the input reference frequency (Fref).
Table 21. Loop Filter Settings
Input Reference
Frequency (MHz)
Loop Bandwidth
Minimum (kHz)
Loop Bandwidth
Maximum (kHz)
1
40
126
350
300
1000
10.5 Fractional Output Dividers (FOD)
The 5P49V6975 has four fractional output dividers (FOD). Each FOD is comprised of a 12-bit integer counter and a 24-bit fractional counter.
The output divider can operate in integer divide only mode for improved performance, or use the fractional counters to generate a clock
frequency accurate to 50ppb.
FODs support the following features.
10.5.1 Individual Spread Spectrum Modulation
The output clock frequencies can be modulated to spread energy across a broader range of frequencies, thereby lowering system EMI. Each
divider has individual spread ability. Spread modulation independent of output frequency, a triangle wave modulation between 30 and 63kHz.
Spread spectrum can be applied to any output clock, clock frequency, or spread amount from ±0.25% to ±2.5% center-spread and -0.5% to -5%
down-spread.
10.5.2 Bypass Mode
Bypass mode (divide by 1) allows the output to behave as a buffered copy from the input or another FOD.
10.5.3 Cascaded Mode
As shown in the block diagram on page 1, FODs can be cascaded for lower output frequency.
For example, if OUT1 is configured to run at 12.288MHz and needs another 48kHz output, the user can cascade FOD2 by taking input from
OUT1, with a divide ratio of 256. As a result, OUT 2 runs at 48kHz while in alignment with 12.288MHz on OUT1.
10.5.4 Dividers Alignment
Each output divider block has a synchronizing pulse to provide startup alignment between outputs dividers. This allows alignment of outputs for
low skew performance.
When the 5P49V6975 is in hardware select mode, outputs are automatically aligned at POR. The same synchronization reset is also triggered
when switching between configurations with the SEL0/1 pins. This ensures that the outputs remain aligned in every configuration.
When the 5P49V6975 is using software mode, I2C is used to reprogram an output divider during operation, and therefore, alignment can be
lost. Alignment can be restored by manually triggering a reset through I2C.
The outputs are aligned on the falling edges of each output by default. Rising edge alignment can also be achieved by using the programmable
skew feature to delay the faster clock by 180 degrees. The programmable skew feature also allows for fine tuning of the alignment.
© 2021 Renesas Electronics Corporation.
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5P49V6975 Datasheet
10.5.5 Programmable Skew
The 5P49V6975 can skew outputs by quadrature values. The skew on each output can be adjusted from 0 to 360 degrees. Skew is adjusted
in units equal to 1/32 of the VCO period. As a result, for 100MHz output and a 2800MHz VCO, the user can select how many 11.161ps units to
be added to the skew (resulting in units of 0.402 degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so on. The granularity of the skew
adjustment is always dependent on the VCO period and the output period.
10.6 Output Drivers
Device output drivers can individually support the following features:
2.5V or 3.3V voltage level for HCSL/LVPECL operation
1.8V, 2.5V, or 3.3V voltage levels for CMOS/LVDS operation
CMOS supports four operating modes:
• CMOSD: OUTx and OUTxB 180 degrees out of phase
• CMOSX2: OUTx and OUTxB phase-aligned
• CMOS1: only OUTx pin is on
• CMOS2: only OUTxB pin is on
When a given output is configured to CMOSD or CMOSX2, then all previously described configuration and control apply equally to both
pins.
Independent output enable/disabled by register bits. When disabled, an output can be either in a logic 1 state or Hi-Z.
The following options are used to disable outputs:
Output turned off by I2C
Output turned off by SD/OE pin
Output unused, which means it is turned off regardless of OE pin status
10.7 SD/OE Pin Function
The SD/OE pin can be programmed as follows:
OE output enable (low active)
OE output enable (high active)
Global shutdown (low active)
Global shutdown (high active)
Output behavior when disabled is also programmable. The user can select the output driver behavior when it is off as follows:
OUTx pin high, OUTxB pin low (controlled by SD/OE pin)
OUTx/OUTxB Hi-Z (controlled by SD/OE pin)
OUTx pin high, OUTxB pin low (configured through I2C)
OUTx/OUTxB Hi-Z (configured by I2C)
The user can disable the output with either I2C or SD/OE pin. For more information, see the VersaClock 6E Programming Guide.
© 2021 Renesas Electronics Corporation.
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5P49V6975 Datasheet
10.8 I2C Operation
The 5P49V6975 acts as a slave device on the I2C bus using one of the two I2C addresses (0xD0 or 0xD4) to allow multiple devices to be used
in the system. The interface accepts byte-oriented block write and block read operations.
Address bytes (2 bytes) specify the register address of the byte position of the first register to write or read.
Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first).
Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not be moved into the
registers until the STOP bit is received, at which point, all data received in the block write will be written simultaneously.
For full electrical I2C compliance, use external pull-up resistors for SDATA and SCLK.
Figure 8.
I2C R/W Sequence
© 2021 Renesas Electronics Corporation.
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5P49V6975 Datasheet
11. Typical Application Circuit
Figure 9.
Typical Application Circuit
© 2021 Renesas Electronics Corporation.
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5P49V6975 Datasheet
11.1 Input – Driving the CLKIN
11.1.1 Wiring the CLKIN Pin to Accept Single-Ended Inputs
CLKIN cannot take a signal larger than 1.2V pk-pk due to the 1.2V regulated input inside. However, since it is internally AC coupled it can
accept both LVDS and LVPECL input signals.
Occasionally it may be desired to have CLKIN to take CMOS levels. The following example shows how this can be achieved. This configuration
has three properties:
1. Total output impedance of Ro and Rs matches the 50Ω transmission line impedance
2. Vrx voltage is generated at the CLKIN, which maintains the LVCMOS driver voltage level across the transmission line for best S/N
3. R1–R2 voltage divider values ensure that Vrx p-p at CLKIN is less than the maximum value of 1.2V
Figure 10. Recommended Schematic for Driving CLKIN with LVCMOS Driver
Table 22 shows resistor values that ensure the maximum drive level for the CLKIN port is not exceeded for all combinations of 5% tolerance
on the driver VDD, VDDO0 and 5% resistor tolerances. The values of the resistors can be adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the impedance of the R1–R2 divider. To better assist this assessment, the total load (Ro+Rs+R1+R2) on the
driver is included in the table.
Table 22. Nominal Voltage Divider Values for Overdriving CLKIN with Single-Ended Driver
LVCMOS Diver VDD
Ro + Rs
R1
R2
Vrx (peak)
Ro+Rs+R1+R2
3.3
50.0
130
75
0.97
255
2.5
50.0
100
100
1.00
250
1.8
50.0
62
130
0.97
242
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5P49V6975 Datasheet
11.1.2 Driving CLKIN with Differential Clock
CLKIN/CLKINB will accept DC coupled HCSL/LVPECL/LVDS signals.
Figure 11. CLKIN, CLKINB Input Driven by an HCSL Driver
Q
CLKIN
nQ
CLKINB
VersaClock 6 Receiver
11.2 Output – Single-ended or Differential Clock Terminations
11.2.1 LVDS Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should
be selected to match the differential impedance (Zo) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel
resistor at the receiver and a 100Ω. Differential transmission-line environment. In order to avoid any transmission-line reflection issues, the
components should be surface mounted and must be placed as close to the receiver as possible. The standard termination schematic as
shown in figure Standard Termination or the termination of figure Optional Termination can be used, which uses a center tap capacitance to
help filter common mode noise. The capacitor value should be approximately 50pF. In addition, since these outputs are LVDS compatible,
the input receiver's amplitude and common-mode input range should be verified for compatibility with the Renesas LVDS output.
For example, the LVDS outputs can be AC coupled by placing capacitors between the LVDS outputs and the 100Ω shunt load. This is a
common practice with a receiver with internal self-bias circuitry. If using a non-standard termination, it is recommended to contact Renesas
and confirm that the termination will function as intended.
Figure 12. Standard and Optional Terminations
LVDS
Driver
ZO
T
LVDS
Receiver
Standard
LVDS
Driver
ZT
2 LVDS
ZT Receiver
ZO
Optional
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5P49V6975 Datasheet
11.2.2 LVPECL Termination
The clock layout topology shown below are typical terminations for LVPECL outputs. The differential outputs generate ECL/LVPECL compatible
outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal
distortion. For VDDO = 2.5V, the VDDO – 2V is very close to ground level. The R3 in 2.5V LVPECL Output Termination can be eliminated and
the termination is shown in 2.5V LVPECL Output Termination (2).
Figure 13. 3.3V LVPECL Output Termination
Figure 15. 2.5V LVPECL Output Termination
VDDO = 2.5V
3.3V
VD DO = 3.3V
Zo=50ohm
Zo=50ohm
+
VersaClock 6+
Output Driver
+
VersaClock 6+
Output Driver
Receiver
Zo=50ohm
2.5V
Receiver
Zo=50ohm
-
-
LVPECL
R1
50ohm
2.5V LVPECL
Driver
R2
50ohm
R1
50ohm
RTT
50ohm
R3
18ohm
Figure 14. 3.3V LVPECL Output Termination (2)
Figure 16. 2.5V LVPECL Output Termination (2)
3.3V
VD DO = 3.3V
R3
125ohm
R2
50ohm
VDDO = 2.5V
2.5V
3.3V
R4
125ohm
Zo=50ohm
+
Zo=50ohm
+
VersaClock 6+
Output Driver
VersaClock 6+
Output Driver
-
Zo=50ohm
LVPECL
Receiver
Zo=50ohm
Receiver
R1
84ohm
2.5V LVPECL
R2
84ohm
R1
50ohm
R2
50ohm
Figure 17. 2.5V LVPECL Output Termination (3)
2.5V
VDDO = 2.5V
R1
250ohm
2.5V
R3
250ohm
Zo=50ohm
+
VersaClock 6+
Output Driver
Receiver
Zo=50ohm
2.5V LVPECL
© 2021 Integrated Device Technology, Inc.
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R2
62.5ohm
R4
62.5ohm
February 11, 2021
5P49V6975 Datasheet
11.2.3 HCSL Termination
HCSL termination scheme applies to both 3.3V and 2.5V VDDO.
Figure 18. HCSL Receiver Terminated
33
Figure 19. HCSL Source Terminated
Zo=50ohm
Zo=50ohm
33
+
VersaClock 6+
Output Driver
+
Receiver
33
Zo=50ohm
VersaClock 6+
Output Driver
Receiver
Zo=50ohm
33
-
-
HCSL
HCSL
50
50
50
50
11.2.4 LVCMOS Termination
Each output pair can be configured as a standalone CMOS or dual-CMOS output driver. An example of CMOSD driver termination is shown in
the following figure:
CMOS1 – Single CMOS active on OUTx pin
CMOS2 – Single CMOS active on OUTxB pin
CMOSD – Dual CMOS outputs active on both OUTx and OUTxB pins, 180 degrees out of phase
CMOSX2 – Dual CMOS outputs active on both OUTx and OUTxB pins, in-phase.
Figure 20. LVCMOS Termination
33
Zo=50ohm
+
VersaClock 6+
Output Driver
Receiver
33
Zo=50ohm
-
CMOSD
12. Package Outline Drawings
The package outline drawings are located at the end of this document. The package information is the most current data available and is subject
to change without revision of this document.
© 2021 Integrated Device Technology, Inc.
26
February 11, 2021
5P49V6975 Datasheet
13. Marking Diagram
1. Line 1 is the truncated part number.
6975A
ddd
YWW**$
2. “ddd” denotes the dash code.
3. “YWW” is the last digit of the year and week that the part was assembled.
4. “**” denotes the sequential lot number.
5. “$” denotes the mark code.
14. Ordering Information
Orderable Part Number
Package
Carrier Type
Temperature
5P49V6975AdddLTGI
4 × 4 mm 24-LGA
Tray
-40° to +85°C
5P49V6975AdddLTGI8
4 × 4 mm 24-LGA
Tape and Reel
-40° to +85°C
5P49V6975A000LTGI
4 × 4 mm 24-LGA
Tray
-40° to +85°C
5P49V6975A000LTGI8
4 × 4 mm 24-LGA
Tape and Reel
-40° to +85°C
1.
2.
“ddd” denotes factory programmed configurations based on required settings. Please contact factory for factory programming.
“000” denotes un-programmed parts for user customization.
© 2021 Integrated Device Technology, Inc.
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February 11, 2021
5P49V6975 Datasheet
15. Revision History
Revision Date
Description of Change
February 11, 2021
Corrected typo for TR and TF units from ns to ps (Table 11).
October 4, 2019
▪ Updated Absolute Maximum Ratings table.
▪ Updated PCI Express Jitter Performance tables (Table 17 and Table 18).
▪ Updated Electrical Characteristics tables (Table 9, Table 11, and Table 14).
June 20, 2019
▪
▪
▪
▪
▪
April 27, 2018
Updated Supply Voltage, Current Consumption and AC Timing Characteristics electrical tables.
March 15, 2018
Updated Current Consumption, AC Timing, LVDS, and CMOS electrical tables.
February 15, 2018
Updated package outline drawings.
January 31, 2018
Updated ordering information package code designator from NLG to LTG.
January 10, 2018
Initial release.
PCIe specification updated.
Added recommended power ramp time.
Expanded spread spectrum value range.
I2C tolerant voltage footnote changed to 3.3V.
LVDS Termination section allows AC-coupling for LVDS signals.
© 2021 Integrated Device Technology, Inc.
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February 11, 2021
24-LGA Package Outline Drawing
4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch
LTG24T2, PSC-4481-02, Rev 00, Page 1
24-LGA Package Outline Drawing
4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch
LTG24T2, PSC-4481-02, Rev 00, Page 2
Package Revision History
Date Created
Rev No.
Sept 15, 2017
Rev 00
Description
Initial Release
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