5P61006PGGI

DATASHEET IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER Description Features The IDT5P61006 is a low-cost, low voltage zero delay buffer for DDR2/800 applications. Using analog/digital Phase-Locked Loop techniques, the device accepts a 425 MHz clock input and provides a zero-delay output of the same frequency. • • • • • • • The IDT5P61006 features an on-chip feedback circuit, eliminating the need for external feedback traces and components. Packaged in 8-pin TSSOP For DDR2/800 applications Maximum input clock frequency of 425 MHz Output duty cycle of 45/55 Operating voltage of 1.8 V Industrial temperature range of -40 to +85° C Advanced, low-power CMOS process Block Diagram 1.8V VDD OUTN INP OUTP INN PLL Internal Feedback GND IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 1 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Pin Assignment VSS 1 8 VDD INP 2 7 OUTP INN 3 6 OUTN VSS 4 5 VDD 8-Pin Package Pin Descriptions Pin Number Pin Name Pin Type 1 VSS GND Connect this pin to ground. 2 INP Input Clock input with a (10k-100k Ohm) internal pull-down resistor. 3 INN Input Complementary clock input with a (10k-100k Ohm) internal pull-down resistor. 4 VSS GND Connect this pin to ground. 5 VDD Power Connect this pin to 1.8 V. 6 OUTN Output Complementary Clock output. PLL power down and output will be LOW when there is no clock input signal or both INP & INN pins are LOW. 7 OUTP Output Clock output. PLL power down and output will be LOW when there is no clock input signal or both INP & INN pins are LOW. 8 VDD Power Connect this pin to 1.8 V. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER Pin Description 2 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB External Components PCB Layout Recommendations The IDT5P61006 requires a minimum number of external components for proper operation. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Decoupling Capacitor 1) The 4.7 µF, 0.1 µF and 2200 pF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Decoupling capacitors of 4.7 µF, 0.1 µF and 2200 pF must be connected between VDD (pins 5, 8) and GND (pins 1, 4), as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5P61006. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5P61006. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 2.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured with respect to GND) +1.7 IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 3 Typ. +1.8 Max. Units +85 °C +1.9 V IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Electrical Characteristics - Input/Supply/Common Output Parameters (note1) Unless stated otherwise, VDD = 1.8 V ±0.1 V, Ambient Temperature -40 to +85° C Parameter Symbol Supply Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 1.7 1.8 1.9 V no load, 333 MHz 65 75 mA no load, 400 MHz 73 85 mA 0.35VDD V Low-level input voltage VIL INP, INN High level input voltage VIH INP, INN DC input signal voltage (note 2) VIN Differential input signal voltage (note 3) VID Input differential cross voltage (note4) VIX Output differential signal voltage VOD Output differential cross voltage (note4) VOX Output High Voltage VOH 0.65 xVDD -0.3 DC - INP, INN VOL 0 0.3 DC - OUTP, OUTN Input Capacitance Output Capacitance CIN 5 COUT V VDD + 0.4 V 0.6 VDD/2 - 0.10 IOH = -100 mA VDD/2 + 0.10 VDD - 0.2 1.1 IOH = 100 mA V V V V 1.45 0.25 IOH = 9 mA 5 VDD+0.3 VDD/2 - 0.15 VDD/2 VDD/2 + 0.15 IOH = -9 mA Low-level Output Voltage V V 0.1 V 0.6 VI = GND or VDD 2 3 pF VOUT = GND or VDD 2 3 pF Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing. 5. Guaranteed by design, not 100% tested in production. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 4 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Timing Requirements Unless stated otherwise,VDD = 1.8 V ±0.1V, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Max clock frequency freqOP Device Operation 125 425 MHz Application frequency range freqAPP Driving to DDR2 Memory 160 400 MHz 30 70 % 6 uS Input clock duty cycle dtin CLK stabilization TSTAB Note 1 Note 1: Output clock stabilization time from the power-down mode after the clock transition at INP/INN. Switching Characteristics (note 1) Unless stated otherwise, VDD = 1.8 V ±0.1 V, Ambient Temperature -40 to +85° C Parameter Symbol Period Jitter tjit(per) Half-period Jitter tjit(hper) Input Slew Rate SLr1(i) Output Clock Slew Rate Cycle-Cycle Period Jitter Static Phase Offset Conditions Min. Max. Units -40 40 ps 160 MHz to 270 MHz -75 75 ps 271 MHz to 400 MHz -50 50 ps 1 2.5 4 V/ns SLr1(o) 1.5 2.5 3 V/ns tjitt(cc+) 0 40 ps tjit(cc-) 0 -40 ps -160 -60 ps tSPO2 Input Clock Typ. Input to Output PLL Loop Bandwidth (-3dB from unity gain) 2.0 MHz Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset between input and output shifted by device. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 5 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Diagrams VDD VDD/2 SCOPE V(CLKC) C = 10pF Z=60O Z=50O R = 10O Z=2.97" V(TT) Z=60O R=1MO C=1pF Z=50O R = 10O Z=2.97" V(CLKC) C = 10pF V(TT) R=1MO C=1pF Note: V(TT) = GND -VDD/2 GND Figure 2: Output load test circuit Figure 1: IBIS model output load OUTP OUTP OUTN INP OUTN tc(n) tc(n+1) INN Tjit(cc) = tc(n) ± tc(n+1) t(Ø)n+1 t(Ø)n Figure 4: Static phase offset (from input to output) Figure 3: Cycle-cycle jitter OUTP OUTN C lock inputs and outputs 80 % 80% 20% 20% tjit(hper_n) tjit(hper_n + 1) 1 f0 t slr t slf tjit(hper) = tjit(hper_n) - 1 2xf0 Figure 6: Half Period Jitter Figure 5: Input and Output Slew Rates IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 6 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Marking Diagram YWW$ 006GI Notes: 1. YWW is the last digits of the year and week that the part was assembled. 2. “$” is the mark code. 3. “G” denotes RoHS compliant package. 4. “I” denotes industrial grade. 5. Bottom marking: Lot number and country of origin if not USA. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 7 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Package Outline and Package Dimensions (8-pin TSSOP, 4.4 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Inches Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° 0.004 A A 1 c -C e b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 5P61006PGGI 5P61006PGGI8 see page 7 Tubes Tape and Reel 8-pin TSSOP 8-pin TSSOP -40 to +85° C -40 to +85° C “G”after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 8 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Revision History Rev. Originator Date Description of Change A K. Beckmeyer 04/16/08 New device/datasheet; Preliminary release. B K. Beckmeyer 10/20/10 Moved to final. C K. Beckmeyer 08/22/11 Added top-side marking. IDT® 1.8 VOLT DDR2/800 ZERO DELAY BUFFER 9 IDT5P61006 REV C 082211 IDT5P61006 1.8 VOLT DDR2/800 ZERO DELAY BUFFER DIFFERENTIAL ZDB Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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