1.8V to 3.3V LVCMOS High-Performance
Clock Buffer Family
5PB11xx
DATASHEET
Description
Features
The 5PB11xx is a high-performance LVCMOS clock buffer
family. It has best-in-class additive phase jitter of 50fsec
RMS.
• High-performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock
•
•
•
•
•
•
•
There are five different fan-out variations available: 1:2 to
1:10.
The 5PB11xx also supports a synchronous glitch-free output
enable (OE) function to eliminate any potential intermediate
incorrect output clock cycles when enabling or disabling
outputs. It’s available in various packages and can operate
from a 1.8V to 3.3V supply.
•
buffer
Very low pin-to-pin skew < 50ps
Very low additive jitter < 50fs
Supply voltage: 1.8V to 3.3V
3.3V tolerant input clock
fMAX = 200MHz
Integrated serial termination for 50 channel
Packaged in 8-, 14-, 16-, 20-pin TSSOP and as small as
2 × 2 mm DFN and QFN packages
Industrial (-40°C to +85°C) and extended (-40°C to
+105°C) temperature ranges
Block Diagram
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Yn
1G
5PB11xx SEPTEMBER 21, 2017
1
©2017 Integrated Device Technology, Inc.
5PB11xx DATASHEET
Pin Assignments for TSSOP Packages
CLKIN 1
1G 2
Y0 3
GND 4
CLKIN
1G
1
2
Y0
GND
3
5PB1102PGG
8
7
6
5
8
7
5PB1104PGG
6
4
5
Y1
NC
VDD
NC
CLKIN
1G
1
2
Y0
GND
3
VDD
Y4
GND
Y1
Y3
VDD
Y2
4
5
6
1
2
Y0
GND
3
Y6
9
8
7
CLKIN
1G
VDD
Y4
GND
5PB1106PGG
14 Y1
13 Y3
12 VDD
11 Y2
10 GND
4
5
5PB1108PGG
6
Y5
VDD
16 Y1
15 Y3
14 VDD
13 Y2
12 GND
CLKIN
1G
1
2
Y0
GND
3
4
5
VDD
Y4
GND
5PB1110PGG
6
7
Y6 8
VDD 9
Y9 10
20 Y1
19 Y3
18 VDD
17 Y2
16 GND
15
14
13
12
11
Y5
VDD
Y7
Y8
GND
11 Y5
10 VDD
9 Y7
7
8
Pin Descriptions for TSSOP Packages
LVCMOS
Clock Input
Clock Output
Enable
LVCMOS Clock Output
Supply Voltage
Ground
CLKIN
1G
Y0, Y1, . . . Y9
VDD
GND
5PB1102PGG
1
2
3, 8
6
4
5PB1104PGG
1
2
3, 8, 5, 7
6
4
5PB1106PGG
1
2
3, 14, 11, 13, 6, 9
5, 8, 12
4, 7, 10
5PB1108PGG
1
2
3, 16, 13, 15, 6, 11, 8, 9
5, 10, 14
4, 7, 12
5PB1110PGG
1
2
3, 20, 17, 19, 6, 15, 8, 13, 12, 10
5, 9, 14, 18
4, 7, 11, 16
Device Number
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
2
SEPTEMBER 21, 2017
5PB11xx DATASHEET
5
CLKIN 1
1G 2
8
7
3
4
6
5
Y0
GND
VDD
Y4
Y1
Y3
VDD
Y2
VDD
Y3
Y1
CLKIN
1G
Y1
Y3
12
11
5PB1106CMG
10
3
9
4
5 6 7 8
1
2
1G
Y0
GND
5PB1104CMG
20 19 18 17 16
16 15 14 13
VDD
Y2
GND
Y5
Y0
GND
1
2
VDD
Y4
GND
4
5
15 Y2
14 GND
3 5PB1110NDG 13 Y5
12
11
VDD
Y7
6 7 8 9 10
Y6
VDD
Y9
GND
Y8
4
NC
VDD
NC
NC
6
NC
VDD
5PB1102CMG
Y1
Y3
3
Y1
1G
Y0
GND
8
7
GND
1
2
CLKIN
CLKIN
1G
CLKIN
Pin Assignments for DFN/QFN Packages
16 15 14 13
GND
Y4
VDD
Y2
GND
Y5
Y7
VDD
VDD
12
11
5PB1108CMG
10
3
9
4
5 6 7 8
1
2
Y6
Y0
GND
Pin Descriptions for DFN/QFN Packages
LVCMOS
Clock Input
Clock Output
Enable
LVCMOS Clock Output
Supply Voltage
Ground
CLKIN
1G
Y0, Y1, . . . Y9
VDD
GND
5PB1102CMG
1
2
3, 8
6
4
5PB1104CMG
1
2
3, 5, 7, 8
6
4
5PB1106CMG
15
16
1, 4, 9, 11, 13, 14
3, 8, 12
2, 5, 10
5PB1108CMG
15
16
1, 4, 6, 7, 9, 11, 13, 14
3, 8, 12
2, 5, 10
5PB1110NDG
19
20
1, 4, 6, 8, 10, 11, 13, 15, 17, 18
3, 7, 12, 16
2, 5, 9, 14
Device Number
Output Logic Table
Inputs
Output
CLKIN
1G
Yn
X
L
L
L
H
L
H
H
H
After at least three cycles of input clock toggling. Output Enable function is asynchronous to eliminate any intermediate incorrect output clock cycles during transition which may cause
frequency peaking to the downstream device.
SEPTEMBER 21, 2017
3
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5PB11xx. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD
3.465V
Output Enable and All Outputs
-0.4 V to VDD+0.5 V
CLKIN
-0.4 V to 3.465V
Ambient Operating Temperature (industrial)
-40 to +85C
Ambient Operating Temperature (extended)
-40 to +105C
Storage Temperature
-65 to +150C
Junction Temperature
125C
Soldering Temperature
260C
Recommended Operation Conditions
Parameter
Max.
Units
Ambient Operating Temperature (industrial)
Min.
-40
+85
C
Ambient Operating Temperature (extended)
-40
+105
C
+1.71
+3.465
V
Power Supply Voltage (measured in respect to GND)
Typ.
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Operating Voltage
VDD
Input High Voltage, CLKIN
VIH
Note 1.
Input Low Voltage, CLKIN
VIL
Note 1.
Input High Voltage, 1G
VIH
Input Low Voltage, 1G
VIL
Min.
Typ.
1.71
0.7 x VDD
1.6
Output High Voltage
VOH
IOH = -5mA.
Output Low Voltage
VOL
IOL = 5mA.
Nominal Output Impedance
ZO
Input Capacitance
CIN
Max.
Units
1.89
V
3.465
V
0.3 x VDD
V
VDD
V
0.6
V
1.4
V
0.4
V
50
CLKIN, 1G pin.
5
pF
5PB1102
100MHz, no load, 25°C.
6
8
5PB1104
100MHz, no load, 25°C.
12
13
100MHz, no load, 25°C.
15
18
5PB1108
100MHz, no load, 25°C.
20
23
5PB1110
100MHz, no load, 25°C.
23
27
Operating Supply Current
5PB1106
IDD
mA
Notes: 1. Nominal switching threshold is VDD/2
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
4
SEPTEMBER 21, 2017
5PB11xx DATASHEET
VDD = 2.5V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Operating Voltage
VDD
Input High Voltage, CLKIN
VIH
Note 1.
Input Low Voltage, CLKIN
VIL
Note 1.
Input High Voltage, 1G
VIH
Input Low Voltage, 1G
VIL
Min.
Typ.
2.375
0.7 x VDD
1.8
Output High Voltage
VOH
IOH = -8mA.
Output Low Voltage
VOL
IOL = 8mA.
Nominal Output Impedance
ZO
Input Capacitance
CIN
Max.
Units
2.625
V
3.465
V
0.3 x VDD
V
VDD
V
0.7
V
1.9
V
0.5
V
50
CLKIN, 1G pin.
5
pF
5PB1102
100MHz, no load, 25°C.
9
11
5PB1104
100MHz, no load, 25°C.
15
18
100MHz, no load, 25°C.
21
24
Operating Supply Current
5PB1106
IDD
mA
5PB1108
100MHz, no load, 25°C.
27
31
5PB1110
100MHz, no load, 25°C.
32
37
Typ.
Max.
Units
3.465
V
VDD = 3.3V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Operating Voltage
VDD
Input High Voltage, CLKIN
VIH
Note 1.
Input Low Voltage, CLKIN
VIL
Note 1.
Input High Voltage, 1G
VIH
Input Low Voltage, 1G
VIL
Min.
3.135
0.7 x VDD
2
Output High Voltage
VOH
IOH = -12mA.
Output Low Voltage
VOL
IOL = 12mA.
Nominal Output Impedance
ZO
Input Capacitance
CIN
3.465
V
0.3 x VDD
V
VDD
V
0.8
V
2.4
V
0.7
V
50
CLKIN, 1G pin.
5
pF
5PB1102
100MHz, no load, 25°C.
12
13
5PB1104
100MHz, no load, 25°C.
20
22
100MHz, no load, 25°C.
25
30
Operating Supply Current
5PB1106
IDD
5PB1108
100MHz, no load, 25°C.
35
38
5PB1110
100MHz, no load, 25°C.
40
45
SEPTEMBER 21, 2017
5
mA
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Input Frequency
Output Rise Time (2pF load)
Min. Typ.
0
Max.
Units
200
MHz
ns
tOR
0.36V to 1.44V, CL = 2pF.
0.5
0.75
Output Fall Time (2pF load)
tOF
1.44V to 0.36V, CL = 2pF.
0.5
0.75
ns
Output Rise Time (5pF load)
tOR
0.36V to 1.44V, CL = 5pF.
0.8
1.0
ns
Output Fall Time (5pF load)
tOF
1.44V to 0.36V, CL = 5pF.
0.8
1.0
ns
3
ms
Start-up Time
tSTART-UP Part start-up time for valid outputs after VDD ramp-up.
Propagation Delay
Note 1.
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz.
1.5
Output to Output Skew (5PB1102/04)
Rising edges at VDD/2, Note 2.
Output to Output Skew (5PB1106)
1.9
2.5
ns
0.05
ps
35
50
ps
Rising edges at VDD/2, Note 2.
35
58
ps
Output to Output Skew (5PB1108/10)
Rising edges at VDD/2, Note 2.
45
Device to Device Skew
Rising edges at VDD/2.
65
ps
200
ps
Output Enable Time
tEN
CL < 5pF.
3
cycles
Output Disable Time
tDIS
CL < 5pF.
3
cycles
Duty Cycle
tDC
See note 3.
50
%
VDD = 2.5V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Input Frequency
Output Rise Time (2pF load)
Min. Typ.
0
Max.
Units
200
MHz
tOR
0.5V to 2.0V, CL = 2pF.
0.4
0.7
ns
Output Fall Time (2pF load)
tOF
2.0V to 0.5V, CL = 2pF.
0.4
0.7
ns
Output Rise Time (5pF load)
tOR
0.5V to 2.0V, CL = 5pF.
0.75
1.0
ns
Output Fall Time (5pF load)
tOF
2.0V to 0.5V, CL = 5pF.
0.75
1.0
ns
3
ms
Start-up Time
tSTART-UP Part start-up time for valid outputs after VDD ramp-up.
Propagation Delay (5PB1102/04)
Propagation Delay (5PB1106/08)
Note 1.
Propagation Delay (5PB1110)
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz.
1.9
2.4
2.9
ns
2.0
2.4
3.3
ns
2.0
2.4
3.0
ns
0.05
ps
Output to Output Skew (5PB1102/04)
Rising edges at VDD/2, Note 2.
35
50
ps
Output to Output Skew (5PB1106)
Rising edges at VDD/2, Note 2.
35
58
ps
Output to Output Skew (5PB1108/10)
Rising edges at VDD/2, Note 2.
45
65
ps
Device to Device Skew
Rising edges at VDD/2.
200
ps
3
cycles
3
cycles
Output Enable Time
tEN
CL < 5pF.
Output Disable Time
tDIS
CL < 5pF.
Duty Cycle
tDC
See note 3.
50
%
VDD = 3.3V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise.
Parameter
Symbol
Conditions
Input Frequency
Min. Typ.
0
Max.
Units
200
MHz
Output Rise Time (2pF load)
tOR
0.66V to 2.64V, CL = 2pF.
0.45
0.6
ns
Output Fall Time (2pF load)
tOF
2.64V to 0.66V, CL = 2pF.
0.45
0.6
ns
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
6
SEPTEMBER 21, 2017
5PB11xx DATASHEET
Max.
Units
Output Rise Time (5pF load)
Parameter
tOR
0.66V to 2.64V, CL = 5pF.
0.7
1.0
ns
Output Fall Time (5pF load)
tOF
2.64V to 0.66V, CL = 5pF.
0.7
1.0
ns
3
ms
Start-up Time
Symbol
Conditions
Min. Typ.
tSTART-UP Part start-up time for valid outputs after VDD ramp-up.
Propagation Delay (5PB1102/04)
Propagation Delay (5PB1106/08)
Note 1.
Propagation Delay (5PB1110)
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz.
1.7
2
2.4
ns
1.7
2
2.7
ns
1.7
2
2.5
ns
0.05
ps
Output to Output Skew (5PB1102/04)
Rising edges at VDD/2, Note 2.
35
50
ps
Output to Output Skew (5PB1106)
Rising edges at VDD/2, Note 2.
35
58
ps
Output to Output Skew (5PB1108/10)
Rising edges at VDD/2, Note 2.
45
65
ps
Device to Device Skew
Rising edges at VDD/2.
200
ps
Output Enable Time
tEN
CL < 5pF.
3
cycles
Output Disable Time
tDIS
CL < 5pF.
3
cycles
Duty Cycle
tDC
See note 3.
50
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle when VIH on CLKIN pin equals VDD power supply voltage. Consult IDT for tight duty cycle clock generators.
%
Phase Noise Plots
Figure 2. 5PB11xx Output Phase Noise 70.9fs
(12kHz to 20MHz)
Figure 1. 5PB11xx Reference Phase Noise 58.9fs
(12kHz to 20MHz)
The phase noise plots above show the low additive jitter of the 5PB11xx high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 58.9fs of RMS phase jitter while the output of 5PB11xx has about 70.9fs of RMS
phase jitter. This results in a low additive phase jitter of only 39fs.
SEPTEMBER 21, 2017
7
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Test Load and Circuit
50ohms
5 inches
CL = 5pF
Marking Diagrams (industrial temperature range)
YWW$
B11AAI
IDT5PB11
06PGGI
YYWW$
IDT5PB11
08PGGI
YYWW$
8-pin TSSOP
14-pin TSSOP
16-pin TSSOP
IDT5PB11
10PGGI
YYWW$
20-pin TSSOP
11AA
YW**
1106
Y**
XXX
YWW$
110I
1108
Y**
8-pin DFN
16-pin QFN
16-pin QFN
20-pin QFN
Notes:
1. “AA” denotes the last two digits of the part number for 8-TSSOP and DFN (e.g. 02, 04).
2. “**” is the lot sequence.
3. “XXX” denotes the last three characters of the Asm lot (20-QFN only).
4. “YYWW”, “YWW”, “YW”, or “Y” is the last digit(s) of the year and week that the part was assembled.
5. “$” denotes the mark code.
6. “G” after the two-letter package code denotes RoHS compliant package.
7. “I” denotes industrial temperature range device.
8. Bottom marking: LOT and COO (TSSOP only).
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
8
SEPTEMBER 21, 2017
5PB11xx DATASHEET
Marking Diagrams (extended temperature range)
YWW$
B11AAK
IDT5PB11
06PGGK
YYWW$
IDT5PB11
08PGGK
YYWW$
8-pin TSSOP
14-pin TSSOP
16-pin TSSOP
IDT5PB11
10PGGK
YYWW$
20-pin TSSOP
1AAK
YWW**
XXX
YWW$
110K
106K
YWW**
108K
YWW**
16-pin QFN
16-pin QFN
8-pin DFN
20-pin QFN
Notes:
1. “AA” denotes the last two digits of the part number for 8-TSSOP and DFN (e.g. 02, 04).
2. “**” is the lot sequence.
3. “XXX” denotes the last three characters of the Asm lot (20-QFN only).
4. “YYWW”, “YWW”, “YW”, or “Y” is the last digit(s) of the year and week that the part was assembled.
5. “$” denotes the mark code.
6. “G” after the two-letter package code denotes RoHS compliant package.
7. “K” denotes extended temperature range device.
8. Bottom marking: LOT and COO (TSSOP only).
Thermal Characteristics
Package
Applies to
ϴJA
ϴJC
ϴJB
Units
8-TSSOP
5PB1102, 5PB1104
122.0
58.2
139.3
°C/W; still air
14-TSSOP
5PB1106
84.5
44.2
64.5
°C/W; still air
16-TSSOP
5PB1108
80.9
43.3
60.1
°C/W; still air
20-TSSOP
5PB1110
72.5
37.9
49.8
°C/W; still air
8-DFN
5PB1102, 5PB1104
120.2
99.4
63.3
°C/W; still air
16-QFN
5PB1106, 5PB1108
115.6
83.1
61.8
°C/W; still air
20-QFN
5PB1110
49.6
94.7
5.1
°C/W; still air
SEPTEMBER 21, 2017
9
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
10
Package Outline and Dimensions (8-DFN, 2 x 2 mm Body, 0.5mm pitch)
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
SEPTEMBER 21, 2017
11
5PB11xx DATASHEET
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
Package Outline and Dimensions, cont. (8-DFN, 2 x 2 mm Body, 0.5mm pitch)
SEPTEMBER 21, 2017
5PB11xx DATASHEET
12
Package Outline and Dimensions (16-VFQFN, 2.5 x 2.5 mm Body, 0.4mm pitch)
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
SEPTEMBER 21, 2017
13
5PB11xx DATASHEET
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
Package Outline and Dimensions, cont. (16-VFQFN, 2.5 x 2.5 mm Body, 0.4mm pitch)
SEPTEMBER 21, 2017
5PB11xx DATASHEET
14
Package Outline and Dimensions (20-QFN, 3 x 3 mm Body, 0.4mm pitch)
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
SEPTEMBER 21, 2017
15
5PB11xx DATASHEET
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
Package Outline and Dimensions, cont. (20-QFN, 3 x 3 mm Body, 0.4mm pitch)
SEPTEMBER 21, 2017
5PB11xx DATASHEET
16
Package Outline and Dimensions (8-, 14-, 16-, 20-TSSOP)
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
SEPTEMBER 21, 2017
17
5PB11xx DATASHEET
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
Package Outline and Dimensions, cont. (8-, 14-, 16-, 20-TSSOP)
SEPTEMBER 21, 2017
5PB11xx DATASHEET
18
Package Outline and Dimensions, cont. (8-, 14-, 16-, 20-TSSOP)
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
SEPTEMBER 21, 2017
5PB11xx DATASHEET
Ordering Information (industrial temperature range)
Part / Order Number
5PB1102PGGI
5PB1102PGGI8
5PB1104PGGI
5PB1104PGGI8
5PB1106PGGI
5PB1106PGGI8
5PB1108PGGI
5PB1108PGGI8
5PB1110PGGI
5PB1110PGGI8
5PB1102CMGI
5PB1102CMGI8
5PB1104CMGI
5PB1104CMGI8
5PB1104CMGI/W*
5PB1106CMGI
5PB1106CMGI8
5PB1108CMGI
5PB1108CMGI8
5PB1110NDGI
5PB1110NDGI8
Marking
see page 8
Shipping Packaging
Package
Temperature
Tubes
8-TSSOP
-40 to +85 C
Tape and Reel
8-TSSOP
-40 to +85 C
Tubes
8-TSSOP
-40 to +85 C
Tape and Reel
8-TSSOP
-40 to +85 C
Tubes
14-TSSOP
-40 to +85 C
Tape and Reel
14-TSSOP
-40 to +85 C
Tubes
16-TSSOP
-40 to +85 C
Tape and Reel
16-TSSOP
-40 to +85 C
Tubes
20-TSSOP
-40 to +85 C
Tape and Reel
20-TSSOP
-40 to +85 C
Cut Tape
8-DFN
-40 to +85 C
Tape and Reel
8-DFN
-40 to +85 C
Cut Tape
8-DFN
-40 to +85 C
Tape and Reel
8-DFN
-40 to +85 C
Tape and Reel
8-DFN
-40 to +85 C
Cut Tape
16-QFN
-40 to +85 C
Tape and Reel
16-QFN
-40 to +85 C
Cut Tape
16-QFN
-40 to +85 C
Tape and Reel
16-QFN
-40 to +85 C
Tubes
20-QFN
-40 to +85 C
Tape and Reel
20-QFN
-40 to +85 C
* “/W” stands for tape and reel with pin 1 orientation: EIA-481-D. All other tape and reels options come with EIA-481-C pin 1
orientation.
SEPTEMBER 21, 2017
19
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Ordering Information (extended temperature range)
Part / Order Number
5PB1102PGGK
5PB1102PGGK8
5PB1104PGGK
5PB1104PGGK8
5PB1106PGGK
5PB1106PGGK8
5PB1108PGGK
5PB1108PGGK8
5PB1110PGGK
5PB1110PGGK8
5PB1102CMGK
5PB1102CMGK8
5PB1104CMGK
5PB1104CMGK8
5PB1106CMGK
5PB1106CMGK8
5PB1108CMGK
5PB1108CMGK8
5PB1110NDGK
5PB1110NDGK8
Marking
see page 9
Shipping Packaging
Package
Temperature
Tubes
8-TSSOP
-40 to +105 C
Tape and Reel
8-TSSOP
-40 to +105 C
Tubes
8-TSSOP
-40 to +105 C
Tape and Reel
8-TSSOP
-40 to +105 C
Tubes
14-TSSOP
-40 to +105 C
Tape and Reel
14-TSSOP
-40 to +105 C
Tubes
16-TSSOP
-40 to +105 C
Tape and Reel
16-TSSOP
-40 to +105 C
Tubes
20-TSSOP
-40 to +105 C
Tape and Reel
20-TSSOP
-40 to +105 C
Cut Tape
8-DFN
-40 to +105 C
Tape and Reel
8-DFN
-40 to +105 C
Cut Tape
8-DFN
-40 to +105 C
Tape and Reel
8-DFN
-40 to +105 C
-40 to +105 C
Cut Tape
16-QFN
Tape and Reel
16-QFN
-40 to +105 C
Cut Tape
16-QFN
-40 to +105 C
Tape and Reel
16-QFN
-40 to +105 C
Tubes
20-QFN
-40 to +105 C
Tape and Reel
20-QFN
-40 to +105 C
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
1.8V TO 3.3V LVCMOS HIGH-PERFORMANCE CLOCK BUFFER FAMILY
20
SEPTEMBER 21, 2017
Revision History
Date
Originator
Description of Change
03/20/15
B. Chandhoke
Initial release.
05/19/15
B. Chandhoke
1. Expanded Output Enable function text in General Description, and within the note under “Output Logic
Table”.
2. Updated all “Buffer Additive Phase Jitter, RMS” conditions from 125MHz to 156.25MHz.
06/09/15
B. Chandhoke
1. Corrected typos in part numbers in DC Electrical Tables.
2. Updated existing Output Rise/Fall Time specs for 5pF load.
3. Added additional Output Rise/Fall specs for 2pF load.
06/15/15
B. Chandhoke
Fixed typos in Output Rise/Fall Time 5pF specs for CL conditions; should be 5pF; not 2pF.
06/22/15
B. Chandhoke
Changed 3.3V Operating Voltage spec from 3.15V min to 3.135V min; 3.45V max to 3.465V max.
08/24/15
B. Chandhoke
1. Added 5PB1104CMGIW orderable part.
2. Updated Abs Max Ratings table for “Output Enable and All outputs” and “CLKIN”; changed -0.5 V to -0.4
and added -0.4 to... respectively.
05/13/16
H.G.
12/15/16
J. Chen
02/10/17
Y.G.
Change Propagation Delay maximum spec in 1.8V AC electrical characterization table from 2.2 to 2.5ns.
03/28/17
Y.G.
1. Updated Propagation Delay specifications for 5PB1106/08/10; 2.5V and 3.3V.
2. Updated output-output skew maximum specifications for 5PB1106; 1.8V, 2.5V, 3.3V.
3. Updated legal disclaimer.
4. Updated package outline drawings.
05/17/17
Y.G.
Added thermal theta JA, JB, JC values to all parts.
05/23/17
Y.G.
1. Updated 3.3V, 2.5V, and 1.8V IDD typical and maximum values.
2. Updated ordering information.
09/19/17
Y.G.
Updated Input High Voltage, CLKIN (VIH) maximum values.
Replace NDG20 package outline drawing with latest version.
Updated marking diagrams for all TSSOP devices.
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www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
5PB11xx SEPTEMBER 21, 2017
21
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