3-Channel High-Performance
TCXO/LVCMOS Clock Buffer Family
Description
5PB12xx
Datasheet
Features
• Extremely low operating and standby current
The 5PB12xx is a high-performance TCXO/LVCMOS clock
fanout buffer family with individual OE pin for each output.
The CLKIN pin can accept either a square wave (LVCMOS)
or clipped sine wave (such as TCXO clipped sine wave
output) as input.
•
•
There are 3 different fan-out versions available: 1:3, 1:4
and 1:6.
•
The 5PB12xx has industry-leading low jitter and extremely
low current consumption, making it ideal for smart mobile
devices.
•
•
Typical Applications
•
•
• Smart Mobile Handsets
• RF and baseband peripheral clock distribution
• Automotive
consumption
Low RMS additive phase jitter
Family supports 1.8V to 3.3V power supply voltage:
• For 1.8V supply: 5PB1203, 5PB1204, 5PB1206
• For 2.5V / 3.3V supply: 5PB1213, 5PB1214, 5PB1216
Three, four, and six outputs with individual Output Enable
pin
One input
OE_OSC control pin to enable/disable reference
TCXO/XO
Small 10-pin, 16-pin and 20-pin packages available
Industrial -40º to +105ºC temperature range
Block Diagram
CLKOUT1
CLKIN
CLKOUT2
OE_OSC
OE1
OE2
Control
Logic
CLKOUT6
OE6
©2021 Renesas Electronics Corporation
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January 15, 2021
5PB12xx Datasheet
3
8
CLKOUT1
E_OSC
4
7
OE2
OE3
5
6
OE1
11
CLKOUT2
GND
3
10
CLKOUT3
OE3
4
8XXXXXX
9
5
5PB1203 / 5PB1213
10-pin 2mm x 2mm DFN
6
7
GND
GND
CLKOUT2
OE1
CLKOUT1
CLKIN
CLKOUT1
GND
2
17
16
OE2
1
15
VDD
OE3
2
14
CLKOUT3
VDD
3
13
CLKOUT4
GND
4
12
GND
OE6
5
11
CLKOUT5
8
6
5PB1204 / 5PB1214
16-pin, 2.5mm x 2.5mm VFQFPN
7
8
9
10
CLKOUT6
CLKIN
VDD
VDD
CLKOUT2
18
OE_OSC
9
VDD
19
OE5
2
1
20
OE4
VDD
OE2
CLKOUT4
CLKOUT3
14
VDD
10
OE_OSC
1
15
13
12
16
OE4
GND
CLKIN
OE1
Pin Assignments
5PB1206 / 5PB1216
20-pin, 3mm x 3mm VFQFPN
Pin Descriptions
Pin Number
5PB1204
5PB1206
5PB1214
5PB1216
Pin Name
5PB1203
5PB1213
VDD
2
2, 7, 12
Pin Type
Pin Description
3, 9, 15
Power
Connect 1.8V to 5PB1203/5PB1204/5PB1206.
Connect 2.5V or 3.3V to 5PB1213/5PB1214/5PB1216.
GND
1
3, 9, 14
4, 12, 18
Power
Power supply ground.
CLKIN
3
15
20
Input
OE_OSC
4
6
8
Output
OE1
6
16
19
Input
Reference input pin. Connect to LVCMOS input or TCXO.
Input Crystal Oscillator enable pin. Follow Enable Function Truth Table.
If all OE pins are low then OE_OSC is low. Otherwise OE_OSC is high,
enabling reference crystal oscillator.
Output Enable pin for CLKOUT1. Active High. Internal 120kΩ pull-down.
OE2
7
1
1
Input
Output Enable pin for CLKOUT2. Active High. Internal 120kΩ pull-down.
OE3
5
4
2
Input
Output Enable pin for CLKOUT3. Active High. Internal 120kΩ pull-down.
OE4
—
5
6
Input
Output Enable pin for CLKOUT4. Active High. Internal 120kΩ pull-down.
OE5
—
—
7
Input
Output Enable pin for CLKOUT5. Active High. Internal 120kΩ pull-down.
OE6
—
—
5
Input
Output Enable pin for CLKOUT6. Active High. Internal 120kΩ pull-down.
CLKOUT1
8
13
17
Output
Clock Output 1. Same frequency as CLKIN.
CLKOUT2
9
11
16
Output
Clock Output 2. Same frequency as CLKIN.
CLKOUT3
10
10
14
Output
Clock Output 3. Same frequency as CLKIN.
CLKOUT4
—
8
13
Output
Clock Output 4. Same frequency as CLKIN.
CLKOUT5
—
—
11
Output
Clock Output 5. Same frequency as CLKIN.
CLKOUT6
—
—
10
Output
Clock Output 6. Same frequency as CLKIN.
©2021 Renesas Electronics Corporation
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5PB12xx Datasheet
Enable Function Truth Table
Input
Output
OE1 OE2 OE3 OE4 OE5 OE6 OE_OSC CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6
0
0
0
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
0
0
0
0
1
CLOCK
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
0
0
0
1
CLOCK
CLOCK
Hi-Z
Hi-Z
Hi-Z
Hi-Z
…
…
…
…
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
External Components
A minimum number of external components are required for proper operation. A 0.01µF bypass capacitor should be used
on each VDD pin. Use a separate ground via to the board ground plane for the capacitor. Use a separate ground via for each
GND pin. Do not share the ground via. Route power from the via to the VDD plane through the bypass capacitor and then
to the VDD pin. A 33 series termination resistor should be used on each clock output pin.
To achieve the low output skew that the 5PB12xx is capable of, careful attention must be paid to board layout. Essentially,
all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output
skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at
least 15ps of skew.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5PB12xx. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
3.8V
Output Enable and All Inputs/Outputs
-0.5 V to VDD + 0.5 V
Ambient Operating Temperature (extended)
-40 to +105C
Storage Temperature
-65 to +150C
Junction Temperature
125C
Soldering Temperature
260C
©2021 Renesas Electronics Corporation
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5PB12xx Datasheet
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, for 5PB1203 / 1204 / 1206, ambient temperature -40° to +105°C, unless stated otherwise.
Parameter
Operating Voltage
Symbol
Conditions
VDD
Input High Voltage, CLKIN
VIH
LVCMOS input. Note 1
Input Low Voltage, CLKIN
VIL
LVCMOS input. Note 1
Input High Voltage, OE
VIH
Min.
Typ.
Max.
Units
1.71
1.89
V
VDD/2 + 200
VDD
mV
VDD/2 - 200
mV
VDD
V
0.3xVDD
V
0.7xVDD
Input Low Voltage, OE
VIL
Output High Voltage
VOH
IOH = -4mA
Output Low Voltage
VOL
IOL = 4mA
Nominal Output Impedance
ZO
17
Input Capacitance
CIN
5
pF
0.8xVDD
V
0.2xVDD
V
Operating Supply Current
5PB1203
5PB1204
IDD
5PB1206
CLKIN = 26MHz, all outputs enabled
4.76
5.91
CLKIN = Low or High, all outputs disabled
0.01
0.01
CLKIN = 26MHz, all outputs enabled
5.99
7.22
CLKIN = Low or High, all outputs disabled
0.01
0.01
CLKIN = 26MHz, all outputs enabled
9.15
11.39
CLKIN = Low or High, all outputs disabled
0.01
0.01
mA
VDD = 2.5V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise.
Parameter
Operating Voltage
Symbol
Conditions
VDD
Min.
Typ.
2.375
Input High Voltage, CLKIN
VIH
LVCMOS input. Note 1
Input Low Voltage, CLKIN
VIL
LVCMOS input. Note 1
Input High Voltage, OE
VIH
Input Low Voltage, OE
VIL
Output High Voltage
VOH
IOH = -4mA
Output Low Voltage
VOL
IOL = 4mA
Nominal Output Impedance
ZO
Input Capacitance
CIN
VDD/2 + 200
0.7xVDD
Max.
Units
2.625
V
VDD
mV
VDD/2 - 200
mV
VDD
V
0.3xVDD
V
0.8xVDD
V
0.2xVDD
ICLK, OE pin
V
17
5
pF
Operating Supply Current
5PB1213
5PB1214
IDD
5PB1216
©2021 Renesas Electronics Corporation
CLKIN = 26MHz, all outputs enabled
6.66
8.54
CLKIN = Low or High, all outputs disabled
0.01
0.02
CLKIN = 26MHz, all outputs enabled
8.36
10.48
CLKIN = Low or High, all outputs disabled
0.01
0.03
CLKIN = 26MHz, all outputs enabled
12.58
16.30
CLKIN = Low or High, all outputs disabled
0.01
0.04
4
mA
January 15, 2021
5PB12xx Datasheet
VDD = 3.3V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
Conditions
VDD
VIH
LVCMOS input. Note 1
Input Low Voltage, CLKIN
VIL
LVCMOS input. Note 1
Input High Voltage, OE
VIH
Input Low Voltage, OE
VIL
Output High Voltage
VOH
IOH = -4mA
IOL = 4mA
Input High Voltage, CLKIN
Output Low Voltage
VOL
Nominal Output Impedance
ZO
Input Capacitance
CIN
Min.
Typ.
Max.
Units
3.135
3.465
V
VDD/2 + 200
VDD
mV
VDD/2 - 200
mV
VDD
V
0.3xVDD
V
0.7xVDD
0.8xVDD
V
0.2xVDD
ICLK, OE pin
V
17
5
pF
Operating Supply Current
5PB1213
5PB1214
IDD
5PB1216
CLKIN = 26MHz, all outputs enabled
8.96
11.65
CLKIN = Low or High, all outputs disabled
0.14
0.45
CLKIN = 26MHz, all outputs enabled
11.34
14.06
CLKIN = Low or High, all outputs disabled
0.20
0.63
CLKIN = 26MHz, all outputs enabled
16.87
21.72
CLKIN = Low or High, all outputs disabled
0.22
0.70
mA
Notes: 1. Nominal switching threshold is VDD/2.
©2021 Renesas Electronics Corporation
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January 15, 2021
5PB12xx Datasheet
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%; for 5PB1203 / 1204 / 1206, ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Min.
Typ.
0
Max.
Units
200
MHz
Output Rise Time
tOR
0.36 to 1.44V, CL = 5pF
0.6
1.0
ns
Output Fall Time
tOF
1.44 to 0.36V, CL = 5pF
0.6
1.0
ns
2.0
2.5
ns
Propagation Delay
Note 1
Buffer Additive Phase Jitter, RMS
Note 1
1.5
26MHz TCXO clipped sine wave input,
Integration Range: 12kHz to 20MHz
420
fs
125MHz LVCMOS input,
Integration Range: 12kHz to 20MHz
42
fs
20
Output to Output Skew
tSKEWO−O
Note 2, Rising edges at VDD/2
Device to Device Skew
tSKEWD-D
Rising edges at VDD/2
tEN/tDIS
Delay for Output Enable / Disable
Time ENABLEx to BCLKn
Start-up Time
CL < 5pF
tSTART-UP
TCXO Clock Clipped Sine Wave
Input Voltage Swing Level
VINpp
VDD = 1.8V, should connect to CLKIN
through AC coupling and bias circuit
50
ps
200
ps
3
cycles
2
ms
0.8
V
VDD = 2.5V ±5%; for 5PB1213 / 1214 / 1216, ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Min.
Typ.
0
Max.
Units
200
MHz
Output Rise Time
tOR
0.5 to 2.0V, CL = 5pF
0.6
1.0
ns
Output Fall Time
tOF
2.0 to 0.5V, CL = 5pF
0.6
1.0
ns
2.2
2.7
ns
Propagation Delay
Note 1
Buffer Additive Phase Jitter, RMS
Note 1
1.7
26MHz TCXO clipped sine wave input,
Integration Range: 12kHz to 20MHz
280
fs
125MHz LVCMOS input,
Integration Range: 12kHz to 20MHz
30
fs
20
Output to Output Skew
tSKEWO−O
Note 2, Rising edges at VDD/2
Device to Device Skew
tSKEWD-D
Rising edges at VDD/2
50
ps
200
ps
CL < 5pF
3
cycles
tSTART-UP
Part start-up time for valid outputs after
VDD ramp-up
2
ms
VINpp
VDD = 2.5V, should connect to CLKIN
through AC coupling and bias circuit
tEN/tDIS
Delay for Output Enable / Disable
Time ENABLEx to BCLKn
Start-up Time
TCXO Clock Clipped Sine Wave
Input Voltage Swing Level
©2021 Renesas Electronics Corporation
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0.8
V
January 15, 2021
5PB12xx Datasheet
VDD = 3.3V ±5%; for 5PB1213 / 1214 / 1216, ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Input Frequency
Min.
Typ.
Max.
Units
200
MHz
0.6
1.0
ns
0.6
1.0
ns
1.9
2.4
ns
0
Output Rise Time
tOR
Output Fall Time
tOF
Propagation Delay
Note 1
Buffer Additive Phase Jitter, RMS
0.66 to 2.64V, CL = 5pF
2.64 to 0.66V, CL = 5pF
Note 1
1.4
26MHz TCXO clipped sine wave input,
Integration Range: 12kHz to 20MHz
377
fs
125MHz LVCMOS input,
Integration Range: 12kHz to 20MHz
18
fs
20
Output to Output Skew
tSKEWO−O
Note 2, Rising edges at VDD/2
50
ps
Device to Device Skew
tSKEWD-D
Rising edges at VDD/2
200
ps
CL < 5pF
3
cycles
tSTART-UP
Part start-up time for valid outputs after
VDD ramp-up
2
ms
VINpp
VDD = 3.3V, should connect to CLKIN
through AC coupling and bias circuit
tEN/tDIS
Delay for Output Enable / Disable
Time ENABLEx to BCLKn
Start-up Time
TCXO Clock Clipped Sine Wave
Input Voltage Swing Level
0.5
V
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
Test Load and Circuit
50ohms
Rs=33ohm
5 inches
CL = 5pF
AC Coupling and Bias Circuit
VDD
C1
R1
TCXO
R2
Component
Value
C1
0.1µF
R1
10k
R2
10k
VDD
IDT
5PB12xx
©2021 Renesas Electronics Corporation
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January 15, 2021
5PB12xx Datasheet
Package Outline Drawings
The package outline drawings (NTG10, CMG16, NDG20) are appended at the end of this document. The package information is the most
current data available.
▪ 5PB1203 / 5PB1213 – 10-DFN (NTG10)
▪ 5PB1204 / 5PB1214 – 16-VFQFPN (CMG16)
▪ 5PB1206 / 5PB1216 – 20-VFQFPN (NDG20)
Ordering Information
Part / Order Number
Shipping Packaging
Package
Temperature
5PB1203NTGK
Cut Tape
10-pin DFN
-40 to +105°C
5PB1203NTGK8
Tape and Reel
10-pin DFN
-40 to +105°C
5PB1213NTGK
Cut Tape
10-pin DFN
-40 to +105°C
5PB1213NTGK8
Tape and Reel
10-pin DFN
-40 to +105°C
5PB1204CMGK
Cut Tape
16-pin VFQFPN
-40 to +105°C
5PB1204CMGK8
Tape and Reel
16-pin VFQFPN
-40 to +105°C
5PB1214CMGK
Cut Tape
16-pin VFQFPN
-40 to +105°C
5PB1214CMGK8
Tape and Reel
16-pin VFQFPN
-40 to +105°C
5PB1206NDGK
Tube
20-pin VFQFPN
-40 to +105°C
5PB1206NDGK8
Tape and Reel
20-pin VFQFPN
-40 to +105°C
5PB1216NDGK
Tube
20-pin VFQFPN
-40 to +105°C
5PB1216NDGK8
Tape and Reel
20-pin VFQFPN
-40 to +105°C
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Marking Diagrams
203K
YW**
204K
Y**
XXX
YWW$
206K
10-pin DFN
16-pin VFQFPN
20-pin VFQFPN
213K
YW**
214K
Y**
XXX
YWW$
216K
10-pin DFN
16-pin VFQFPN
20-pin VFQFPN
Notes:
1. “**” is the lot number.
2. “YWW”, “YW”, or “Y” are the last digit(s) of the year and week that the part was assembled.
3. “$” denotes mark code.
4. “K” denotes extended temperature range device.
5. “XXX” denotes last three characters of Asm lot.
©2021 Renesas Electronics Corporation
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January 15, 2021
5PB12xx Datasheet
Revision History
Date
Description of Change
January 15, 2021
Updated 1st paragraph text in External Components section.
February 3, 2020
▪ Updated the capacitor value for C1 in AC Coupling and Bias Circuit
November 22, 2019
▪ Updated “Operating Supply Current” data in DC Electrical Characteristics for VDD = 1.8V ±5%, VDD =
2.5V ±5%, and VDD = 3.3V ±5%
▪ Updated Package Outline Drawings; however, no mechanical changes
February 28, 2018
1. Updated CLKIN input high and low voltage ratings in DC characterization tables.
2. Updated Absolute Maximum supply voltage (VDD) from 3.465V to 3.8V.
April 10, 2017
1. Updated Operating Supply Current and Operating Voltage values in DC electrical characteristics tables.
2. Updated Propagation Delay and Output skew values in AC electrical characteristics tables.
3. Updated package outline drawings.
4. Updated legal disclaimer.
July 11, 2016
Initial release.
©2021 Renesas Electronics Corporation
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January 15, 2021
20-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad
NDG20P2, PSC-4179-02, Rev 01, Page 1
© Integrated Device Technology, Inc.
20-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad
NDG20P2, PSC-4179-02, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
Sept 13, 2018
Rev 01
Change QFN to VFQFPN
Mar 30, 2016
Rev 00
Initial Release
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